TPSM84A21MOJR [TI]

具有集成输入和输出电容器的 8V 至 14V 输入、0.508V 至 1.35V 输出、10A 电源模块 | MOJ | 20 | -40 to 85;


型号：	TPSM84A21MOJR
厂家：	TEXAS INSTRUMENTS
描述：	具有集成输入和输出电容器的 8V 至 14V 输入、0.508V 至 1.35V 输出、10A 电源模块 \| MOJ \| 20 \| -40 to 85 开关输出元件电容器电源电路
文件：	总27页 (文件大小：1292K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPSM84A21

ZHCSFS5 –DECEMBER 2016

TPSM84A21 8V 至 14V 输入、0.508V 至 1.35V 输出、10A SWIFT™电源

模块

1 降压稳压器

3 说明

•

全集成电源解决方案，包括输入和输出电容

只需一个电阻即可设置电压

9mm x 15mm 尺寸

TPSM84A21 是一套易于使用的集成电源解决方案，它

将 TPS54A20 10A、DC/DC 同步降压转换器与功率

MOSFET、隔离电感、输入和输出电容以及无源器件

完美融合于薄型封装中。这套完备的电源解决方案只需

一个电阻即可设置电压，设计过程中无需考虑回路补偿

和磁件选型。

–

最大高度 2.3mm

与 TPSM84A22 引脚兼容

•

超快速负载阶跃响应

效率高达 88%

对于标准应用而言，凭借这套全集成电源解决方案，

无需使用额外的输入或输出电容即可正常运行，而且只

需通过一个外部电阻即可设置输出电压。此

1% 的输出电压精度

4MHz 开关频率

MSL 3/245°C 峰值回流焊温度

与外部时钟同步

外，TPSM84A21 还支持高频运行，同时兼具超快瞬态

响应和精准的稳压能力，轻松满足严格的稳压规范。

电源正常输出

该器件采用 9mm × 15mm 的小巧尺寸，方便焊接在印

刷电路板上，从而打造一种紧凑的薄型负载点设计。

预偏置输出启动

可编程欠压闭锁 (UVLO)

工作 IC 结温范围：-40°C 至 +125°C

工作环境温度范围：-40°C 至 +85°C

符合 EN55022 B 类辐射标准

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

TPSM84A21

QFM

9.00mm × 15.00mm

(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

2 应用

器件比较

•

电信和无线基础设施

器件编号

V_OUT调节范围

0.55V - 1.35V

1.2V - 2.05V

测试和测量

TPSM84A21

TPSM84A22

Compact PCI/PCI Express/PXI Express

空白

简化电路原理图

瞬态响应

V_IN

VIN

VS+

EN/UVLO

VOUT

V_OUT

TPSM84A21

PGOOD

VADJ

SYNC

ILIM

AGND PGND

w_{9Ç

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSDF7

TPSM84A21

ZHCSFS5 –DECEMBER 2016

www.ti.com.cn

7.3 Feature Description................................................. 11

7.4 Device Functional Modes........................................ 15

Application and Implementation ........................ 16

8.1 Application Information............................................ 16

8.2 Typical Application ................................................. 16

Power Supply Recommendations...................... 18

降压稳压器............................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings ............................................................ 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Switching Characteristics.......................................... 7

6.7 Package Specifications............................................. 7

6.8 Typical Characteristics ............................................. 8

Detailed Description ............................................ 10

7.1 Overview ................................................................. 10

7.2 Functional Block Diagram ....................................... 10

10 Layout................................................................... 19

10.1 Layout Guidelines ................................................. 19

10.2 Layout Examples................................................... 19

11 器件和文档支持 ..................................................... 21

11.1 文档支持 ............................................................... 21

11.2 接收文档更新通知 ................................................. 21

11.3 社区资源................................................................ 21

11.4 商标....................................................................... 21

11.5 静电放电警告......................................................... 21

11.6 Glossary................................................................ 21

12 机械、封装和可订购信息....................................... 21

4 修订历史记录

日期

修订版本

注释

2016 年 12 月

最初发布。

TPSM84A21

www.ti.com.cn

ZHCSFS5 –DECEMBER 2016

5 Pin Configuration and Functions

MOJ Package

20-Pin QFM

Top View

VIN

PGND

VIN

PGND

VOUT

PGND

Pin Functions

I/O

DESCRIPTION

NAME

NO.

Zero voltage reference for analog control circuitry. Connect RSET between this pin and VADJ close

to the device. Do not connect this pin to PGND; the connection is made internal to the device.

AGND

—

Enable and UVLO adjust pin. When this pin voltage is low, the device is disabled. Use an open drain,

open collector, or a suitable logic gate device to control the enable function. A resistor divider

between this pin, PGND, and VIN adjusts the UVLO voltage.

EN/UVLO

Current limit setting pin. Leave this open for the full current limit threshold of 15 A. Connect a 47 kΩ

resistor between this pin and PGND to reduce the current limit threshold to 11.25 A.

ILIM

1, 4, 5, 6, 7,

8, 10, 18, 20

Power ground of the device. Connect these pins to the power ground plane of the PCB. Thermal vias

to internal ground planes should be added beneath pin 20.

PGND

—

Power good indicator. This pin is an open-drain output and will assert low if the output voltage is

greater than ±5% from the programmed value or due to thermal shutdown, under-voltage, or EN

shutdown. A pull-up resistor is required. VG can be used as a PGOOD pull-up source.

PGOOD

VS+

Remote sense connection. This pin must be connected to VOUT at the load or at the device pins.

Connect the pin to VOUT at the load for improved regulation.

External clock synchronization pin. An external clock signal can be applied to this pin to synchronize

the switching frequency within ±10% of the nominal switching frequency (4 MHz).

SYNC

VADJ

Output voltage adjust pin. Connecting a resistor between this pin and AGND sets the output voltage.

Gate driver supply pin. If this pin is left open, an internal LDO will generate the gate driver supply

voltage from the VIN pin. To reduce power consumption and improve efficiency, power this pin with

an external 5-V supply. This pin can be used as a PGOOD pull-up source.

Input Voltage. These pins supply all of the power to the converter. Connect VIN to a supply voltage

between 8 V and 14 V.

VIN

17, 19

VOUT

Output voltage. Connect any external output capacitors between these pins and PGND.

TPSM84A21

ZHCSFS5 –DECEMBER 2016

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

VIN

EN/UVLO

Input voltage

PGOOD, SYNC, VG

ILIM, VADJ, VS+

PGND

0.3

Output voltage

Source current

VOUT

EN/UVLO

100

µA

Sink current

PGOOD

Mechanical shock

Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted

500

125

150

Mechanical vibration

Mil-STD-883D, Method 2007.2, 20-2000Hz

(2)

Operating IC junction temperature, T_J

–40

–55

°C

(2)

Operating ambient temperature, T_A

Storage temperature, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the

internal power IC when the device is powered. Operating below the maximum ambient temperature, as shown in the safe operating area

(SOA) curves, ensures that the maximum junction temperature of any component inside the module is never exceeded.

6.2 ESD Ratings

VALUE

±2500

±1500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V_IN

Input voltage

V_OUT

V_VG

V_EN

Output voltage

0.55

5.0

1.35

5.5

Gate drive voltage

EN voltage

V_PGOOD

V_SYNC

I_OUT

T_J

PGOOD pull-up voltage

SYNC voltage

Output current

(1)

Operating IC junction temperature

–40

125

°C

(1)

T_A

Operating ambient temperature

(1) The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the

internal power IC when the device is powered. Operating below the maximum ambient temperature, as shown in the safe operating area

(SOA) curves, ensures that the maximum junction temperature of any component inside the module is never exceeded.

TPSM84A21

www.ti.com.cn

ZHCSFS5 –DECEMBER 2016

6.4 Thermal Information

TPSM84A21

THERMAL METRIC⁽¹⁾

MOJ (QFM)

20 PINS

14.9

UNIT

(2)

R_θJA

ψ_JT

Junction-to-ambient thermal resistance

°C/W

(3)

Junction-to-top characterization parameter

2.2

(4)

ψ_JB

Junction-to-board characterization parameter

5.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) The junction-to-ambient thermal resistance, Θ_JA, applies to devices soldered directly to a 50 mm x 100 mm double-sided PCB with 2 oz.

copper and natural convection cooling. Additional airflow reduces Θ_JA

(3) The junction-to-top board characterization parameter, Θ_JT, estimates the junction temperature, T_J, of a device in a real system, using a

procedure described in JESD51-2A (section 6 and 7). T_J= ψ_JT* Pdis + T_T; where Pdis is the power dissipated in the device and TT is

the temperature of the top of the device.

(4) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature, T_J, of a device in a real system, using a

procedure described in JESD51-2A (sections 6 and 7). T_J= ψ_JB* Pdis + T_B; where Pdis is the power dissipated in the device and T_Bis

the temperature of the board 1mm from the device.

6.5 Electrical Characteristics

Over –40°C to +85°C free-air temperature range, VIN = 12 V, V_OUT= 1.0 V, I_OUT= I_OUTmax, F_SW= 4 MHz,

External C_IN= 2 × 22 µF 25 V 1210 ceramic plus 1 × 100 µF electrolytic (unless otherwise noted)

PARAMETER

INPUT VOLTAGE (VIN)

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_IN

VIN input voltage range

Over V_OUTrange

V_INincreasing

V_INdecreasing

7.65

7.4

7.95

V_{IN_UVLO}

VIN under voltage lock out

V_{IN_HYS}

I_{VIN_EN}

VIN UVLO hysteresis

VIN standby current

250

µA

EN = 0 V

OUTPUT VOLTAGE (VOUT)

V_OUT(ADJ)Output voltage adjust range

Over I_OUTrange

0.55

1.35

Set-point voltage tolerance

Temperature variation

Line regulation

V_OUT= 1.0 V, T_A= 25°C, I_OUT= 0 A

-1.0%

+1.0%⁽¹⁾

V_OUT= 1.0 V, –40°C ≤ T_A≤ 85°C, I_OUT= 0 A

V_OUT= 1.0 V, over V_INrange, I_OUT= 0 A, T_A= 25°C

V_OUT= 1.0 V, over I_OUTrange, T_A= 25°C

±0.2%⁽²⁾

±0.03%

±0.1%

V_OUT

Load regulation

V_OUT

Ripple

Output Voltage Ripple

20-MHz Bandwidth, peak-to-peak

OUTPUT CURRENT

Output current

See SOA graph for derating over temperature.

I_OUT

ILIM = open

Overcurrent threshold

ILIM = 47 kΩ

11.25

(1) The stated limit of the set-point tolerance includes the tolerance of both the internal voltage reference and the internal adjustment

resistor. The overall output voltage tolerance will be affected by the tolerance of the external R_SETresistor.

(2) Specified by design. Not production tested.

TPSM84A21

ZHCSFS5 –DECEMBER 2016

www.ti.com.cn

Electrical Characteristics (continued)

Over –40°C to +85°C free-air temperature range, VIN = 12 V, V_OUT= 1.0 V, I_OUT= I_OUTmax, F_SW= 4 MHz,

External C_IN= 2 × 22 µF 25 V 1210 ceramic plus 1 × 100 µF electrolytic (unless otherwise noted)

PARAMETER

PERFORMANCE

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_OUT= 0.8 V, VG = open

79.8%

82.5%

82.6%

84.9%

84.5%

86.5%

V_OUT= 0.8 V, VG = 5 V

V_OUT= 1.0 V, VG = open

V_OUT= 1.0 V, VG = 5 V

V_OUT= 1.2 V, VG = open

V_OUT= 1.2 V, VG = 5 V

VOUT over/undershoot

Efficiency⁽²⁾

V_IN= 12 V, I_OUT= 5 A

1 A/µs load step,

25% to 75% IOUT(max),

COUT= 0 µF

µs

Recovery Time

Transient Response⁽²⁾

5 A/µs load step,

25% to 75% IOUT(max),

COUT= 0 µF

VOUT over/undershoot

Recovery Time

µs

SOFT START

T_SS

Internal soft start time⁽²⁾

4.1

4.8

INTERNAL REGULATOR (VG)

V_VG

VG pin output voltage

4.4

5.0

ENABLE AND UNDER-VOLTAGE LOCK-OUT (EN/UVLO)

V_EN

I_EN

EN threshold range

Input current

1.17

1.23

–4

1.27

EN threshold + 50 mV

EN threshold – 50 mV

µA

Hysteresis current

–1

POWER GOOD (PGOOD)

V_VOUTfalling (Fault)

V_VOUTrising (Good)

V_VOUTrising (Fault)

V_VOUTfalling (Good)

89%

95%

(2)

V_PGOOD

PGOOD Thresholds

109%

104%

Minimum V_INfor valid

_PGOOD≤ 0.5 V at 100 µA

1.2

2.75

0.3

PGOOD⁽²⁾

PGOOD Low Voltage

I_PGOOD= 1.7 mA

0.25

THERMAL SHUTDOWN

Thermal shutdown threshold

Thermal shutdown hysteresis

CAPACITANCE

135

°C

Ceramic type

0⁽³⁾

0⁽⁴⁾

µF

C_IN

External Input Capacitance

Non-ceramic type

Ceramic type

100

1000⁽⁵⁾µF

2200⁽⁵⁾µF

35 mΩ

C_OUT

External Output Capacitance

Non-ceramic type

Equivalent series resistance (ESR)

(3) Internal to the device, 66.1 µF (nominal) ceramic input capacitance is present. This device does not require additional input capacitance.

If adding additional input capacitance, locate the capacitors close to the device.

(4) Internal to the device, 185 µF (nominal) ceramic output capacitance is present. This device does not require additional output

capacitance to operate. Adding additional output capacitance near the load improves the response of the device to load transients.

(5) The maximum output capacitance listed in the table is the maximum amount that has been tested and validated for proper start-up,

stability, and transient response. It may be possible to operate with additional output capacitance, however, additional validation is

required.

TPSM84A21

www.ti.com.cn

ZHCSFS5 –DECEMBER 2016

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(1)

FREQUENCY AND SYNCHRONIZATION (SYNC)

F_SW

Switching frequency

SYNC = open

3.7

3.6

2.0

4.3

4.4

MHz

F_SYNC

V_SYNC-H

V_SYNC-L

D_SYNC

Synchronization frequency range

SYNC high threshold

SYNC low threshold

SYNC Control

0.8

SYNC duty cycle

20%

80%

(1) Specified by design. Not production tested.

6.7 Package Specifications

TPSM84A21

VALUE

UNIT

Weight

0.91

grams

Flammability

Meets UL 94 V-O

MTBF Calculated Reliability

Per Bellcore TR-332, 50% stress, T_A= 40°C, ground benign

30.6

MHrs

TPSM84A21

ZHCSFS5 –DECEMBER 2016

www.ti.com.cn

6.8 Typical Characteristics

The electrical characteristic data has been developed from actual products tested at 25°C. This data is

considered typical for the converter. Applies to 图 1 through 图 4.

The temperature derating curves represent the conditions at which internal components are at or below the

manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 50 mm ×

100 mm double-sided PCB with 2 oz. copper. Applies to 图 5 and 图 6.

V_OUT

1.35 V

1.2 V

1.0 V

0.8 V

0.55 V

V_OUT

1.35 V

1.2 V

1.0 V

0.8 V

0.55 V

Output Current (A)

D001

D004

VIN = 12 V

VG = open

VIN = 12 V

VG = 5 V

图 1. Efficiency

图 2. Efficiency

3.0

2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

V_OUT

1.35 V

1.2 V

1.0 V

0.8 V

0.55

V_OUT

1.35 V

1.2 V

1.0 V

0.8 V

0.55

Output Current (A)

D0021

D003

VIN = 12 V

VG = open

VIN = 12 V

图 3. Power Dissipation

图 4. Output Voltage Ripple

TPSM84A21

www.ti.com.cn

ZHCSFS5 –DECEMBER 2016

Typical Characteristics (接下页)

Airflow

100 LFM

Nat conv

Airflow

Nat conv

Output Current (A)

D005

VIN = 12 V

VOUT = 0.8 V

VIN = 12 V

VOUT = 1.2 V

图 5. Safe Operating Area

图 6. Safe Operating Area

VIN = 12 V

VOUT = 1.0 V

IOUT = 1 A

VIN = 12 V

VOUT = 1.0 V

IOUT = 1 A

图 7. VIN Start-up Waveforms

图 8. VIN Shut-down Waveforms

VIN = 12 V

VOUT = 1.0 V

IOUT = 1 A

VIN = 12 V

VOUT = 1.0 V

IOUT = 1 A

图 9. EN Start-up Waveforms

图 10. EN Shut-down Waveforms

TPSM84A21

ZHCSFS5 –DECEMBER 2016

www.ti.com.cn

7 Detailed Description

7.1 Overview

The TPSM84A21 is a 14-V, 10-A, synchronous series capacitor step-down (buck) power module. The

TPSM84A21 combines a 10-A DC/DC converter with power MOSFETs, shielded inductors, series capacitor,

input and output capacitors, and passives into a low profile, overmolded package. The integrated input and

output capacitors allows standard applications to operate with no additional input or output capacitors and only a

single resistor to set the output voltage.

The integrated components allow for high-efficiency, high-density, complete power supply designs with

continuous output currents up to 10 A. The TPSM84A21 reduces the external component count by integrating

both the input and output capacitors. The TPSM84A21 input voltage range is 8 V to 14 V with an output voltage

range of 0.508 V to 1.35 V.

The TPSM84A21 is a two-phase power supply with each phase switching at a fixed 2 MHz frequency, resulting

in the internal oscillator frequency of 4 MHz. An external synchronization clock can also be provided via the

SYNC pin.

The TPSM84A21 starts up safely into loads with pre-biased outputs (non-zero volts at startup). The device

implements an internal input voltage under voltage lockout (UVLO) feature which can be adjusted higher by

adding an external resistor divider on the EN/UVLO pin. Electrical ON/OFF control is provided using the enable

(EN) feature. The TPSM84A21 is disabled by pulling the EN pin low. When the device is disabled, the supply

current is typically less than 50 μA.

The TPSM84A21 has a power good comparator (PGOOD) which monitors the output voltage through the VS+

pin. The PGOOD pin is an open-drain MOSFET which is held low until the output voltage is within ±5% of the set

voltage. The PGOOD pin is held low during startup or when a fault occurs.

7.2 Functional Block Diagram

ILIM

TPSM84A21

VIN

REG

UVLO

Protection

EN/UVLO

PGOOD

VIN

and

Supervisory

Circuits

Oscillator

4 MHz

SYNC

Power

Stage

and

Control

Logic

ëhÜÇ

10 O

VOUT

VS+

1 kO

VADJ

Error

Amp

Soft

Start

VREF

AGND

PGND

TPSM84A21

www.ti.com.cn

ZHCSFS5 –DECEMBER 2016

7.3 Feature Description

7.3.1 Adjusting the Output Voltage (VADJ)

The VADJ pin programs the output voltage of the TPSM84A21. The output voltage adjustment range is from

0.508 V to 1.35 V. The adjustment method requires the addition of R_SETconnected between VADJ and AGND. If

an R_SETresistor is not populated, the module will default to 0.508 V. The VS+ pin (pin 14) must be connected to

VOUT. TI recommends to make the VS+ connection at the load for the best load regulation performance. The

R_SETresistor must be connected directly between the VADJ pin (pin 15) and AGND (pin 16).

公式 1 can be used to calculate the ideal R_SETresistor value for a given output voltage, V_OUT. Use 公式 2 to

calculate the actual V_OUTfor a given R_SETresistor. 表 1 lists the ideal R_SETresistor values for a number of

common voltages. 表 1 also lists the closest E96 standard resistor values to the ideal R_SETvalues along with the

actual output voltage and the set-point error when using the E96 resistor value. For the most accurate output

voltage set-point it is best to use the ideal resistor value. The ideal resistor value may not be a standard value

and may require two standard value resistors in series or parallel to obtain the desired output voltage.

R_SET

(kꢀ)

V_OUT

œ1

0.508

(1)

(2)

V_OUT

0.508 *

+1 (V)

(

)

R_SET(kꢀ)

表 1. R_SETResistor Values

Closest E96 Resistor Value

V_OUT(V)

0.508

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.9

Ideal R_SET(kΩ)

Open

R_SET(kΩ)

Open

12.1

Actual V_OUT(V)

0.508

0.549

0.601

0.65

–

12.095

5.522

–0.003

0.088

0.046

–0.248

–0.013

–0.006

–0.392

–0.137

–0.027

0.603

0.348

–0.490

0.303

0.166

0.317

–0.712

–0.070

5.49

3.578

3.57

2.646

2.67

0.698

0.749

0.799

0.847

0.899

0.949

1.006

1.053

1.095

1.153

1.202

1.254

1.291

1.349

2.099

2.10

1.739

1.74

1.485

1.50

1.296

1.30

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.149

1.15

1.033

1.02

0.937

0.931

0.866

0.787

0.732

0.681

0.649

0.604

0.858

0.791

0.734

0.685

0.641

0.603

TPSM84A21

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7.3.2 Input and Output Capacitance

The TPSM84A21 requires no external input or output capacitance to operate. Internal to the TPSM84A21 there is

66.1 µF (nominal) of ceramic input capacitance. Additionally, internal to the TPSM84A21 there is 185 µF

(nominal) of ceramic output capacitance.

Applications requiring additional ripple voltage reduction should add ceramic input and output capacitors directly

at the VIN and VOUT pins of the device. Applications requiring improved transient response can also benefit by

adding additonal ceramic or low-ESR bulk output capacitance. See the Capacitance section of the Electrical

Characteristics table for more information when adding external input and output capacitors.

7.3.3 Transient Response

The exceptional transient response of the TPSM84A21 allows many applications to operate with little or no

additional output capacitance. 图 11 through 图 14 show typical transient waveforms for the TPSM84A21.

7.3.3.1 Transient Response Waveforms

VIN = 12 V

VOUT = 0.8 V

Load Step = 5 A

VIN = 12 V

VOUT = 0.8 V

Load Step = 5 A

COUT = 0 µF Slew Rate = 1 A/µs

COUT = 300 µF Slew Rate = 5 A/µs

图 11. Transient Response

图 12. Transient Response

VIN = 12 V

VOUT = 1.0 V

Load Step = 5 A

VIN = 12 V

VOUT = 1.0 V

Load Step = 5 A

COUT = 0 µF Slew Rate = 1 A/µs

COUT = 100 µF Slew Rate = 5 A/µs

图 13. Transient Response

图 14. Transient Response

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7.3.4 Oscillator Frequency

The oscillator frequency of this converter is set at 4 MHz. The per phase switching frequency of the converter is

half the oscillator frequency, or 2 MHz per phase. The oscillator frequency is fixed internally.

During load transients, the internal control loop will momentarily change the switching frequency in order to meet

the output voltage recovery.

7.3.5 External Clock Syncronization

An external clock can be connected to the SYNC pin. The external clock signal overrides the internal oscillator

and is used as the system clock. This feature enables the user to synchronize the switching events to a master

clock on their board. The internal phase locked loop (PLL) has been implemented to allow synchronization at

frequencies between ±10% of the nominal oscillator frequency. This allows the user to easily switch between the

internal oscillator mode and the external clock mode while converting power. Before the external clock is present

or after it is removed, the device with default to the internal oscillator setting.

To implement the synchronization feature, connect a square wave clock signal to the SYNC pin with a duty cycle

between 20% and 80%. The clock signal amplitude must transition lower than 0.8 V and higher than 2 V. The

start of the switching cycle is synchronized to the rising edge of the SYNC pin. The device can be configured for

operation in applications where both an internal oscillator mode and an external synchronization clock mode are

needed. Before the external clock is present, the switching frequency of the device is set by the internal

oscillator. When the external clock is present, the SYNC mode overrides the internal oscillator. The first time the

SYNC pin is pulled above the SYNC high threshold (2 V), the device switches from the internal oscillator mode to

the SYNC mode and the PLL starts to lock onto the frequency of the external clock. When the external SYNC

clock is removed, the converter will transition back to the internal oscillator after 4 internal clock cycles.

7.3.6 Soft Start

The TPSM84A21 has a pre-programmed soft start time of 4.1 ms (typ). The soft start time is the time it takes for

the output voltage to rise from zero volts to the voltage set by the R_SETresistor. Soft start is an important feature

that limits inrush current and reduces the load on the input supply to this device. During soft start, the internal

reference voltage is slowly ramped up to the internal reference voltage. This slowly increases the commanded

output voltage of the converter and reduces the initial surge in current. During soft start PGOOD remains low, the

PLL is not active, and output UVP/OVP faults are disabled.

7.3.7 Power Good (PGOOD)

The Power Good (PGOOD) pin is an open drain output. After startup, when the VADJ pin is typically between

95% and 105% of the internal voltage reference, the PGOOD pin pull-down is released and the pin floats. The

recommended pull-up resistor value is between 10 kΩ and 100 kΩ to a voltage source of 5.5 V or less. For

convenience, VG can be used as the pull-up voltage. The PGOOD is in a defined state once the VIN input

voltage is greater than approximately 1.2 V, but with reduced current sinking capability. The PGOOD achieves

full current sinking capability once the VIN input voltage is above the input UVLO. The PGOOD pin is pulled low

when the VADJ pin voltage is typically lower than 95% or greater than 105% of the nominal internal reference

voltage. The PGOOD pin is also pulled low if a fault is detected, the EN pin is pulled low, or the converter is

performing its soft-start power up sequence.

7.3.8 Gate Driver (VG)

A linear regulator internal to the TPSM84A21 generates a 4.8 V internal supply rail on the VG pin. The input of

the linear regulator comes from the VIN pin. The VG supply rail is used to power the internal gate drivers and is

the input to another regulator that generates the internal supply rails used by the controller. To improve converter

efficiency, an external 5 V supply is recommended to be connected to the VG pin, thereby overriding the internal

4.8 V regulator. This external supply must be between 5.0 V and 5.5 V and must be present before applying

input voltage to the VIN pin. If not supplying an external voltage to this pin, leave this pin open.

7.3.9 Startup into Pre-biased Outputs

The TPSM84A21 prevents the low-side MOSFETs from discharging a pre-biased output. During pre-biased

startup, the low-side MOSFETs do not turn on until after the high-side MOSFETs have started switching. The

high-side MOSFETs do not start switching until the internal soft-start reference voltage exceeds the voltage at

the VADJ pin.

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7.3.10 Thermal Shutdown

The internal thermal shutdown fault is triggered if the junction temperature exceeds 135°C (typ). This interrupts

regulation by making the output high impedance. The device reinitiates the power up sequence when the junction

temperature drops below 115°C (typ).

7.3.11 Overcurrent Protection

For protection against load faults, the TPSM84A21 incorporates output overcurrent protection. Applying a load

that exceeds the module's overcurrent threshold causes the output to shut down and PGOOD is pulled low.

Following shut down, the module attempts to restart after a 32.8-ms hiccup interval counter has expired. This

provides a hiccup response to an overcurrent condition. During this period, the average current flowing into the

fault is significantly reduced which reduces power dissipation. Once the fault is removed, the module

automatically recovers and returns to normal operation.

The TPSM84A21 overcurrent trip point is 15 A (typ) when the ILIM pin is left open. This provides enough margin

for brief overshoots in inductor currents during a load transient while at the same time protecting against short

circuits or other potentially catastrophic faults on the output. The overcurrent trip point can be reduced to

11.25 A (typ) by placing a 47 kΩ between the ILIM pin and PGND. Programming resistors with up to ±5%

variation can be used. The current limit selection is latched in at power up and cannot be changed without

cycling input power or the EN pin voltage.

7.3.12 Output Undervoltage/Overvoltage Protection

The device incorporates an output undervoltage/overvoltage protection (UVP/OVP) circuit to prevent damage to

the load. This fault can be triggered during large, fast load transients if insufficient output capacitance is used.

The UVP/OVP feature compares the VADJ pin voltage to internal thresholds. If the VADJ pin voltage is lower

than 90% or greater than 110% of the nominal internal reference voltage, the module is turned off, a fault is

triggered, and the PGOOD pin is pulled low. When the fault hiccup interval is complete, the module will attempt

to restart.

7.3.13 Enable (EN)

The EN pin provides electrical on and off control of the TPSM84A21. Once the EN pin voltage exceeds the

threshold voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the

module stops switching and enters a low power state. There is no voltage hysteresis in the EN threshold. The

rising and falling voltage thresholds occur at the same level. The EN pin has an internal pull-up current source,

allowing the user to float the EN pin for enabling the device.

If an application requires controlling the EN pin, use an open drain/collector device or a suitable logic gate to

interface with the pin. 图 15 shows controlling the EN/UVLO pin using a MOSFET, Q1. Turning Q1 on, disables

the device. Using a voltage superviser to control the EN pin allows control of the turn-on and turn-off of the

device as opposed to relying on the ramp up or down of the input voltage source.

VIN

EN/

UVLO

Control

PGND

图 15. Enable Control

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7.3.14 Undervoltage Lockout (UVLO)

The TPSM84A21 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin

voltage is below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 7.65 V(max) with a

typical hysteresis of 250 mV.

If an application requires a higher UVLO threshold, the UVLO pin can be configured as shown in 图 16. The

value of R_UVLO1and R_UVLO2can be calculated using 公式 3 and 公式 4 or selected from 表 2. It is recommended

to set the UVLO hysteresis of approximately 500mV in order to avoid repeated chatter during start up or shut

down. 表 2 shows recommended R_UVLO1and R_UVLO2values for various VIN UVLO rising thresholds, with 500 mV

of hysteresis.

V_IN(RISE)œ V_IN(FALL)

R_UVLO1

3 µA

R_UVLO1x 1.23

V_IN(FALL)œ 1.23 + (R_UVLO1x 4 µA)

(3)

(4)

R_UVLO2

VIN

w_Üë[h1

EN/

UVLO

w_Üë[h2

PGND

图 16. Adjustable UVLO

表 2. Standard Resistor Values For Adjusting VIN UVLO

VIN UVLO RISING THRESHOLD (V)

VIN UVLO FALLING THRESHOLD (V)

R_UVLO1(kΩ)

8.0

7.5

8.5

8.0

9.0

8.5

9.5

9.0

10.0

9.5

169

29.4

169

27.4

169

25.5

169

24.3

169

22.6

R_UVLO2(kΩ)

7.4 Device Functional Modes

7.4.1 Active Mode

The TPSM84A21 is in Active Mode when VIN is above the UVLO threshold and the EN/UVLO pin voltage is

above the EN high threshold. The simplest way to enable the TPSM84A21 is to leave the EN/UVLO pin floating.

This allows self start-up of the TPSM84A21 when the input voltage is above the UVLO threshold.

7.4.2 Light Load Operation

The TPSM84A21 operates in forced continuous conduction mode (FCCM) under light load conditions. When

operating in FCCM, the switching frequency remains constant and the high side and low side MOSFETs are

turned on and off in a complementary fashion allowing negative inductor current for part of the switching cycle.

7.4.3 Shutdown Mode

The EN/UVLO pin provides electrical ON and OFF control for the TPSM84A21. When the EN/UVLO pin voltage

is below the EN threshold, the device is in shutdown mode. In shutdown mode the stand-by current is typically

less than 50 μA. The TPSM84A21 also employs under voltage lock out protection. If VIN is below the UVLO

level, the output of the regulator turns off.

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPSM84A21 is a synchronous series capacitor step down DC-DC power module. It is used to convert a

higher DC voltage to a lower DC voltage with a maximum output current of 10 A. The following design

procedure can be used to select components for the TPSM84A21. Alternately, the WEBENCH^®software

may be used to generate complete designs. When generating a design, the WEBENCH software utilizes an

iterative design procedure and accesses comprehensive databases of components. Please visit

www.ti.com/webench for more details.

8.2 Typical Application

The TPSM84A21 includes both input and output capacitors internal to the device, therefore it only requires a

voltage setting resistor and possibly a pull-up resistor on the PGOOD pin in most applications. 图 17 shows a

typical TPSM84A21 schematic with only the minimum required components.

TPSM84A21

12 V

VIN

VS+

VOUT

1.0 V

10 kO

VADJ

PGOOD

AGND

PGND

1.02 kO

图 17. Typical Application Schematic

8.2.1 Design Requirements

For this design example, use the parameters listed in 表 3 and follow the design procedures below.

表 3. Design Parameters

DESIGN PARAMETER

Input Voltage V_IN

VALUE

12 V typical

Output Voltage V_OUT

Output Current Rating

Key care-abouts

1.0 V

10 A

Tight transient response, small footprint, high efficiency, PGOOD signal

±2% voltage deviation, 5 A load step, 5 A/µs slew rate

Transient Response Requirements

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8.2.2 Detailed Design Procedure

8.2.2.1 Setting the Output Voltage

The output voltage of the TPSM84A21 is externally adjustable using a single resistor (R_SET). Select the value of

R_SETfrom or calculate using 公式 5:

R_set

( )

V_out

- 1

0.508

(5)

To set the output voltage to 1.0 V, the calculated value for R_SETis 1.03 kΩ. The closest E96 value is 1.02 kΩ.

8.2.2.2 Input and Output Capacitance

The TPS84A21 requires no external input or output capacitance to operate. Input and output capacitors can be

added to improve ripple or transient response. In this design example, in order to meet the ±2% voltage deviation

for a 5-A, 5-A/µs load step, 100 µF of output capacitance is required.

8.2.2.3 Power Good (PGOOD)

Applications requiring voltage rail sequencing can benefit from the PGOOD signal present with the TPSM84A21.

The PGOOD pin is an open drain output. When the output voltage is typically between 95% and 105% of the set

point, the PGOOD pin pull-down is released and the pin floats, requiring an external pull-up resistor for a high

signal. A 10-kΩ pull-up resistor is placed between the PGOOD pin and an external 5V rail.

8.2.2.4 External VG Voltage

The VG supply rail is used to power the internal gate drivers and other internal supply rails used by the

controller. For best efficiency, supply an external 5 V to the VG pin, thereby overriding the internal 4.8 V

regulator. Expect a 2-3% efficiency improvement by driving the VG pin with an external 5V.

8.2.3 Application Curves

VIN = 12 V

VOUT = 1.0 V

VIN = 12 V

VOUT = 1.0 V

Load Step = 5 A

COUT = 100 µF Slew Rate = 1 A/µs

图 18. Start-up Waveforms

图 19. Application Transient Response

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9 Power Supply Recommendations

The TPSM84A21 is designed to operate from an input voltage supply range between 8 V and 14 V. This input

supply should be well regulated and able to withstand maximum input current and maintain a stable voltage. The

resistance of the input supply rail should be low enough that an input current transient does not cause a high

enough drop at the supply voltage that can cause a false UVLO fault triggering and system reset.

If the input supply is located more than a few inches from the TPSM84A21, additional bulk capacitance may be

required at the input pins. A typical recommended amount of bulk input capacitance is 47 μF - 100 μF.

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10 Layout

10.1 Layout Guidelines

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. 图 20 and 图 22

show typical, top-side PCB layouts. Some considerations for an optimized layout are:

•

Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal

stress.

When adding input and output ceramic capacitors, place them close to the device pins to minimize high

frequency noise.

•

Locate any additional output capacitors between the ceramic capacitors and the load.

Keep AGND and PGND separate from one another. The connection is made internal to the device.

Place R_SETas close as possible to the VADJ pin.

Use multiple vias to connect the power planes to internal layers.

10.2 Layout Examples

The layout shown in 图 20 shows the minimum solution size with only a single voltage setting resistor (R1) as the

only additional required component. 图 21 shows a typical internal PCB layer with a trace connecting the VS+ pin

to VOUT near the load.

图 20. Minimum Component Layout

图 21. VS+ Trace on Internal Layer

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Layout Examples (接下页)

图 22 shows a layout with the placement of additional ceramic input capacitors (C1, C3) and ceramic output

capacitors (C2, C4) for designs that require additional ripple reduction or improved transient response. 图 23

shows a typical internal PCB layer with a trace connecting the VS+ pin to VOUT near the load

图 22. Layout with Optional CIN and COUT

图 23. VS+ Trace on Internal Layer

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11 器件和文档支持

11.1 文档支持

11.1.1 相关文档ꢀ

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