TRF2052 [TI]
LOW-VOLTAGE 2-GHz SYNTHESIZER; 低电压2 - GHz的合成器
| 型号： | TRF2052 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW-VOLTAGE 2-GHz SYNTHESIZER |
| 文件： | 总9页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TRF2052
LOW-VOLTAGE 2-GHz SYNTHESIZER
SLWS066 – JULY 1998
PW PACKAGE
(TOP VIEW)
3-V Power Supply Operation
2-GHz Operation
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Normal and Speed-Up Charge Pumps
Dual PLL: One RF and One IF
CLOCK
DATA
STROBE
VSS
RFINP
RFINN
VCCP
REFIN
RA
VDD
NENM
LOCK
NENA
RN
VDDA
PHP
PHI
VSSA
PHA
Additional, Directly Accessible
Power-Down Modes
description
The TRF2052 is a dual-channel, low-power,
phase-locked loop (PLL) frequency synthesizer
component designed specifically for digitally en-
hanced cordless telephone (DECT) applications.
The device is suitable for a variety of applications
AUXIN
up through 2 GHz. A speed-up integral charge pump is used for fast channel switching. The simple serial
interface is compatible with the extended performance mode (EPM) of other devices in Texas Instruments’
synthesizer family.
Along with the external loop filters, the TRF2052 provides all functions for voltage-controlled oscillators (VCO)
in a dual-PLL frequency synthesizer system. A main channel is provided for RF frequencies and an auxiliary
channel for IF frequencies. The current-output charge pumps directly drive passive RC filter networks, to
generate VCO control voltages. Fast main-channel frequency switching is achieved with a charge pump
arrangement that increases the current drive and alters the loop-filter frequency response during a portion of
the switching interval.
The speed-up mode is controlled by the serial interface strobe signal, which goes high when a new frequency
is loaded. At this time, the internal speed-up timer is activated and it enables the speed-up mode into the
speed-up timer for the preprogrammed duration. During speed-up mode, the charge pump current to the
external loop filter can be changed in two ways. First, the main charge pump current can be increased. Second,
an additional integral charge pump can be separately and directly connected to the external loop-filter capacitor
to further decrease the loop-filter charge and discharge times.
Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device placed in conductive
foam during storage or handling to prevent electrostatic damage to the MOS gates.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TRF2052
LOW-VOLTAGE 2-GHz SYNTHESIZER
SLWS066 – JULY 1998
functional block diagram
2
1
DATA
Serial Control Shift Register
CLOCK
STROBE
NENM
Band Gap
and Bias
3
19
17
Control and Selection
Internal Control Register
NENA
G
Speed-Up
Counter
8
2
CL
CN
MCP
Main
Charge Pump
14
16
N
5
6
PHP
RN
RFINP
RFINN
Main Phase
Detector
18
12
8
Main Divider
1/–1
CK
Intergral
Charge Pump
4
SM
13
SELECT
M
2
PHI
Reference
Divider
8
REFIN
AUXIN
1 2 4 8
SA
2
SELECT
Lock
Detector
18
9
LOCK
PA
ACP
1/–1
NA
Auxiliary
Charge Pump 11
RA
Auxiliary
4/1
Auxiliary
Phase Detector
10
12
Divider
PHA
Terminal Functions
TERMINAL
NAME
AUXIN
DESCRIPTION
NO.
10
1
Auxiliary channel RF input
Serial interface clock signal
Serial interface data signal
Lock detector output
CLOCK
DATA
LOCK
NENA
NENM
PHA
2
18
17
19
11
13
14
9
Enable signal for the auxiliary channel/main channel/open loop. See modes of operation logic table. Active low
Enable signal for the auxiliary channel/main channel/open loop. See modes of operation logic table. Active low
Auxiliary charge pump output
PHI
Integral charge pump output
PHP
Main (proportional) charge pump output
Resistor to VSSA sets auxiliary charge pump current
Reference frequency input signal
Prescaler negative RF input
RA
REFIN
RFINN
RFINP
RN
8
6
5
Prescaler positive RF input
16
3
Resistor to VSSA sets main charge pump current
Serial interface load signal
STROBE
VCCP
VDD
7
Prescaler positive supply voltage
Digital supply voltage
20
15
4
VDDA
VSS
Analog supply voltage
Digital/prescaler ground
VSSA
12
Analog ground
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TRF2052
LOW-VOLTAGE 2-GHz SYNTHESIZER
SLWS066 – JULY 1998
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range (See Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 to 4.7 Vdc
Input voltage, logic signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 to 4.7 Vdc
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
ESD protection, all pins, human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
NOTE 1: Voltage values are with respect to VSSA.
recommended operating conditions
MIN
2.7
MAX
3.3
UNIT
V
Supply voltage, VCCP, VDD, VDDA
Operating free-air temperature, T
–10
55
°C
A
dc electrical characteristics over full range of operating conditions,
typical values are at VCCP = VDD = VDDA = 3 V, T = 25°C (unless otherwise noted)
A
supply current
PARAMETER
TEST CONDITIONS
EM = EA = 1 ES = 0
|I
MIN
TYP
MAX
UNIT
Average operational supply current (see Note 2)
NOTE 2: Charge pump output current not included.
|I
|I
| = 1 mA
PHA
| = 0.5 mA
11.4
mA
PHP N
| | = 0 mA
IPHI
| = 2.5 mA
PHP S
digital interface
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
UNIT
V
V
V
V
High-level output voltage (LOCK)
Low-level output voltage (LOCK)
I
I
I
I
= 1 mA
V
V
– 0.5
V
V
V
V
OH
OL
IH
OH
CC
= –1 mA
OL
High-level input voltage (DATA, CLOCK, STROBE, NENA, NENM)
Low-level input voltage (DATA, CLOCK, STROBE, NENA, NENM)
= 10 µA
= 10 µA
– 0.5
IH
IL
CC
0.5
IL
ac electrical characteristics over full range of operating conditions,
typical values are at VCCP = VDD = VDDA = 3 V, T = 25°C (unless otherwise noted)
A
PARAMETER
TEST CONDITIONS
MIN
0.1
TYP
MAX
2.0
UNIT
GHz
dBm
MHz
RF input frequency
Differential RF input voltage
Reference input frequency
Reference input voltage
Auxiliary input frequency
Auxiliary input voltage
–16
–3
13.8
0.3
0.2
V
pp
MHz
(see Note 3)
150
V
pp
NOTE 3: Used with predivider (1/4)
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TRF2052
LOW-VOLTAGE 2-GHz SYNTHESIZER
SLWS066 – JULY 1998
charge pump output currents
The steepness of the phase detector charge-pump chains is determined by external resistors between the
dedicated pins RA and RN and ground, as well as by user programmable variables. The charts that follow
indicate how the charge-pump peak currents can be set by the external resistors and the control variables.
auxiliary charge pump
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
|I
|I
|
|
Open loop mode (NENA = 1)
0
V
V
DDA
10
pA
PHA
PHA
0.5 V
R
V
V
DDA
– 0.5 V,
PHA
= 18 kΩ
Closed loop mode (NENA = 0)
20 × 1.25/R [kΩ]
mA
PHA
A
A
main charge pump
PARAMETER
Normal mode
Speed-up mode (see Note 4)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mA
18.75/(R [kΩ] + 0.75) ×
N
|I
|I
|
PHM_N
0.5 V
V
V
DDA
– 0.5 V,
PHP
= 18 kΩ
CN/256
R
N
CL + 1
|
|I
| × (1 + 2
PHM_N
)
mA
PHM_S
4. The maximum allowable current is 12 mA. It is recommended to use the speedup mode only before the PLL is locked. Switching
between speedup and normal modes as well as changing the current setting factor CN, under PLL operation, may cause
disturbances in the VCO control voltage.
integral charge pump
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
|I
|I
|
Normal mode
0
V
V
DDA
0
mA
PHI_N
PHI
0.5 V
R
V
V
DDA
– 0.5 V,
PHI
= 18 kΩ,
CL + 1
|I | × 2
PHM_N
|
Speed-up mode (see Note 5)
× CK
mA
PHI_S
N
|I
|
16 mA
PHM_S
5. Maximum allowable current is 24 mA
The instantaneous values of the charge pump currents are related to the phase error by:
error
2
I
I
PH_inst
PH_peak
(1)
†
modes of operation
CHIP MODE
NENM
NENA
ACTIVE STAGES
Both synthesizers on
Main synthesizers on
Auxiliary synthesizer on
Shutdown
0
0
1
1
0
1
0
1
Everything on
Only auxiliary charge pump set to triple state; everything else working
Main loop disabled, auxiliary loop working
All off
†
Enable signals, NENM and NENA, are active low.
timing requirements, serial data interface (see Figure 1)
PARAMETER
MIN
MAX
UNIT
MHz
ns
f
t
t
t
t
t
t
t
Clock frequency
10
(CLOCK)
Clock high-time pulse width, Clock high
Clock low-time pulse width, Clock low
Set-up time, data valid before CLOCK↑
Hold time, data valid after CLOCK↑
Set-up time, STROBE↑ before CLOCK↑
STROBE high-time pulse width, STROBE high
STROBE low-time pulse width, STROBE low
30
30
30
30
30
30
30
w(CLKHI)
w(CLKLO)
su(D)
ns
ns
ns
h(D)
ns
su(STROBE)
w(STROBEHI)
w(STROBELO)
ns
ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TRF2052
LOW-VOLTAGE 2-GHz SYNTHESIZER
SLWS066 – JULY 1998
PARAMETER MEASUREMENT INFORMATION
DATA
t
h(D)
t
su(D)
t
w(CLKH)
CLOCK
f(CLOCK)
t
su(STROBE)
t
w(CLKLO)
STROBE
t
w(STROBEHI)
t
w(STROBELO)
Figure 1. Serial-Data Interface Timing
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TRF2052
LOW-VOLTAGE 2-GHz SYNTHESIZER
SLWS066 – JULY 1998
PRINCIPLES OF OPERATION
serial control
TheTRF2052internalregisterscontainalltheuserprogrammablevariablessuchasdividerratios, chargepump
settings, etc. They are programmed using a three-wire (CLOCK, DATA, STROBE) serial interface.
At every rising slope of the CLOCK signal, the actual logical value on the DATA pin is written into a 24-bit shift
register. A rising slope on the STROBE pin causes the actual content of the shift register to be input as a control
word.
The control word is, therefore, 24-bits long and the first incoming bit functions as the least significant bit (LSB),
bit 0. If the most significant bit (MSB), bit 23, is 1, the word functions as control word A. If the MSB is 0, bits 20
to 22 become address bits, which label the words as control word B through E, respectively. To fully program
the synthesizer, four words must be sent: A, B, C, and D. Word E is for test purposes only.
The position of the individual variables within the control words is illustrated in Figure 2. Table 1 briefly describes
their functions. The G parameter, which specifies the duration of the speed-up mode in reference divider cycles,
splits into most significant (G2) and least significant (G1) nibbles.
MSB
LSB
Last In
First In
A
B
nc
0
G1
N
23 22 21 20 1918 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
M A
1
0
0
0
G2
CN
CK
CL
C
P
C
P
P
A
1
1
0
0
0
1
1
0
NA
nc
C
D
E
M
E
A S
E
P
M
NR
SM
SA
1
1
1
1
E
TST<10:0>
nc
Figure 2. Serial Word Format
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TRF2052
LOW-VOLTAGE 2-GHz SYNTHESIZER
SLWS066 – JULY 1998
PRINCIPLES OF OPERATION
Table 1. Function Table
SYMBOL
BITS
18
8
FUNCTION
N
Overall main divider integer division ratio
CN
G2
Binary current setting factor for main charge pumps
MS bits for the speed-up mode duration (number of reference divider cycles)
LS bits for the speed-up mode duration (number of reference divider cycles)
Binary acceleration factor for integral charge pump current
Binary acceleration factor for increase in main charge pump current during speed-up mode
Main charge pump polarity
4
G1
4
CK
CL
4
2
MCP
ACP
NA
PA
1
1
Auxiliary charge pump polarity
12
1
Auxiliary divider ratio
Auxiliary prescaler select:
0 = divide by 4
1 = divide by 1
NR
SM
EM
SA
EA
ES
12
2
Reference divider ratio
Reference select for main phase detector
Main divider enable flag
1
2
Reference select for auxiliary phase detector
Auxiliary divider enable flag
1
1
Speed-up mode standby control:
0 = speed-up charge pump switches off completely if no fast mode
1 = speed-up charge pump always in standby
PM
1
Phase detector mode. Change between two modes for reset pulse generation:
0 = analog internal generated delay
1 = high-pulse duration for REF-CLOCK
RF inputs
The differential main divider input has a resistance of several k and can be matched to the system impedance
by an external resistor. To form a single ended input, any one of the input pins can be grounded by a blocking
capacitor.
The auxiliary channel RF and reference inputs have a high resistance, as well, and are single ended. If needed,
matching can be accomplished with an external resistor.
enabling the PLLs
Both PLLs can be enabled and disabled independently, either by the serial control variables EM and EA or by
the digital inputs pins NENM and NENA.
The serial control variables and the hardware signal NENM disable the charge pump and the divider of the
corresponding loop, while NENA affects the auxiliary charge pump output only. This helps to avoid spikes that
might occur after re–enabling the auxiliary loop by the serial interface.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TRF2052
LOW-VOLTAGE 2-GHz SYNTHESIZER
SLWS066 – JULY 1998
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,30
0,19
0,65
M
0,10
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
0,75
A
0,50
Seating Plane
0,10
1,20 MAX
0,05 MIN
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/E 08/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明