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TRF371109IRGZR

更新时间：2024-09-18 12:31:23
品牌：TI
描述：Direct Downconversion Receiver

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TRF371109IRGZR 概述

Direct Downconversion Receiver 直接下变频接收机

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TRF371109  
www.ti.com  
SLWS225B –DECEMBER 2010–REVISED MAY 2011  
Direct Downconversion Receiver  
Check for Samples: TRF371109  
1
FEATURES  
DESCRIPTION  
The TRF371109 is a highly linear direct-conversion  
quadrature receiver. The TRF371109 integrates  
balanced I and Q mixers, LO buffers, and phase  
splitters to convert an RF signal directly to I and Q  
baseband. The on-chip programmable gain amplifiers  
allow adjustment of the output signal level without the  
need for external variable gain (attenuator) devices.  
The TRF371109 integrates programmable baseband  
low-pass filters that attenuate nearby interference,  
eliminating the need for an external baseband filter.  
2
•
Frequency Range: 300 MHz to 1700 MHz  
•
Integrated Baseband Programmable Gain  
Amplifier  
•
•
•
•
•
•
•
On-Chip Programmable Baseband Filter  
High Cascaded IP3: 27 dBm at 900 MHz  
High IP2: 68 dBm at 900 MHz  
Hardware and Software Power Down  
Three-Wire Serial Interface  
Single Supply: 4.5-V to 5.5-V Operation  
Silicon Germanium Technology  
Housed in a 7-mm × 7-mm VQFN package, the  
TRF371109 provides the smallest and most  
integrated  
receiver  
solution  
available  
for  
high-performance equipment.  
APPLICATIONS  
•
•
•
Multicarrier Wireless Infrastructure  
WiMAX  
High-Linearity Direct-Downconversion  
Receiver  
•
LTE (Long Term Evolution)  
To Microcontroller  
To Microcontroller  
48 47 46 45 44 43 42 41 40 39 38 37  
GNDDIG  
VCCDIG  
CHIP_EN  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VCCBBI  
GND  
2
BBIOUTP  
BBIOUTN  
3
To ADC I  
VCCMIX1  
GND  
4
5
GND  
LOIP  
LOIN  
RFIN  
MIXINP  
MIXINN  
LOIN  
6
TRF371109  
7
GND  
VCCMIX2  
NC  
8
VCCLO  
BBQOUTP  
BBQOUTN  
9
To ADC Q  
10  
11  
12  
NC  
GND  
GND  
VCCBBQ  
13 14 15 16 17 18 19 20 21 22 23 24  
30 kW  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2010–2011, Texas Instruments Incorporated  
TRF371109  
SLWS225B –DECEMBER 2010–REVISED MAY 2011  
www.ti.com  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
AVAILABLE DEVICE OPTIONS(1)  
SPECIFIED  
TEMPERATURE  
RANGE  
PACKAGE-  
LEAD  
PACKAGE  
DESIGNATOR  
PACKAGE  
MARKING  
ORDERING  
NUMBER  
TRANSPORT  
MEDIA, QUANTITY  
PRODUCT  
TRF371109IRGZR  
TRF371109IRGZT  
Tape and Reel, 2500  
Tape and Reel, 250  
TRF371109  
VQFN-48  
RGZ  
–40°C to +85°C  
TRF371109IRGZ  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the  
device product folder at www.ti.com.  
space  
FUNCTIONAL DIAGRAM  
ADC Driver  
33  
BBIOUTP  
BBIOUTN  
VCC  
PGA  
34  
GND  
24  
VCM  
DC Offset Control I  
30  
31  
LOIN  
LOIP  
0°  
6
7
90°  
MIXINP  
MIXINN  
DC Offset Control Q  
27  
28  
BBQOUTN  
BBQOUTP  
PGA  
ADC Driver  
3
48  
47  
46  
37  
Power  
Down  
CHIP_EN  
CLOCK  
DC Offset Control  
LPFADJ Control  
PGA Control  
DATA  
SPI  
STROBE  
READBACK  
2
Copyright © 2010–2011, Texas Instruments Incorporated  
TRF371109  
www.ti.com  
SLWS225B –DECEMBER 2010–REVISED MAY 2011  
ABSOLUTE MAXIMUM RATINGS  
Over operating free-air temperature range (unless otherwise noted).(1)  
VALUE  
–0.3 to 5.5  
UNIT  
V
Supply voltage range(2)  
Digital I/O voltage range  
–0.3 to VCC +0.5  
–40 to +150  
–40 to +85  
V
Operating virtual junction temperature range, TJ  
Operating ambient temperature range, TA  
Storage temperature range, Tstg  
°C  
°C  
°C  
–65 to +150  
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltage values are with respect to network ground terminal.  
RECOMMENDED OPERATING CONDITIONS  
Over operating free-air temperature range (unless otherwise noted).  
MIN NOM  
MAX  
5.5  
UNIT  
V
VCC  
Power-supply voltage  
4.5  
5.0  
Power-supply voltage ripple  
940  
µVPP  
°C  
TA  
TJ  
Operating free-air temperature range  
Operating virtual junction temperature range  
–40  
–40  
+85  
+150  
°C  
THERMAL CHARACTERISTICS  
Over recommended operating free-air temperature range (unless otherwise noted).  
PARAMETER(1)  
TEST CONDITIONS  
Soldered slug, no airflow  
MIN  
TYP  
26  
MAX  
UNIT  
°C/W  
°C/W  
RθJA  
Soldered slug, 200-LFM airflow  
Soldered slug, 400-LFM airflow  
7-mm × 7-mm, 48-pin PDFP  
7-mm × 7-mm 48-pin PDFP  
20.1  
17.4  
25  
Thermal resistance, junction-to-ambient  
Thermal resistance, junction-to-board  
(2)  
RθJA  
RθJB  
12  
(1) Determined using JEDEC standard JESD-51 with high-K board  
(2) 16 layers, high-K board  
THERMAL INFORMATION  
TRF371109  
RGZ  
48 PINS  
26.9  
THERMAL METRIC(1)  
UNITS  
θJA  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
θJCtop  
θJB  
11.2  
3.4  
°C/W  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
0.2  
ψJB  
3.4  
θJCbot  
0.6  
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.  
Copyright © 2010–2011, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Link(s): TRF371109  
TRF371109  
SLWS225B –DECEMBER 2010–REVISED MAY 2011  
www.ti.com  
ELECTRICAL CHARACTERISTICS  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C,unless otherwise noted.  
PARAMETERS  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
DC PARAMETERS  
ICC  
Total supply current  
Power-down current  
360  
2
mA  
mA  
IQ DEMODULATOR AND BASEBAND SECTION  
fRF  
Frequency range  
Gain range  
300  
22  
1700  
MHz  
dB  
24  
1
Gain step  
See(1)  
dB  
PinMax  
OIP3  
Maximum RF power input  
Before damage  
Gain setting = 24(2)  
One tone(3)  
25  
30  
3
dBm  
dBVRMS  
dBVRMS  
P1dBMin  
Minimum baseband low-pass filter  
(LPF) cutoff frequency  
fMin  
1-dB point(4)  
3-dB point(4)  
3-dB point(5)  
700  
kHz  
MHz  
MHz  
Maximum baseband LPF cutoff  
frequency  
fMax  
15  
Baseband LPF cutoff frequency in  
bypass mode  
fBypass  
30  
1 × fC  
1.5 × fC  
2 × fC  
3 × fC  
4 × fC  
5 × fC  
1
8
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
kΩ  
pF  
32  
54  
75  
90  
–40  
3
Baseband relative attenuation at  
LPF cutoff frequency (fC)(6)  
Fsel  
Image suppression  
Output BB attenuator  
Parallel resistance  
Parallel capacitance  
1
Output load impedance(7)  
Output, common-mode  
Baseband harmonic level  
20  
Measured at I- and Q-channel baseband  
outputs  
Second harmonic(8)  
Third harmonic(8)  
VCM  
1.5  
V
–100  
–93  
dBc  
dBc  
LOCAL OSCILLATOR PARAMETERS  
Local oscillator frequency  
LO input level  
300  
1700  
6
MHz  
dBm  
dBm  
(9)  
See  
–3  
0
LO leakage  
At MIXINN/MIXINP at 0-dBm LO drive level  
–58  
DIGITAL INTERFACE  
VIH  
VIL  
High-level input voltage  
Low-level input voltage  
High-level output voltage  
Low-level output voltage  
0.6 × VCC  
0
5
VCC  
0.8  
V
V
V
V
VOH  
VOL  
0.8 × VCC  
0.2 × VCC  
(1) Two consecutive gain settings.  
(2) Two CW tones at an offset from LO frequency smaller than the baseband-filter cutoff frequency. Performance is set by baseband  
circuitry regardless of LO frequency.  
(3) Single CW tone at an offset from LO frequency smaller than the baseband-filter cutoff frequency. Performance is set by baseband  
circuitry regardless of LO frequency.  
(4) Baseband low-pass filter cutoff frequency is programmable through SPI register LPFADJ. LPFADJ = 0 corresponds to max bandwidth;  
LPFADJ = 255 corresponds to minimum BW.  
(5) Filter Ctrl setting equal to 0.  
(6) Attenuation relative to passband gain.  
(7) The typical value for this parameter is the load impedance that the device is able to drive.  
(8) LO frequency set to 900 MHz. Power-in set to –40 dBm. Gain setting at 24. DC offset calibration engaged. Input signal set at 2.5-MHz  
offset.  
(9) LO power outside of this range is possible but may introduce degraded performance.  
4
Submit Documentation Feedback  
Copyright © 2010–2011, Texas Instruments Incorporated  
Product Folder Link(s): TRF371109  
TRF371109  
www.ti.com  
SLWS225B –DECEMBER 2010–REVISED MAY 2011  
ELECTRICAL CHARACTERISTICS (continued)  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C,unless otherwise noted.  
PARAMETERS  
fLO = 300 MHz(10)  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
GMax  
NF  
Maximum gain(11)  
Gain setting = 24  
48.7  
8.7  
dB  
dB  
Noise figure  
Gain setting = 24  
IIP3  
Third-order input intercept point  
Gain setting = 24(12)(13)  
Gain setting = 24(13)(14)  
13.9  
45  
dBm  
dBm  
IIP2  
Second-order input intercept point  
fLO = 700 MHz(10)  
GMax  
NF  
Maximum gain(11)  
Gain setting = 24  
43  
10.7  
25  
dB  
dB  
Noise figure  
Gain setting = 24  
IIP3  
Third-order input intercept point  
Gain setting = 24(12)(13)  
Gain setting = 24(13)(14)  
dBm  
dBm  
IIP2  
Second-order input intercept point  
70  
fLO = 900 MHz(10)  
GMax  
Maximum gain(11)  
Gain setting = 24  
41  
12.4  
14.8  
27  
dB  
dB  
Gain setting = 24  
NF  
Noise figure  
Gain setting = 16  
dB  
IIP3  
IIP2  
Third-order input intercept point  
Second-order input intercept point  
Gain setting = 24(12)(13)  
Gain setting = 24(13)(14)  
dBm  
dBm  
68  
fLO = 1425 MHz(10)  
GMax  
NF  
Maximum gain(11)  
Gain setting = 24  
36.9  
15.5  
27  
dB  
dB  
Noise figure  
Gain setting = 24  
IIP3  
Third-order input intercept point  
Gain setting = 24(12)(13)  
Gain setting = 24(13)(14)  
dBm  
dBm  
IIP2  
Second-order input intercept point  
65  
fLO = 1700 MHz(10)  
GMax  
NF  
Maximum gain(11)  
Gain setting = 24  
35.9  
17.5  
25.5  
60  
dB  
dB  
Noise figure  
Gain setting = 24  
IIP3  
IIP2  
Third-order input intercept point  
Second-order input intercept point  
Gain setting = 24(12)(13)  
Gain setting = 24(13)(14)  
dBm  
dBm  
(10) For broadband frequency sweeps, the Picosecond balun (model #5310A) is used at the RF and LO input. For frequency bands between  
600 MHz and 1250 MHz, the Murata balun LDB21897M005C-001 is used. Performance parameters adjusted for balun insertion loss.  
Recommended baluns for respective frequency band are listed:  
700 MHz and 900 MHz: Murata LDB21897M005C-001 (or equivalent)  
1740 MHz: Murata LDB211G8005C-001 (or equivalent)  
1950 MHz: Murata LDB211G9005C-001 (or equivalent)  
2025 MHz: Murata LDB211G9005C-001 (or equivalent)  
2500 MHz: Murata LDB212G4005C-001 (or equivalent)  
3500 MHz: Johanson 3600BL14M050E (or equivalent)  
(11) Gain defined as voltage gain from MIXIN (VRMS) to either baseband output: BBI/QOUT (VRMS  
)
(12) Two CW tones of –30 dBm at fRF1 = fLO ±(2 ● fc) and fRF2= fLO ±[(4 ● fc) + 100 kHz]; fc = Baseband filter 1-dB cutoff frequency.  
(13) Because the two-tone interference sources are outside of the baseband filter bandwidth, the results are inherently independent of the  
gain setting. Intermodulation parameters are recorded at maximum gain setting, where measurement accuracy is best.  
(14) Two CW tones at –30 dBm at fRF1 = fLO ±(2 ● fc) and fRF2= fLO ±[(2 ● fc) + 100 kHz]; IM2 product measured at 100-kHz output  
frequency. fC = Baseband filter 1-dB cutoff frequency.  
Copyright © 2010–2011, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Link(s): TRF371109  
TRF371109  
SLWS225B –DECEMBER 2010–REVISED MAY 2011  
www.ti.com  
TIMING REQUIREMENTS  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C (unless otherwise noted).  
PARAMETER  
TEST CONDITIONS  
MIN  
50  
TYP MAX  
UNIT  
ns  
t(CLK)  
tSU1  
tH  
Clock period  
Setup time, data  
10  
ns  
Hold time, data  
10  
ns  
tW  
Pulse width, STROBE  
Setup time, STROBE  
20  
ns  
tSU2  
10  
ns  
DEVICE INFORMATION  
PIN ASSIGNMENTS  
space  
RGZ PACKAGE  
VQFN-48  
(TOP VIEW)  
48 47 46 45 44 43 42 41 40 39 38 37  
GNDDIG  
VCCDIG  
CHIP_EN  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VCCBBI  
2
GND  
BBIOUTP  
BBIOUTN  
3
VCCMIX1  
GND  
4
5
GND  
LOIP  
LOIN  
MIXINP  
MIXINN  
6
7
GND  
VCCMIX2  
NC  
8
VCCLO  
BBQOUTP  
BBQOUTN  
9
10  
11  
12  
NC  
GND  
GND  
VCCBBQ  
13 14 15 16 17 18 19 20 21 22 23 24  
6
Submit Documentation Feedback  
Copyright © 2010–2011, Texas Instruments Incorporated  
Product Folder Link(s): TRF371109  
TRF371109  
www.ti.com  
SLWS225B –DECEMBER 2010–REVISED MAY 2011  
PIN FUNCTIONS  
PIN  
I/O  
DESCRIPTION  
NO.  
1
NAME  
GNDDIG  
VCCDIG  
CHIP_EN  
VCCMIX1  
GND  
Digital ground  
Digital power supply  
Chip enable  
2
3
I
4
Mixer power supply  
Ground  
5
6
MIXINP  
MIXINN  
GND  
I
I
Mixer input: positive terminal  
Mixer input: negative terminal  
Ground  
7
8
9
VCCMIX2  
NC  
Mixer power supply  
No connect  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
NC  
No connect  
GND  
Ground  
GND  
Ground  
GND  
Ground  
GND  
Ground  
MIXQOUTP  
MIXQOUTN  
NC  
O
O
Mixer Q output: positive terminal (test pin)  
Mixer Q output: negative terminal (test pin)  
No connect  
NC  
No connect  
REXT  
O
Reference bias external resistor  
Bias block power supply  
Bias block ground  
No connect  
VCCBIAS  
GNDBIAS  
NC  
VCM  
I
Baseband input common-mode voltage  
Baseband Q chain power supply  
Ground  
VCCBBQ  
GND  
BBQOUTN  
BBQOUTP  
VCCLO  
LOIN  
O
O
Baseband Q (in quadrature) output: negative terminal  
Baseband Q (in quadrature) output: positive terminal  
Local oscillator power supply  
Local oscillator input: negative terminal  
Local oscillator input: positive terminal  
Ground  
I
I
LOIP  
GND  
BBIOUTN  
BBIOUTP  
GND  
O
O
Baseband I (in-phase) output: positive terminal  
Baseband I (in-phase) output: negative terminal  
Ground  
VCCBBI  
NC  
Baseband I (in phase) power supply  
No connect  
READBACK  
Gain_B2  
Gain_B1  
Gain_B0  
NC  
O
I
SPI readback data  
PGA fast gain control bit 2  
PGA fast gain control bit 1  
PGA fast gain control bit 0  
No connect  
I
I
NC  
No connect  
MIXIOUTN  
MIXIOUTP  
STROBE  
DATA  
O
O
I
Mixer I output: negative terminal  
Mixer I output: positive terminal  
SPI enable  
I
SPI data input  
CLOCK  
I
SPI clock input  
Copyright © 2010–2011, Texas Instruments Incorporated  
Submit Documentation Feedback  
7
Product Folder Link(s): TRF371109  
TRF371109  
SLWS225B –DECEMBER 2010–REVISED MAY 2011  
www.ti.com  
TYPICAL CHARACTERISTICS  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
Table of Graphs  
Gain  
vs LO frequency(1)(2)(3)  
vs LO frequency(1)(2)(3)  
vs LO frequency(4)(5)(6)  
vs LO frequency(4)(5)(6)  
vs LO frequency  
Figure 1, Figure 2, Figure 3  
Figure 4, Figure 5, Figure 6  
Figure 7, Figure 9, Figure 8  
Figure 10, Figure 12, Figure 11  
Figure 13, Figure 14, Figure 15  
Figure 16, Figure 17, Figure 18, Figure 19  
Figure 20, Figure 21, Figure 22, Figure 23  
Figure 24, Figure 25, Figure 26  
Figure 27, Figure 28, Figure 29, Figure 30  
Figure 31  
Noise figure  
IIP3  
IIP2  
Gain  
IIP3  
vs LO frequency(5)(6)  
vs LO frequency(5)(6)  
vs LO frequency(3)  
vs Frequency offset(7)(3)  
vs BB gain setting(8)  
IIP2  
Noise figure  
OIP3  
Noise figure  
Gain  
vs BB gain setting(8)  
Figure 32  
Gain  
vs Frequency offset(9)  
vs Frequency offset (bypass mode)(9)  
vs LPFADJ setting  
vs Frequency offset(10)  
vs BB frequency offset  
vs Temperature(11)  
Figure 33, Figure 34  
Gain  
Figure 35, Figure 36  
1-dB LPF corner frequency  
Relative LPF group delay  
Image rejection  
DC offset limit  
Out-of-band P1dB  
Figure 37  
Figure 38  
Figure 39  
Figure 40  
vs Relative offset multiplier to corner frequency(12)  
Figure 41  
(1) Measured with broadband Picosecond 5310A balun on the LO input and single ended connection on the RF input. Performance gain  
adjusted for the 3-dB differential to single-ended insertion loss.  
(2) Performance ripple because of impedance mismatch on the RF input.  
(3) Measured with the maximum baseband gain (BB gain) setting, unless otherwise noted.  
(4) Measured with broadband Picosecond 5310A balun on the LO input and RF input. Balun insertion loss is compensated for in the  
measurement.  
(5) Out-of-band intercept point is defined with tones that are at least two times farther out than the programmed LPF corner frequency that  
generate an intermodulation tone that falls inside the LPF passband.  
(6) Out-of-band intercept point depends on the demodulator performance and not the baseband circuitry; the measurement is taken at max  
gain but is valid across all PGA settings.  
(7) Measured with filter in bypass mode to characterize the passband circuitry across baseband frequencies.  
(8) Data taken with LO frequency = 900 MHz.  
(9) Normalized gain.  
(10) Relative to the low frequency offset group delay in bypass mode.  
(11) Idet set to 50 µA; RF signal is off; LO at 2.4 GHz at 0 dBm; Det filter set to 1 kHz; Clk Div set to 1024.  
(12) In-band tone set to 1 MHz; out-of-band jammer tone set to specified relative offset ratio from the programmed corner frequency. Jammer  
tone is increased until in-band tone compresses 1 dB.  
8
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Copyright © 2010–2011, Texas Instruments Incorporated  
Product Folder Link(s): TRF371109  
TRF371109  
www.ti.com  
SLWS225B –DECEMBER 2010–REVISED MAY 2011  
TYPICAL CHARACTERISTICS  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
GAIN vs LO FREQUENCY  
GAIN vs LO FREQUENCY  
52  
50  
48  
46  
44  
42  
40  
38  
36  
34  
32  
52  
50  
48  
46  
44  
42  
40  
38  
36  
34  
32  
TA = -40°C  
TA = -10°C  
TA = +25°C  
TA = +85°C  
VCC = 4.5 V  
VCC = 5 V  
VCC = 5.5 V  
See Notes (1) and (2)  
200 400 600  
See Notes (1) and (2)  
200 400 600  
800 1000 1200 1400 1600 1800  
LO Frequency (MHz)  
800 1000 1200 1400 1600 1800  
LO Frequency (MHz)  
Figure 1.  
Figure 2.  
GAIN vs LO FREQUENCY  
NOISE FIGURE vs LO FREQUENCY  
20  
18  
16  
14  
12  
10  
8
52  
50  
48  
46  
44  
42  
40  
38  
36  
34  
32  
TA = -40°C  
TA = -10°C  
TA = +25°C  
TA = +85°C  
LO Pwr = -3 dBm  
LO Pwr = 0 dBm  
LO Pwr = 3 dBm  
LO Pwr = 6 dBm  
See Notes (1) and (2)  
200 400 600  
See Notes (1) and (2)  
6
800 1000 1200 1400 1600 1800  
LO Frequency (Hz)  
200  
400  
600  
800 1000 1200 1400 1600 1800  
LO Frequency (MHz)  
Figure 3.  
Figure 4.  
NOISE FIGURE vs LO FREQUENCY  
NOISE FIGURE vs LO FREQUENCY  
20  
18  
16  
14  
12  
10  
8
20  
18  
16  
14  
12  
10  
8
VCC = 4.5 V  
VCC = 5 V  
VCC = 5.5 V  
LO Pwr = -3 dBm  
LO Pwr = 0 dBm  
LO Pwr = 3 dBm  
LO Pwr = 6 dBm  
See Notes (1) and (2)  
800 1000 1200 1400 1600 1800  
See Notes (1) and (2)  
200 400 600  
6
6
200  
400  
600  
800 1000 1200 1400 1600 1800  
LO Frequency (Hz)  
LO Frequency (Hz)  
Figure 5.  
Figure 6.  
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TYPICAL CHARACTERISTICS (continued)  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
IIP3 vs LO FREQUENCY  
I
36  
TA = -40°C  
34  
TA = -10°C  
32  
TA = +25°C  
TA = +85°C  
30  
28  
26  
24  
22  
20  
18  
16  
14  
12  
10  
200  
400  
600  
800 1000 1200 1400 1600 1800  
LO Frequency (Hz)  
Q
36  
34  
32  
30  
28  
26  
24  
22  
20  
18  
16  
14  
12  
10  
TA = -40°C  
TA = -10°C  
TA = +25°C  
TA = +85°C  
See Notes (3), (4) and (5)  
200  
400  
600  
800 1000 1200 1400 1600 1800  
LO Frequency (Hz)  
Figure 7.  
10  
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TYPICAL CHARACTERISTICS (continued)  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
IIP3 vs LO FREQUENCY  
I
36  
34  
32  
30  
28  
26  
24  
22  
20  
18  
LO Pwr = -3 dBm  
16  
LO Pwr = 0 dBm  
LO Pwr = 3 dBm  
LO Pwr = 6 dBm  
14  
12  
10  
200  
400  
600  
800 1000 1200 1400 1600 1800  
LO Frequency (Hz)  
Q
36  
34  
32  
30  
28  
26  
24  
22  
20  
18  
16  
14  
12  
10  
LO Pwr = -3 dBm  
LO Pwr = 0 dBm  
LO Pwr = 3 dBm  
LO Pwr = 6 dBm  
See Notes (3), (4) and (5)  
200  
400  
600  
800 1000 1200 1400 1600 1800  
LO Frequency (Hz)  
Figure 8.  
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TYPICAL CHARACTERISTICS (continued)  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
IIP3 vs LO FREQUENCY  
I
36  
VCC = 4.5 V  
VCC = 5 V  
VCC = 5.5 V  
34  
32  
30  
28  
26  
24  
22  
20  
18  
16  
14  
12  
10  
200  
400  
600  
800 1000 1200 1400 1600 1800  
LO Frequency (Hz)  
Q
36  
34  
32  
30  
28  
26  
24  
22  
20  
18  
16  
14  
12  
10  
VCC = 4.5 V  
VCC = 5 V  
VCC = 5.5 V  
See Notes (3), (4) and (5)  
200  
400  
600  
800 1000 1200 1400 1600 1800  
LO Frequency (Hz)  
Figure 9.  
12  
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TYPICAL CHARACTERISTICS (continued)  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
IIP2 vs LO FREQUENCY  
I
100  
TA = -40°C  
TA = -10°C  
TA = +25°C  
TA = +85°C  
90  
80  
70  
60  
50  
40  
30  
200  
400  
600  
800 1000 1200 1400 1600 1800  
LO Frequency (Hz)  
Q
100  
90  
80  
70  
60  
50  
40  
30  
TA = -40°C  
TA = -10°C  
TA = +25°C  
TA = +85°C  
See Notes (3), (4) and (5)  
200  
400  
600  
800 1000 1200 1400 1600 1800  
LO Frequency (Hz)  
Figure 10.  
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TYPICAL CHARACTERISTICS (continued)  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
IIP2 vs LO FREQUENCY  
I
100  
LO Pwr = -3 dBm  
LO Pwr = 0 dBm  
LO Pwr = 3 dBm  
90  
LO Pwr = 6 dBm  
80  
70  
60  
50  
40  
30  
200  
400  
600  
800 1000 1200 1400 1600 1800  
LO Frequency (Hz)  
Q
100  
90  
80  
70  
60  
50  
40  
30  
LO Pwr = -3 dBm  
LO Pwr = 0 dBm  
LO Pwr = 3 dBm  
LO Pwr = 6 dBm  
See Notes (3), (4) and (5)  
200  
400  
600  
800 1000 1200 1400 1600 1800  
LO Frequency (Hz)  
Figure 11.  
14  
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TYPICAL CHARACTERISTICS (continued)  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
IIP2 vs LO FREQUENCY  
I
100  
90  
80  
70  
60  
50  
VCC = 4.5 V  
VCC = 5 V  
40  
30  
VCC = 5.5 V  
600  
700  
800  
900  
1000  
1100  
1200  
LO Frequency (MHz)  
Q
100  
90  
80  
70  
60  
50  
40  
30  
VCC = 4.5 V  
VCC = 5 V  
VCC = 5.5 V  
See Notes (4) and (5)  
1000 1100 1200  
600  
700  
800  
900  
LO Frequency (MHz)  
Figure 12.  
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TYPICAL CHARACTERISTICS (continued)  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
GAIN vs LO FREQUENCY  
GAIN vs LO FREQUENCY  
52  
50  
48  
46  
44  
42  
40  
38  
36  
34  
32  
52  
50  
48  
46  
44  
42  
40  
38  
36  
34  
32  
TA = -40°C  
TA = -10°C  
TA = +25°C  
TA = +85°C  
VCC = 4.5 V  
VCC = 5 V  
VCC = 5.5 V  
600  
700  
800  
900  
1000  
1100  
1200  
600  
700  
800  
900  
1000  
1100  
1200  
LO Frequency (MHz)  
LO Frequency (MHz)  
Figure 13.  
Figure 14.  
GAIN vs LO FREQUENCY  
52  
50  
48  
46  
44  
42  
40  
38  
36  
34  
32  
LO Pwr = -3 dBm  
LO Pwr = 0 dBm  
LO Pwr = 3 dBm  
LO Pwr = 6 dBm  
600  
700  
800  
900  
1000  
1100  
1200  
LO Frequency (MHz)  
Figure 15.  
16  
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SLWS225B –DECEMBER 2010–REVISED MAY 2011  
TYPICAL CHARACTERISTICS (continued)  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
IIP3 vs LO FREQUENCY  
I
36  
34  
32  
30  
28  
26  
24  
22  
20  
TA = -40°C  
TA = -10°C  
TA = +25°C  
TA = +85°C  
18  
16  
14  
12  
10  
600  
700  
800  
900  
1000  
1100  
1200  
LO Frequency (MHz)  
Q
36  
34  
32  
30  
28  
26  
24  
22  
20  
18  
16  
14  
12  
10  
TA = -40°C  
TA = -10°C  
TA = +25°C  
TA = +85°C  
See Notes (4) and (5)  
1000 1100 1200  
600  
700  
800  
900  
LO Frequency (MHz)  
Figure 16.  
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TYPICAL CHARACTERISTICS (continued)  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
IIP3 vs LO FREQUENCY  
I
36  
34  
32  
30  
28  
26  
24  
22  
20  
18  
16  
14  
12  
10  
VCC = 4.5 V  
VCC = 5 V  
VCC = 5.5 V  
600  
700  
800  
900  
1000  
1100  
1200  
LO Frequency (MHz)  
Q
36  
34  
32  
30  
28  
26  
24  
22  
20  
18  
16  
14  
12  
10  
VCC = 4.5 V  
VCC = 5 V  
VCC = 5.5 V  
See Notes (4) and (5)  
1000 1100 1200  
600  
700  
800  
900  
LO Frequency (MHz)  
Figure 17.  
18  
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SLWS225B –DECEMBER 2010–REVISED MAY 2011  
TYPICAL CHARACTERISTICS (continued)  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
IIP3 vs LO FREQUENCY  
I
36  
34  
32  
30  
28  
26  
24  
22  
20  
18  
LO Pwr = -3 dBm  
16  
LO Pwr = 0 dBm  
LO Pwr = 3 dBm  
LO Pwr = 6 dBm  
14  
12  
10  
600  
700  
800  
900  
1000  
1100  
1200  
LO Frequency (MHz)  
Q
36  
34  
32  
30  
28  
26  
24  
22  
20  
18  
16  
14  
12  
10  
LO Pwr = -3 dBm  
LO Pwr = 0 dBm  
LO Pwr = 3 dBm  
LO Pwr = 6 dBm  
See Notes (4) and (5)  
600 700 800  
900  
1000  
1100  
1200  
LO Frequency (MHz)  
Figure 18.  
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TYPICAL CHARACTERISTICS (continued)  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
IIP3 vs LO FREQUENCY  
I
36  
34  
32  
30  
28  
26  
24  
22  
20  
18  
LPFADJ = 0  
LPFADJ = 25  
16  
14  
LPFADJ = 85  
LPFADJ = 142  
12  
10  
600  
700  
800  
900  
1000  
1100  
1200  
LO Frequency (MHz)  
Q
36  
34  
32  
30  
28  
26  
24  
22  
20  
18  
16  
14  
12  
10  
LPFADJ = 0  
LPFADJ = 25  
LPFADJ = 85  
LPFADJ = 142  
See Notes (4) and (5)  
600 700 800  
900  
1000  
1100  
1200  
LO Frequency (MHz)  
Figure 19.  
20  
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SLWS225B –DECEMBER 2010–REVISED MAY 2011  
TYPICAL CHARACTERISTICS (continued)  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
IIP2 vs lO FREQUENCY  
I
100  
90  
80  
70  
60  
TA = -40°C  
50  
TA = -10°C  
TA = +25°C  
TA = +85°C  
40  
30  
600  
700  
800  
900  
1000  
1100  
1200  
LO Frequency (MHz)  
Q
100  
90  
80  
70  
60  
50  
40  
30  
TA = -40°C  
TA = -10°C  
TA = +25°C  
TA = +85°C  
See Notes (4) and (5)  
1000 1100 1200  
600  
700  
800  
900  
LO Frequency (MHz)  
Figure 20.  
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TYPICAL CHARACTERISTICS (continued)  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
IIP2 vs LO FREQUENCY  
I
100  
90  
80  
70  
60  
50  
VCC = 4.5 V  
VCC = 5 V  
40  
30  
VCC = 5.5 V  
600  
700  
800  
900  
1000  
1100  
1200  
LO Frequency (MHz)  
Q
100  
90  
80  
70  
60  
50  
40  
30  
VCC = 4.5 V  
VCC = 5 V  
VCC = 5.5 V  
See Notes (4) and (5)  
1000 1100 1200  
600  
700  
800  
900  
LO Frequency (MHz)  
Figure 21.  
22  
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SLWS225B –DECEMBER 2010–REVISED MAY 2011  
TYPICAL CHARACTERISTICS (continued)  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
IIP2 vs LO FREQUENCY  
I
100  
90  
80  
70  
60  
50  
LO Pwr = -3 dBm  
LO Pwr = 0 dBm  
LO Pwr = 3 dBm  
LO Pwr = 6 dBm  
40  
30  
600  
700  
800  
900  
1000 1100 1200  
LO Frequency (MHz)  
Q
100  
90  
80  
70  
60  
50  
40  
30  
LO Pwr = -3 dBm  
LO Pwr = 0 dBm  
LO Pwr = 3 dBm  
LO Pwr = 6 dBm  
See Notes (4) and (5)  
600 700 800  
900  
1000  
1100  
1200  
LO Frequency (MHz)  
Figure 22.  
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TYPICAL CHARACTERISTICS (continued)  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
IIP2 vs LO FREQUENCY  
I
100  
90  
80  
70  
60  
50  
LPFADJ = 0  
LPFADJ = 25  
40  
LPFADJ = 85  
LPFADJ = 142  
30  
600  
700  
800  
900  
1000 1100 1200  
LO Frequency (MHz)  
Q
100  
90  
80  
70  
60  
50  
40  
30  
LPFADJ = 0  
LPFADJ = 25  
LPFADJ = 85  
LPFADJ = 142  
See Notes (4) and (5)  
600 700 800  
900  
1000  
1100  
1200  
LO Frequency (MHz)  
Figure 23.  
24  
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TYPICAL CHARACTERISTICS (continued)  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
NOISE FIGURE vs LO FREQUENCY  
NOISE FIGURE vs LO FREQUENCY  
20  
18  
16  
14  
12  
10  
8
20  
18  
16  
14  
12  
10  
8
VCC = 4.5 V  
VCC = 5 V  
TA = -40°C  
TA = -10°C  
TA = +25°C  
TA = +85°C  
VCC = 5.5 V  
See Notes (1) and (2)  
600 700 800  
See Notes (1) and (2)  
600 700 800  
6
6
900  
1000  
1100  
1200  
900  
1000  
1100  
1200  
LO Frequency (Hz)  
LO Frequency (Hz)  
Figure 24.  
Figure 25.  
NOISE FIGURE vs LO FREQUENCY  
OIP3 vs FREQUENCY OFFSET  
20  
18  
16  
14  
12  
10  
8
38  
36  
34  
32  
30  
28  
26  
24  
22  
20  
TA = -40°C  
TA = +25°C  
TA = +85°C  
LO Pwr = -3 dBm  
LO Pwr = 0 dBm  
LO Pwr = 3 dBm  
LO Pwr = 6 dBm  
See Notes (1) and (2)  
600 700 800  
See Note (6)  
5
6
900  
1000  
1100  
1200  
0
10  
15  
20  
25  
LO Frequency (Hz)  
Frequency Offset (MHz)  
Figure 26.  
Figure 27.  
OIP3 vs FREQUENCY OFFSET  
OIP3 vs FREQUENCY OFFSET  
38  
36  
34  
32  
30  
28  
26  
24  
22  
20  
38  
36  
34  
32  
30  
28  
26  
24  
22  
20  
VCC = 4.5 V  
BB Gain = 12 dB  
BB Gain = 16 dB  
BB Gain = 20 dB  
BB Gain = 24 dB  
VCC = 5 V  
VCC = 5.5 V  
See Note (6)  
5
See Note (6)  
5
0
10  
15  
20  
25  
0
10  
15  
20  
25  
Frequency Offset (MHz)  
Frequency Offset (MHz)  
Figure 28.  
Figure 29.  
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TYPICAL CHARACTERISTICS (continued)  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
OIP3 vs FREQUENCY OFFSET  
NOISE FIGURE vs BB GAIN SETTING  
28  
25  
22  
19  
16  
13  
38  
36  
34  
32  
30  
28  
26  
24  
22  
20  
3-dB Attn On  
3-dB Attn Off  
3-dB Attn On  
3-dB Attn Off  
See Note (6)  
5
0
2
4
6
8
10 12 14 16 18 20 22 24  
BB Gain Setting  
0
10  
15  
20  
25  
Frequency Offset (MHz)  
Figure 30.  
Figure 31.  
GAIN vs BB GAIN SETTING  
43  
40  
37  
34  
31  
28  
25  
22  
19  
16  
13  
GAIN vs FREQUENCY OFFSET  
3-dB Attn On  
3-dB Attn Off  
20  
0
-20  
-40  
-60  
LPFADJ = 0  
LPFADJ = 25  
LPFADJ = 85  
LPFADJ = 142  
-80  
0
2
4
6
8
10 12 14 16 18 20 22 24  
BB Gain Setting  
-100  
0.1  
1
10  
100  
Frequency Offset (MHz)  
G035  
Figure 32.  
Figure 33.  
GAIN vs FREQUENCY OFFSET  
GAIN vs FREQUENCY OFFSET  
5
20  
0
LPFADJ = 0  
4
3
LPFADJ = 25  
LPFADJ = 85  
LPFADJ = 142  
2
-20  
-40  
-60  
-80  
-100  
1
0
-1  
-2  
-3  
-4  
-5  
Filter Ctrl 0  
Filter Ctrl 1  
Filter Ctrl 2  
Filter Ctrl 3  
0.1  
1
10  
100  
0.1  
1
10  
100  
1000  
Frequency Offset (MHz)  
Frequency Offset (MHz)  
G036  
G037  
Figure 34.  
Figure 35.  
26  
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TYPICAL CHARACTERISTICS (continued)  
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).  
GAIN vs FREQUENCY OFFSET  
1-dB LPF CORNER FREQUENCY vs LPFADJ SETTING  
16  
5
4
Filter Ctrl 0  
Filter Ctrl 1  
Filter Ctrl 2  
Filter Ctrl 3  
14  
12  
10  
8
3
2
1
0
-1  
-2  
-3  
-4  
-5  
6
4
2
0
0.1  
1
10  
100  
0
50  
100  
150  
200  
250  
Frequency Offset (MHz)  
LPFADJ Setting  
G038  
G039  
Figure 36.  
Figure 37.  
RELATIVE LPF GROUP DELAY vs FREQUENCY OFFSET  
500  
IMAGE REJECTION vs BB FREQUENCY OFFSET  
0
See Note 8  
Bypass  
LPFADJ = 0  
LPFADJ = 25  
LPFADJ = 85  
LPFADJ = 142  
400  
300  
200  
100  
0
-10  
-20  
-30  
-40  
-50  
-60  
-100  
0.1  
1
10  
100  
-25 -20 -15 -10  
-5  
0
5
10  
15  
20  
25  
Frequency Offset (MHz)  
BB Frequency Offset (MHz)  
G040  
G041  
Figure 38.  
Figure 39.  
OUT-OF-BAND P1dB vs RELATIVE OFFSET MULTIPLIER  
TO CORNER FREQUENCY  
15  
DC OFFSET LIMIT vs TEMPERATURE  
See Note 9  
See Note (9)  
60  
40  
10  
5
0
20  
-5  
-10  
0
LPFADJ = 0  
LPFADJ = 25  
LPFADJ = 85  
LPFADJ = 142  
-15  
-20  
-25  
-20  
-40  
-60  
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
4.5  
Relative Offset Multiplier to Corner Frequency  
-45 -35 -25 -15 -5  
5
15 25 35 45 55 65 75 85  
Temperature (°C)  
G042  
Figure 40.  
Figure 41.  
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REGISTER INFORMATION  
SERIAL INTERFACE PROGRAMMING REGISTERS DEFINITION  
The TRF371109 features a three-wire serial programming interface (SPI) that controls an internal 32-bit shift  
register. There are three signals that must be applied: CLOCK (pin 48), serial DATA (pin 47), and STROBE (pin  
46). DATA (DB0–DB31) is loaded LSB-first and is read on the rising edge of CLOCK. STROBE is asynchronous  
to CLOCK, and at its rising edge the data in the shift register is loaded into the selected internal register. The first  
two bits (DB0–DB1) are the address to select the available internal registers.  
READBACK Mode  
The TRF371109 implements the capability to read back the content of the serial programming interface registers.  
In addition, it is possible to read back the status of the internal DAC registers that are automatically set after an  
auto dc-offset calibration. Each readback is composed by two phases: writing followed by the actual reading of  
the internal data (refer to Figure 42).  
During the writing phase, a command is sent to the TRF371109 to set it in readback mode and to specify which  
register is to be read. In the proper reading phase, at each rising clock edge, the internal data is transferred into  
the READBACK pin and can be read at the following falling edge (LSB first). The first clock after LE goes high  
(end of writing cycle) is idle, and the following 32 clock pulses transfer the internal register content to the  
READBACK pin.  
t(CLK)  
tSU1  
tH  
tCL  
tCH  
1st  
Write  
32nd  
Write  
CLOCK  
DATA  
CLOCK  
Pulse  
CLOCK  
Pulse  
DB29  
DB30  
DB31 (MSB)  
READBACK DATA  
Bit 31  
DB0 (LSB)  
Address Bit 0  
DB1  
Address Bit 1  
DB2  
Address Bit 2  
DB3  
Address Bit 3  
READBACK DATA READBACK DATA  
Bit 29 Bit 30  
tSU2  
tW  
End of Write  
Cycle Pulse  
Latch  
Enable  
32nd  
1st  
2nd  
32nd  
Read  
33rd  
Read  
CLOCK  
Write  
CLOCK  
Pulse  
Read  
CLOCK  
Pulse  
Read  
CLOCK  
Pulse  
CLOCK  
Pulse  
CLOCK  
Pulse  
tSU2  
tW  
tD  
End of Write  
Cycle Pulse  
STROBE  
READ  
BACK  
Data  
READ  
READBACK  
DATA  
READBACK  
Data Bit 0  
READBACK  
Data Bit 30  
READBACK  
Data Bit 31  
BACK  
Data  
Bit 29  
Bit 1  
Figure 42. Serial Programming Timing Diagram  
Table 1 shows the register summary. Table 2 through Table 6 list the device setup information for Register 1 to  
Register 5, respectively. Table 7 lists the device setup for Register 0.  
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Table 1. Register Summary(1)  
Bit #  
Bit0  
Reg 1  
Reg 2  
Bit #  
Bit0  
Reg 3  
Reg 5  
Bit #  
Bit0  
Reg 0  
Bit1  
Register address  
Register address  
Bit1  
Register address  
Register address  
Bit1  
Register address  
Bit2  
Bit2  
Bit2  
Bit3  
Bit3  
Bit3  
SPI bank addr  
SPI bank addr  
En auto-cal  
SPI bank addr  
ILoadA  
SPI bank addr  
Mix GM trim  
Mix LO trim  
LO trim  
SPI bank addr  
ID  
Bit4  
Bit4  
Bit4  
Bit5  
PWD RF  
Bit5  
Bit5  
Bit6  
NU  
Bit6  
Bit6  
Bit7  
PWD buf  
Bit7  
Bit7  
Bit8  
P
Bit8  
Bit8  
Bit9  
NU  
PWD DC OFF DIG  
NU  
Bit9  
Bit9  
IDAC for dc offset  
Bit10  
Bit11  
Bit12  
Bit13  
Bit14  
Bit15  
Bit16  
Bit17  
Bit18  
Bit19  
Bit20  
Bit21  
Bit22  
Bit23  
Bit24  
Bit25  
Bit26  
Bit27  
Bit28  
Bit29  
Bit30  
Bit31  
Bit10  
Bit11  
Bit12  
Bit13  
Bit14  
Bit15  
Bit16  
Bit17  
Bit18  
Bit19  
Bit20  
Bit21  
Bit22  
Bit23  
Bit24  
Bit25  
Bit26  
Bit27  
Bit28  
Bit29  
Bit30  
Bit31  
Bit10  
Bit11  
Bit12  
Bit13  
Bit14  
Bit15  
Bit16  
Bit17  
Bit18  
Bit19  
Bit20  
Bit21  
Bit22  
Bit23  
Bit24  
Bit25  
Bit26  
Bit27  
Bit28  
Bit29  
Bit30  
Bit31  
NU  
Mix buf trim  
Fltr trim  
ILoadB  
QLoadA  
QLoadB  
BB gain  
Out buf trim  
QDAC for dc offset  
DC offset Q DAC  
LPFADJ  
IDet  
Cal sel  
NU  
DC detector  
bandwidth  
CLK div ratio  
Cal clk sel  
Osc trim  
Fast gain  
Gain sel  
Osc test  
NU  
DC offset I DAC  
Bypass  
Fltr ctrl  
En 3dB attn  
(1) Register 4 is not used.  
Table 2. Register 1 Device Setup  
REGISTER 1  
Bit0  
NAME  
ADDR<0>  
ADDR<1>  
ADDR<2>  
ADDR<3>  
ADDR<4>  
PWD_MIX  
NU  
RESET VALUE  
WORKING DESCRIPTION  
1
0
0
1
0
0
0
1
0
0
1
Bit1  
Register address  
SPI bank address  
Bit2  
Bit3  
Bit4  
Bit5  
Mixer power down (Off = '1')  
Not used  
Bit6  
Bit7  
PWD_BUF  
PWD_FILT  
NU  
Mixer out test buffer power down (Off = '1')  
Baseband filter power down (Off = '1')  
Not used  
Bit8  
Bit9  
Bit10  
PWD_DC_OFF_DIG  
DC offset calibration power down (Off = '1')  
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Table 2. Register 1 Device Setup (continued)  
REGISTER 1  
Bit11  
Bit12  
Bit13  
Bit14  
Bit15  
Bit16  
Bit17  
Bit18  
Bit19  
Bit20  
Bit21  
Bit22  
Bit23  
Bit24  
Bit25  
Bit26  
Bit27  
Bit28  
Bit29  
Bit30  
Bit31  
NAME  
NU  
RESET VALUE  
WORKING DESCRIPTION  
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Not used  
BBGAIN_0  
BBGAIN_1  
BBGAIN_2  
BBGAIN_3  
BBGAIN_4  
LPFADJ_0  
LPFADJ_1  
LPFADJ_2  
LPFADJ_3  
LPFADJ_4  
LPFADJ_5  
LPFADJ_6  
LPFADJ_7  
EN_FLT_B0  
EN_FLT_B1  
EN_FASTGAIN  
GAIN_SEL  
OSC_TEST  
NU  
Baseband gain setting. Default = 15. Range is from 0 (minimum gain  
setting) to 24 (maximum gain setting). See the Application Information  
section for more information on gain setting and fast gain control  
options.  
Sets programmable low-pass filter corner frequency. Range = 255  
(lowest corner frequency) to 0 (highest corner frequency). Default value  
is 128.  
Selects dc offset detector filter bandwidth.  
Setting {00, 01, 11} = {10 MHz, 10 kHz, 1 kHz}  
Enable external fast-gain control  
Fast-gain control multiplier bit (×2 = 1)  
Enables Osc out on readback pin if = 1  
Not used  
EN 3dB Attn  
Enables output 3-dB attenuator  
EN_FLT_B0/1: These bits control the bandwidth of the detector used to measure the dc offset during the  
automatic calibration. There is an RC filter in front of the detector that can be fully bypassed. EN_FLT_B0  
controls the resistor (bypass = 1), while EN_FLT_B1 controls the capacitor (bypass = 1). The typical 3-dB cutoff  
frequencies of the detector bandwidth are summarized in Table 3 (see the Application Information section for  
more detail on the dc offset calibration and the detector bandwidth).  
Table 3. Detector Bandwidth Settings  
EN_FLT_B1 EN_FLT_B0  
TYPICAL 3-dB CUTOFF FREQ  
NOTES  
Maximum bandwidth, bypass R, C  
Enable R  
x
0
1
0
1
1
10 MHz  
10 kHz  
1 kHz  
Minimum bandwidth, enable R, C  
Table 4. Register 2 Device Setup  
REGISTER 2  
Bit0  
NAME  
RESET VALUE  
WORKING DESCRIPTION  
ADDR<0>  
ADDR<1>  
ADDR<2>  
ADDR<3>  
ADDR<4>  
0
1
0
1
0
0
Bit1  
Register address  
Bit2  
Bit3  
SPI bank address  
Bit4  
Bit5  
EN_AUTOCAL  
Enable autocal when = '1'; reset to '0' when done.  
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Table 4. Register 2 Device Setup (continued)  
REGISTER 2  
NAME  
IDAC_BIT0  
IDAC_BIT1  
IDAC_BIT2  
IDAC_BIT3  
IDAC_BIT4  
IDAC_BIT5  
IDAC_BIT6  
IDAC_BIT7  
QDAC_BIT0  
QDAC_BIT1  
QDAC_BIT2  
QDAC_BIT3  
QDAC_BIT4  
QDAC_BIT5  
QDAC_BIT6  
QDAC_BIT7  
IDET_B0  
RESET VALUE  
WORKING DESCRIPTION  
Bit6  
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
Bit7  
Bit8  
Bit9  
I-DAC bits to be set during manual dc offset cal  
Bit10  
Bit11  
Bit12  
Bit13  
Bit14  
Bit15  
Bit16  
Bit17  
Bit18  
Bit19  
Bit20  
Bit21  
Bit22  
Bit23  
Bit24  
Bit25  
Bit26  
Bit27  
Bit28  
Bit29  
Bit30  
Bit31  
Q-DAC bits to be set during manual dc offset cal  
Set reference current for digital calibration; Settings {00 to 11}  
= {50 µA to 200 µA}. Setting '00' = highest resolution.  
IDET_B1  
CAL_SEL  
DC offset calibration select. '0' = manual cal; '1' = autocal.  
Clk_div_ratio<0>  
Clk_div_ratio<1>  
Clk_div_ratio<2>  
Cal_clk_sel  
Osc_trim<0>  
Osc_trim<1>  
Osc_trim<2>  
Clk divider ratio. Setting {000 to 111} = {1, 8, 16, 128, 256, 1024, 2048,  
16684}. A higher div ratio (slower clk) improves cal accuracy and  
reduces speed.  
Select internal oscillator when 1, SPI clk when '0'  
Internal oscillator frequency trimming; Setting {000} = ~300 kHz;  
Setting {111} = ~1.8 MHz. Nominal setting {110} = ~900 kHz.  
Table 5. Register 3 Device Setup  
REGISTER 3  
Bit0  
NAME  
RESET VALUE  
WORKING DESCRIPTION  
ADDR<0>  
1
Bit1  
ADDR<1>  
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Register address  
SPI bank address  
Bit2  
ADDR<2>  
Bit3  
ADDR<3>  
Bit4  
ADDR<4>  
Bit5  
ILOAD_a<0>  
ILOAD_a<1>  
ILOAD_a<2>  
ILOAD_a<3>  
ILOAD_a<4>  
ILOAD_a<5>  
ILOAD_b<0>  
ILOAD_b<1>  
ILOAD_b<2>  
ILOAD_b<3>  
ILOAD_b<4>  
ILOAD_b<5>  
Bit6  
Bit7  
I mixer offset side A  
Bit8  
Bit9  
Bit10  
Bit11  
Bit12  
Bit13  
Bit14  
Bit15  
Bit16  
I mixer offset side B  
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Table 5. Register 3 Device Setup (continued)  
REGISTER 3  
Bit17  
NAME  
RESET VALUE  
WORKING DESCRIPTION  
QLOAD_a<0>  
QLOAD_a<1>  
QLOAD_a<2>  
QLOAD_a<3>  
QLOAD_a<4>  
QLOAD_a<5>  
QLOAD_b<0>  
QLOAD_b<1>  
QLOAD_b<2>  
QLOAD_b<3>  
QLOAD_b<4>  
QLOAD_b<5>  
Bypass  
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Bit18  
Bit19  
Q mixer offset side A  
Bit20  
Bit21  
Bit22  
Bit23  
Bit24  
Bit25  
Q mixer offset side B  
Engage filter bypass  
Bit26  
Bit27  
Bit28  
Bit29  
Bit30  
Fltr Ctrl_b<0>  
Fltr Ctrl_b<1>  
Used to adjust for filter peaking response; set to 0 in bypass mode, 1  
otherwise  
Bit31  
I/Q Mixer Load A/B: these bits adjust the load on the mixer output. All values should be 0. No modification is  
necessary.  
Register 4: No programming required for Register 4.  
Table 6. Register 5 Device Setup  
REGISTER 5  
Bit0  
NAME  
RESET VALUE  
WORKING DESCRIPTION  
ADDR<0>  
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Bit1  
ADDR<1>  
Register address  
Bit2  
ADDR<2>  
Bit3  
ADDR<3>  
SPI bank address  
Bit4  
ADDR<4>  
Bit5  
MIX_GM_TRIM<0>  
MIX_GM_TRIM<1>  
MIX_LO_TRIM<0>  
MIX_LO_TRIM<1>  
LO_TRIM<0>  
Mixer gm current trim  
Bit6  
Bit7  
Mixer switch core VCM trim  
LO buffers current trim  
Bit8  
Bit9  
Bit10  
Bit11  
Bit12  
Bit13  
Bit14  
Bit15  
Bit16  
LO_TRIM<1>  
MIX_BUFF_TRIM<0>  
MIX_BUFF_TRIM<1>  
FLTR_TRIM<0>  
FLTR_TRIM<1>  
OUT_BUFF_TRIM<0>  
OUT_BUFF_TRIM<1>  
Mixer output buffer current trim  
Filter current trim  
Filter output buffer current trim  
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Table 6. Register 5 Device Setup (continued)  
REGISTER 5  
NAME  
RESET VALUE  
WORKING DESCRIPTION  
Bit17  
Bit18  
Bit19  
Bit20  
Bit21  
Bit22  
Bit23  
Bit24  
Bit25  
Bit26  
Bit27  
Bit28  
Bit29  
Bit30  
Bit31  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NU  
Not used  
Readback (Write Command)  
0
0
0
1
0
Zero Fill  
Bit0  
Bit1  
Bit2  
Bit3  
Bit4  
Bit5  
Bit6  
Bit7  
Bit8  
Bit9  
Bit10  
Bit11  
Bit27  
Bit12  
Bit13  
Bit14  
Bit15  
1
Zero fill  
Register address  
Bit16  
Bit17  
Bit18  
Bit19  
Bit20  
Bit21  
Bit22  
Bit23  
Bit24  
Bit25  
Bit26  
Bit28  
Bit29  
Bit30  
Bit31  
Reg 0:DAC/Device ID Readback  
Register Address  
SPI Bank Addr  
Bit3 Bit4  
DC offset Q DAC  
Bit19 Bit20  
ID  
NU  
Bit0  
Bit1  
Bit2  
Bit5  
Bit6  
Bit7  
Bit8  
Bit9  
Bit10  
Bit26  
Bit11  
Bit12  
Bit13  
Bit29  
Bit14  
Bit30  
Bit15  
Bit31  
DC offset I DAC  
Bit27 Bit28  
Bit16  
Bit17  
Bit18  
Bit21  
Bit22  
Bit23  
Bit24  
Bit25  
Table 7. Register 0 Device Setup (Read-Only)  
READBACK REGISTER  
NAME  
ADDR<0>  
ADDR<1>  
ADDR<2>  
ADDR<3>  
ADDR<4>  
ID<0>  
RESET VALUE  
WORKING DESCRIPTION  
Bit0  
Bit1  
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
Select SPI register 1 to 5  
Bit2  
Bit3  
Select SPI bank 1 to 3  
Bit4  
Bit5  
Version ID: 01 = –25  
Bit6  
ID<1>  
Bit7  
Bit8  
Bit9  
Bit10  
Bit11  
Bit12  
Bit13  
Bit14  
Bit15  
NU  
Not used  
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Table 7. Register 0 Device Setup (Read-Only) (continued)  
READBACK REGISTER  
NAME  
RESET VALUE  
WORKING DESCRIPTION  
Bit16  
Bit17  
Bit18  
Bit19  
Bit20  
Bit21  
Bit22  
Bit23  
Bit24  
Bit25  
Bit26  
Bit27  
Bit28  
Bit29  
Bit30  
Bit31  
DC_OFFSET_Q<0>  
DC_OFFSET_Q<1>  
DC_OFFSET_Q<2>  
DC_OFFSET_Q<3>  
DC_OFFSET_Q<4>  
DC_OFFSET_Q<5>  
DC_OFFSET_Q<6>  
DC_OFFSET_Q<7>  
DC_OFFSET_I<0>  
DC_OFFSET_I<1>  
DC_OFFSET_I<2>  
DC_OFFSET_I<3>  
DC_OFFSET_I<4>  
DC_OFFSET_I<5>  
DC_OFFSET_I<6>  
DC_OFFSET_I<7>  
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
DC offset DAC Q register  
DC offset DAC I register  
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APPLICATION INFORMATION  
Gain Control  
The TRF371109 integrates a baseband programmable gain amplifier (PGA) that provides 24 dB of gain range  
with 1-dB steps. The PGA gain is controlled through SPI by a 5-bit word (register 1 bits<12,16>). Alternatively,  
the PGA can be programmed by a combination of five bits programmed through the SPI and three parallel  
external bits (pins Gain_B2, Gain_B1, Gain_B0). The external bits are used to reduce the PGA setting quickly  
without having to reprogram the SPI registers. The fast gain control multiplier bit (register 1, bit 28) sets the step  
size of each bit to either 1 dB or 2 dB. This configuration allows a fast gain reduction of 0 dB to 7 dB in 1-dB  
steps or 0 dB to 14 dB in 2-dB steps.  
The PGA gain control word (BBgain<0,4>) can be programmed to a setting between 0 and 24. This word is the  
SPI programmed gain (register 1 bits<12,16>) minus the parallel external three bits, as shown in Figure 43. Note  
that the PGA gain setting rails at 0 and does not go any lower. Typical applications set the nominal PGA gain  
setting to 17 and use the fast gain control bits to protect the analog-to-digital converter (ADC) in the event of a  
strong input jammer signal.  
Composite  
PGA Setting  
(min: 0, max 24)  
SPI  
+
X
(x1, x2)  
Fast Gain Select  
Figure 43. PGA Gain Control Word  
For example, if a PGA gain setting of 19 is desired, then the SPI can be programmed directly to a value of 19.  
Alternatively, the SPI gain register can be programmed to 24 and the parallel external bits set to '101' (binary),  
corresponding to 5-dB reduction.  
Automated DC Offset Calibration  
The TRF371109 provides an automatic calibration procedure for adjusting the dc offset in the baseband I/Q  
paths. The internal calibration requires a clock in order to function. The TRF371109 can use the internal  
relaxation oscillator or the external SPI clock. Using the internal oscillator is the preferred method, which is  
selected by setting the Cal_Sel_Clk (register 2, bit 28) to '1'. The internal oscillator frequency is set through the  
Osc_Trim bits (register 2, bits <29,31>). The oscillator frequency is detailed in Table 8.  
Table 8. Internal Oscillator Frequency Control  
OSC_TRIM<2>  
OSC_TRIM<1>  
OSC_TRIM<0>  
FREQUENCY  
300 kHz  
500 kHz  
700 kHz  
900 kHz  
1.1 MHz  
1.3 MHz  
1.5 MHz  
1.8 MHz  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
The default settings of these registers correspond to a 900-kHz oscillator frequency. This frequency is sufficient  
for auto calibration and does not need to be modified.  
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The output full-scale range of the internal dc offset correction digital-to-analog converters (DACs) is  
programmable (IDET_B<0,1, register 2 bit<22,23>). The range is shown in Table 9.  
Table 9. DC Offset Correction DAC Programmable Range  
I(Q) Det_B0  
I(Q) Det_B1  
FULL-SCALE  
50 µA  
0
0
1
1
0
1
0
1
100 µA  
150 µA  
200 µA  
The I- and Q-channel output maximum dc offset correction range can be calculated by multiplying the values in  
Table 9 by the baseband PGA gain. The LSB of the digital correction depends on the programmed maximum  
correction range. For optimum resolution and best correction. the dc offset DAC range should be set to 10 mV for  
both the I- and Q-channels with the PGA gain set for the nominal condition. The dc offset correction DAC output  
is affected by changes in the PGA gain; if the initial calibration yields optimum results, however, then PGA gain  
adjustment during normal operation does not significantly impair the dc offset balance. For example, if the  
optimized calibration yields a dc offset balance of 2 mV at a gain setting of 17, then the dc offset maintains a  
balance of less than 10 mV as the gain is adjusted ±7 dB.  
The dc offset correction DACs are programmed from the internal registers when the AUTO_CAL bit (register 2,  
bit 24) is set to '1'. At start-up, the internal registers are loaded at half-scale, corresponding to a decimal value of  
128. The auto calibration is initiated by toggling the EN_AUTOCAL bit (register 2, bit 5) to '1'. When the  
calibration is complete, this bit automatically resets to '0'. During calibration, the RF Local Oscillator (LO) must be  
applied.  
The dc offset DAC state is stored in the internal registers and maintained as long as the power supply remains  
on, or until a new calibration begins.  
The required clock speed for the optimum calibration is determined by the internal detector behavior (integration  
bandwidth, gain, and sensitivity). The input bandwidth of the detector can be adjusted by changing the cutoff  
frequency of the RC low-pass filter (LPF) in front of the detector (register 1, bits 25-26). EN_FLT_B0 controls the  
resistor (bypass = '1') and EN_FLT_B1 controls the capacitor (bypass = '1'). The typical 3-dB cutoff frequencies  
of the detector bandwidth are summarized in Table 3. The clock speed can be slowed down by selecting a clock  
divider ratio (register 2, bits 25-27).  
The detector has more averaging time the slower the clock; therefore, it can be desirable to slow down the clock  
speed for a given condition to achieve optimum results. For example, if there is no RF present on the RF input  
port, the detection filter can be left wide (10 MHz) and the clock divider can be left at divide-by-1. The auto  
calibration yields a dc offset balance between the differential baseband output ports (I and Q) that is less than 15  
mV. Some minor improvement may be obtained by increasing the averaging of the detector through increasing  
the clock divider up to 256.  
On the other hand, if there is a modulated RF signal present at the input port, it is desirable to reduce the  
detector bandwidth to filter out most of the modulated signal. The detector bandwidth can be set to a 1-kHz  
corner frequency. With the modulated signal present and with the detection bandwidth reduced, additional  
averaging is required to get the optimum results. A clock divider setting of 1024 yields optimum results.  
Of course, an increase in the averaging is possible by increasing the clock divider at the expense of a longer  
converging time. The convergence time can be calculated by the following:  
(Auto_Cal_Clk_Cycles) ´ (Clk_Divider)  
tc  
=
Osc_Freq  
(1)  
For the case with a clock divider of 1024 and with the nominal oscillator frequency of 900 kHz, the convergence  
time is:  
(9) ´ (1024)  
tc  
=
= 10.24 ms  
900 kHz  
(2)  
36  
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Product Folder Link(s): TRF371109  
 
TRF371109  
www.ti.com  
SLWS225B –DECEMBER 2010–REVISED MAY 2011  
Alternate Method for Adjusting DC Offset  
The internal registers that control the internal dc current DAC are accessible through the SPI and provide a  
user-programmable method for implementing the dc offset calibration. To employ this option, the CAL_SEL bit  
must be set to '0'. During this calibration, an external instrument monitors the output dc offset between the I/Q  
differential outputs and programs the internal registers (IDAC_BIT<0,7> and QDAC_BIT<0,7> bits) to cancel the  
dc offset.  
PCB Layout Guidelines  
The TRF371109 device is fitted with a ground slug on the back of the package that must be soldered to the  
printed circuit board (PCB) ground with adequate ground vias to ensure good thermal and electrical connections.  
The recommended via pattern and ground pad dimensions are shown in Figure 44. The recommended via  
diameter is 8 mils (0.2 mm). The ground pins of the device can be directly tied to the ground slug pad for a  
low-inductance path to ground. Additional ground vias may be added if space allows. The no-connect (NC) pins  
can also be tied to the ground plane.  
Decoupling capacitors at each of the supply pins are recommended. The high-frequency decoupling capacitors  
for the RF mixers (VCCMIX) should be placed close to the respective pins. The value of the capacitor should be  
chosen to provide a low-impedance RF path to ground at the frequency of operation. Typically, this value is  
approximately 10 pF or lower. The other decoupling capacitors at the other supply pins should be kept as close  
as possible to the respective pins.  
The device exhibits symmetry with respect to the quadrature output paths. It is recommended that the PCB  
layout maintain that symmetry in order to ensure that the quadrature balance of the device is not impaired. The  
I/Q output traces should be routed as differential pairs and the respective lengths all kept equal to each other.  
Decoupling capacitors for the supply pins should be kept symmetrical where possible. The RF differential input  
lines related to the RF input and the LO input should also be routed as differential lines with the respective  
lengths kept equal. If an RF balun is used to convert a single-ended input to a differential input, then the RF  
balun should be placed close to the device. Implement the RF balun layout according to the manufacturer  
guidelines to provide best gain and phase balance to the differential outputs. On the RF traces, maintain proper  
trace widths to keep the characteristic impedance of the RF traces at a nominal 50 Ω.  
0.200 (5.08)  
0.025 (0.635)  
Ø0.008 (0.203)  
0.025 (0.635)  
0.0125 (0.318)  
0.200 (5.08)  
Note: Dimensions are in inches (mm)  
M0177-01  
Figure 44. PCB Layout Guidelines  
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SLWS225B –DECEMBER 2010–REVISED MAY 2011  
www.ti.com  
Application Schematic  
Figure 45 shows the typical application schematic. The RF bypass capacitors and coupling capacitors on the  
supply pins should be adjusted to provide the best high-frequency bypass based on the frequency of operation.  
To Microcontroller  
To Microcontroller  
48 47 46 45 44 43 42 41 40 39 38 37  
GNDDIG  
VCCDIG  
CHIP_EN  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VCCBBI  
GND  
2
BBIOUTP  
BBIOUTN  
3
To ADC I  
VCCMIX1  
GND  
4
5
GND  
LOIP  
LOIN  
RFIN  
MIXINP  
MIXINN  
LOIN  
6
TRF371109  
7
GND  
VCCMIX2  
NC  
8
VCCLO  
BBQOUTP  
BBQOUTN  
9
To ADC Q  
10  
11  
12  
NC  
GND  
GND  
VCCBBQ  
13 14 15 16 17 18 19 20 21 22 23 24  
30 kW  
Figure 45. TRF371109 Application Schematic  
The RF input port and the RF LO port require differential input paths. Single-ended RF inputs to these ports can  
be converted with an RF balun that is centered at the band of interest. Linearity performance of the TRF371109  
depends on the amplitude and phase balance of the RF balun; therefore, care should be taken with the selection  
of the balun device and with the RF layout of the device. The recommended RF balun devices are listed in  
Table 10.  
Table 10. RF Balun Devices  
MANUFACTURER  
Murata  
PART NUMBER  
LDB21897M005C-001  
LDB211G8005C-001  
LDB211G9005C-001  
LDB212G4005C-001  
3600BL14M050E  
FREQUENCY RANGE  
897 MHz ±100 MHz  
1800 MHz ±100 MHz  
1900 MHz ±100 MHz  
2.3 GHz to 2.7 GHz  
3.3 GHz to 3.8 GHz  
UNBALANCE IMPEDANCE BALANCE IMPEDANCE  
50 Ω  
50 Ω  
50 Ω  
50 Ω  
50 Ω  
50 Ω  
50 Ω  
50 Ω  
50 Ω  
50 Ω  
Murata  
Murata  
Murata  
Johanson  
38  
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TRF371109  
www.ti.com  
SLWS225B –DECEMBER 2010–REVISED MAY 2011  
ADC Interface  
The TRF3711 has an integrated ADC driver buffer that allows direct connection to an ADC without additional  
active circuitry. The common-mode voltage generated by the ADC can be directly supplied to the TRF3711  
through the VCM pin (pin 24). Otherwise, a nominal common-mode voltage of 1.5 V should be applied to that  
pin. The TRF3711 device can operate with a common-mode voltage from 1.5 V to 2.8 V without any negative  
imact on the output performance. Figure 46 illustrates the degradation of the output compression point as the  
common-mode voltage exceeds those values.  
P1dB vs COMMON-MODE VOLTAGE  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
Common-Mode Voltage (V)  
Figure 46. P1dB Performance vs. Common Mode Voltage  
Application for a High-Performance RF Receiver Signal Chain  
The TRF371109 is the centerpiece component of a high-performance, direct-downconversion receiver. This  
device is a highly-integrated, direct-downconversion demodulator that requires minimal additional devices to  
complete the signal chain. A signal chain block diagram example is shown in Figure 47.  
ADS5232  
TRF371109  
12  
0
LNA  
90  
12  
TRF3761  
Figure 47. Block Diagram of Direct Downconvert Receiver  
The lineup requires a low-noise amplifier (LNA) that operates at the frequency of interest with typical 1- to 2-dB  
noise figure (NF) performance. An RF bandpass filter (BPF) is selected at the frequency band of interest to  
prevent unwanted signals and images outside the band from reaching the demodulator. The TRF371109  
incorporates the direct downconvert demodulation, baseband filtering, and baseband gain-control functions. An  
external synthesizer, such as the TRF3761, provides the LO source to the TRF371109. The differential outputs  
of the TRF3761 directly match with the LO input of the TRF371109. The quadrature outputs (I/Q) of the  
TRF371109 directly drive the input to the ADC. A dual ADC such as the ADS5232 12-bit, 65-MSPS ADC  
matches perfectly with the differential I/Q output of the TRF371109. In addition, the common-mode output  
voltage generated by the ADS5232 is fed directly into the common-mode ports (pin 24) to ensure that the  
optimum dynamic range of the ADC is maintained.  
Copyright © 2010–2011, Texas Instruments Incorporated  
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SLWS225B –DECEMBER 2010–REVISED MAY 2011  
www.ti.com  
EVALUATION TOOLS  
An evaluation module is available to test the TRF371109 performance. The TRF371109EVM can be configured  
with different baluns to enable operation in various frequency bands. The TRF371109EVM is available for  
purchase through the Texas Instruments web site at www.ti.com.  
REVISION HISTORY  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
Changes from Revision A (March, 2011) to Revision B  
Page  
•
Updated Automated DC Offset Calibration section with correct information about the dc Offset Correction DACs .......... 35  
Changes from Original (December, 2010) to Revision A  
Page  
•
Revised the Register Information section ........................................................................................................................... 28  
40  
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Copyright © 2010–2011, Texas Instruments Incorporated  
Product Folder Link(s): TRF371109  
PACKAGE OPTION ADDENDUM  
www.ti.com  
3-May-2011  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
TRF371109IRGZR  
TRF371109IRGZT  
ACTIVE  
ACTIVE  
VQFN  
VQFN  
RGZ  
RGZ  
48  
48  
2500  
250  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-2-260C-1 YEAR  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-2-260C-1 YEAR  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
16-Feb-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TRF371109IRGZR  
TRF371109IRGZT  
VQFN  
VQFN  
RGZ  
RGZ  
48  
48  
2500  
250  
330.0  
330.0  
16.4  
16.4  
7.3  
7.3  
7.3  
7.3  
1.5  
1.5  
12.0  
12.0  
16.0  
16.0  
Q2  
Q2  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
16-Feb-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TRF371109IRGZR  
TRF371109IRGZT  
VQFN  
VQFN  
RGZ  
RGZ  
48  
48  
2500  
250  
336.6  
336.6  
336.6  
336.6  
28.6  
28.6  
Pack Materials-Page 2  
IMPORTANT NOTICE  
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TRF371109IRGZR CAD模型

  • 引脚图

    • TRF371109IRGZR 替代型号

    型号 制造商 描述 替代类型 文档
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    TRF371135IRGZT TI INTEGRATED IQ DEMODULATOR 获取价格
    TRF372017 TI Integrated IQ Modulator PLL/VCO 获取价格
    TRF372017IRGZR TI 具有集成宽带 PLL/VCO 的 300MHz 至 4.8GHz 正交调制器 | RGZ | 48 | -40 to 85 获取价格
    TRF372017IRGZT TI 具有集成宽带 PLL/VCO 的 300MHz 至 4.8GHz 正交调制器 | RGZ | 48 | -40 to 85 获取价格

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