TRF372017IRGZR [TI]
具有集成宽带 PLL/VCO 的 300MHz 至 4.8GHz 正交调制器 | RGZ | 48 | -40 to 85;
| 型号： | TRF372017IRGZR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成宽带 PLL/VCO 的 300MHz 至 4.8GHz 正交调制器 | RGZ | 48 | -40 to 85 电话 蜂窝 电信 电信集成电路 蜂窝电话电路 电信电路 |
| 文件： | 总62页 (文件大小：2816K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TRF372017
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SLWS224C –AUGUST 2010–REVISED MAY 2012
Integrated IQ Modulator PLL/VCO
1
FEATURES
•
•
•
Fully Integrated PLL/VCO and IQ Modulator
LO Frequency from 300MHz to 4.8GHz
76-dBc Single-Carrier WCDMA ACPR at –8dBm
Channel Power
PS
RDBK
1
2
3
4
5
6
7
8
9
36 EXT_VCO
VCC_VCO1
LO_OUT_P
LO_OUT_N
VCC_VCO2
35
34
33
32
•
•
•
•
OIP3 of 26 dBm
VCC_DIG
GND_DIG
LD
P1dB of 11.5 dBm
Integer/Fractional PLL
GND
31 GND
Phase Noise –132 dBc/Hz
(at 1MHz, fVCO of 2.3 GHz)
VCC_LO1
GND
30 VCC_LO2
29 GND
•
•
Low Noise Floor: –160 dBm/Hz
28 BBI_N
27 BBI_P
26 GND
BBQ_N
Input Reference Frequency Range: Up to
160MHz
BBQ_P 10
GND 11
GND 12
25 GND
•
VCO Frequency Divided by 1-2-4-8 Output
APPLICATIONS
•
Wireless Infrastructure
–
–
–
CDMA: IS95, UMTS, CDMA2000, TD-SCDMA
TDMA: GSM, IS-136, EDGE/UWC-136
LTE
•
•
•
Wireless Local Loop
Point-to-Point Wireless Access
Wireless MAN Wideband Transceivers
DESCRIPTION
TRF372017 is a high performance direct up-conversion device, integrating a high linearity, low noise IQ
modulator and an integer-fractional PLL/VCO. The VCO uses integrated frequency dividers to achieve a wide,
continuous tuning range of 300MHz–4800MHz. The LO is available as an output with independent frequency
dividers. The device also accepts input from an external LO or VCO. The modulator baseband inputs can be
biased either internally or externally. Internal DC offset adjustment enables carrier cancellation. The device is
controlled through a 3 wire serial programming interface (SPI). A control pin invokes power-save mode to reduce
power consumption while keeping the VCO locked for fast startup.
FREQUENCY RANGE OPERATION
VCO Frequency
Div by 2
Div by 4
Div by 8
Fmin
2400
Fmax
4800
Fmin
1200
Fmax
2400
Fmin
600
Fmax
1200
Fmin
300
Fmax
600
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2012, Texas Instruments Incorporated
TRF372017
SLWS224C –AUGUST 2010–REVISED MAY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE DEVICE OPTIONS
SPECIFIED
OPERATING
TEMPERATURE
PACKAGE
LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
PRODUCT
MEDIA, QUANTITY
TRF372017IRGZT
TRF372017IRGZR
QFN-48
QFN-48
RGZ
RGZ
–40°C to 85°C
–40°C to 85°C
TRF372017
TRF372017
Tape and Reel, 250
Tape and Reel, 2500
FUNCTIONAL BLOCK DIAGRAM
BBQ
From
SPI
CP_OUT
Charge
Pump
Poly-
Phase
RFOUT
PFD
Div2/
4/8
S
LE
From
SPI
DATA
CLK
From
SPI
From
SPI
LD
BBI
Figure 1. TRF372017 Block Diagram
2
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SLWS224C –AUGUST 2010–REVISED MAY 2012
PIN FUNCTIONS
PIN
TYPE
DESCRIPTION
NAME
PS
NO
1
I
Power saving mode enable (Low = normal mode; High = power saving mode)
RDBK
VCC_DIG
GND_DIG
LD
2
O
SPI internal registers readback output
3
3.3V digital power supply
4
Digital ground
5
O
PLL lock detect output
GND
6
Ground
VCC_LO1
GND
7
3.3V Tx path local oscillator chain power supply
8
Ground
BBQ_N
BBQ_P
GND
9
I
I
Base-band in-quadrature input: negative terminal
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Base-band in-quadrature input: positive terminal
Ground
GND
Ground
GND
Ground
RSVD
GND
Reserved. Normally open.
Ground
GND
Ground
GND
Ground
RFOUT
GND
O
RF output
Ground
VCC_D2S
VCC_MIX
GND
5V modulator output buffer power supply
5V modulator power supply
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
BBI_P
BBI_N
GND
I
I
Base-band in-phase input: positive terminal
Base-band in-phase input: negative terminal
Ground
VCC_LO2
GND
3.3V output local oscillator chain power supply
Ground
VCC_VCO2
LO_OUT_N
LO_OUT_P
VCC_VCO1
EXT_VCO
GND
3.3 – 5.0V VCO power supply
Local oscillator output: negative terminal
Local oscillator output: positive terminal
3.3V VCO power supply
External local oscillator input
Ground
O
O
I
I
VTUNE
GND
VCO control voltage input
Ground
CP_OUT
VCC_PLL
GND
O
Charge pump output
3.3V PLL power supply
Ground
REFIN
GND
I
Reference clock input
Ground
LE
I
I
SPI latch enable. Digital input
SPI data input. Digital input
DATA
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PIN FUNCTIONS (continued)
PIN
TYPE
DESCRIPTION
NAME
CLK
NO
47
I
I
SPI clock input. Digital input
Internal testing mode. Connect to ground in normal operation
SCAN_EN
48
THERMAL INFORMATION
TRF372017
THERMAL METRIC(1)
RGZ
UNITS
48 PINS
θJA
Junction-to-ambient thermal resistance
30
10
8
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
7
ψJB
θJCbot
0.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
(2)
VALUE
–0.3 to 5.5
UNIT
V
Supply voltage range(3)
Digital I/O voltage range
–0.3 to VCC + 0.5
–40 to 150
V
Operating virtual junction temperature range, TJ
Operating ambient temperature range, TA
Storage temperature range, Tstg
°C
°C
°C
–40 to 85
–40 to 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) ESD rating not valid for RF sensitive pins.
(3) All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
VCC5V
VCC3V
5V Power supply voltage
3.3V Power supply voltage
4.5
3.0
5.0
3.3
3.3
5.5
3.6
5.5
85
V
V
VCC_VCO2 3.3–5V Power supply voltage
3.0
V
TA
TJ
Operating ambient temperature range
–40
–40
°C
°C
Operating virtual junction temperature range
125
4
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SLWS224C –AUGUST 2010–REVISED MAY 2012
ELECTRICAL CHARACTERISTICS
VCC5V = 5.0V, VCC3V = 3.3V, VCC_VCO2 = 3.3V, TA = 25°C, internal LO, internal VCM (unless otherwise noted)
PARAMETER
DC PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.3V power supply, LO on
200
117
3
250
148
5
mA
mA
mA
mA
mA
mA
ICC
Total supply current, LO on(1)
5V power supply, LO on
VCC_DIG, LO on
VCC_LO1 and VCC_LO2
VCC_D2S
121
43
130
60
VCC_MIX
74
90
Supply current, LO on(1)
VCC_VCO1
20
28
mA
VCC_VCO2
17
20
LO_OUT_N and LO_OUT_P
VCC_PLL
17
28
mA
mA
mA
mA
mA
mA
24
40
3.3V power supply, LO off
5V power supply, LO off
3.3V power supply, PS on
5V power supply, PS on
165
117
65
204
149
94
Total supply current, LO off(1)
Total supply current, PS on(1)
51
73
BASEBAND INPUTS
Externally generated
Set internally
1.7
1.7
1000
5
V
V
Vcm
BW
ZI
I and Q Input DC common voltage(2)
1.6
1.85
1dB Input frequency bandwidth
Input Impedance
MHz
kΩ
pF
Resistance
Parallel Capacitance
3
BASEBAND INPUT DC OFFSET CONTROL D/A(3)
Number of bits
Programmed via SPI
8
|BBI_P - BBI_N| or |BBQ_P - BBQ_N|, 100-Ω
differential load
Programmable DC offset setting
0.02
V
DIGITAL INTERFACE
VIH
VIL
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
2
0
3.3
V
V
V
V
0.8
VOH
VOL
Referenced to VCC_DIG
Referenced to VCC_DIG
0.8xVcc
0.2xVcc
REFERENCE OSCILLATOR PARAMETERS
Fref
Reference Frequency
160
3.3
MHz
Vp-p
pF
Reference input sensitivity
0.2
Parallel capacitance
Parallel resistance
5
Reference input impedance
3900
Ω
PFD CHARGE PUMP
PFD frequency(4)
Charge pump current
100
MHz
mA
ICP
SPI programmable
1.94
(1) Maximum current is worst-case over voltage, temperature, and expected process variations.
(2) The TRF372017 can generate the input common voltage internally or can accept an external common mode voltage. The two modes
are selectable via SPI
(3) When the internal input common mode voltage is selected, it is possible to apply some dc offset with the integrated D/A
(4) See Application Information for discussion on selection of PFD frequency.
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TRF372017 ELECTRICAL CHARACTERISTICS
VCC5V = 5.0V, VCC3V = 3.3V, VCC_VCO2 = 3.3V, TA = 25°C, internal LO, internal VCM (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IQ MODULATOR OUTPUT, FLO = 750 MHz
G
Voltage gain
Output rms voltage over se input I (or Q) rms voltage
–4
–3.2
11
–2.4
–2.4
–2
dB
P1dB
IP3
IP2
Output compression point
Output IP3
dBm
dBm
dBm
dBm
dBc
dB
2 input tones at 4.5 and 5.5MHz
2 input tones at 4.5 and 5.5MHz
Unadjusted
26
Output IP2
56.5
–43.5
–46
10
Carrier feedthrough
Sideband suppression
Output return loss
Unadjusted
DC only to BB inputs; 13 MHz offset from LO; Pout = –10
dBm
Output noise
–162
dBm/Hz
IQ MODULATOR OUTPUT, FLO = 900 MHz
G
Voltage Gain
Output rms voltage over se input I (or Q) rms voltage
–4
–3.4
11
dB
P1dB
IP3
IP2
Output Compression Point
Output IP3
dBm
dBm
dBm
dBm
dBc
dB
2 input tones at 4.5 and 5.5 MHz
2 input tones at 4.5 and 5.5 MHz
Unadjusted
26.5
56.5
–43
–45
10
Output IP2
Carrier Feedthrough
Sideband suppression
Output Return Loss
Unadjusted
DC only to BB inputs; 13 MHz offset from LO; Pout = –10
dBm
Output Noise
–160
dBm/Hz
IQ MODULATOR OUTPUT, FLO = 2150 MHz
G
Voltage Gain
Output rms voltage over se input I (or Q) rms voltage
–4.2
–3.1
11.5
25
dB
P1dB
IP3
IP2
Output Compression Point
Output IP3
dBm
dBm
dBm
dBm
dBc
dB
2 input tones at 4.5 and 5.5 MHz
2 input tones at 4.5 and 5.5 MHz
Unadjusted
Output IP2
56
Carrier Feedthrough
Sideband suppression
Output Return Loss
–40
–32
10
Unadjusted
DC only to BB inputs; 13 MHz offset from LO; Pout = –10
dBm
Output Noise
–158
dBm/Hz
1 WCDMA signal; Pout = –8 dBm
–75
–71
dBc
dBc
ACPR
Adjacent-channel power ratio
2 WCDMA signals; Pout = –11 dBm per carrier
IQ MODULATOR OUTPUT, FLO = 2700 MHz
G
Voltage gain
Output rms voltage over se input I (or Q) rms voltage
–4.1
–2.7
12
–1.3
dB
P1dB
IP3
IP2
Output compression point
Output IP3
dBm
dBm
dBm
dBm
dBc
dB
2 input tones at 4.5 and 5.5 MHz
2 input tones at 4.5 and 5.5 MHz
Unadjusted
26.5
50
Output IP2
Carrier feedthrough
Sideband suppression
Output return loss
–43
–41
10
Unadjusted
DC only to BB inputs; 13 MHz offset from LO; Pout = –10
dBm
Output noise
–153
dBm/Hz
6
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SLWS224C –AUGUST 2010–REVISED MAY 2012
TRF372017 ELECTRICAL CHARACTERISTICS (continued)
VCC5V = 5.0V, VCC3V = 3.3V, VCC_VCO2 = 3.3V, TA = 25°C, internal LO, internal VCM (unless otherwise noted)
PARAMETER
LOCAL OSCILLATOR
TEST CONDITIONS
MIN
TYP
MAX UNIT
VCO range
2400
1200
600
4800
Divide by 2
2400
MHz
1200
FVCO
Frequency Range
Divide by 4
Divide by 8
300
600
Free running VCO
10kHz
–85
–132
–150
–153
3
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBm
Phase Noise, Fout=2.3GHz
1MHz
10MHz
50MHz
PLO
LO Output power(1)
100 Ω differential, external load; single-ended
–2.5
(1) With VCO frequency at 4.6 GHz and LO in divide-by-2 mode at 2.3 GHz
tsu1
t(CL)
th
t(CLK)
t(CH)
32nd
Write
clock
1st Write
CLOCK
clock
pulse
pulse
DB0 (LSB)
Address Bit0
DB1
Address Bit1
DB2
Address Bit2
DB3
Address Bit3
DB29
DB30
DB31 (MSB)
DATA
tsu3
tsu2
tw
End of
Write
Cycle pulse
LATCH
ENABLE
Figure 2. SPI Write Timing Diagram
Table 1. SPI Timing: Writing Phase
PARAMETER
MIN
20
20
20
20
20
50
50
70
TYP
MAX UNITS
th
Hold time, data to clock
Setup time, data to clock
Clock low duration
ns
ns
ns
ns
ns
ns
ns
ns
tSU1
T(CH)
T(CL)
tSU2
t(CLK)
tW
Clock high duration
Setup time, clock to enable
Clock period
Enable time
tSU3
Setup time, latch to Data
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tsu1
th
t(CLK)
T(CL)
1st Write
clock
pulse
T(CH)
32nd Write
clock pulse
CLOCK
DATA
)
DB0 (LSB
Address Bit0
DB1
Address Bit1
DB2
Address Bit2
DB3
Address Bit3
)
DB31(MSB
DB29
DB30
LATCH ENABLE
nd
32
1st Read
clock pulse
2nd Read
clock pulse
32nd Read
clock pulse
33rdRead
clock pulse
tsu3
Write
clock
pulse
CLOCK
“End of Write Cycle”
pulse
td
LATCH ENABLE
tw
Read
Back
Data
Bit1
Read
ReadBack
Data Bit30
ReadBack
Data Bit 0
ReadBack
Data Bit31
Back
Data
Bit29
READBACK DATA
Figure 3. SPI Read-Back Timing Diagram
Table 2. SPI Timing Read-Back Phase
PARAMETER
Hold time, data to clock
MIN
20
20
20
20
20
10
50
50
TYP
MAX UNITS COMMENTS
th
ns
ns
ns
ns
ns
ns
ns
ns
tSU1
T(CH)
T(CL)
tSU2
td
Setup time, data to clock
Clock low duration
Clock High duration
Setup time, clock to enable
Delay time, clock to readback data output
Enable Time
tW
Equals Clock period
t(CLK)
Clock period
8
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TYPICAL CHARACTERISTICS
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
OPEN LOOP PHASE NOISE
vs
OPEN LOOP PHASE NOISE
vs
FREQUENCY AND TEMPERATURE
FREQUENCY AND TEMPERATURE
-40
-60
-40
-60
F_LO_OUT = 3.35 GHz
VCC = 3.3, 5 V
F_LO_OUT = 2.6 GHz
VCC = 3.3, 5 V
-80
-80
TA = 85°C
TA = 85°C
-100
-120
-140
-160
-100
-120
-140
-160
TA = -40°C
TA = -40°C
TA = 25°C
TA = 25°C
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G001
G002
Figure 4.
Figure 5.
TEXT
TEXT
OPEN LOOP PHASE NOISE
vs
OPEN LOOP PHASE NOISE
vs
FREQUENCY AND TEMPERATURE
FREQUENCY AND TEMPERATURE
-40
-60
-40
-60
F_LO_OUT = 4.05 GHz
VCC = 3.3, 5 V
F_LO_OUT = 4.7 GHz
VCC = 3.3, 5 V
-80
-80
TA = 85°C
TA = 85°C
-100
-120
-140
-160
-100
-120
-140
-160
TA = -40°C
TA = -40°C
TA = 25°C
TA = 25°C
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G003
G004
Figure 6.
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
OPEN LOOP PHASE NOISE
vs
OPEN LOOP PHASE NOISE
vs
FREQUENCY AND SUPPLY VOLTAGE
FREQUENCY AND SUPPLY VOLTAGE
-40
-60
-40
-60
F_LO_OUT = 2.6 GHz
TA = 25°C
F_LO_OUT = 3.35 GHz
TA = 25°C
-80
-80
VCC = 3.6 V
VCC = 3.6 V
-100
-120
-140
-160
-100
-120
-140
-160
VCC = 3 V
VCC = 3 V
VCC = 3.3 V
VCC = 3.3 V
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G005
G006
Figure 8.
Figure 9.
TEXT
TEXT
OPEN LOOP PHASE NOISE
vs
OPEN LOOP PHASE NOISE
vs
FREQUENCY AND SUPPLY VOLTAGE
FREQUENCY AND SUPPLY VOLTAGE
-40
-60
-40
-60
F_LO_OUT = 4.05 GHz
TA = 25°C
F_LO_OUT = 4.7 GHz
TA = 25°C
VCC = 3 V
VCC = 3 V
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
VCC = 3.6 V
VCC = 3.6 V
VCC = 3.3 V
VCC = 3.3 V
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G007
G008
Figure 10.
Figure 11.
10
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
CLOSED LOOP PHASE NOISE
vs
CLOSED LOOP PHASE NOISE
vs
FREQUENCY AND TEMPERATURE
FREQUENCY AND TEMPERATURE
-40
-60
-40
-60
F_LO_OUT = 2.6 GHz
CC = 3.3, 5 V
Div 1 Mode
F_LO_OUT = 1.3 GHz
CC = 3.3, 5 V
Div 2 Mode
V
V
-80
-80
TA = 85èC
-100
-120
-140
-160
-100
-120
-140
-160
TA = -40èC
TA = 85èC
TA = -40èC
TA = 25èC
TA = 25èC
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G009
G010
Figure 12.
Figure 13.
TEXT
TEXT
CLOSED LOOP PHASE NOISE
vs
CLOSED LOOP PHASE NOISE
vs
FREQUENCY AND TEMPERATURE
FREQUENCY AND TEMPERATURE
-40
-60
-40
-60
F_LO_OUT = 650 MHz
CC = 3.3, 5 V
Div 4 Mode
F_LO_OUT = 325 MHz
CC = 3.3, 5 V
Div 8 Mode
V
V
-80
-80
TA = 25èC
-100
-120
-140
-160
-100
-120
-140
-160
TA = 85èC
TA = 25èC
TA = -40èC
TA = 85èC
TA = -40èC
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G011
G012
Figure 14.
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
CLOSED LOOP PHASE NOISE
vs
CLOSED LOOP PHASE NOISE
vs
FREQUENCY AND TEMPERATURE
FREQUENCY AND TEMPERATURE
-40
-60
-40
-60
F_LO_OUT = 3.4 GHz
CC = 3.3, 5 V
Div 1 Mode
F_LO_OUT = 1.7 GHz
CC = 3.3, 5 V
Div 2 Mode
V
V
-80
-80
TA = 85èC
TA = 85èC
-100
-120
-140
-160
-100
-120
-140
-160
TA = -40èC
TA = -40èC
TA = 25èC
TA = 25èC
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G013
G014
Figure 16.
Figure 17.
TEXT
TEXT
CLOSED LOOP PHASE NOISE
vs
CLOSED LOOP PHASE NOISE
vs
FREQUENCY AND TEMPERATURE
FREQUENCY AND TEMPERATURE
-40
-60
-40
-60
F_LO_OUT = 850 MHz
CC = 3.3, 5 V
Div 4 Mode
F_LO_OUT = 425 MHz
CC = 3.3, 5 V
Div 8 Mode
V
V
-80
-80
TA = 85èC
-100
-120
-140
-160
-100
-120
-140
-160
TA = 85èC
TA = -40èC
TA = 25èC
TA = -40èC
TA = 25èC
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G015
G016
Figure 18.
Figure 19.
12
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
CLOSED LOOP PHASE NOISE
vs
CLOSED LOOP PHASE NOISE
vs
FREQUENCY AND TEMPERATURE
FREQUENCY AND TEMPERATURE
-40
-60
-40
-60
F_LO_OUT = 4 GHz
CC = 3.3, 5 V
Div 1 Mode
F_LO_OUT = 2 GHz
CC = 3.3, 5 V
Div 2 Mode
V
V
-80
-80
TA = 85èC
TA = 85èC
-100
-120
-140
-160
-100
-120
-140
-160
TA = -40èC
TA = -40èC
TA = 25èC
TA = 25èC
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G017
G018
Figure 20.
Figure 21.
TEXT
TEXT
CLOSED LOOP PHASE NOISE
vs
CLOSED LOOP PHASE NOISE
vs
FREQUENCY AND TEMPERATURE
FREQUENCY AND TEMPERATURE
-40
-60
-40
-60
F_LO_OUT = 1 GHz
CC = 3.3, 5 V
Div 4 Mode
F_LO_OUT = 500 MHz
CC = 3.3, 5 V
Div 8 Mode
V
V
-80
-80
TA = 85èC
-100
-120
-140
-160
-100
-120
-140
-160
TA = 85èC
TA = 25èC
TA = -40èC
TA = 25èC
TA = -40èC
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G019
G020
Figure 22.
Figure 23.
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
CLOSED LOOP PHASE NOISE
vs
CLOSED LOOP PHASE NOISE
vs
FREQUENCY AND TEMPERATURE
FREQUENCY AND TEMPERATURE
-40
-60
-40
-60
F_LO_OUT = 4.6 GHz
CC = 3.3, 5 V
Div 1 Mode
F_LO_OUT = 2.3 GHz
CC = 3.3, 5 V
Div 2 Mode
V
V
-80
-80
TA = 85èC
TA = 85èC
-100
-120
-140
-160
-100
-120
-140
-160
TA = 25èC
TA = -40èC
TA = -40èC
TA = 25èC
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G021
G022
Figure 24.
Figure 25.
TEXT
TEXT
CLOSED LOOP PHASE NOISE
vs
CLOSED LOOP PHASE NOISE
vs
FREQUENCY AND TEMPERATURE
FREQUENCY AND TEMPERATURE
-40
-60
-40
-60
F_LO_OUT = 1.15 GHz
CC = 3.3, 5 V
Div 4 Mode
F_LO_OUT = 575 MHz
CC = 3.3, 5 V
Div 8 Mode
V
V
-80
-80
TA = 85èC
-100
-120
-140
-160
-100
-120
-140
-160
TA = 85èC
TA = 25èC
TA = -40èC
TA = 25èC
TA = -40èC
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G023
G024
Figure 26.
Figure 27.
14
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
NOISE AT 13-MHz OFFSET
vs
NOISE AT 13-MHz OFFSET
vs
FREQUENCY AND TEMPERATURE
WITH INTERNAL VCO
FREQUENCY AND SUPPLY VOLTAGE
WITH INTERNAL VCO
-130
-140
-150
-160
-170
-180
-190
-130
-140
-150
-160
-170
-180
-190
VCC = 3.3, 5 V
Internal VCO
PO = -10 dBm
TA = 25°C
Internal VCO
PO = -10dBm
TA = 85°C
VCC = 3 V
VCC = 3.3 V
TA = 25°C
VCC = 3.6 V
TA = -40°C
350 700 1050 1400 1750 2100 2450 2800 3150 3500
Frequency (MHz)
350 700 1050 1400 1750 2100 2450 2800 3150 3500
Frequency (MHz)
G025
G026
Figure 28.
Figure 29.
TEXT
TEXT
NOISE AT 13-MHz OFFSET
vs
NOISE AT 13-MHz OFFSET
vs
FREQUENCY AND TEMPERATURE
WITH EXTERNAL VCO
FREQUENCY AND SUPPLY VOLTAGE
WITH EXTERNAL VCO
-130
-140
-150
-160
-170
-180
-190
-130
-140
-150
-160
-170
-180
-190
VCC = 3.3, 5 V
External VCO
PO = -10dBm
TA = 25°C
External VCO
PO = -10dBm
TA = 85°C
VCC = 3.3 V
VCC = 3.6 V
TA = 25°C
VCC = 3 V
TA = -40°C
350 700 1050 1400 1750 2100 2450 2800 3150 3500
Frequency (MHz)
350 700 1050 1400 1750 2100 2450 2800 3150 3500
Frequency (MHz)
G027
G028
Figure 30.
Figure 31.
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
NOISE AT 13-MHz OFFSET
vs
VOLTAGE GAIN
vs
OUTPUT POWER AND FREQUENCY
FREQUENCY AND TEMPERATURE
-130
-135
-140
-145
-150
-155
-160
-165
-170
-175
-180
2
1
VCC = 3.3, 5 V
TA = 25°C
f = 2140 MHz
f = 3500 MHz
f = 2700 MHz
0
-1
-2
-3
-4
-5
-6
-7
TA = 25°C
TA = -40°C
f = 900 MHz
f = 750 MHz
f = 450 MHz
TA = 85°C
-15
-10
-5
0
5
10
300 800 1300 1800 2300 2800 3300 3800 4300 4800
Frequency (MHz)
Output Power (dBm)
G029
G030
Figure 32.
Figure 33.
TEXT
TEXT
VOLTAGE GAIN
vs
VOLTAGE GAIN
vs
FREQUENCY AND TEMPERATURE at 750 MHz
FREQUENCY AND TEMPERATURE at 900 MHz
-3
-3.1
-3.2
-3.3
-3.4
-3.5
-3.2
-3.25
-3.3
TA = 25°C
TA = -40°C
-3.35
-3.4
TA = -40°C
TA = 85°C
-3.45
-3.5
TA = 25°C
TA = 85°C
-3.55
-3.6
720 725 730 735 740 745 750 755 760 765 770
Frequency (MHz)
880
885
890
895
900
905
910
915
920
Frequency (MHz)
G031
G032
Figure 34.
Figure 35.
16
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
VOLTAGE GAIN
VOLTAGE GAIN
vs
vs
FREQUENCY AND TEMPERATURE at 1500 MHz
FREQUENCY AND TEMPERATURE at 2150 MHz
-3.6
-3.7
-3.8
-3.9
-4
-3.4
-3.5
-3.6
-3.7
-3.8
-3.9
-4
TA = -40°C
TA = -40°C
TA = 25°C
-4.1
-4.2
-4.3
-4.4
-4.1
-4.2
-4.3
TA = 25°C
TA = 85°C
TA = 85°C
1465 1470 1475 1480 1485 1490 1495 1500 1505 1510
Frequency (MHz)
2100
2110
2120
2130
Frequency (MHz)
2140
2150
2160
2170
G033
G034
Figure 36.
Figure 37.
TEXT
TEXT
VOLTAGE GAIN
VOLTAGE GAIN
vs
vs
FREQUENCY AND TEMPERATURE at 2650 MHz
COMMON-MODE VOLTAGE AND FREQUENCY
-2.7
-2.8
-2.9
-3
-2.4
-2.6
-2.8
-3
f = 2700 MHz
TA = -40°C
f = 750 MHz
TA = 25°C
-3.2
-3.4
-3.6
-3.8
-4
f = 900 MHz
-3.1
-3.2
-3.3
-3.4
-3.5
f = 2150 MHz
TA = 85°C
-4.2
f = 1500 MHz
-4.4
2610 2620 2630 2640 2650 2660 2670 2680 2690
Frequency (MHz)
1.55
1.6
1.65
1.7
1.75
1.8
1.85
1.9
Common-Mode Voltage (V)
G035
G036
Figure 38.
Figure 39.
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
VOLTAGE GAIN
VOLTAGE GAIN
vs
vs
BASEBAND VOLTAGE AMPLITUDE AND FREQUENCY
FREQUENCY AND SUPPLY VOLTAGE
-2.5
1
0
f = 2700 MHz
-2.7
-2.9
-3.1
-3.3
-3.5
-3.7
-3.9
-4.1
-4.3
-4.5
f = 750 MHz
-1
-2
-3
-4
-5
f = 900 MHz
f = 2150 MHz
VCC = 3.3 V
VCC = 3.6 V
f = 1500 MHz
VCC = 3 V
BB Voltage is Single-Ended RMS
0
100 200 300 400 500 600 700 800 900 1000
Baseband Voltage Amplitude (mV)
300 800 1300 1800 2300 2800 3300 3800 4300 4800
Frequency (MHz)
G037
G038
Figure 40.
Figure 41.
TEXT
TEXT
P1dB
P1dB
vs
vs
FREQUENCY AND TEMPERATURE
FREQUENCY AND TEMPERATURE at 750 MHz
15
14
13
12
11
10
9
11.3
11.2
11.1
11
TA = 25°C
TA = 25°C
TA = 85°C
10.9
10.8
10.7
10.6
10.5
TA = 85°C
TA = -40°C
8
7
TA = -40°C
6
5
300 800 1300 1800 2300 2800 3300 3800 4300 4800
Frequency (MHz)
700 710 720 730 740 750 760 770 780 790 800
Frequency (MHz)
G039
G040
Figure 42.
Figure 43.
18
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
P1dB
P1dB
vs
vs
FREQUENCY AND TEMPERATURE at 900 MHz
FREQUENCY AND TEMPERATURE at 1500 MHz
11.4
11.3
11.2
11.1
11
11.5
11.4
11.3
11.2
11.1
11
TA = 25°C
TA = 25°C
TA = 85°C
TA = 85°C
10.9
10.8
10.7
10.6
10.5
10.9
10.8
10.7
10.6
10.5
TA = -40°C
TA = -40°C
850 860 870 880 890 900 910 920 930 940 950
Frequency (MHz)
1450 1460 1470 1480 1490 1500 1510 1520 1530 1540 1550
Frequency (MHz)
G041
G042
Figure 44.
Figure 45.
TEXT
TEXT
P1dB
P1dB
vs
vs
FREQUENCY AND TEMPERATURE at 2150 MHz
FREQUENCY AND TEMPERATURE at 2700 MHz
12.2
12
12.6
12.4
12.2
12
TA = 25°C
TA = 25°C
11.8
11.6
11.4
11.2
11
TA = -40°C
11.8
11.6
11.4
11.2
11
TA = -40°C
TA = 85°C
TA = 85°C
10.8
2100 2110 2120 2130 2140 2150 2160 2170 2180 2190 2200
Frequency (MHz)
2650 2660 2670 2680 2690 2700 2710 2720 2730 2740 2750
Frequency (MHz)
G043
G044
Figure 46.
Figure 47.
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
P1dB
P1dB
vs
vs
COMMON-MODE VOLTAGE AND FREQUENCY
FREQUENCY AND SUPPLY VOLTAGE
14
13
12
11
10
9
15
14
13
12
11
10
9
f = 2700 MHz
f = 2150 MHz
VCC = 3.6 V
VCC = 3.3 V
f = 1500 MHz
f = 900 MHz
VCC = 3 V
8
f = 750 MHz
7
8
6
1.55
1.6
1.65
1.7
1.75
1.8
1.85
1.9
300 800 1300 1800 2300 2800 3300 3800 4300 4800
Frequency (MHz)
Common-Mode Voltage (V)
G045
G046
Figure 48.
Figure 49.
TEXT
TEXT
OIP3
vs
OIP3
vs
FREQUENCY AND TEMPERATURE
TEMPERATURE AND FREQUENCY at 900 MHz
34
32
30
28
26
24
22
20
18
16
14
28
27.5
27
TA = -40°C
TA = 25°C
TA = -40°C
26.5
26
TA = 85°C
TA = 25°C
25.5
25
TA = 85°C
24.5
24
300 800 1300 1800 2300 2800 3300 3800 4300 4800
Frequency (MHz)
880
885
890
895
900
905
910
915
920
Frequency (MHz)
G047
G048
Figure 50.
Figure 51.
20
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
OIP3
OIP3
vs
vs
FREQUENCY AND TEMPERATURE at 1030 MHz
FREQUENCY AND TEMPERATURE at 1650 MHz
28
27.5
27
26
25.5
25
TA = 25°C
TA = -40°C
TA = -40°C
26.5
26
24.5
24
TA = 25°C
25.5
25
23.5
23
TA = 85°C
TA = 85°C
24.5
22.5
24
22
1000 1005 1010 1015 1020 1025 1030 1035 1040
Frequency (MHz)
1620 1625 1630 1635 1640 1645 1650 1655 1660 1665 1670
Frequency (MHz)
G049
G050
Figure 52.
Figure 53.
TEXT
TEXT
OIP3
OIP3
vs
vs
FREQUENCY AND TEMPERATURE at 2850 MHz
FREQUENCY AND TEMPERATURE at 2300 MHz
30
29
28
27
26
25
24
23
27
26
25
24
23
22
21
TA = -40°C
TA = 25°C
TA = -40°C
TA = 25°C
TA = 85°C
TA = 85°C
2260
2270
2280
2290
2300
2310
2320
2770 2780 2790 2800 2810 2820 2830 2840 2850
Frequency (MHz)
Frequency (MHz)
G051
G052
Figure 54.
Figure 55.
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
OIP3
OIP3
vs
vs
BASEBAND VOLTAGE AMPLITUDE AND FREQUENCY
COMMON-MODE VOLTAGE AND FREQUENCY
29
28
27
26
25
24
23
22
21
30
29
28
27
26
25
24
23
22
21
20
f = 900 MHz
f = 900 MHz
f = 2700 MHz
f = 2150 MHz
f = 2700 MHz
f = 2150 MHz
f = 750 MHz
f = 1500 MHz
f = 1500 MHz
f = 750 MHz
TA = 25°C
BB Voltage is Single-Ended RMS
1.5
1.55
1.6
1.65
1.7
1.75
Common-Mode Voltage (V)
1.8
1.85
1.9
0
100 200 300 400 500 600 700 800 900 1000
Baseband Voltage Amplitude (mV)
G053
G083
Figure 56.
Figure 57.
TEXT
TEXT
OIP2
vs
OIP2
vs
FREQUENCY AND TEMPERATURE
FREQUENCY AND TEMPERATURE at 750 MHz
70
58
65
60
55
50
45
40
35
30
57.5
57
TA = -40°C
TA = 85°C
TA = 25°C
56.5
56
TA = 25°C
TA = 85°C
TA = -40°C
55.5
55
300 800 1300 1800 2300 2800 3300 3800 4300 4800
Frequency (MHz)
730
735
740
745
750
755
760
765
770
Frequency (MHz)
G054
G055
Figure 58.
Figure 59.
22
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
OIP2
OIP2
vs
vs
FREQUENCY AND TEMPERATURE at 900 MHz
FREQUENCY AND TEMPERATURE at 1500 MHz
58
57.5
57
58
57.5
57
TA = -40°C
TA = 85°C
TA = 25°C
56.5
56
56.5
56
55.5
55
TA = 25°C
TA = 85°C
55.5
55
TA = -40°C
54.5
54
880
885
890
895
900
905
910
915
920
1470 1475 1480 1485 1490 1495 1500 1505 1510
Frequency (MHz)
Frequency (MHz)
G056
G057
Figure 60.
Figure 61.
TEXT
TEXT
OIP2
vs
OIP2
vs
FREQUENCY AND TEMPERATURE at 2150 MHz
FREQUENCY AND TEMPERATURE at 2650 MHz
57
56.5
56
54
53
52
51
50
49
48
47
46
TA = 85°C
TA = -40°C
TA = 25°C
55.5
55
54.5
54
TA = 25°C
TA = -40°C
TA = 85°C
53.5
53
2100 2110 2120 2130 2140 2150 2160 2170 2180
Frequency (MHz)
2620
2630
2640
2650
Frequency (MHz)
2660
2670
2680
2690
G058
G059
Figure 62.
Figure 63.
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
UNADJUSTED SIDEBAND SUPPRESSION
UNADJUSTED SIDEBAND SUPPRESSION
vs
vs
FREQUENCY AND TEMPERATURE
FRQUENCY AND TEMPERATURE at 900 MHz
55
50
45
40
35
30
25
46.5
TA = 85°C
TA = 25°C
TA = -40°C
46
TA = 85°C
45.5
TA = 25°C
TA = -40°C
45
880
300 800 1300 1800 2300 2800 3300 3800 4300 4800
Frequency (MHz)
885
890
895
900
905
910
915
920
Frequency (MHz)
G060
G061
Figure 64.
Figure 65.
TEXT
TEXT
UNADJUSTED SIDEBAND SUPPRESSION
UNADJUSTED SIDEBAND SUPPRESSION
vs
vs
FREQUENCY AND TEMPERATURE at 1030 MHz
FREQUENCY AND TEMPERATURE at 1650 MHz
47
46.5
46
43
42.5
42
TA = -40°C
TA = -40°C
45.5
45
41.5
41
TA = 85°C
TA = 25°C
44.5
44
40.5
40
TA = 85°C
TA = 25°C
43.5
39.5
43
39
1000 1005 1010 1015 1020 1025 1030 1035 1040
Frequency (MHz)
1610
1620
1630
1640
1650
1660
1670
Frequency (MHz)
G062
G063
Figure 66.
Figure 67.
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
UNADJUSTED SIDEBAND SUPPRESSION
UNADJUSTED SIDEBAND SUPPRESSION
vs
vs
FREQUENCY AND TEMPERATURE at 2300 MHz
FREQUENCY AND TEMPERATURE at 2850 MHz
37
36
35
34
33
32
31
30
44
43
42
41
40
39
TA = -40°C
TA = 85°C
TA = -40°C
TA = 25°C
TA = 25°C
TA = 85°C
2250 2260 2270 2280 2290 2300 2310 2320 2330
Frequency (MHz)
2760 2770 2780 2790 2800 2810 2820 2830 2840 2850
Frequency (MHz)
G064
G065
Figure 68.
TEXT
Figure 69.
TEXT
UNADJUSTED CARRIER SUPPRESSION
UNADJUSTED SIDEBAND SUPPRESSION
vs
vs
FRQUENCY AND TEMPERATURE
COMMON-MODE VOLTAGE AND FREQUENCY
-21
-24
-27
-30
-33
-36
-39
-42
-45
-48
-51
50
48
46
44
42
40
38
36
34
TA = 25°C
f = 750 MHz
TA = -40°C
TA = 25°C
f = 2700 MHz
f = 900 MHz
f = 1500 MHz
f = 2150 MHz
TA = 85°C
300 800 1300 1800 2300 2800 3300 3800 4300 4800
Frequency (MHz)
1.55
1.6
1.65
1.7
1.75
1.8
1.85
1.9
Common-Mode Voltage (V)
G066
G067
Figure 70.
Figure 71.
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
UNADJUSTED CARRIER SUPPRESSION
UNADJUSTED CARRIER SUPPRESSION
vs
vs
FREQUENCY AND TEMPERATURE at 900 MHz
FRQUENCY AND TEMPERATURE at 1030 MHz
-41
-41.5
-42
-42
-42.5
-43
TA = 25°C
TA = -40°C
TA = 25°C
-42.5
-43
-43.5
-44
-43.5
-44
-44.5
-45
TA = -40°C
-44.5
-45
TA = 85°C
TA = 85°C
-45.5
-45.5
-46
-46
880
885
890
895
900
905
910
915
920
990
1000
1010
1020
1030
1040
1050
Frequency (MHz)
Frequency (MHz)
G068
G069
Figure 72.
Figure 73.
TEXT
TEXT
UNADJUSTED CARRIER SUPPRESSION
vs
UNADJUSTED CARRIER SUPPRESSION
vs
FREQUENCY AND TEMPERATURE at 1650 MHz
FREQUENCY AND TEMPERATURE at 2300 MHz
-43
-43.5
-44
-35
-36
-37
-38
-39
-40
-41
-42
-43
-44
-45
TA = -40°C
TA = 25°C
TA = 85°C
-44.5
-45
-45.5
-46
TA = 25°C
TA = 85°C
-46.5
TA = -40°C
-47
1610
1620
1630
1640
1650
1660
1670
2250 2260 2270 2280 2290 2300 2310 2320 2330
Frequency (MHz)
Frequency (MHz)
G070
G071
Figure 74.
Figure 75.
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
UNADJUSTED CARRIER SUPPRESSION
UNADJUSTED CARRIER SUPPRESSION
vs
vs
FREQUENCY AND TEMPERATURE at 2850 MHz
COMMON- MODE VOLTAGE AND FREQUENCY
-34
-36
-38
-40
-42
-44
-46
-48
-50
-52
-39
-40
-41
-42
-43
-44
-45
-46
-47
-48
-49
TA = -40°C
f = 2150 MHz
f = 2700 MHz
TA = 25°C
TA = 85°C
f = 900 MHz
f = 1500 MHz
f = 750 MHz
TA = 25°C
2760 2770 2780 2790 2800 2810 2820 2830 2840 2850
Frequency (MHz)
1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95
Common-Mode Voltage (V)
2
G073
G072
Figure 76.
Figure 77.
TEXT
TEXT
COMMON-MODE VOLTAGE
BASEBAND VOLTAGE OFFSET
vs
vs
VREF_SEL SETTING AND TEMPERATURE
IOFF SETTING AND TEMPERATURE
2
1.9
1.8
1.7
1.6
1.5
1.4
20
TA = -40°C
TA = 25°C
TA = 85°C
15
10
5
TA = 25°C
0
DCOFFSET_I = 1
-5
TA = -40°C
-10
-15
-20
-25
-30
TA = 85°C
DCOFFSET_I = 3
0
1
2
3
4
5
6
7
0
30
60
90
120
150
180
210
240
VREF_SEL Setting
IOFF Setting
G074
G075
Figure 78.
Figure 79.
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
TEXT
GAIN at 2300 MHz DISTRIBUTION
P1dB at 2300 MHz DISTRIBUTION
20
18
16
14
12
10
8
40
35
30
25
20
15
10
5
6
4
2
0
0
Voltage Gain (dB)
P1dB (dBm)
G078
G079
Figure 80.
Figure 81.
TEXT
TEXT
OIP3 at 2300 MHz DISTRIBUTION
UNADJUSTED CARRIER SUPPRESSION
at 2300 MHz DISTRIBUTION
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
0
0
OIP3 (dBm)
G080
Unadjusted Carrier Suppression (dBm)
G081
Figure 82.
Figure 83.
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TYPICAL CHARACTERISTICS (continued)
VCM = 1.7 V (internal), VinBB = 300 mVrms single-ended sine wave in quadrature, VCC3V = 3.3 V, VCC5V = 5 V, fBB = 4.5 MHz
and 5.5 MHz, internal LO, TA = 25°C; FPFD = 1.6 MHz (unless otherwise noted).
TEXT
UNADJUSTED SIDEBAND SUPPRESSION
at 2300 MHz DISTRIBUTION
45
40
35
30
25
20
15
10
5
0
Unadjusted Sideband Suppression (dBc)
G082
Figure 84.
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SERIAL INTERFACE PROGRAMMING REGISTERS DEFINITION
The TRF372017 features a 3-wire serial programming interface (SPI) that controls an internal 32-bit shift register.
There are a total of 3 signals that need to be applied: the clock (CLK, pin 47), the serial data (DATA, pin 46) and
the latch enable (LE, pin 45). The TRF372017 has an additional pin (RDBK, pin 2) for read-back functionality.
This pin is a digital pin and can be used to read-back values of different internal registers.
The DATA (DB0-DB31) is loaded LSB first and is read on the rising edge of the CLOCK. The LE is
asynchronous to the CLOCK and at its rising edge the data in the shift register gets loaded onto the selected
internal register. The 5 LSB of the Data field are the address bits to select the available internal registers.
PLL SPI REGISTERS
Register 1
Register address
Bit1 Bit2 Bit3
Reference Clock Divider
Bit0
Bit4
VCO
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
RSV
….
RSV
REF
INV
Charge Pump Current
CP
VCO Cal CLK div/Mult
NEG
DOUBLE
Bit16 Bit17 Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
Register 1
Bit0
Name
Reset Value
Description
Register address bits
ADDR_0
ADDR_1
ADDR_2
ADDR_3
ADDR_4
RDIV_0
RDIV_1
RDIV_2
RDIV_3
RDIV_4
RDIV_5
RDIV_6
RDIV_7
RDIV_8
RDIV_9
RDIV_10
RDIV_11
RDIV_12
RSV
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
1
0
Bit1
Bit2
Bit3
Bit4
Bit5
13-bit Reference Divider value
(minimum value Rmin= 1, B[17..5] = [00 0000 0000 001];
maximum value Rmax=8191, B[17..5] = [11 1111 1111 111];
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
REF_INV
NEG_VCO
ICP_0
Invert Reference Clock polarity; 1 = use falling edge
VCO polarity control; 1= negative slope (negative Kv)
Program Charge Pump dc current, ICP
1.94mA, B[25..21] = [00 000]
0.47mA, B[25..21] = [11 111]
ICP_1
0.97mA, default value, , B[25..21] = [01 010]
ICP_2
ICP_3
ICP_4
ICPDOUBLE
1 = set ICP to double the current
CAL_CLK_SEL_0
CAL_CLK _SEL_1
CAL_CLK _SEL_2
CAL_CLK _SEL_3
RSV
Multiplication or division factor to create VCO calibration clock from PFD frequency
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CAL_CLK_SEL[3..0]: Set the frequency divider value used to derive the VCO calibration clock from the phase
detector frequency
CAL_CLK_SEL
1111
Scaling Factor
1/128
1/64
1/32
1/16
1/8
1/4
½
1110
1101
1100
1011
1010
1001
1000
1
0110
2
0101
4
0100
8
0011
16
0010
32
0001
64
0000
128
ICP[4..0]: Set the charge pump current
ICP[4..0]
00 000
00 001
00 010
00 011
00 100
00 101
00 110
00 111
01 000
01 001
01 010
01 011
01 100
01 101
01 110
01 111
10 000
10 001
10 010
10 011
10 100
10 101
10 110
10 111
11 000
11 001
11 010
11 011
Current (mA)
1.94
1.76
1.62
1.49
1.38
1.29
1.21
1.14
1.08
1.02
0.97
0.92
0.88
0.84
0.81
0.78
0.75
0.72
0.69
0.67
0.65
0.63
0.61
0.59
0.57
0.55
0.54
0.52
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ICP[4..0]
11 100
11 101
11 110
11 111
Current (mA)
0.51
0.5
0.48
0.47
Register 2
Register address
N-divider value
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
CAL
...
PLL divider
setting
Prescaler RSV
Select
RSV
VCO select
FCO
sel
Cal accuracy
mode
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24 Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
Register 2 Name
Reset Value Description
Register address bits
Bit0
Bit1
ADDR_0
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
ADDR_1
ADDR_2
ADDR_3
ADDR_4
NINT_0
NINT_1
NINT_2
NINT_3
NINT_4
NINT_5
NINT_6
NINT_7
NINT_8
NINT_9
NINT_10
NINT_11
NINT_12
NINT_13
NINT_14
NINT_15
Bit2
Bit3
Bit4
Bit5
PLL N-divider division setting
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
PLL_DIV_SEL0
PLL_DIV_SEL1
PRSC_SEL
RSV
Select division ratio of divider in front of prescaler
Set prescaler modulus (0 → 4/5; 1 → 8/9)
RSV
VCO_SEL_0
Selects between the four integrated VCO's
00 = lowest frequency VCO; 11 = highest frequency VCO
Bit27
Bit28
Bit29
Bit30
Bit31
VCO_SEL_1
VCOSEL_MODE
CAL_ACC_0
CAL_ACC_1
EN_CAL
1
0
0
0
0
Single VCO auto-calibration mode (1 = active)
Error count during the cap array calibration
Recommended programming [00]
Execute a VCO frequency auto-calibration. Set to 1 to initiate a calibration. Resets
automatically.
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PLL_DIV<1,0>: Select division ratio of divider in front of prescaler
PLL DIV
Frequency Divider
00
01
10
1
2
4
VCOSEL_MODE<0>: when it is 1, the cap array calibration is run on the VCO selected through bits
VCO_SEL<2,1>
Register 3
Register address
Fractional N-divider value…
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit28
Bit13
Bit29
Bit14
Bit15
...
RSV
RSV
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit30
Bit31
Register 3 Name
Reset Value
Description
Register address bits
Bit0
Bit1
ADDR_0
ADDR_1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit2
ADDR_2
Bit3
ADDR_3
Bit4
ADDR_4
Bit5
NFRAC<0>
NFRAC<1>
NFRAC<2>
NFRAC<3>
NFRAC<4>
NFRAC<5>
NFRAC<6>
NFRAC<7>
NFRAC<8>
NFRAC<9>
NFRAC<10>
NFRAC<11>
NFRAC<12>
NFRAC<13>
NFRAC<14>
NFRAC<15>
NFRAC<16>
NFRAC<17>
NFRAC<18>
NFRAC<19>
NFRAC<20>
NFRAC<21>
NFRAC<22>
NFRAC<23>
NFRAC<24>
RSV
Fractional PLL N divider value 0 to 0.99999.
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
RSV
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Register 4
Register address
PD
Power Down PLL blocks
PD
PLL
VCM
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
PD DC EXT
PLL Test Control
ΣΔ Mode order
ΣΔ Mode controls
EN
off
VCO
Bit17
Fract
mode
Bit16
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
Register 4 Name
Reset Value
Description
Bit0
Bit1
ADDR_0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
Register address bits
ADDR_1
ADDR_2
ADDR_3
ADDR_4
PWD_PLL
PWD_CP
PWD_VCO
Bit2
Bit3
Bit4
Bit5
Power down all PLL blocks (1 = off)
When 1, charge pump is off
When 1, VCO is off
Bit6
Bit7
Bit8
PWD_VCOMUX
PWD_DIV124
PWD_PRESC
RSV
Power down the 4 VCO mux block (1 = Off)
Bit9
Power down programmable RF divider in PLL feedback path (1 = off)
Power down programmable prescaler (1 = off)
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
PWD_OUT_BUFF
PWD_LO_DIV
PWD_TX_DIV
PWD_BB_VCM
PWD_DC_OFF
EN_EXTVCO
EN_ISOURCE
Power down LO output buffer (1 = off).
Power down frequency divider in LO output chain 1 (1 = off)
Power down frequency divider in modulator chain (1 = off)
Power down baseband input DC common block (1 = off)
Power down baseband input DC offset control block (1 = off)
Enable external LO/VCO input buffer (1 = enabled)
Enable offset current at Charge Pump output (to be used in fractional mode only, 1 =
on).
Bit19
Bit20
Bit21
Bit22
LD_ANA_PREC_0
LD_ANA_PREC_1
CP_TRISTATE_0
CP_TRISTATE_1
0
0
0
0
Control precision of analog lock detector (1 1 = low; 0 0 = high). See LOCK DETECT
section of Application Information for usage details.
Set the charge pump output in Tristate mode.
Normal, B[22..21] = [00]
Down, B[22..21] = [01]
Up, B[22..21] = [10]
Tristate, B[22..21] = [11]
Bit23
Bit24
Bit25
Bit26
Bit27
SPEEDUP
0
0
1
0
1
Speed up PLL and Tx blocks by bypassing bias stabilizer capacitors.
Lock detector precision (increases sampling time if set to 1)
Enable ΔΣ modulator dither (1=on)
LD_DIG_PREC
EN_DITH
MOD_ORD_0
MOD_ORD_1
ΔΣ modulator order (1 through 4). Not used in integer mode.
1st order, B[27..26] = [00]
2nd order, B[27..26] = [01]
3rd order, B[27..26] = [10]
4th order, B[27..26] = [11]
Bit28
Bit29
Bit30
DITH_SEL
0
0
1
Select dither mode for ΔΣ modulator (0 = const; 1 = pseudo-random)
DEL_SD_CLK_0
DEL_SD_CLK_1
ΔΣ modulator clock delay. Not used in integer mode.
Min delay = 00
Max delay = 11
Bit31
EN_FRAC
0
Enable fractional mode (1 = fractional enabled)
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Register 5
Register address
Bit1 Bit2 Bit3
VCO_R Trim
Bit6
PLL_R_Trim
Bit8 Bit9
VCO Current
Bit11 Bit12
VCOBUF BIAS
Bit14 Bit15
Bit0
VCOMUX BIAS OUTBUF BIAS
Bit4
Bit5
RSV
Bit7
VCO CAL REF
Bit10
Bit13
BIAS
SEL
VCOMUX
VCO Bias
RSV EN_LD
ISRC
AMPL Voltage
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26 Bit27 Bit28 Bit29
Bit30
Bit31
Register 5 Name
Reset Value
Description
Register address bits
Bit0
Bit1
ADDR_0
1
0
1
1
0
0
0
1
0
1
0
0
0
1
ADDR_1
ADDR_2
ADDR_3
ADDR_4
Bit2
Bit3
Bit4
Bit5
VCOBIAS_RTRIM_0
VCOBIAS_RTRIM_1
VCOBIAS_RTRIM_2
PLLBIAS_RTRIM_0
PLLBIAS_RTRIM_1
VCO_BIAS_0
VCO bias resistor trimming. Recommended programming [100].
PLL bias resistor trimming. Recommended programming [10].
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
VCO bias reference current.
300 µA, B[13..10] = [00 00]
600 µA, B[13..10] = [11 11]
Bias current varies directly with reference current
Recommended programming
VCO_BIAS_1
VCO_BIAS_2
VCO_BIAS_3
400 µA, B[13..10] = [0101] with VCC_VCO2 = 3.3 V
600 µA, B[13..10] = [1111] with VCC_VCO2 = 5.0 V
Bit14
Bit15
VCOBUF_BIAS_0
VCOBUF_BIAS_1
0
1
VCO buffer bias reference current.
300 µA, B[15..14] = [00]
600 µA, B[15..14] = [11]
Bias current varies directly with reference current
Recommended programming [10]
Bit16
Bit17
VCOMUX_BIAS_0
VCOMUX_BIAS_1
0
1
VCO’s muxing buffer bias reference current.
300 µA, B[17..16] = [00]
600 µA, B[17..16] = [11]
Bias current varies directly with reference current
Recommended programming [11]
Bit18
Bit19
BUFOUT_BIAS_0
BUFOUT_BIAS_1
0
1
PLL output buffer bias reference current.
300 µA, B[19..18] = [00]
600 µA, B[19..18] = [11]
Bias current varies directly with reference current
Bit20
Bit21
Bit22
RSV
0
1
0
RSV
VCO_CAL_IB
Select bias current type for VCO calibration circuitry
0 = PTAT; 1 = constant over temperature
Recommended programming [0]
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
VCO_CAL_REF_0
VCO_CAL_REF_1
VCO_CAL_REF_2
VCO_AMPL_CTRL_0
VCO_AMPL_CTRL_1
VCO_VB_CTRL_0
VCO_VB_CTRL _1
0
0
1
0
1
0
1
VCO calibration reference voltage trimming.
0.9 V, B[25..23] = [000]
1.4 V, B[25..23] = [111]
Recommended programming [010]
Adjust the signal amplitude at the VCO mux input
Recommended programming [11]
VCO core bias voltage control
1.2 V, B[29..28] = [00]
1.35 V, B[29..28] = [01]
1.5 V, B[29..28] = [10]
1.65 V, B[29..28] = [11]
Recommended programming [00]
Bit30
RSV
0
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Register 5 Name
Reset Value
Description
Bit31
EN_LD_ISOURCE
1
Enable monitoring of LD to turn on Isource when in frac-n mode (EN_FRAC=1).
0 = ISource set by EN_ISOURCE.
1 = ISource set by LD.
Recommended programming [0]
Register 6
Register address
BB DC OFFSET
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
TXDIV SEL
Bit24 Bit25
Bit9
Bit10
LODIV SEL
Bit26 Bit27
Bit11
Bit12
TXDIV BIAS
Bit28 Bit29
Bit13
Bit14
LODIV BIAS
Bit30 Bit31
Bit15
BB DC OFFSET
VREF SEL
Bit22
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit23
Register 6 Name
Reset Value Description
Register address bits
Bit0
Bit1
ADDR_0
0
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
ADDR_1
ADDR_2
ADDR_3
ADDR_4
IOFF_0
Bit2
Bit3
Bit4
Bit5
Adjust Iref current used for defining I DC offset.
Full range, 2 × Iref, B[12..5] = [1 1111 111]
Mid scale, Iref B[12..5] = [1 0000 000]
Bit6
IOFF_1
Bit7
IOFF_2
Bit8
IOFF_3
Bit9
IOFF_4
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
IOFF_5
IOFF_6
IOFF_7
QOFF_0
QOFF_1
QOFF_2
QOFF_3
QOFF_4
QOFF_5
QOFF_6
QOFF_7
VREF_SEL_0
VREF_SEL_1
VREF_SEL_2
Adjust Iref current used for defining Q DC offset.
Full range, 2 × Iref, B[20..13] = [1 1111 111]
Mid scale, Iref B[20..13] = [1 0000 000]
Adjust Vref in baseband common mode generation circuit.
0.65 V, B[23..21] = [000]
1 V, B[23..21] = [111]
Modulator common mode is Vref + Vbe.
Recommended programming [100]
Bit24
Bit25
TX_DIV_SEL_0
TX_DIV_SEL_1
0
0
Adjust Tx path divider.
Div1, [B25..24] = [00]
Div2, [B25..24] = [01]
Div4, [B25..24] = [10]
Div8, [B25..24] = [11]
Bit26
Bit27
LO_DIV_SEL_0
LO_DIV_SEL_1
0
0
Adjust LO path divider
Div1, [B28..27] = [00]
Div2, [B28..27] = [01]
Div4, [B28..27] = [10]
Div8, [B28..27] = [11]
Bit28
Bit29
TX_DIV_BIAS_0
TX_DIV_BIAS_1
0
1
TX divider bias reference current
25 µA, [B29..28] = [00]
37.5 µA, [B29..28] = [01]
50 µA, [B29..28] = [10]
62.5 µA, [B29..28] = [11]
Bias current varies directly with reference current
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Register 6 Name
Reset Value Description
Bit30
Bit31
LO_DIV_BIAS_0
0
1
LO divider bias reference current
25 µA, [B29..28] = [00]
37.5 µA, [B29..28] = [01]
50 µA, [B29..28] = [10]
62.5 µA, [B29..28] = [11]
LO_DIV_BIAS_1
Bias current varies directly with reference current
Register 7
Register address
VCO CAP ARRAY CONTROL
RSV
VCO
test
CAL
bypass
mode
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
MUX CONTROL
ISRC
SINK
OFFSET CURRENT
ADJUST
LP PD
VCM
Bias
MIX LO VCM
DC OFF REF
VCO
BIAS
SEL
TimeConst
Bit23 Bit24
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
Register 7 Name
Reset Value
Description
Register address bits
Bit0
Bit1
ADDR_0
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
ADDR_1
ADDR_2
ADDR_3
ADDR_4
RSV
Bit2
Bit3
Bit4
Bit5
Bit6
RSV
Bit7
VCO_TRIM_0
VCO_TRIM_1
VCO_TRIM_2
VCO_TRIM_3
VCO_TRIM_4
VCO_TRIM_5
RSV
VCO capacitor array control bits, used in manual cal mode
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
VCO_TEST_MODE
CAL_BYPASS
Counter mode: measure max/min frequency of each VCO
Bypass of VCO auto-calibration. When ‘1’ VCO_TRIM and VCO_SEL bits are
used to select the VCO and the cap array setting
Bit16
Bit17
Bit18
MUX_CTRL_0
MUX_CTRL_1
MUX_CTRL_2
1
0
0
Select signal for test output (pin 5, LD).
[000] = Ground
[001] = Lock detector
[010] = NDIV counter output
[011] = Ground
[100] = RDIV counter output
[101] = Ground
[110] = A_counter output
[111] = Logic high;
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
ISOURCE_SINK
ISOURCE_TRIM_0
ISOURCE_TRIM_1
ISOURCE_TRIM_2
PD_TC_0
0
0
0
1
0
0
Charge pump offset current polarity.
Adjust isource bias current in frac-n mode.
Time constant control for PWD_OUT_BUFF
[00] = Minimum time constant
[11] = Maximum time constant
PD_TC_1
Bit25
IB_VCM_SEL
0
Select constant/ptat current for Common mode bias generation block
0 = PTAT
1 = const
Bit26
RSV
0
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Register 7 Name
Reset Value
Description
Bit27
Bit28
Bit29
Bit30
RSV
0
1
0
1
RSV
DCOFFSET_I_0
DCOFFSET_I_1
Adjust BB input DC offset Iref
50 µA, B[27..26] = [00]
100 µA, B[27..26] = [01]
150 µA, B[27..26] = [10]
200 µA, B[27..26] = [11]
Bit31
VCO_BIAS_SEL
0
Select VCO_BIAS trim settings stored in EEPROM
0 = Use EEPROM settings if parity check is 1; otherwise, use SPI settings
1 = Use SPI settings
Recommended programming [1]
READBACK MODE
Register 0 functions as a Readback register. TRF372017 implements the capability to read-back the content of
any serial programming interface register by initializing register 0.
Each read-back is composed by two phases: writing followed by the actual reading of the internal data. This is
shown in the timing diagram in Figure 3. During the writing phase a command is sent to TRF372017 register 0 to
set it in read-back mode and to specify which register is to be read. In the proper reading phase, at each rising
clock edge, the internal data is transferred into the RDBK pin and can be read at the following falling edge (LSB
first). The first clock after the LE goes high (end of writing cycle) is idle and the following 32 clocks pulses will
transfer the internal register content to the RDBK pin.
Readback From the Internal Registers Banks
TRF372017 integrates 8 registers: Register 0 (000) to Register 7 (111). Registers 1 through 7 are used to set-up
and control the TRF372017 functionalities, while register 0 is used for the readback function.
The latter register needs to be programmed with a specific command that sets TRF372017 in read-back mode
and specifies the register to be read:
•
•
•
set B[31] to 1 to put TRF372017 in read-back mode.
set B[30,28] equal to the address of the register to be read (000 to 111).
Set B27 to control the VCO frequency counter in VCO test mode.
Register 0 Write
Name
ADDR<0>
ADDR<1>
ADDR<2>
ADDR<3>
ADDR<4>
N/C
Reset Value
Description
Address
Bits
B0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register 0 to be programmed to set TRF372017 in readback mode.
B1
B2
B3
B4
Data Field
B5
B6
N/C
B7
N/C
B8
N/C
B9
N/C
B10
B11
B12
B13
B14
B15
B16
B17
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
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Name
Reset Value
Description
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
N/C
0
0
0
0
0
0
0
0
0
0
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
COUNT_MODE_MUX_SEL
Select Readback for VCO maximum frequency or minimum
frequency.
0 = Max
1 = Min
B28
B29
B30
B31
RB_REG<0>
RB_REG<1>
RB_REG<2>
RB_ENABLE
X
X
X
1
3 LSB’s of the address for the register that is being read
Reg 1, B[30..28] = [000]
Reg 7, B[30..28] = [111]
1 ≥ Put the device in Readback Mode
The contents of any register specified in RB_REG can be read back during the read cycle, including register 0.
Register address
Bit1 Bit2
CHIP_ID
Bit5
NU
R_SAT_ERR
Bit12
Bit0
Bit3
COUNT0-7/VCO_TRM
Bit4
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
COUNT8-10/VCO_SEL
COUNT11-17
Bit13 Bit14 Bit15 Bit16 Bit17 Bit18 Bit19 Bit20
Bit21
Bit22
Bit23
Bit24 Bit25 Bit26 Bit27 Bit28 Bit29 Bit30
COUNT_MODE-MUX-SEL
Bit31
Register 0 Name
Reset Value
Description
Bit0
Bit1
ADDR_0
0
0
0
1
0
1
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Register address bits
ADDR_1
Bit2
ADDR_2
Bit3
ADDR_3
Bit4
ADDR_4
Bit5
CHIP_ID_0
CHIP_ID_1
NU
Bit6
Bit7
Bit8
NU
Bit9
NU
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
NU
NU
R_SAT_ERR
count_0/NU
count_1/NU
count_2/VCO_TRIM_0
count_3/VCO_TRIM_1
count_4/VCO_TRIM_2
count_5/VCO_TRIM_3
count_6/VCO_TRIM_4
count_7/VCO_TRIM_5
Error flag for calibration speed
B[30..13] = VCO frequency counter high when
COUNT_MODE_MUX_SEL = 0 and VCO_TEST_MODE = 1
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Register 0 Name
Reset Value
Description
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
count_8/NU
x
x
x
x
x
x
x
x
x
x
x
B[30..13] = VCO frequency counter low when
COUNT_MODE_MUX_SEL = 1 and VCO_TEST_MODE = 1
count_9/VCO_sel_0
count_10/VCO_sel_1
count<11>
B[20..15] = Autocal results for VCO_TRIM,
B[23..22] = Autocal results for VCO_SEL when
VCO_TEST_MODE = 0
count<12>
count<13>
count<14>
count<15>
count<16>
count<17>
COUNT_MODE_MUX_SEL
0 = Minimum frequency
1 = Maximum frequency
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APPLICATION INFORMATION
INTEGER AND FRACTIONAL MODE SELECTION
The PLL is designed to operate in either Integer mode or Fractional mode. If the desired local oscillator (LO)
frequency is an integer multiple of the phase frequency detector (PFD) frequency, fPFD, then Integer mode can be
selected. The normalized in-band phase noise floor in Integer mode is lower than in Fractional mode. In Integer
mode, the feedback divider is an exact integer, and the fraction is zero. While operating in Integer mode, the
register bits corresponding to the fractional control are don’t care.
In Fractional mode, the feedback divider fractional portion is non-zero on average. With 25-bit fractional
resolution, RF stepsize fPFD/225 is less than 1 Hz with a fPFD up to 33 MHz. The appropriate fractional control bits
in the serial register must be programmed.
DESCRIPTION OF PLL STRUCTURE
EXT_VCO
VCO0
fLO
fREF
fPFD
Divide by
1/2/4/8
Divide
by R
PHASE
LOP,LON
VCO1
VCO2
VCO3
LOOP
FILTER
Z(f)
REFIN
FREQUENCY
DETECTOR +
CHARGE PUMP
CP_OUT
VTUNE
fComp
fVCO
fmixer
Divide by
1/2/4/8
RF Div
Dig Div
fN
fPM
Divide
by N.f
Divide
by 1/2/4
Prescaler
4/5 or 8/9
NINT & NFRAC Div
Figure 85. Block Diagram of the PLL Loop
The output frequency is given by Equation 1:
fREF
NFRAC
225
fVCO
=
(PLL_DIV_SEL) NINT +
RDIV
(1)
The rate at which phase comparison occurs is fREF/RDIV. In Integer mode, the fractional setting is ignored and
Equation 2 is applied.
fVCO
= NINT ´ PLL_DIV_SEL
fPFD
(2)
The feedback divider block consists of a programmable RF divider, a prescaler divider, and an NF divider. The
prescaler can be programmed as either a 4/5 or an 8/9 prescaler. The NF divider includes an A counter and an
M counter.
Selecting PLL Divider Values
Operation of the PLL requires the LO_DIV_SEL, RDIV, PLL_DIV_SEL, NINT, and NFRAC bits to be calculated.
The LO or mixer frequency is related to fVCO according to divide-by-1/-2/-4/-8 blocks and the operating range of
fVCO
.
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a. LO_DIV_SEL
1
2
3
4
2400 MHz £ fRF £ 4800 MHz
1200 MHz £ fRF £ 2400 MHz
600 MHz £ fRF £ 1200 MHz
300 MHz £ fRF £ 600 MHz
LO_DIV_SEL =
Therefore:
fVCO = LO_DIV_SEL ´ fRF
b. PLL_DIV_SEL
Given fVCO, select the minimum value for PLL_DIV_SEL so that the programmable RF divider limits the input
frequency into the prescaler block, fPM, to a maximum of 3000 MHz.
PLL _ DIV _ SEL = min(1, 2, 4) such that fPM ≤ 3000 MHz
This calculation can be restated as Equation 3.
LO_DIV_SEL ´ fRF
PLL_DIV_SEL = Ceiling
3000 MHz
(3)
Higher values of fPFD correspond to better phase noise performance in Integer mode or Fractional mode.
fPFD, along with PLL_DIV_SEL, determines the fVCO stepsize in Integer mode. Therefore, in Integer mode,
select the maximum fPFD that allows for the required RF stepsize, as shown by Equation 4.
fVCO, Stepsize
f
RF, Stepsize ´ LO_DIV_SEL
=
fPFD
=
PLL_DIV_SEL
PLL_DIV_SEL
(4)
In Fractional mode, a small RF stepsize is accomplished through the Fractional mode divider. A large fPFD
should be used to minimize the effects of fractional controller noise in the output spectrum. In this case, fPFD
may vary according to the reference clock and fractional spur requirements; for example, fPFD = 20 MHz.
c. RDIV, NINT, NFRAC, PRSC_SEL
fREF
RDIV =
fPFD
fVCORDIV
NINT = floor
fREFPLL_DIV_SEL
fVCORDIV
NFRAC = floor
- NINT 225
(
fREFPLL_DIV_SEL
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The P/(P+1) programmable prescaler is set to 8/9 or 4/5 through the PRSC_SEL bit. To allow proper
fractional control, set PRSC_SEL according to Equation 5.
8
9
NINT ³ 75 in Fractional Mode or NINT ³ 72 in Integer mode
PRSC_SEL =
4
23 £ NINT < 75 in Fractional mode or 20 £ NINT < 72 in Integer mode
5
(5)
The PRSC_SEL limit at NINT < 75 applies to Fractional mode with third-order modulation. In Integer mode,
the PRSC_SEL = 8/9 should be used with NINT as low as 72. The divider block accounts for either value of
PRSC_SEL without requiring NINT or NFRAC to be adjusted. Then, calculate the maximum frequency to be
input to the digital divider at fN. Use the lower of the possible prescaler divide settings, P = (4,8), as shown
by Equation 6.
fVCO
fN,Max
=
PLL_DIV_SEL ´ P
(6)
Verify that the frequency into the digital divider, fN, is less than or equal to 375 MHz. If fN exceeds 375 MHz,
choose a larger value for PLL_DIV_SEL and recalculate fPFD, RDIV, NINT, NFRAC, and PRSC_SEL.
Setup Example for Integer Mode
Suppose the following operating characteristics are desired for Integer mode operation:
•
•
•
fREF = 40 MHz (reference input frequency)
Step at RF = 2 MHz (RF channel spacing)
fRF = 1600 MHz (RF frequency)
The VCO range is 2400 MHz to 4800 MHz. Therefore:
•
•
LO_DIV_SEL = 2
fVCO = LO_DIV_SEL × 1600 MHz = 3200 MHz
In order to keep the frequency of the prescaler below 3000 MHz:
PLL_DIV_SEL = 2
The desired stepsize at RF is 2 MHz, so:
•
•
•
fPFD = 2 MHz
fVCO, stepsize = PLL_DIV_SEL × fPFD = 4 MHz
Using the reference frequency along with the required fPFD gives:
•
•
RDIV = 20
NINT = 800
NINT ≥ 75; therefore, select the 8/9 prescaler.
fN,Max = 3200 MHz/(2 × 8) = 200 MHz < 375 MHz
This example shows that Integer mode operation gives sufficient resolution for the required stepsize.
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Setup Example for Fractional Mode
Suppose the following operating characteristics are desired for Fractional mode operation:
•
•
•
fREF = 40 MHz (reference input frequency)
Step at RF = 5 MHz (RF channel spacing)
fRF = 1,600,000,045 Hz (RF frequency)
The VCO range is 2400 MHz to 4800 MHz. Therefore:
•
•
LO_DIV_SEL = 2
fVCO = LO_DIV_SEL × 1,600,000,045 Hz = 3,200,000,090 Hz
In order to keep the frequency of the prescaler below 3000 MHz:
PLL_DIV_SEL = 2
Using a typical fPFD of 20 MHz:
•
•
•
•
RDIV = 2
NINT = 80
NFRAC = 75
NINT ≥ 75; therefore, select the 8/9 prescaler.
fN,Max = 3200 MHz/(2 × 8) = 200 MHz < 375 MHz
The actual frequency at RF is:
•
fRF = 1600000044.9419 Hz
For a frequency error of –0.058 Hz.
Fractional Mode Setup
Optimal operation of the PLL in fractional mode requires several additional register settings. Recommended
values are listed in Table 3. Optimal performance may require tuning the MOD_ORD, ISOURCE_SINK, and
ISOURCE_TRIM values according to the chosen frequency band.
Table 3. Fractional Mode Register Settings
REGISTER BIT
EN_ISOURCE
REGISTER ADDRESSING
Reg4B18
RECOMMENDED VALUE
1
1
EN_DITH
Reg4B25
MOD_ORD
Reg4B[27..26]
Reg4B28
B[27..26] = [10]
DITH_SEL
0
DEL_SD_CLK
EN_LD_ISOURCE
ISOURCE_SINK
ISOURCE_TRIM
Reg4B[30..29]
Reg5B31
B[30..29] = [10]
0
Reg7B19
0
Reg7B[22..20]
B[22..20] = [100]
SELECTING THE VCO AND VCO FREQUENCY CONTROL
To achieve a broad frequency tuning range, the TRF372017 includes four VCOs. Each VCO is connected to a
bank of capacitors that determine its valid operating frequency. For any given frequency setting, the appropriate
VCO and capacitor array must be selected.
The device contains logic that will automatically select the appropriate VCO and capacitor bank. Set bit EN_CAL
to initiate the calibration algorithm. During the calibration process, the device will select a VCO and a capacitor
state so that VTune matches the reference voltage set by VCO_CAL_REF_n. Accuracy of the tune is increased
through bits CAL_ACC_n. Since a calibration begins immediately when EN_CAL is set, all registers must contain
valid value prior to initiating calibration.
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Calibration logic is driven by a CAL_CLK clock derived from the phase frequency detector frequency scaled
according to the setting in CAL_CLK_SEL. Faster CAL_CLK frequency enables faster calibration, but the logic is
limited to clock frequencies around 1MHz. Table 4 provides suggested CAL_CLK_SEL scaling recommendations
for several phase frequency detector frequencies. The flag R_SAT_ERR is evaluated during the calibration
process to indicate calibration counter overflow errors, which will occur if CAL_CLK runs too fast. If R_SAT_ERR
is set during a calibration, the resulting calibration is not valid and CAL_CLK_SEL must be used to slow the
CAL_CLK. CAL_CLK frequencies should not be set below 0.1MHz.
Table 4. Example CAL_CLK_SEL Scaling
PFD FREQUENCY
MHz
CAL_CLK_SEL
SCALING
CAL_CLK FREQUENCY
MHz
20
1
1/32
1
0.625
1
0.1
8
0.8
When VCOSEL_MODE is 0, the device will automatically select both the VCO and capacitor bank within 23
CAL_CLK cycles. When VCOSEL_MODE is 1, the device will use the VCO selected in VCO_SEL_0 and
VCO_SEL_1 and automatically select the capacitor array within 17 CAL_CLK cycles. The VCO and capacitor
array settings resulting from calibration cannot be read from the VCO_SEL_n and VCO_TRIM_n bits in registers
2 and 7. They can only be read from register 0.
Automatic calibration can be disabled by setting CAL_BYPASS to 1. In this manual cal mode, the VCO is
selected through register bits VCO_SEL_n, while the capacitor array is selected through register bits
VCO_TRIM_n. Calibration modes are summarized in Table 5. After calibration is complete, the PLL is released
from calibration mode to reach an analog lock.
During the calibration process, the TRF372017 will scan through many frequencies. RF and LO outputs should
be disabled until calibration is complete. At power up the RF and LO output will be disabled by default.
Once a calibration has been performed at a given frequency setting, the calibration is valid over all operating
temperature conditions.
Table 5. VCO Calibration Modes
CAL_BYPASS VCOSEL_MODE
MAX CYCLES
CAL_CLK
VCO
CAPACITOR ARRAY
Automatic
0
0
1
0
1
46
34
na
VCO_SEL_n
VCO_SEL_n
automatic
don't care
VCO_TRIM_n
EXTERNAL VCO
An external LO or VCO signal may be applied. EN_EXTVCO powers the input buffer and selects the buffered
external signal instead of an internal VCO. Dividers, the pfd, and the charge pump remain enabled and may be
used to drive an external VCO. NEG_VCO must correspond to the gain of the external VCO.
VCO TEST MODE
Setting VCO_TEST_MODE forces the currently selected VCO to the edge of its frequency range by
disconnecting the charge pump input from the pfd and loop filter and forcing its output high or low. The upper or
lower edge of the VCO range is selected through COUNT_MODE_MUX_SEL.
VCO_TEST_MODE also reports the value of a frequency counter in COUNT, which can be read back in register
0. COUNT reports the number of digital N divider cycles in the PLL, directly related to the period of fN, that occur
during each CAL_CLK cycle. Counter operation is initiated through the bit EN_CAL.
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Table 6. VCO Test Mode
VCO_TEST_MODE
COUNT_MODE_MUX_SEL
VCO Operation
Register 0 B[30..13]
B[30..24] = undefined
B[23..22] = VCO_SEL selected during autocal
B21 = undefined
0
don't care
Normal
B[20..13] = VCO_TRIM selected during autocal
1
1
0
1
Max frequency
Min frequency
B[30..13] = Max frequency counter
B[30..13] = Min frequency counter
LOOP FILTER
Loop filter design is critical for achieving low closed loop phase noise. Some typical loop filter component values
are given in Table 7, referenced to designators in Figure 86. These loop filters are designed using charge pump
current of 1.94mA to minimize noise.
Table 7. Typical Loop Filter Components
fPFD (MHz)
40
C1 (pF)
1000
47
C2 (pF)
10000
560
R2 (kΩ)
0.47
10
C3 (pF)
39
R3 (kΩ)
C4 (pF)
1.8
R4 (kΩ)
1.4
5
3.3
1.6
4.7
open
open
open
220
0
0
6.4
100
1000
5
20
5
10
270
4700
1.5
4700
220
1.5
0.475
0
30.72
2200
20000
0.47
0.475
R3
R4
VTUNE
CP_OUT
C1
C2
R2
C3
C4
Figure 86. Loop Filter Component Reference Designators
LOCK DETECT
The lock detect signal is generated in the phase frequency detector by comparing the VCO target frequency
against the VCO actual frequency. When the phase of the two compared frequencies remains aligned for several
clock cycles, an internal signal goes high. The precision of this comparison is controlled through the
LD_ANA_PREC bits. This internal signal is then averaged and compared against a reference voltage to generate
the LD signal. The number of averages used is controlled through LD_DIG_PREC. Therefore, when the VCO is
frequency locked, LD is high. When the VCO frequency is not locked, LD may pulse high or exhibit periodic
behavior.
By default, the internal lock detect signal is driven on the LD terminal. Register bits MUX_CTRL_n can be used
to control a mux to output other diagnostic signals on the LD output. The LD control signals are shown in
Table 8.
Table 8. LD Control Signals
ADJUSTMENT
REGISTER BITS
LD_ANA_PREC_0
LD_ANA_PREC_1
LD_DIG_PREC
MUX_CTRL_n
BIT ADDRESSING
Register 4 Bit 19
Register 4 Bit 20
Register 4 Bit 24
Register 7 Bits 18..16
Lock detect precision
Unlock detect precision
LD averaging count
Diagnostic Output
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Table 9. LD Control Signal Mode Settings
CONDITION
RECOMMENDED SETTINGS
Integer Mode
LD_ANA_PREC_0 = 0
LD_ANA_PREC_1 = 0
LD_DIG_PREC = 1
Fractional Mode
LD_ANA_PREC_0 = 1
LD_ANA_PREC_1 = 1
LD_DIG_PREC = 1
Tx DIVIDER
The Tx divider, illustrated in Figure 87, converts the differential output of the VCO into differential I and Q mixer
components. The divide by 1 differential quadrature phases are provided through a polyphase. Divide by 2, 4,
and 8 differential quadrature phases are provided through flip-flop dividers. Only one of the dividers operates at a
time, and the appropriate output is selected by a mux. DIVn bits are controlled through TX_DIV_SELn.
TX_DIV_I determines the bias level for the divider blocks. The SPEEDUP control is used to bypass a
stabilization resistor and reach the final bias level faster after a change in the divider selection. SPEEDUP should
be disabled during normal operation.
DIV8
DIV4
DIV2
DIV1
PWD_TX_DIV
VCO P/N
Polyphase
Imix P/N
Div2
Div4
Qmix P/N
Div8
Speedup
bias
Tx_DIV_I
Figure 87. Tx Divider
LO DIVIDER
The LO divider is shown in Figure 88. It frequency divides the VCO output. Only one of the dividers operates at a
time, and the appropriate output is selected by a mux. DIVn bits are controlled through LO_DIV_SELn. The
output is buffered and provided on output pins LO_OUT_P and LO_OUT_N. The output level is controlled
through BUFOUT_BIASn.
LO_DIV_I determines the bias level for the divider blocks. The SPEEDUP control is used to bypass a
stabilization resistor and reach the final bias level faster after a change in the divider selection. SPEEDUP should
be disabled during normal operation. Although SPEEDUP controls both the Tx and LO divider biases, the Tx and
LO divider biases are generated independently.
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DIV8
DIV4
DIV2
DIV1
PWD_LO_DIV
Buffer
VCO P/N
BUFOUT_BIASn
Div2
LO_OUT_P/N
Div4
PWD_OUT_BUFF
Div8
Speedup
bias
LO_DIV_I
Figure 88. LO Divider
LO OUTPUTS
The LO outputs are open collector outputs. They require a pull-up to VCC. 75Ω pull-up resistors to VCC with
local decoupling provides a good broadband match and is shown in an example circuit in Figure 89. An inductor
pull-up in parallel with a cap can provide a tuned load for excellent narrowband load matching.
+3.3 V
75
LO_OUT_P
47 pF
75
LO_OUT_N
47 pF
Figure 89. Example LO_OUT Circuit for Broadband Operation
MIXER
A diagram of the mixer is shown in Figure 90. The mixer is followed by a differential to single-ended converter
and buffer for output.
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Imix P
Imix N
BBI_P
BBI_N
Diff2Single
RFOUT
Qmix N
Qmix P
BBQ_N
BBQ_P
Figure 90. Mixer
DISABLING OUTPUTS
RF frequency outputs are generated at the RFOUT and LO* terminals. Unused RF frequency outputs should be
disabled to minimize power consumption and noise generation. Table 10 lists settings used to disable the
outputs. Power save mode can also be used to disable outputs.
Table 10. Register Controls for Disabling Outputs
DISABLED OUTPUT
REGISTER BIT
PWD_TX_DIV
SETTING
RFOUT
1
1
1
PWD_OUT_BUFF
PWD_LO_DIV
LOP and LON
POWERSAVE MODE
Powersave mode can be used to put the device into a low power consumption mode. The PLL block remains
active in Powersave mode, reducing the time required for startup. However, the modulator, dividers, output
buffers and baseband common mode generation blocks are powered down. The SPI block remains active, and
registers are addressable. Use the PS pin to activate powersave mode.
POWER SUPPLY DISTRIBUTION
Power supply distribution for the TRF372017 is shown in Figure 91. Proper isolation and filtering of the supplies
is critical for low noise operation of the device. Each supply pin should be supplied with local decoupling
capacitance and isolated with a ferrite bead. VCC_VCO2 is tolerant of 5V supply voltages to permit additional
supply filtering.
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IQ
Offset
Buffer
Bias
AN DIG VCO Tank
Divider
Buffer
PLL
LODIV
BB VCM Gen
VCC
VCC
Mixer
Buffer
SPI &
EEPROM
TxDIV
Mod
Figure 91. Power Supply Distribution
DAC INTERFACING WITH EXTERNAL BASEBAND BIAS VOLTAGE
Common mode voltage on the baseband inputs can be generated either internally or externally. An external
interface should provide 1.7V dc and any necessary filtering. A typical interface to a DAC device is shown in
Figure 92.
+5 V
1mF
68 nH
125 Ω
450 Ω
60.4 Ω
500 Ω
10 nH
2.2 pF
DNI
90.9 Ω
+5 V
2.7 pF
GND
DAC3283
TRF3720
1mF
10 nH
125 Ω
450 Ω
60.4 Ω
500 Ω
68 nH
GND
Figure 92. DAC to TRF372017 Interface With External VCM Generation
INTERNAL BASEBAND BIAS VOLTAGE GENERATION
The TRF372017 has the ability to generate DC voltage levels for its baseband inputs internally. Register settings
in the device allow the user to adjust common mode voltage of the I and Q signals separately. There are three
adjustment factors for the baseband inputs. These are described in Table 1.
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Table 11. Baseband Adjustment Factors
ADJUSTMENT
VCM setting
VCM Enable
Bias select
REGISTER BITS
VREF_SEL_n
PWD_BB_VCM
IB_VCM_SEL
BIT ADDRESSING
Register 6 Bits 23..21
Register 4 Bit 15
Register 7 Bit 25
Each baseband input pair includes the circuitry depicted in Figure 93. The Vref set voltage impacts all four
terminals: IP, IN, QP, and QN. The effect of changing the reference voltage is shown in Figure 78. Each node
also includes a programmable current DAC that injects current into the positive and negative terminals of each
input.
IDAC
IDAC
100 (external)
external
external
IN
IP
5000
Vref Set
5000
Figure 93. Block Diagram of the Baseband I Input Nodes
A typical DAC to TRF372017 interface using internal VCM generation is shown in Figure 94.
+5 V
68 nH
115
1 mF
60.4
634
10 nH
2.2 pF
DNI
90.9
2.7 pF
+5 V
GND
DAC3283
TRF3720
10 nH
115
1 mF
60.4
634
68 nH
GND
Figure 94. DAC to TRF372017 Interface With Internal VCM Generation
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CARRIER FEEDTHROUGH CANCELLATION
The structure of the baseband current DAC is shown in Figure 95. For each input pair, there is a programmable
reference current. The reference current for each pair (I and Q) is identical and is programmed through the same
register bits, but the reference current source itself is duplicated in the device for both I and Q inputs. This
current can be set to change the total current flowing into the P and N nodes, which in turn changes the offset
programmability range.
The reference current is then mirrored and multiplied before getting injected into the input node. The total
mirrored current will be routed into the two sides of the differential pair and routed according to eight
programmable bits. As the 8 bit setting is changed, current is shifted from one side of the pair into the other side
for each of the I and Q input pairs. In practical usage, the offset current routing distributes the adjustment for
each side of the pair, while the reference current sets the range of adjustment. This effect can be seen in
Figure 79, which shows that the gain of the current routing is greater when the reference current setting is higher.
However the step size also increases with increase in range. Figure 79 shows the effect on common mode
voltage of varying the DAC reference current. Adjustment register bits are shown in Table 12.
Offset adjustment may be provided by an external source, such as a DAC QMC block, for dc-coupled systems.
Current Mirror
I/Q Offset Ref Current, 8 bit
Iref
-----
1
Iref
-----
2
Iref
-----
128
B8
Iref
-----
1
Iref
-----
2
Iref
-----
128
B0
...
...
DC Offset Iref
B0
B1
B8
B7
IP
IN
Figure 95. Block Diagram of the Programmable Current DAC
Table 12. Baseband Differential Offset Adjustment Factors
ADJUSTMENT
REGISTER BITS
BIT ADDRESS
I input differential offset programmability
I Offset Ref Curr
IOFF_n
Register 6
Bits 12..5
Q input differential offset programmability
Offset Programmability Range
Q Offset Ref Curr
DCoffset_I_n
QOFF
Register 6
Bits 20..13
Register 7
Bits 30..29
ESD SENSITIVITY
RF devices may be extremely sensitive to electrostatic discharge (ESD) (see ABSOLUTE MAXIMUM RATINGS
table). To prevent damage from electrostatic discharge (ESD), devices should be stored and handled in a way
that prevents the build up of electrostatic voltages that exceed the rated level. Rated electrostatic discharge
(ESD) levels shall also not be exceeded while the device is installed on a PC board.
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APPLICATION SCHEMATIC
+3.3 V
Loop Filter:
values described
in table
FB-1K
R3
C3
R4
C4
C1
C2
1 mF
4.7 pF
REFIN
R2
22 pF
LE
DATA
CLK
RDBK
+3.3 V
4.7 pF
+3.3 V
EXT_VCO
FB-1K
+3.3 V/+5.0 V
FB-1K
+3.3V
FB-1K
FB-1K
1 mF
100 pF
+3.3 V
PS
LD
1 mF
4.7 pF
PS
RDBK
VCC_DIG
EXT_VCO
FB-1K
1 mF
4.7 pF
VCC_VCO1
LO_OUT_P
LO_OUT_N
VCC_VCO2
GND
4.7 pF
100 pF
GND_DIG
LD
GND
100 pF
4.7 pF
VCC_LO2
GND
VCC_LO1
GND
BBI_N
BBI_P
Baseband interface
BBQ_N
described in application information BBQ_P
BBI_N
BBQ_N
BBQ_P
GND
Baseband interface
described in application information
BBI_P
GND
GND
+3.3 V
+3.3 V
GND
1.8 pF
1000 pF
1 mF
1.8 pF
4.7 pF
1000 pF
1 mF
NC
75
75
LO_OUT_P
LO_OUT_N
22 pF
RFOUT
4.7 pF
+5.0 V
+5.0 V
FB-1K
FB-1K
100 pF
4.7 pF
100 pF
4.7 pF
Figure 96. Application Schematic
Table 13. Pin Termination Requirements and Limitations
NAME
RDBK
LD
PIN NO
DESCRIPTION
2
5
SPI Readback output. Digital output pins can source or sink up to 8mA of current.
Lock detector digital output, as configured by MUX_CTRL. Digital output pins can source or sink up to 8mA of
current.
BBQ_N
BBQ_P
9
Base-band in-quadrature input: negative terminal. Internal 5kΩ to VCM generator. If VCM is internally generated
(PWD_BB_VCM = 0), external AC coupling caps and 100Ω differential termination to BBQ_P is required.
10
Base-band in-quadrature input: positive terminal. Internal 5KΩ to VCM generator. If VCM is internally generated
(PWD_BB_VCM = 0), external AC coupling caps and 100Ω differential termination to BBQ_N is required.
RSVD
RFOUT
BBI_P
14
18
27
Reserved. Normally open.
RF output. Internally matched to 50Ω output. Normally AC coupled.
Base-band in-phase input: positive terminal. Internal 5kΩ to VCM generator. If VCM is internally generated
(PWD_BB_VCM = 0), external AC coupling caps and 100Ω differential termination to BBI_N is required.
BBI_N
28
Base-band in-phase input: negative terminal. Internal 5kΩ to VCM generator. If VCM is internally generated
(PWD_BB_VCM = 0), external AC coupling caps and 100Ω differential termination to BBI_P is required.
LO_OUT_N
LO_OUT_P
EXT_VCO
REFIN
33
34
36
43
45
46
47
48
Local oscillator output: negative terminal. Open collector output. A pull-up is required. Normally AC coupled.
Local oscillator output: positive terminal. Open collector output. A pull-up is required. Normally AC coupled.
External local oscillator input. High impedance. Normally AC coupled.
Reference clock input. High impedance. Normally AC coupled.
LE
SPI latch enable. Digital input. High impedance.
DATA
SPI data input. Digital input. High impedance.
CLK
SPI clock input. Digital input. High impedance.
SCAN_EN
Internal testing mode digital input. Connect to ground in normal operation.
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APPLICATION LAYOUT
Layout of the application board significantly impacts the analog performance of the TRF372017 device. Noise
and high-speed signals should be prevented from leaking onto power-supply pins or analog signals. Follow these
recommendations:
1. Place supply decoupling capacitors physically close to the device, on the same side of the board. Each
supply pin should be isolated with a ferrite bead.
2. Maintain a continuous ground plane in the vicinity of the device and as return paths for all high-speed signal
lines. Place reference plane vias or decoupling capacitors near any signal line reference transition.
3. The pad on the bottom of the device must be electrically grounded. Connect GND pins directly to the pad on
the surface layer. Connect the GND pins and pad directly to surface ground where possible.
4. Power planes should not overlap each other or high-speed signal lines.
5. Isolate REF_IN routing from loop filter lines, control lines, and other high-speed lines.
See Figure 97 for an example of critical component layout (for the top PCB layer).
Figure 97. Critical Layout of the TRF372017 EVM Board
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REVISION HISTORY
Note: Page numbers of current version may differ from previous versions.
Changes from Revision A (August 2010) to Revision B
Page
•
•
•
•
•
•
•
•
Deleted Comments column from Table 1 ............................................................................................................................. 7
Changed graphic entities in Figures 12 through Figure 27 ................................................................................................ 11
Changed column heading from "Default Value" to "Reset Value" in Register tables 1, 2, 3, 4, 5, 6 and 7 ....................... 30
Added "Recommended programming [xx]" to various Description statements in Register 2,5,6, and 7. ......................... 32
Changed Register 4, Bit21/Bit22 Description statement from "Off" to "Normal" ................................................................ 34
Changed Column heading from "Default Value to "Reset Value" in READBACK MODE section, Register 0 ................... 38
Changed Column heading from "Default Value to "Reset Value" in READBACK MODE section, Register 0 ................... 39
Changed Bit5 name from "CHIP_ID" to "CHIP_ID _0" and changed Bit6 name from "NU" to "CHIP_ID_1", Reset
Value to 1 ............................................................................................................................................................................ 39
•
•
Changed Bit5 name from "CHIP_ID" to "CHIP_ID _0" and changed Bit6 name from "NU" to "CHIP_ID_1", Reset
Value to 1 ............................................................................................................................................................................ 40
Changed the text under INTEGER and FRACTIONAL MODE SELECTION through sub section "Practical Limit on
Maximum PFD Frequency" for clarification. ....................................................................................................................... 41
•
•
•
•
Changed "RDIV = 20" to "RDIV = 2" in the Setup Example for Fractional Mode paragraph ......................................... 44
Changed EN_LD_ISOURCE Recommended Value from 1 to 0 in Table 3, ...................................................................... 44
Changed the graphic entity in Figure 94 for clarification. ................................................................................................... 51
Changed the text in the APPLICATION LAYOUT section, and added crossreference to Figure 97 ................................. 54
Changes from Revision B (March 2012) to Revision C
Page
•
Added graph titles to Figure 56 and 57 that were missing in Rev B .................................................................................. 22
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Apr-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TRF372017IRGZR
TRF372017IRGZT
ACTIVE
ACTIVE
VQFN
VQFN
RGZ
RGZ
48
48
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Apr-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TRF372017IRGZR
TRF372017IRGZT
VQFN
VQFN
RGZ
RGZ
48
48
2500
250
330.0
330.0
16.4
16.4
7.3
7.3
7.3
7.3
1.5
1.5
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Apr-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TRF372017IRGZR
TRF372017IRGZT
VQFN
VQFN
RGZ
RGZ
48
48
2500
250
336.6
336.6
336.6
336.6
28.6
28.6
Pack Materials-Page 2
IMPORTANT NOTICE
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Audio
Applications
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
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Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Medical
Logic
Security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense www.ti.com/space-avionics-defense
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page
e2e.ti.com
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