TRF3722 [TI]
具有集成宽带 PLL/VCO 的 400MHz 至 4.2GHz 正交调制器;
| 型号： | TRF3722 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成宽带 PLL/VCO 的 400MHz 至 4.2GHz 正交调制器 |
| 文件： | 总69页 (文件大小：3081K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TRF3722
ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
TRF3722 具有集成 PLL 和 VCO 的正交调制器
1 特性
3 说明
1
•
•
•
•
具有集成 PLL 和 VCO 的 IQ 调制器
TRF3722 是一款高性能直接转换正交调制器，具有优
异的线性和低噪声性能。基带共模电压典型值为
0.25V，支持与电流源 DAC 的无缝连接。
整数 N/分数 N PLL
调制器支持 400MHz 至 4200MHz 频率范围
此器件集成了 PLL 和 VCO，能够为调制器提供本地振
荡器 (LO)。PLL 和 VCO 可实现卓越的相位噪声性
能，能够满足最为严格的传输通信要求。此器件还提供
了额外的 LO 输出，用于驱动其它调制器或降频混频
器。该调制器 具有 一个可实现典型 3dB 增益提升的高
增益模式和一个适用于需要对功耗进行优化的应用的低
功耗模式。
PLL 和 VCO 支持 280MHz 至 4100MHz 的频率范
围
•
•
•
900MHz 时的 OIP3 为 31 dBm
1800MHz 时的 OIP3 为 30 dBm
VCO 1800MHz 开环相位噪声：1MHz 偏移时为
-141 dBc/Hz
•
•
•
独立式 LO 输出支持 1/2/4/8 分频
调制器低功耗和高增益模式
多种断电模式
器件信息(1)
器件型号
TRF3722
封装
VQFN (48)
封装尺寸（标称值）
7.00mm x 7.00mm
2 应用
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
•
无线基础设施
–
CDMA：IS95，UMTS，CDMA2000，TD-
SCDMA
–
–
LTE，TD-LTE，LTE Advanced
TDMA：GSM，EDGE，MC-GSM
•
•
•
点对点微波，点对多点微波
软件定义的无线电
射频中继器，分布式天线系统
方框图
NC
VTUNE EXT_VCO BBI_N BBI_P
VCC_TK
VCC
32
35
33
42
23
21
16
14
38
39
LO_OUTN
LO_OUTP
LO Div
9
PLL Div
Charge
Pump
41
44
CP_OUT
REFIN
4
0h
PFD
Pre
Scaler
18
RFOUT
GND
TX Div
S
90h
R Div
N Div
45
43
SDM
40
37
30
26
LE
DATA
CLK
46
47
48
Serial Interface
PD RDBK LD
BBQ_N BBQ_P
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLWS245
TRF3722
ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
www.ti.com.cn
目录
6.19 Typical Characteristics - Current Consumption .... 29
6.20 Typical Characteristics - Power Dissipation.......... 31
Parameter Measurement Information ................ 33
7.1 Serial Interface Timing Diagram ............................. 33
Detailed Description ............................................ 35
8.1 Overview ................................................................. 35
8.2 Functional Block Diagram ....................................... 35
8.3 Feature Description................................................. 36
8.4 Device Functional Modes........................................ 39
8.5 Register Maps ........................................................ 42
Application and Implementation ........................ 55
9.1 Application Information............................................ 55
9.2 Typical Application .................................................. 55
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 9
6.7 Typical Characteristics - Output Power................... 10
6.8 Typical Characteristics - Gain................................. 11
6.9 Typical Characteristics - OIP3 ................................ 12
6.10 Typical Characteristics - OIP2 .............................. 13
6.11 Typical Characteristics - OP1dB........................... 14
6.12 Typical Characteristics - Noise ............................. 15
6.13 Typical Characteristics - Unadjusted CF............... 16
6.14 Typical Characteristics - Unadjusted SBS ............ 17
6.15 Typical Characteristics - LO Harmonic ................. 18
6.16 Typical Characteristics - BB Harmonic ................. 20
6.17 Typical Characteristics - RF Output Return Loss . 22
6.18 Typical Characteristics - PLL/VCO ....................... 23
7
8
9
10 Power Supply Recommendations ..................... 58
11 Layout................................................................... 59
11.1 Layout Guidelines ................................................. 59
11.2 Layout Example .................................................... 59
12 器件和文档支持 ..................................................... 60
12.1 接收文档更新通知 ................................................. 60
12.2 社区资源................................................................ 60
12.3 商标....................................................................... 60
12.4 静电放电警告......................................................... 60
12.5 Glossary................................................................ 60
13 机械、封装和可订购信息....................................... 60
4 修订历史记录
Changes from Revision A (June 2014) to Revision B
Page
•
•
•
•
•
已更改 256MHz 更改为 280MHz（PLL 和 VCO 特性 要点部分） ......................................................................................... 1
Changed ESD Ratings table title, updated to current standards ........................................................................................... 4
Added Typical and footnote 2 to Typical VCO frequency range and Typical output frequency range parameters ............... 8
Changed Figure 1 .................................................................................................................................................................. 9
Changed location of TRF3722 Application Schematic figure and all associated text to be under Typical Application
section .................................................................................................................................................................................. 55
Changes from Original (May 2014) to Revision A
Page
•
从单页产品预览更改为生产..................................................................................................................................................... 1
2
Copyright © 2014–2017, Texas Instruments Incorporated
TRF3722
www.ti.com.cn
ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
5 Pin Configuration and Functions
RGZ Package
48-Pin VQFN
Top View
1
36
35
34
PD
NC
2
RDBK
VCC_LO2
VTUNE
3
LD
4
5
VCC_DIG
GND
33 VCC_VCO
32 VCC_TK
31
30
VCC_LO1
GND
6
EXT_VCO
GND
TRF3722
7
BBQ_N
NC
8
29 BBI_N
28 NC
9
BBQ_P
GND
27 BBI_P
10
11
12
26
25
GND
NC
NC
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
BBI_N
BBI_P
BBQ_N
BBQ_P
CLK
29
27
8
I
I
BB in-phase input: negative
BB in-phase input: positive
BB quadrature input: negative
BB quadrature input: positive
I
10
48
41
47
31
I
I
Serial interface clock input; digital input
Charge pump output
CP_OUT
DATA
O
I
Serial interface data input; digital input
External local oscillator input
EXT_VCO
I
5, 7, 11, 15, 17, 19, 20,
22, 26, 30, 37, 40, 43,
45
GND
Ground
LD
3
O
I
PLL lock detect output
LE
46
Serial interface latch enable; digital input
Local oscillator output: negative
Local oscillator output: positive
No connect
LO_OUTN
LO_OUTP
NC
38
O
O
39
9, 12, 13, 24, 25, 36
28
NC
No connect; N/C or ground to paddle
Copyright © 2014–2017, Texas Instruments Incorporated
3
TRF3722
ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
1
PD
I
LO Div, TX Div, modulator power down (High = PD)
Serial interface internal registers readback output
Reference clock input
RDBK
REFIN
RFOUT
2
O
I
44
18
4
O
RF output
VCC_DIG
VCC_LO1
VCC_LO2
VCC_MOD1
VCC_MOD2
VCC_MOD3
VCC_MOD4
VCC_PLL
VCC_TK
3.3 V digital power supply
6
3.3 V TX Div power supply
35
14
16
21
23
42
32
33
34
3.3 V LO Div power supply
3.3 V modulator power supply
3.3 V modulator power supply
3.3 V modulator power supply
3.3 V modulator power supply
3.3 V PLL power supply
3.3 V or 5 V VCO tank power supply
3.3 V VCO power supply
VCC_VCO
VTUNE
I
VCO control voltage input
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–40
MAX
UNIT
All VCC except VCC_TK
+3.6
+5.5
3.6
Supply voltage
VCC_TK
V
Digital I/O voltage
V
Operating junction temperature
Storage temperature, Tstg
150
150
°C
°C
–40
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
3.3
MAX
3.6
UNIT
V
3.3 V power-supply voltage
VCC
5 V or 3.3 V power-supply voltage, VCC _TK
Operating junction temperature range
Ambient temperature range
3
3.3/5
5.5
V
TJ
–40
–40
125
85
°C
°C
TA
4
Copyright © 2014–2017, Texas Instruments Incorporated
TRF3722
www.ti.com.cn
ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
6.4 Thermal Information
TRF3722
THERMAL METRIC(1)
RGZ (VQFN)
48 PINS
27.5
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
12.8
4.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
4.3
RθJC(bot)
0.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Over recommended operating conditions: VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C. Optimized bias settings as per Table 16.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC PARAMETERS
Typical Operating Mode; LO out = Off
Typical Operating Mode; LO out = On
328(1)
374
21
mA
mA
mA
W
ICC
3.3 V Supply Current
5 V Supply Current
ICC_TK
Typical Operating Mode; LO out = Off
Typical Operating Mode; LO out = On
Low Power Mode (Mod); LO out = Off
Hardware Power Down
1.18
1.34
0.91
76
PDISS
Total Power Dissipation
W
W
mA
mA
IPD
Power Down Current
Serial interface Power Down
2
RFOUT FREQUENCY
Frequency
400
4200
0.5
MHz
IQ MODULATOR ƒLO = 750 MHz
Typical Operating Mode
High Gain Mode
0.8
3.6
dB
dB
Gain
G
Gain Flatness
In 300MHz bandwidth
–0.5
dB
OP1dB
OIP3
Output Compression Point
10.2
31
dBm
dBm
dBm
dBc
Output 3rd Order Intercept Point
Output 2nd Order Intercept Point
Unadj. SideBand Suppression
Unadj. Carrier Feedthrough
Output Noise Spectral Density
LO Second Harmonic
FBB = 4.5, 5.5 MHz
FBB = 4.5, 5.5 MHz
OIP2
62
SBS
–42
–50
–159
–49
–47
–72
–70
CF
dBm
dBm/Hz
dBc
NSDO
HD2LO
HD3LO
HD2BB
HD3BB
BB inputs terminated on 50 Ω
Measured at 2 x fLO
LO Third Harmonic
Measured at 3 x fLO
dBc
Baseband Second Harmonic
Baseband Third Harmonic
Measured at fLO ± 2 x fBB
Measured at fLO ± 3 x fBB
dBc
dBc
(1) Powered down output buffer and LO divider.
Copyright © 2014–2017, Texas Instruments Incorporated
5
TRF3722
ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
www.ti.com.cn
Electrical Characteristics (continued)
Over recommended operating conditions: VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C. Optimized bias settings as per Table 16.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IQ MODULATOR ƒLO = 900 MHz
Typical Operating Mode
0.8
3.6
dB
dB
Gain
G
High Gain Mode
Gain Flatness
In 300MHz bandwidth
–0.5
0.5
dB
OP1dB
OIP3
Output Compression Point
Output 3rd Order Intercept Point
Output 2nd Order Intercept Point
Unadj. Side Band Suppression
Unadj. Carrier Feed through
Output Noise Spectral Density
LO Second Harmonic
10
31
dBm
dBm
dBm
dBc
FBB = 4.5, 5.5 MHz
FBB = 4.5, 5.5 MHz
OIP2
62.5
–42.5
–50
SBS
CF
dBm
dBm/Hz
dBc
NSDO
HD2LO
HD3LO
HD2BB
HD3BB
BB inputs terminated on 50 Ω
Measured at 2 x fLO
–159
–47
LO Third Harmonic
Measured at 3 x fLO
–54.5
–65.5
–71.5
dBc
Baseband Second Harmonic
Baseband Third Harmonic
Measured at fLO ± 2 x fBB
Measured at fLO ± 3 x fBB
dBc
dBc
IQ MODULATOR ƒLO = 1800 MHz
Typical Operating Mode
High Gain Mode
0.3
3
dB
dB
Gain
G
Gain Flatness
In 300 MHz bandwidth
–0.5
0.5
dB
OP1dB
OIP3
OIP2
SBS
Output Compression Point
Output 3rd Order Intercept Point
Output 2nd Order Intercept Point
Unadj. Side Band Suppression
Unadj. Carrier Feed through
Output Noise Spectral Density
LO Second Harmonic
13
29.5
57
dBm
dBm
dBm
dBc
dBm
dBm/Hz
dBc
dBc
dBc
dBc
dB
fBB = 4.5, 5.5 MHz
fBB = 4.5, 5.5 MHz
–54.5
–57
CF
NSDO
HD2LO
HD3LO
HD2BB
HD3BB
RLO
BB inputs terminated on 50 Ω
Measured at 2 x fLO
–158
–36.5
–33.5
–65.5
–73
LO Third Harmonic
Measured at 3 x fLO
Baseband Second Harmonic
Baseband Third Harmonic
RF Output Return Loss
Measured at fLO ± 2 x fBB
Measured at fLO ± 3 x fBB
6
IQ MODULATOR ƒLO = 2150 MHz
Typical Operating Mode
High Gain Mode
0.2
3
dB
dB
Gain
G
Gain Flatness
In 300 MHz bandwidth
–0.5
0.5
dB
OP1dB
OIP3
Output Compression Point
Output 3rd Order Intercept Point
Output 2nd Order Intercept Point
Unadj. Side Band Suppression
Unadj. Carrier Feedt hrough
Output Noise Spectral Density
LO Second Harmonic
11.6
30
dBm
dBm
dBm
dBc
FBB = 4.5, 5.5 MHz
FBB = 4.5, 5.5 MHz
OIP2
43
SBS
–43
–42
–157
–40
–31
–51
–69
CF
dBm
dBm/Hz
dBc
NSDO
HD2LO
HD3LO
HD2BB
HD3BB
BB inputs terminated on 50 Ω
Measured at 2 x fLO
LO Third Harmonic
Measured at 3 x fLO
dBc
Baseband Second Harmonic
Baseband Third Harmonic
Measured at fLO ± 2 x fBB
Measured at fLO ± 3 x fBB
dBc
dBc
6
Copyright © 2014–2017, Texas Instruments Incorporated
TRF3722
www.ti.com.cn
ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
Electrical Characteristics (continued)
Over recommended operating conditions: VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C. Optimized bias settings as per Table 16.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IQ MODULATOR ƒLO = 2700 MHz
Typical Operating Mode
0
dB
dB
Gain
G
High Gain Mode
2.4
Gain Flatness
In 300MHz bandwidth
–0.5
0.5
dB
OP1dB
OIP3
Output Compression Point
Output 3rd Order Intercept Point
Output 2nd Order Intercept Point
Unadj. Side Band Suppression
Unadj. Carrier Feed through
Output Noise Spectral Density
LO Second Harmonic
10.4
29.5
45.5
–33
dBm
dBm
dBm
dBc
FBB = 4.5, 5.5 MHz
FBB = 4.5, 5.5 MHz
OIP2
SBS
CF
–39.6
–156
–29
dBm
dBm/Hz
dBc
NSDO
HD2LO
HD3LO
HD2BB
HD3BB
BB inputs terminated on 50 Ω
Measured at 2 x fLO
LO Third Harmonic
Measured at 3 x fLO
–37
dBc
Baseband Second Harmonic
Baseband Third Harmonic
Measured at fLO ± 2 x fBB
Measured at fLO ± 3 x fBB
–53
dBc
–68
dBc
IQ MODULATOR ƒLO = 3600 MHz
Typical Operating Mode
High Gain Mode
–2
0.4
dB
dB
G
Gain
OP1dB
OIP3
Output Compression Point
Output 3rd Order Intercept Point
Output 2nd Order Intercept Point
Unadj. Side Band Suppression
Unadj. Carrier Feed through
LO Second Harmonic
8.7
dBm
dBm
dBm
dBc
dBm
dBc
dBc
dBc
dBc
FBB = 4.5, 5.5 MHz
FBB = 4.5, 5.5 MHz
24.5
45.5
–31.5
–39.5
–28.4
–31.5
–55
OIP2
SBS
CF
HD2LO
HD3LO
HD2BB
HD3BB
Measured at 2 x fLO
LO Third Harmonic
Measured at 3 x fLO
Baseband Second Harmonic
Baseband Third Harmonic
Measured at fLO ± 2 x fBB
Measured at fLO ± 3 x fBB
–65
BASEBAND INPUTS
VCM
Common Mode Voltage
Baseband I/Q input
1 dB Bandwidth
Resistance
0
0.25
900
5
0.5
V
MHz
kΩ
BWBB
Baseband Bandwidth
ZinBB
Baseband Input Impedance
Capacitance
4
pF
REFERENCE OSCILLATOR PARAMETERS
Reference Frequency
Fref
Max
350
MHz
VPP
pF
Reference Input Sensitivity
0.2
3.3
65
Parallel capacitance
Parallel resistance
2
Zinref
Reference Input Impedance
2.2
kΩ
PFD, CP
FPFD
PFD Frequency
Max, refer to the Typical Application
MHz
mA
ICP_OUT
Charge Pump Current
In-band Normalized PN Floor
Max
1.94
Integer Mode
–221
dBc/Hz
Copyright © 2014–2017, Texas Instruments Incorporated
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TRF3722
ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
www.ti.com.cn
Electrical Characteristics (continued)
Over recommended operating conditions: VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C. Optimized bias settings as per Table 16.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCO
fVCO
KV
Typical VCO frequency range(2)
VCO gain
2050
4100
MHz
VTUNE = 1.1 V
30
–74
MHz/V
VCO Open Loop Phase Noise;
fVCO = 3600 MHz;
TX Div = Div-by-1;
fOUT = 3600 MHz
10 kHz
100 kHz
1 MHz
–109
–135
–152
–156
–80
dBc/Hz
dBc/Hz
VTUNE = 1.1 V
10 MHz
40 MHz
10 kHz
100 kHz
1 MHz
PN
VCO Open Loop Phase Noise;
fVCO = 3600 MHz;
TX Div = Div-by-2;
fOUT = 1800 MHz;
–115
–141
–156
–158
VTUNE = 1.1 V
10 MHz
40 MHz
LO OUTPUT
fOUT
Divide by 1
2050
1025
4100
2050
1025
512.5
Divide by 2
Typical output frequency range(2)
MHz
Divide by 4
512.5
256.25
Divide by 8
PLO
Output power
SE at 1800 MHz, OUTBUF_BIAS = 2
1
0
dBm
MHz
dBm
External VCO input Frequency Range
External VCO Input Level
250
–10
4200
10
CLOSE LOOP PLL OR VCO
Frac-N; PFD = 15.36 MHz; fOUT
3532.89 MHz;
Integration BW =1 kHz to 10 MHz; SSB
=
-45.2
-49.8
dB
dB
Integrated Phase Noise
Int-N; PFD = 2.56 MHz; fOUT = 1799.68
MHz;
Integration BW = 500 Hz to 20 MHz; SSB
10 kHz
100 kHz
1 MHz
–96
–114
–140
–156
–158
VCO Close Loop Phase Noise;
fVCO = 3600 MHz;
TX DIV = Div-by-2;
fOUT = 1800 MHz;
Integer Mode, PFD = 2.56MHz
dBc/Hz
10 MHz
40 MHz
DIGITAL INTERFACE
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
2
0
3.3
V
V
V
V
0.8
VOH
VOL
Referenced to VCC_DIG
Referenced to VCC_DIG
0.8 x VCC
0.2 x VCC
(2) Divided-down ranges minimum and maximum values are typical but are not specified.
8
Copyright © 2014–2017, Texas Instruments Incorporated
TRF3722
www.ti.com.cn
ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
6.6 Typical Characteristics
6.6.1 Modulator Output Spectrum
Graphical illustration of the modulator output spectrum with two tones is shown in Figure 1.
Freq.
FBBn = Baseband Frequency
Fn = RF Frequency
F3rdH/L
F2ndH/L
=
=
3rd Order Intermodulation Product Frequency (High Side / Low Side)
2nd Order Intermodulation Product Frequency (High Side / Low Side)
LO = Local Oscillator Frequency
LSBn
HD2BB
HD3BB
=
=
=
Lower Sideband Frequency
Baseband second harmonic (High Side / Low Side)
Baseband thrid harmonic (High Side / Low Side)
Figure 1. Graphical Illustration of Modulator Output Spectrum
Copyright © 2014–2017, Texas Instruments Incorporated
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TRF3722
ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
www.ti.com.cn
6.7 Typical Characteristics - Output Power
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C, I/Q frequency (fBB
4.5 MHz and 5.5 MHz, 500 mVPP, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per
Table 16. Total Pout is two tones combined power.
)
6
4
6
4
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
2
2
0
0
-2
-4
-6
-8
-10
-2
-4
-6
-8
-10
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D015
D218
Figure 2. Total POUT vs Temperature, Typical Operating
Mode
Figure 3. Total POUT vs Supply, Typical Operating Mode
6
6
4
4
2
2
0
0
-2
-4
-2
-4
-6
-6
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
-8
-8
-10
-10
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D017
D219
Figure 4. Total POUT vs Temperature, High Gain Mode
Figure 5. Total POUT vs Supply, High Gain Mode
6
6
4
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
4
2
2
0
0
-2
-4
-6
-8
-10
-2
-4
-6
-8
-10
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D019
D220
Figure 6. Total POUT vs Temperature, Low Power Mode
Figure 7. Total POUT vs Supply, Low Power Mode
10
Copyright © 2014–2017, Texas Instruments Incorporated
TRF3722
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ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
6.8 Typical Characteristics - Gain
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C, I/Q frequency (fBB
)
4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
6
4
6
4
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
2
2
0
0
-2
-4
-6
-8
-10
-2
-4
-6
-8
-10
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D003
D004
Figure 8. Voltage Gain vs Temperature, Typical Operating
Mode
Figure 9. Voltage Gain vs Supply, Typical Operating Mode
6
6
4
4
2
2
0
0
-2
-4
-2
-4
-6
-6
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
-8
-8
-10
-10
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D005
D006
Figure 10. Voltage Gain vs Temperature, High Gain Mode
Figure 11. Voltage Gain vs Supply, High Gain Mode
6
6
4
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
4
2
2
0
0
-2
-4
-6
-8
-10
-2
-4
-6
-8
-10
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D007
D008
Figure 12. Voltage Gain vs Temperature, Low Power Mode
Figure 13. Voltage Gain vs Supply, Low Power Mode
Copyright © 2014–2017, Texas Instruments Incorporated
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ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
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6.9 Typical Characteristics - OIP3
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C, I/Q frequency (fBB
4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
Reported OIP3 is minimum of low side and high side.
)
34
32
30
28
26
24
22
20
18
16
34
32
30
28
26
24
22
20
18
16
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D009
D010
Figure 14. OIP3 vs Temperature, Typical Operating Mode
Figure 15. OIP3 vs Supply, Typical Operating Mode
34
34
32
30
28
26
24
22
20
18
16
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
32
30
28
26
24
22
20
18
16
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D011
D012
Figure 16. OIP3 vs Temperature, High Gain Mode
Figure 17. OIP3 vs Supply, High Gain Mode
34
32
30
28
26
24
22
20
18
16
34
32
30
28
26
24
22
20
18
16
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D013
D014
Figure 18. OIP3 vs Temperature, Low Power Mode
Figure 19. OIP3 vs Supply, Low Power Mode
12
Copyright © 2014–2017, Texas Instruments Incorporated
TRF3722
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ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
6.10 Typical Characteristics - OIP2
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C, I/Q frequency (fBB
)
4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
Reported OIP2 is minimum of low side and high side.
70
65
60
55
50
45
40
35
30
70
65
60
55
50
45
40
35
30
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D021
D022
Figure 20. OIP2 vs Temperature, Typical Operating Mode
Figure 21. OIP2 vs Supply, Typical Operating Mode
70
70
65
60
55
50
45
40
35
30
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
65
60
55
50
45
40
35
30
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D023
D024
Figure 22. OIP2 vs Temperature, High Gain Mode
Figure 23. OIP2 vs Supply, High Gain Mode
70
65
60
55
50
45
40
35
30
70
65
60
55
50
45
40
35
30
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D025
D026
Figure 24. OIP2 vs Temperature, Low Power Mode
Figure 25. OIP2 vs Supply, Low Power Mode
Copyright © 2014–2017, Texas Instruments Incorporated
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6.11 Typical Characteristics - OP1dB
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C, I/Q frequency (fBB
)
5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
16
14
12
10
8
16
14
12
10
8
TA = -40èC
TA = 25èC
TA = 85èC
6
6
4
4
2
2
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0
0
-2
-2
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D027
D028
Figure 26. OP1dB vs Temperature, Typical Operating Mode
Figure 27. OP1dB vs Supply, Typical Operating Mode
16
16
TA = -40èC
TA = 25èC
TA = 85èC
14
12
10
8
14
12
10
8
6
6
4
4
2
2
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0
0
-2
-2
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D029
D030
Figure 28. OP1dB vs Temperature, High Gain Mode
Figure 29. OP1dB vs Supply, High Gain Mod
16
14
12
10
8
16
14
12
10
8
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
6
6
4
4
2
2
0
0
-2
-2
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D031
D032
Figure 30. OP1dB vs Temperature, Low Power Mode
Figure 31. OP1dB vs Supply, Low Power Mode
14
Copyright © 2014–2017, Texas Instruments Incorporated
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ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
6.12 Typical Characteristics - Noise
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, TA = 25°C, BB inputs terminated to
50 Ω and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
-150
-152
-154
-156
-158
-160
-162
-164
-166
-168
-170
-150
-152
-154
-156
-158
-160
-162
-164
-166
-168
-170
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
200
600
1000
1400
1800
2200
2600
200
600
1000
1400
1800
2200
2600
Frequency (MHz)
Frequency (MHz)
D045
D046
Figure 32. Noise vs Temperature, Typical Operating Mode
Figure 33. Noise vs Supply, Typical Operating Mode
-150
-152
-154
-156
-158
-160
-162
-164
-150
-152
-154
-156
-158
-160
-162
-164
-166
-168
-170
-166
TA = -40èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
TA = 25èC
-168
TA = 85èC
-170
200
600
1000
1400
1800
2200
2600
200
600
1000
1400
1800
2200
2600
Frequency (MHz)
Frequency (MHz)
D047
D048
Figure 34. Noise vs Temperature, High Gain Mode
Figure 35. Noise vs Supply, High Gain Mode
-150
-152
-154
-156
-158
-160
-162
-164
-166
-168
-170
-150
-152
-154
-156
-158
-160
-162
-164
-166
-168
-170
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
200
600
1000
1400
1800
2200
2600
200
600
1000
1400
1800
2200
2600
Frequency (MHz)
Frequency (MHz)
D049
D050
Figure 36. Noise vs Temperature, Low Power Mode
Figure 37. Noise vs Supply, Low Power Mode
Copyright © 2014–2017, Texas Instruments Incorporated
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ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
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6.13 Typical Characteristics - Unadjusted CF
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK= 5 V, TA = 25°C, I/Q frequency (fBB
)
4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
-30
-35
-40
-45
-50
-55
-60
-65
-70
-30
-35
-40
-45
-50
-55
-60
-65
-70
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D033
D034
Figure 38. Unadjustable CF vs Temperature,
Typical Operating Mode
Figure 39. Unadjustable CF vs Supply,
Typical Operating Mode
-30
-35
-40
-45
-50
-55
-60
-65
-70
-30
-35
-40
-45
-50
-55
-60
-65
-70
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D035
D036
Figure 40. Unadjustable CF vs Temperature,
High Gain Mode
Figure 41. Unadjustable CF vs Supply, High Gain Mode
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D037
D038
Figure 42. Unadjustable CF vs Temperature,
Low Power Mode
Figure 43. Unadjustable CF vs Supply, Low Power Mode
16
Copyright © 2014–2017, Texas Instruments Incorporated
TRF3722
www.ti.com.cn
ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
6.14 Typical Characteristics - Unadjusted SBS
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK= 5 V, and TA = 25°C, I/Q frequency (fBB
)
4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
-25
-30
-35
-40
-45
-50
-55
-60
-25
-30
-35
-40
-45
-50
-55
-60
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D221
D222
Figure 44. Unadjustable SBS vs Temperature,
Typical Operating Mode
Figure 45. Unadjustable SBS vs Supply,
Typical Operating Mode
-25
-30
-35
-40
-45
-50
-55
-60
-25
-30
-35
-40
-45
-50
-55
-60
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D223
D224
Figure 46. Unadjustable SBS vs
Temperature, High Gain Mode
Figure 47. Unadjustable SBS vs Supply,
High Gain Mode
-25
-30
-35
-40
-45
-50
-55
-60
-25
-30
-35
-40
-45
-50
-55
-60
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D225
D226
Figure 48. Unadjustable SBS vs Temperature,
Low Power Mode
Figure 49. Unadjustable SBS vs Supply, Low Power Mode
Copyright © 2014–2017, Texas Instruments Incorporated
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6.15 Typical Characteristics - LO Harmonic
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C, I/Q frequency (fBB
)
4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
-20
-25
-30
-35
-40
-45
-50
-55
-60
-20
-25
-30
-35
-40
-45
-50
-55
-60
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0
0
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
0
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D051
D201
Figure 50. LO Second Harmonic vs Temperature,
Typical Operating Mode
Figure 51. LO Second Harmonic vs Supply,
Typical Operating Mode
-20
-25
-30
-35
-40
-45
-50
-55
-60
-20
-25
-30
-35
-40
-45
-50
-55
-60
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
500 1000 1500 2000 2500 3000 3500 4000 4500
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D053
D202
Figure 52. LO Second Harmonic vs Temperature,
High Gain Mode
Figure 53. LO Second Harmonic vs Supply,
High Gain Mode
-20
-25
-30
-35
-40
-45
-50
-55
-60
-20
-25
-30
-35
-40
-45
-50
-55
-60
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
500 1000 1500 2000 2500 3000 3500 4000 4500
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D055
D203
Figure 54. LO Second Harmonic vs Temperature,
Low Power Mode
Figure 55. LO Second Harmonic vs Supply,
Low Power Mode
18
Copyright © 2014–2017, Texas Instruments Incorporated
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ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
Typical Characteristics - LO Harmonic (continued)
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C, I/Q frequency (fBB
)
4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0
0
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
0
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D057
D204
Figure 56. LO Third Harmonic vs Temperature,
Typical Operating Mode
Figure 57. LO Third Harmonic vs Supply,
Typical Operating Mode
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
500 1000 1500 2000 2500 3000 3500 4000 4500
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D059
D205
Figure 58. LO Third Harmonic vs Temperature,
High Gain Mode
Figure 59. LO Third Harmonic vs Supply,
High Gain Mode
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
500 1000 1500 2000 2500 3000 3500 4000 4500
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D061
D206
Figure 60. LO Third Harmonic vs Temperature,
Low Power Mode
Figure 61. LO Third Harmonic vs Supply,
Low Power Mode
Copyright © 2014–2017, Texas Instruments Incorporated
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6.16 Typical Characteristics - BB Harmonic
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK= 5 V, and TA = 25°C, I/Q frequency (fBB
4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
Reported BB harmonic is from (fBB) 4.5MHz.
)
-40
-45
-50
-55
-60
-65
-70
-75
-80
-40
-45
-50
-55
-60
-65
-70
-75
-80
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D063
D207
Figure 62. BB-HD2 vs Temperature, Typical Operating Mode
Figure 63. BB-HD2 vs Supply, Typical Operating Mode
-40
-40
-45
-50
-55
-60
-65
-45
-50
-55
-60
-65
-70
-75
-80
-70
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
-75
-80
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D065
D208
Figure 64. BB-HD2 vs Temperature, High Gain Mode
Figure 65. BB-HD2 vs Supply, High Gain Mode
-40
-45
-50
-55
-60
-65
-70
-75
-80
-40
-45
-50
-55
-60
-65
-70
-75
-80
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D067
D209
Figure 66. BB-HD2 vs Temperature, Low Power Mode
Figure 67. BB-HD2 vs Supply, Low Power Mode
20
Copyright © 2014–2017, Texas Instruments Incorporated
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ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
Typical Characteristics - BB Harmonic (continued)
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK= 5 V, and TA = 25°C, I/Q frequency (fBB
)
4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
Reported BB harmonic is from (fBB) 4.5MHz.
-50
-55
-60
-65
-70
-75
-80
-85
-90
-50
-55
-60
-65
-70
-75
-80
-85
-90
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D069
D210
Figure 68. BB-HD3 vs Temperature, Typical Operating Mode
Figure 69. BB-HD3 vs Supply, Typical Operating Mode
-50
-50
-55
-60
-65
-70
-75
-55
-60
-65
-70
-75
-80
-85
-90
-80
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
-85
-90
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D071
D211
Figure 70. BB-HD3 vs Temperature, High Gain Mode
Figure 71. BB-HD3 vs Supply, High Gain Mode
-50
-55
-60
-65
-70
-75
-80
-85
-90
-50
-55
-60
-65
-70
-75
-80
-85
-90
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D073
D212
Figure 72. BB-HD3 vs Temperature, Low Power Mode
Figure 73. BB-HD3 vs Supply, Low Power Mode
Copyright © 2014–2017, Texas Instruments Incorporated
21
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ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
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6.17 Typical Characteristics - RF Output Return Loss
Unless specified all plots were created at RFOUT pin using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C
5
2.5
0
-2.5
-5
-7.5
-10
-12.5
-15
-17.5
-20
400 800 1200 1600 2000 2400 2800 3200 3600 4000
Frequency (MHz)
D120
Frequency (400 MHz to 4200 MHz)
Figure 75. RFOUT S22 vs Frequency
Figure 74. Smith Chart
22
Copyright © 2014–2017, Texas Instruments Incorporated
TRF3722
www.ti.com.cn
ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
6.18 Typical Characteristics - PLL/VCO
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C. Measured at
LO_OUTP with 50 Ω bias resistor and 47 pF series capacitor. Modulator section powered down. Reference frequency is set
to 61.44 MHz. Optimized bias settings as per Table 16.
-25
-50
-25
-50
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
-75
-75
-100
-125
-150
-175
-100
-125
-150
-175
500 1k
10k
100k
1M
10M 40M
500 1k
10k
100k
1M
10M 40M
Offset Frequency (Hz)
Offset Frequency (Hz)
D087
D088
Figure 76. Open Loop Phase Noise at 450 MHz vs
Temperature
Figure 77. Open Loop Phase Noise at 450 MHz vs Supply
-25
-50
-25
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
-50
-75
-75
-100
-125
-150
-175
-100
-125
-150
-175
500 1k
10k
100k
1M
10M 40M
500 1k
10k
100k
1M
10M 40M
Offset Frequency (Hz)
Offset Frequency (Hz)
D089
D090
Figure 78. Open Loop Phase Noise at 900 MHz vs
Temperature
Figure 79. Open Loop Phase Noise at 900 MHz vs Supply
-25
-50
-25
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
-50
-75
-75
-100
-125
-150
-175
-100
-125
-150
-175
500 1k
10k
100k
1M
10M 40M
500 1k
10k
100k
1M
10M 40M
Offset Frequency (Hz)
Offset Frequency (Hz)
D091
D092
Figure 80. Open Loop Phase Noise at 1800 MHz vs
Temperature
Figure 81. Open Loop Phase Noise at 1800 MHz vs Supply
Copyright © 2014–2017, Texas Instruments Incorporated
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Typical Characteristics - PLL/VCO (continued)
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C. Measured at
LO_OUTP with 50 Ω bias resistor and 47 pF series capacitor. Modulator section powered down. Reference frequency is set
to 61.44 MHz. Optimized bias settings as per Table 16.
-25
-40
-50
450 MHz
900 MHz
1800 MHz
2150 MHz
2700 MHz
3600 MHz
4000 MHz
TA = -40èC
TA = 25èC
TA = 85èC
-60
-50
-70
-80
-75
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-100
-125
-150
-175
500 1k
10k
100k
1M
10M 40M
500 1k
10k
100k
1M
10M 40M
Offset Frequency (Hz)
Offset Frequency (Hz)
D215
D095
Figure 82. Open Loop Phase Noise vs Frequency
Figure 83. 450 MHz Frac-N (Closed Loop Phase Noise) vs
Temperature
-40
-50
-40
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
TA = -40èC
TA = 25èC
TA = 85èC
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-100
-110
-120
-130
-140
-150
-160
-170
-180
500 1k
10k
100k
1M
10M 40M
500 1k
10k
100k
1M
10M 40M
Offset Frequency (Hz)
Offset Frequency (Hz)
D096
D097
Figure 84. 450 MHz Frac-N (Closed Loop Phase Noise) vs
Supply
Figure 85. 1800 MHz Frac-N (Closed Loop Phase Noise) vs
Temperature
-40
-40
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
TA = -40èC
TA = 25èC
TA = 85èC
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-100
-110
-120
-130
-140
-150
-160
-170
-180
500 1k
10k
100k
1M
10M 40M
500 1k
10k
100k
1M
10M 40M
Offset Frequency (Hz)
Offset Frequency (Hz)
D098
D099
Figure 86. 1800 MHz Frac-N (Closed Loop Phase Noise) vs
Supply
Figure 87. 2150 MHz Frac-N (Closed Loop Phase Noise) vs
Temperature
24
Copyright © 2014–2017, Texas Instruments Incorporated
TRF3722
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ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
Typical Characteristics - PLL/VCO (continued)
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C. Measured at
LO_OUTP with 50 Ω bias resistor and 47 pF series capacitor. Modulator section powered down. Reference frequency is set
to 61.44 MHz. Optimized bias settings as per Table 16.
-40
-50
-40
-50
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
TA = -40èC
TA = 25èC
TA = 85èC
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-100
-110
-120
-130
-140
-150
-160
-170
-180
500 1k
10k
100k
1M
10M 40M
500 1k
10k
100k
1M
10M 40M
Offset Frequency (Hz)
Offset Frequency (Hz)
D100
D101
Figure 88. 2150 MHz Frac-N (Closed Loop Phase Noise) vs
Supply
Figure 89. 2700 MHz Frac-N (Closed Loop Phase Noise) vs
Temperature
-40
-40
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
TA = -40èC
TA = 25èC
TA = 85èC
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-100
-110
-120
-130
-140
-150
-160
-170
-180
500 1k
10k
100k
1M
10M 40M
500 1k
10k
100k
1M
10M 40M
Offset Frequency (Hz)
Offset Frequency (Hz)
D102
D103
Figure 90. 2700 MHz Frac-N (Closed Loop Phase Noise) vs
Supply
Figure 91. 3600 MHz Frac-N (Closed Loop Phase Noise) vs
Temperature
-40
-40
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
450MHz, Div8
900MHz, Div4
1800MHz, Div2
3600MHz, Div1
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-100
-110
-120
-130
-140
-150
-160
-170
-180
500 1k
10k
100k
1M
10M 40M
500 1k
10k
100k
1M
10M 40M
Offset Frequency (Hz)
Offset Frequency (Hz)
D104
D105
Figure 92. 3600 MHz Frac-N (Closed Loop Phase Noise) vs
Supply
Figure 93. 450, 900, 1800, 3600 MHz Closed Loop Phase
Noise vs Offset Frequency
Copyright © 2014–2017, Texas Instruments Incorporated
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ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
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Typical Characteristics - PLL/VCO (continued)
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C. Measured at
LO_OUTP with 50 Ω bias resistor and 47 pF series capacitor. Modulator section powered down. Reference frequency is set
to 61.44 MHz. Optimized bias settings as per Table 16.
-70
-75
-80
-70
-75
-80
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15,4.75
VCC = 3.30,5.00
VCC = 3.45,5.25
-85
-85
-90
-90
-95
-95
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D106
D107
Figure 94. PFD Spur vs Temperature
Figure 95. PFD Spur vs Supply
-70
-75
-80
-70
-75
-80
1 x PFD
2 x PFD
3 x PFD
-85
-85
-90
-90
-95
-95
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
PFD = 0.68MHz
PFD = 1.28MHz
PFD = 2.56MHz
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D108
D227
Figure 96. PFD Spur vs PFD Multiples
Figure 97. PFD Spur vs Frequency
-70
-75
-80
-70
-75
-80
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15,4.75
VCC = 3.30,5.00
VCC = 3.45,5.25
-85
-85
-90
-90
-95
-95
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D213
D214
Figure 98. 1 x Reference Spur vs Temperature
Figure 99. Reference Spur vs Supply
26
Copyright © 2014–2017, Texas Instruments Incorporated
TRF3722
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ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
Typical Characteristics - PLL/VCO (continued)
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C. Measured at
LO_OUTP with 50 Ω bias resistor and 47 pF series capacitor. Modulator section powered down. Reference frequency is set
to 61.44 MHz. Optimized bias settings as per Table 16.
-70
-75
-80
-10
-20
-30
TA = -40èC
TA = 25èC
TA = 85èC
-85
-40
-90
-50
-95
-60
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
1 x REF
2 x REF
3 x REF
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0.0001
0.001
0.01
0.10.2 0.5 1 2 3 5 10 20
Frequency (MHz) - 61.44MHz
Frequency (MHz) - 3609.6MHz
D111
D112
Figure 100. Reference Spur vs Reference Multiples
Figure 101. 3609.6 MHz Integer Boundary Spur vs
Temperature
-10
-20
-30
-10
-20
-30
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
TA = -40èC
TA = 25èC
TA = 85èC
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-140
-150
-160
-170
-100
-110
-120
-130
-140
-150
-160
-170
0.0001
0.001
0.01
0.10.2 0.5 1 2 3 5 10 20
0.0001
0.001
0.01
0.10.2 0.5 1 2 3 5 10 20
Frequency (MHz) - 3609.6MHz
Frequency (MHz) - 1843.2MHz
D113
D114
Figure 102. 3609.6 MHz Integer Boundary Spur vs Supply
Figure 103. 1843.2 MHz Integer Boundary Spur vs
Temperature
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-18
-20
-22
-24
-26
-28
-30
-32
-34
-36
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
VCO_SEL 0
VCO_SEL 1
VCO_SEL 2
VCO_SEL 3
0.0001
0.001
0.01
0.10.2 0.5 1 2 3 5 10 20
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VCO_TRIM
Frequency (MHz) - 1843.2MHz
D115
D217
V(tune) = 1.1 V
Figure 105. KVCO vs VCO Trim
Figure 104. 1842.2 MHz Integer Boundary Spur vs Supply
Copyright © 2014–2017, Texas Instruments Incorporated
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Typical Characteristics - PLL/VCO (continued)
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C. Measured at
LO_OUTP with 50 Ω bias resistor and 47 pF series capacitor. Modulator section powered down. Reference frequency is set
to 61.44 MHz. Optimized bias settings as per Table 16.
8
4600
4400
4200
4000
3800
3600
3400
3200
3000
2800
2600
2400
2200
2000
1800
VCO_SEL 0
VCO_SEL 1
VCO_SEL 2
VCO_SEL 3
7
6
5
4
3
2
1
0
TA = -40èC
TA = 25èC
TA = 85èC
-1
-2
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VCO_TRIM
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
D216
D116
V(tune) = 1.1 V
Figure 106. Frequency vs VCO_TRIM
Figure 107. LO Output Power at LO_OUTP vs Temperature
8
7
10
5
0
2nd Harmonic
3rd Harmonic
5th Harmonic
-5
6
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
5
4
3
2
1
0
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
-1
-2
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D117
D118
Figure 108. LO Output Power at LO_OUTP vs Supply
Figure 109. LO Harmonics at LO_OUTP vs Frequency
28
Copyright © 2014–2017, Texas Instruments Incorporated
TRF3722
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ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
6.19 Typical Characteristics - Current Consumption
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C. Optimized bias
settings as per Table 16
420
412
404
396
388
380
372
364
356
348
340
420
412
404
396
388
380
372
364
356
348
340
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D228
D229
Figure 110. 3.3V Supply Current vs Temperature, Typical
Operating Mode
Figure 111. 3.3V Supply Current vs Supply, Typical
Operating Mode
420
420
TA = -40èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
412
412
404
396
388
380
372
364
356
348
340
TA = 25èC
TA = 85èC
404
396
388
380
372
364
356
348
340
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D230
D231
Figure 112. 3.3V Supply Current vs Temperature, High Gain
Mode
Figure 113. 3.3V Supply Current vs Supply, High Gain Mode
256
256
254
252
250
248
246
244
242
240
238
236
TA = -40èC
254
TA = 25èC
252
TA = 85èC
250
248
246
244
242
240
238
236
234
232
230
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
234
232
230
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D232
D233
Figure 114. 3.3V Supply Current vs Temperature, Low Power
Mode
Figure 115. 5V Supply Current vs Supply, Low Power Mode
Copyright © 2014–2017, Texas Instruments Incorporated
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ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
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Typical Characteristics - Current Consumption (continued)
28
27.8
27.6
27.4
27.2
27
28
27.8
27.6
27.4
27.2
27
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
26.8
26.6
26.4
26.2
26
26.8
26.6
26.4
26.2
26
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D234
D235
Figure 116. 5V Supply Current vs Temperature, Typical
Operating Mode
Figure 117. 5V Supply Current vs Temperature, Typical
Operating Mode
30
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6.20 Typical Characteristics - Power Dissipation
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C. Optimized bias
settings as per Table 16.
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0.9
0.8
0.9
0.8
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D075
D076
Figure 118. 3.3 V PDISS vs Temperature,
Typical Operating Mode
Figure 119. 3.3 V PDISS vs Supply,
Typical Operating Mode
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0.9
0.8
0.9
0.8
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D077
D078
Figure 120. 3.3 V PDISS vs Temperature,
High Gain Mode
Figure 121. 3.3 V PDISS vs Supply,
High Gain Mode
1.4
1.3
1.2
1.1
1
1.4
1.3
1.2
1.1
1
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0.9
0.8
0.7
0.6
0.5
0.4
0.9
0.8
0.7
0.6
0.5
0.4
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D079
D080
Figure 122. 3.3 V PDISS vs Temperature, Low Power Mode
Figure 123. 3.3 V PDISS vs Supply, Low Power Mode
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Typical Characteristics - Power Dissipation (continued)
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA = 25°C. Optimized bias
settings as per Table 16.
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
0.9
0.8
0.9
0.8
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D081
D082
Figure 124. Total PDISS vs Temperature,
Typical Operating Mode
Figure 125. Total PDISS vs Supply, Typical Operating Mode
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
1.8
TA = -40èC
TA = 25èC
TA = 85èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.9
0.8
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D083
D084
Figure 126. Total PDISS vs Temperature, High Gain Mode
Figure 127. Total PDISS vs Supply, High Gain Mode
1.4
1.4
1.3
1.2
1.1
1
TA = -40èC
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
1.3
TA = 25èC
TA = 85èC
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.9
0.8
0.7
0.6
0.5
0.4
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Frequency (MHz)
Frequency (MHz)
D085
D086
Figure 128. Total PDISS vs Temperature, Low Power Mode
Figure 129. Total PDISS vs Supply, Low Power Mode
32
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7 Parameter Measurement Information
7.1 Serial Interface Timing Diagram
The TRF3722 features a four-wire serial programming interface (4WI) that controls an internal 32-bit shift register
with seven parallel registers. There are total of three signals that must be applied: the clock (CLK), the serial data
(DATA), and the latch enable (LE). The fouth signal is the read back (RDBK) signal. The serial data (DB0-DB31)
are loaded least significant bit (LSB) first, and read on the rising edge of the CLK. LE is asynchronous to the CLK
signal; at its rising edge, the data in the shift register are loaded into the selected internal register. Figure 130
shows the timing diagram the 4WI. Table 1 lists the 4WI timing for the write operation.
t(CL)
tsu1
th
t(CLK)
t(CH)
32nd
Write
clock
pulse
1st Write
CLOCK
DATA
clock
pulse
DB0 (LSB)
Address Bit0
DB1
Address Bit1
DB2
Address Bit2
DB3
Address Bit3
DB29
DB30
DB31 (MSB)
tsu3
tsu2
tw
End of
Write
Cycle pulse
LATCH
ENABLE
Figure 130. 4WI Writing Timing Diagram
Table 1. 4WI Timing for Write Operation
MIN
20
TYP
MAX
UNIT
ns
th
Hold time, data to clock
Setup time, data to clock
Clock low duration
tSU1
tCH
tCL
20
ns
20
ns
Clock High duration
20
ns
tSU2
tCLK
tW
Setup time, clock to enable
Clock period
20
50
50
70
ns
ns
Enable Time
ns
tSU3
Setup time, Latch to Data
ns
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TRF3722 integrates 7 registers: Register 0 (000) to Register 6 (110). Registers 1 through 6 are used to set-up
and control the TRF3722 functionalities, while register 0 is used for the read-back function. Each read-back is
composed by two phases: writing followed by the actual reading of the internal data. This is shown in the timing
diagram in Figure 131.
tsu1
th
T(CL)
t( CLK)
nd
1st Write
clock
32
T(CH)
Write
clock
pulse
pulse
CLOCK
DATA
DB0(LSB)
Address Bi0t
DB3
Address Bi3t
DB1
Address Bi1t
DB2
Address Bi2t
DB29
DB30
DB31(MSB)
tsu2
tw
—End of Write Cycle“
pulse
LATCH ENABLE
nd
32
Write
clock
pulse
1st Read
clock pulse
nd
rd
2nd Read
clock pulse
32 Read
clock pulse
33 Read
clock pulse
CLOCK
tw
—End of Write Cycle“
pulse
td
LATCH
ENABLE
Read
Back
Data
Bit29
Read
Back
Data
Bit1
ReadBack
Data Bit31
ReadBack
Data Bi3t 0
ReadBack
Data Bi0t
READBACK DATA
Figure 131. 4WI Read-Back Timing Diagram
During the writing phase a command is sent to TRF3722 register 0 to set it in read-back mode and to specify
which register is to be read. In the proper reading phase, at each rising clock edge, the internal data is
transferred into the RDBK pin and can be read at the following falling edge (LSB first). The first clock after the LE
goes high (end of writing cycle) is idle and the following 32 clocks pulses will transfer the internal register content
to the RDBK pin. Table 2 shows the Readback timing.
Table 2. 4WI Timing for Readback Timing
MIN
20
20
20
20
20
20
TYP
MAX
UNIT
ns
COMMENT
th
Hold time, data to clock
Setup time, data to clock
Clock low duration
tSU1
tCH
tCL
ns
ns
Clock High duration
ns
tSU2
tSU3
Setup time, clock to enable
Setup time, enable to Readback clock
ns
ns
Delay time, clock to Readback data
output
td
10
tW
Enable Time
Clock period
50
50
ns
ns
Equals Clock period
t(CLK)
34
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8 Detailed Description
8.1 Overview
TRF3722 integrates a high performance direct conversion quadrature modulator with exceptional linearity and
low noise performance. The modulator which upconverts low frequency baseband signal to high frequency RF
typically operates at 0.25 V common mode. It supports seamless interface with current source DACs. It also
features high gain and low power operating modes. Additionally, TRF3722 integrates PLL and VCO to provide
the local oscillator (LO) to the integrated modulator. The PLL and VCO provides excellent phase noise and
extremely low spurious performance. The device also provides an LO output for driving another modulator or
mixer. TRF3722 supports the use of an external VCO or LO signal.
8.2 Functional Block Diagram
NC
VTUNE EXT_VCO BBI_N BBI_P
VCC_TK
VCC
32
35
33
42
23
21
16
14
38
39
LO_OUTN
LO_OUTP
LO Div
9
PLL Div
Charge
Pump
41
44
CP_OUT
REFIN
4
0h
PFD
Pre
Scaler
18
RFOUT
GND
TX Div
S
90h
R Div
N Div
45
43
SDM
40
37
30
26
LE
DATA
CLK
46
47
48
Serial Interface
PD RDBK LD
BBQ_N BBQ_P
GND
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8.3 Feature Description
8.3.1 RF Output
The RF output is single ended and can drive a 50-Ω load. It can be tuned with the use of an output matching
network to optimize the linearity and return loss performance within a selected band.
8.3.2 Baseband Inputs
The baseband inputs consist of the in-phase signal (I) and the quadrature-phase signals (Q). These I and Q
signals are differential. The baseband lines are nominally biased at 0.25-V common-mode voltage (VCM);
however, the device can operate with a VCM in the range of 0 V to 0.5 V. The baseband input lines are normally
terminated externally 50 Ω on TRF3722 evaluation board, though it is possible to modify this value if necessary
to match to an external filter load impedance requirement.
8.3.3 LO Output
The LO outputs are open collector differential outputs and are biased externally. These differential outputs can
be tuned to optimized output power along with OUTBUF_BIAS register settings. It also is possible to use LO
outputs in single ended mode.
8.3.4 PLL Architecture
Figure 132 illustrates a block diagram of the PLL architecture.
The VCO output frequency (fVCO) is given by Equation 1:
æ
ö
÷
÷
÷
÷
ø
f
NFRAC
REF
ç
f
=
x PLL DIV x çNINT +
VCO
ç
ç
è
25
2
RDIV
(1)
f
REF
f
=
PFD
RDIV
(2)
(3)
PLL_DIV_SEL
PLL DIV = 2
æ
ö
÷
÷
÷
÷
ø
NFRAC
ç
f
= f x PLL DIV x çNINT +
VCO
PFD
ç
25
2
ç
è
(4)
Where fREF is the reference input frequency, RDIV is the reference divider division ratio and the phase -
frequency detector frequency is fPFD. PLL_DIV_SEL controls the division ratio of the programmable divider (PLL
DIV) before the dual-modulus prescaler (DMP). NINT and NFRAC/225 is the integer and fractional part of the
fractional divider (N.f), respectively. In Integer mode, the fractional setting is ignored and Equation 5 is applied.
f
= f x PLL DIV x NINT
PFD
VCO
(5)
The complete feedback divider block consists of a PLL DIV, DMP, and N.f. The prescaler can be programmed as
either a 4/5 or an 8/9. N.f includes an A and M digital counters.
36
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Feature Description (continued)
9xt ë/hꢀ
9xt [h
Ext
Loop
Filter
LO_DIV_SEL
fLO
LO Div
O°
TX
Charge
Pump
VTUNE
fVCO
fREF
fPFD
Quad
Div
fTX
9O°
RDIV
PFD
TX_DIV_SEL
NINT
DMP
4/5 8/9
N Div
PLL DIV
PRSC_SEL PLL_DIV_SEL
SDM
NFRAC_DIV
Figure 132. PLL Architecture
8.3.5 External VCO
An external LO or VCO signal may be applied. If an external LO is used the internal PLL can be powered down.
Alternatively, dividers, phase-frequency detector, and charge pump can remain enabled and may be used to
control the VTUNE of an external VCO. EN_EXTVCO is used to select the internal or external VCO.
8.3.6 Loop Filter
Loop filter design is critical for achieving low closed loop phase noise. Complete modulator performance data has
been measured using integer mode loop filter. The integer mode loop filter was designed considering loop
bandwidth 40 kHz and fPFD 2.56 MHz. Phase margin of 60 degrees was considered. Refer to TRF3722EVM
User’s Guide to obtain the details on TRF3722 loop component calculations. Figure 133 shows integer loop filter.
ëÇÜb9
/t_hÜÇ
R3
1.5K
R4
0R
C2
2.2nF
C1
150pF
C4
NS
C3
150pF
R2
6.49K
Figure 133. Integer Loop Filter
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Feature Description (continued)
Frac-N performance data is obtained using the fractional loop filter shown in Figure 134. 40 kHz loop bandwidth
and 15.36 MHz PFD was considered.
ëÇÜb9
/t_hÜÇ
R3
R4
1.1K
1.1K
C2
10nF
C1
1nF
C4
330pF
C3
330pF
R2
1.1K
Figure 134. Fractional Loop Filter
8.3.7 Lock Detect
The lock detect signal is generated in the phase frequency detector by comparing the two input signals. When
the two compared phase signals remain aligned for several clock cycles, an internal signal goes high. The
precision of this comparison is controlled through the LD_ANA_PREC bits. This internal signal is then averaged
and compared against a reference voltage to generate the lock detect (LD) signal. The number of averages used
is controlled through LD_DIG_PREC. Therefore, when the VCO is frequency locked, LD is high. When the VCO
frequency is not locked, LD may pulse high or exhibit periodic behavior.
By default, the internal lock detect signal is made available on the LD terminal. Register bits MUX_CTRL can be
used to control a multiplexer to output other diagnostic signals on the LD output.
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8.4 Device Functional Modes
8.4.1 Selecting PLL Divider Values
With reference to the PLL architecture illustrated in Figure 132, operation of the PLL requires TX_DIV_SEL /
LO_DIV_SEL, PLL_DIV_SEL, RDIV, NINT, NFRAC and PRSC_SEL bits to be calculated.
a. TX_DIV_SEL / LO_DIV_SEL
The LO to the integrated modulator (ƒTX) and additional LO output (ƒLO) frequency is related to fVCO
according to the following:
ƒTX = fVCO / TX DIV
ƒLO = fVCO / LO DIV
Where TX DIV and LO DIV are related to TX_DIV_SEL and LO_DIV_SEL as:
TX_DIV_SEL / LO_DIV_SEL
TX_DIV_SEL = 0
TX_DIV_SEL = 1
TX_DIV_SEL = 2
TX_DIV_SEL = 3
LO_DIV_SEL = 0
LO_DIV_SEL = 1
LO_DIV_SEL = 2
LO_DIV_SEL = 3
TX_DIV / LO_DIV
TX DIV = 1
TX DIV = 2
TX DIV = 4
TX DIV = 8
LO DIV = 1
LO DIV = 2
LO DIV = 4
LO DIV = 8
FREQUENCY RANGE
2050 MHz ≤ ƒTX ≤ 4100 MHz
1025 MHz ≤ ƒTX ≤ 2050 MHz
512.5 MHz ≤ ƒTX ≤ 1025 MHz
256.25 MHz ≤ ƒTX ≤ 512.5 MHz
2050 MHz ≤ ƒLO ≤ 4100 MHz
1025 MHz ≤ ƒLO ≤ 2050 MHz
512.5 MHz ≤ ƒLO ≤ 1025 MHz
256.25 MHz ≤ ƒLO ≤ 512.5 MHz
b. PLL_DIV_SEL
Given fVCO, select PLL_DIV_SEL so that the division ratio PLL DIV limits the input frequency to the
prescaler , fDMP, is limited to a maximum of 3000 MHz.
PLL DIV = min(1, 2, 4) such that fDMP ≤ 3000 MHz
PLL DIV is related to PLL_DIV_SEL according to the following equation:
PLL_DIV = 2PLL_DIV_SEL
This calculation can be restated as Equation 6.
æ
ö
æ
ö
LO DIV x f
LO
3000 MHz
TX DIV x f
TX
÷
÷
÷
÷
ç
ç
PLL DIV = Ceiling
÷ = Ceiling
ç
ç
÷
ç
÷
ç
è
÷
ø
3000 MHz
è
ø
(6)
For both integer and fractional mode it is preferable to operate the fPFD at the highest possible frequency
determined by the required frequency step of the RFOUT or LO_OUT. In Integer mode, select the maximum
fPFD according to Equation 7.
f
f
x TX DIV
VCO, Stepsize
PLL DIV
TX, Stepsize
PLL DIV
f
=
=
PFD
(7)
In Fractional mode, small RF stepsize can be obtained through the fractional divider. In this case, the highest
fPFD frequency should be selected according to the reference clock and system requirements.
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c. RDIV, NINT, NFRAC, PRSC_SEL
The remaing PLL parameters are calculated according to the following equations:
f
REF
RDIV =
f
PFD
æ
ç
ö
÷
÷
÷
f
VCO x RDIV
NINT = floor ç
ç
ç
è
÷
ø
f
x PLL DIV
REF
é
ù
ú
ú
æ
ö
æ
ö
÷
÷
÷
f
÷
ç
25
ç
VCO x RDIV
x PLL DIV
ê
÷
ç
NFRAC = floor
ç
-NINT x 2
÷
êç
ç
÷
÷
ø
ç
ç
÷
f
è
è
ø
ê
ú
REF
The DMP division ratio (P/P+1) can be set to 4/5 or 8/9 through the PRSC_SEL bit. To allow proper
fractional operation, set PRSC_SEL according to:
PRSC_SEL = 0, (P/P+1) = 4/5 for 20 ≤ NINT < 72 in integer mode or 23 ≤ NINT < 75 in fractional mode.
PRSC_SEL = 1, (P/P+1) = 8/9 for NINT ≥ 72 in integer mode or NINT ≥ 75 in fractional mode.
The PRSC_SEL limit at NINT < 75 applies to Fractional mode with third-order modulation. In Integer mode,
the PRSC_SEL = 8/9 should be used with NINT as low as 72. The divider block accounts for either value of
PRSC_SEL without requiring NINT or NFRAC to be adjusted. Then, calculate the maximum input frequency
(fN) to the digital divider. Use the lower of the possible prescaler divide settings, P = (4,8), as shown by
Equation 8.
f
VCO
f
=
N
PLL DIV x P
(8)
Verify that the frequency into the digital divider, fN, is less than or equal to 375 MHz. If fN exceeds 375 MHz,
choose a larger value for PLL_DIV_SEL and recalculate fPFD, RDIV, NINT, NFRAC, and PRSC_SEL.
8.4.2 Setup Example for Integer Mode
Suppose the following operating characteristics fractional example are desired for Integer mode operation:
•
•
•
fREF = 61.44 MHz (reference input frequency)
Step at RF = 2.56 MHz (RF channel spacing)
fRF = 1799.68 MHz (RF frequency)
The VCO range is 2050 MHz to 4100 MHz. Therefore:
•
•
LO DIV = 2 (LO_DIV_SEL = 1)
fVCO = LO DIV × 1799.68 MHz = 3599.36 MHz
In order to keep the frequency of the prescaler below 3000 MHz:
PLL_DIV = 2 (PLL_DIV_SEL = 1)
The desired stepsize at RF is 2.56 MHz, so:
•
•
•
fPFD = 2.56 MHz
fVCO, stepsize = PLL_DIV × fPFD = 5.12 MHz
Using the reference frequency along with the required fPFD gives:
•
•
RDIV = 24
NINT = 703
NINT ≥ 75; therefore, select the 8/9 prescaler.
fN = 3599.36 MHz/(2 × 8) = 224.96 MHz < 375 MHz
This example shows that Integer mode operation gives sufficient resolution for the required stepsize.
8.4.3 Integer and Fractional Mode Selection
The PLL is designed to operate in either Integer mode or Fractional mode. If the desired local oscillator (LO)
frequency is an integer multiple of fPFD, then select integer mode otherwise select fractional mode. In Integer
mode, the feedback divider ratio is an integer, and the fraction is zero. Thus, bits corresponding to the fractional
control in integer mode are don’t care and fractional divider functionality is disabled.
40
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In Fractional mode, the accuracy of the final frequency is set by 25-bit resolution. The RF stepsize is fPFD/225
which is less than 1 Hz for fPFD up to 33 MHz. The appropriate fractional control bits in the serial register must be
programmed. Optimal performance may require tuning the MOD_ORD, ISOURCE_SINK, and ISOURCE_TRIM
values according to the chosen frequency band.
8.4.4 Selecting the VCO and VCO Frequency Control
To achieve a broad frequency tuning range, the TRF3722 integrates multiple VCOs. Each VCO tank uses a bank
of coarse tuning capacitor to bring VCO frequency within a few MHz of the desired value. For a given LO
frequency an appropriate VCO and capacitor array must be selected. The device integrates logic that
automatically selects an appropriate VCO and capacitor array, such that in closed loop V(TUNE) is approximately
equal to the open loop calibration reference voltage set by VCO_CAL_REF. An on-chip temperature sensor
automatically adjusts this reference voltage so that proper lock can be maintained over the temperature range.
The calibration logic is driven by a CAL_CLK signal which is scaled version of the reference frequency according
to CAL_CLK_SEL. For optimum accuracy It is recommended to limit the CAL_CLK frequency to 600 kHz.
When VCO_SEL_MODE is '0', the device automatically selects the VCO and the capacitor array. When
VCO_SEL_MODE is '1', the VCO selected by VCO_SEL is used and the logic automatically selects the capacitor
array. The VCO and capacitor array settings resulting from the calibration can be read from Register 0 - read
back register.
Automatic calibration can be disabled by setting CAL_BYPASS to '1'. In this manual calibration mode, the VCO is
selected through register bits VCO_SEL, while the capacitor array is selected through register bits VCO_TRIM.
Calibration modes are summarized in Table 3.
Table 3. VCO Calibration Modes
MAX CYCLES
CAL_CLK
CAPACITOR
ARRAY
CAL_BYPASS
VCO_SEL_MODE
VCO
0
0
1
0
1
46
34
Automatic
VCO_SEL
VCO_SEL
Automatic
don't care
N/A
VCO_TRIM
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8.5 Register Maps
Table 4. Serial interface Register Summary
Bit
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Bit0
Bit1
Bit2
Register Address
Register Address
Register Address
Register Address
Register Address
Register Address
Bit3
Bit4
Bit5
PWD_PLL
PWD_CP
RSV
RSV
Bit6
IB_MOD_GM
Bit7
PWD_VCO
Bit8
PWD_VCO_MUX
PWD _DIV124
PWD_PRESC
RSV
IB_MOD_LO
VCO_BIAS
Bit9
VCO_TRIM
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
RDIV
PWD_OUTBUF
PWD_LO_DIV
PWD_TX_DIV
PWD_MOD
EN_EXTVCO
RSV
NINT
EN_LOCKDET
VCO_TEST_MODE
CAL_BYPASS
VCOBUF_BIAS
VCOMUX_BIAS
OUTBUF_BIAS
NFRAC
MUX_CTRL
RSV
EN_ISOURCE
REF_INV
NEG_VCO
ISOURCE_SINKB
ISOURCE_TRIM
LD_ANA_PREC
CP_TRISTATE
RSV
PLL_DIV_SEL
PRSC_SEL
RSV
VCO_CAL_IB
ICP
SPEEDUP
LO_DIV_SEL
LO_DIV_BIAS
TX_DIV_SEL
LD_DIG_PREC
VCO_CAL_REF
ICPDOUBLE
CAL_CLK_SEL
RSV
MOD_ORD
VCO_SEL
VCO_SEL_MODE
CAL_ACC
VCO_AMPL_CTRL
VCO_VB_CTRL
DITH_SEL
DEL_SD_CLK
TX_DIV_BIAS
GAIN_CTRL
RSV
RSV
EN_CAL
EN_FRAC_MODE
EN_LD_ISOURCE
42
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8.5.1 Serial interface Register Definition
Table 5. Register 1
Register 1
Bit0
Bit Name
ADDR<0>
ADDR<1>
ADDR<2>
ADDR<3>
ADDR<4>
RDIV<0>
Reset Value
Description
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
1
0
Bit1
Bit2
Register Address Bits
Bit3
Bit4
Bit5
Bit6
RDIV<1>
Bit7
RDIV<2>
Bit8
RDIV<3>
Bit9
RDIV<4>
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
RDIV<5>
13-bit Reference Divider Value
(Rmin = 1, Rmax = 8191)
RDIV<6>
RDIV<7>
RDIV<8>
RDIV<9>
RDIV<10>
RDIV<11>
RDIV<12>
RSV
Reserved
REF_INV
Invert Reference Clock Polarity; 1 = use falling edge
VCO polarity control; 1 = negative slope (negative Kv)
NEG_VCO
ICP<0>
Program charge pump DC current:
[00000] = 1.94 mA
ICP<1>
ICP<2>
[11111] = 0.47 mA
[01010] = 0.97 mA
ICP<3>
ICP<4>
ICPDOUBLE
CAL_CLK_SEL<0>
CAL_CLK_SEL<1>
CAL_CLK_SEL<2>
CAL_CLK_SEL<3>
RSV
1 = Set ICP to double the current
Multiplication or division factor to create VCO calibration clock from
the PFD frequency:
[0000] = Fastest ( Rdiv / 128)
[1111] = Slowest (Rdiv x 128), [1000] = Default (1x Rdiv)
Reserved
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CAL_CLK_SEL[3..0]: Set the frequency divider value used to derive the VCO calibration clock from the reference
frequency.
Table 6. CAL_CLK_SEL Scaling Factor Setting
CAL_CLK_SEL
1111
Scaling Factor
CAL_CLK_SEL
0111
Scaling Factor
1/128
1/64
1/32
1/16
1/8
NA
2
1110
0110
1101
0101
4
1100
0100
8
1011
0011
16
32
64
128
1010
1/4
0010
1001
1/2
0001
1000
1
0000
ICP[4..0]: Set the charge pump current.
Table 7. Charge Pump Current Set-Point
ICP[4..0]
00 000
00 001
00 010
00 011
00 100
00 101
00 110
00 111
01 000
01 001
01 010
01 011
01 100
01 101
01 110
01 111
Current (mA)
1.94
ICP[4..0]
10 000
10 001
10 010
10 011
10 100
10 101
10 110
10 111
11 000
11 001
11 010
11 011
11 100
11 101
11 110
11 111
Current (mA)
0.75
1.76
0.72
1.62
0.69
1.49
0.67
1.38
0.65
1.29
0.63
1.21
0.61
1.14
0.59
1.08
0.57
1.02
0.55
0.97
0.54
0.92
0.52
0.88
0.51
0.84
0.50
0.81
0.48
0.78
0.47
44
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Table 8. Register 2
Register 2
Bit0
Bit Name
ADDR<0>
ADDR<1>
ADDR<2>
ADDR<3>
ADDR<4>
NINT<0>
Reset Value
Description
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
Bit1
Bit2
Register Address Bits
Bit3
Bit4
Bit5
Bit6
NINT<1>
Bit7
NINT<2>
Bit8
NINT<3>
Bit9
NINT<4>
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
NINT<5>
NINT<6>
NINT<7>
PLL N-Divider Value
NINT<8>
NINT<9>
NINT<10>
NINT<11>
NINT<12>
NINT<13>
NINT<14>
NINT<15>
PLL_DIV_SEL<0>
PLL_DIV_SEL<1>
PRSC_SEL
RSV
Select division ratio of divider in front of prescaler
[00] = 1X, [01] = div2, [10] = div4
Select precaler modulus: [0] = 4/5, [1] =8/9
Reserved
RSV
VCO_SEL<0>
VCO_SEL<1>
VCO_SEL_MODE
CAL_ACC<0>
CAL_ACC<1>
EN_CAL
Selects between the four integrated VCOs
[00] = lowest frequency, [11] = highest frequency
Single VCO auto-calibration mode: [1] = active
Error count during the cap array calibration
[00] = 0, [01] = 1/32, [10] = 1/64, [11] =1/128)
Initiate VCO auto-calibration, resets automatically
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Table 9. Register 3
Register 3
Bit0
Bit Name
ADDR<0>
Reset Value
Description
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit1
ADDR<1>
Bit2
ADDR<2>
Register Address Bits
Bit3
ADDR<3>
Bit4
ADDR<4>
Bit5
NFRAC<0>
NFRAC<1>
NFRAC<2>
NFRAC<3>
NFRAC<4>
NFRAC<5>
NFRAC<6>
NFRAC<7>
NFRAC<8>
NFRAC<9>
NFRAC<10>
NFRAC<11>
NFRAC<12>
NFRAC<13>
NFRAC<14>
NFRAC<15>
NFRAC<16>
NFRAC<17>
NFRAC<18>
NFRAC<19>
NFRAC<20>
NFRAC<21>
NFRAC<22>
NFRAC<23>
NFRAC<24>
RSV
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
Fractional PLL N-Divider
0 to 0.99999 in fractional mode
Reserved
RSV
46
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Table 10. Register 4
Register 4
Bit0
Bit Name
ADDR<0>
Reset Value
Description
0
0
Bit1
ADDR<1>
Bit2
ADDR<2>
1
1
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
Register Address Bits
Bit3
ADDR<3>
Bit4
ADDR<4>
Bit5
PWD_PLL
Power -down all PLL blocks: (1 = off)
Bit6
PWD_CP
Power-down Charge Pump: (1=off)
Power-down VCO: (1=off)
Bit7
PWD_VCO
Bit8
PWD_VCO_MUX
PWD _DIV124
PWD_PRESC
RSV
Power-down VCO Mux blocks: (1=off)
Power-down the div 1,2,4 in the PLL f/b path: (1=off)
Power-down Prescaler: (1=off)
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
Reserved
PWD_OUTBUF
PWD_LO_DIV
PWD_TX_DIV
PWD_MOD
Power-down Ouptut Buffer: (1=off)
Power-down LO divider block: (1=off)
Power-down TX divider block: (1=off)
Power-down modulator block: (1=off)
Enable external VCO input buffer: (1 = enabled)
Reserved
EN_EXTVCO
RSV
EN_ISOURCE
LD_ANA_PREC<0>
LD_ANA_PREC<1>
CP_TRISTATE<0>
CP_TRISTATE<1>
SPEEDUP
Enable offset current at CP output (frac-n mode only).
Control precision of Analog Lock Detector:
[00] = H/H (High), [01] = L/L (Low), [10] = H/L , [11] = L/L
Set the charge pump output in Tristate mode:
[00] = Off, [01] = Down, [10] = Up, [11] = Tristate
Enable fast turn on/off time of bias blocks.
LD_DIG_PREC
MOD_ORD<0>
MOD_ORD<1>
MOD_ORD<2>
DITH_SEL
Lock detector precision (increases sampling time if set to 1)
Modulator order (1-4). Not used in integer mode
(defaul 3rd order + dither)
Dither Mode: [0] = pseudo-random, [1] = constant
DEL_SD_CLK<0>
DEL_SD_CLK<1>
EN_FRAC_MODE
DS modulator clock delay. Frac-n mode only.
[00] = Min delay, [11] = max delay
Enable Frac-n mode when set to 1
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Table 11. Register 5
Register 5
Bit0
Bit Name
ADDR<0>
Reset Value
Description
1
0
Bit1
ADDR<1>
Bit2
ADDR<2>
1
1
0
0
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
Register Address Bits
Bit3
ADDR<3>
Bit4
ADDR<4>
Bit5
RSV
Reserved
Bit6
IB_MOD_GM<0>
IB_MOD_GM<1>
IB_MOD_LO<0>
IB_MOD_LO<1>
VCO_BIAS<0>
VCO_BIAS<1>
VCO_BIAS<2>
VCO_BIAS<3>
VCOBUF_BIAS<0>
VCOBUF_BIAS<1>
VCOMUX_BIAS<0>
VCOMUX_BIAS<1>
OUTBUF_BIAS<0>
OUTBUF_BIAS<1>
RSV
Adjust modulator bias current gm
Bit7
Bit8
Adjust modulator BB and LO bias current
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Adjust VCO bias reference current
Adjust VCO buffer reference current
Adjust VCO Mux reference current
Adjust output buffer current
Reserved
RSV
VCO_CAL_IB
Bias current for CAL reference voltage: [0] = PTAT, [1] = Constant
VCO_CAL_REF<0>
VCO_CAL_REF<1>
VCO_CAL_REF<2>
VCO_AMPL_CTRL<0>
VCO_AMPL_CTRL<1>
VCO_VB_CTRL<0>
VCO_VB_CTRL<1>
RSV
VCO calibration reference voltage adjustment
[000] = 0.9 V, [111] = 1.4 V
[011] = recommended = 1.11 V
Adjusts the signal level at the VCO_MUX input:
[00] =max, [11] = min
Adjusts the VCO core bias voltage:
[00] = 1.2 V, [01] = 1.35 V, [10] = 1.5 V, [11] = 1.65 V
Reserved
Enable monitoring of LD to turn on Isource; recommend [0] =
Isource ctrl
Bit31
EN_LD_MON_ISOURCE
1
48
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ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
Table 12. Register 6
Register 6
Bit0
Bit Name
ADDR<0>
Reset Value
Description
0
1
Bit1
ADDR<1>
Bit2
ADDR<2>
1
1
0
0
0
0
0
0
0
0
1
0
0
Register Address Bits
Bit3
ADDR<3>
Bit4
ADDR<4>
Bit5
RSV
Reserved
Bit6
RSV
Bit7
VCO_TRIM<0>
VCO_TRIM<1>
VCO_TRIM<2>
VCO_TRIM<3>
VCO_TRIM<4>
VCO_TRIM<5>
EN_LOCKDET
VCO_TEST_MODE
Bit8
Bit9
VCO capacitor array control bits;
used in manual cal mode
Bit10
Bit11
Bit12
Bit13
Bit14
Enable monitor of lock detector output for autocal mode
Counter mode, measure max and min freq for each VCO
Bypass auto-cal; sets VCO_SEL and VCO_TRIM from Serial
interface
Bit15
CAL_BYPASS
0
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
MUX_CTRL<0>
MUX_CTRL<1>
1
0
0
0
0
0
1
0
0
0
1
0
1
0
1
0
Select signal for test output:
[001] = LD, [010] = NDIV, [100] = RDIV, [110] = A_counter
MUX_CTRL<2>
ISOURCE_SINKB
ISOURCE_TRIM<0>
ISOURCE_TRIM<1>
ISOURCE_TRIM<2>
LO_DIV_SEL<0>
LO_DIV_SEL<1>
LO_DIV_BIAS<0>
LO_DIV_BIAS<1>
TX_DIV_SEL<0>
TX_DIV_SEL<1>
TX_DIV_BIAS<0>
TX_DIV_BIAS<1>
GAIN_CTRL
Offset current polarity
Adjust Isource bias current in frac-n mode.
Adjust LO path divider:
[00] = Div/1, [01] = Div/2, [10] = Div/4. [11] = Div/8
Adjust LO divider bias current:
[00] = 25 uA, [01] = 37.5 uA, [10] = 50 uA, [11] = 62.5 uA
Adjust TX path divider.
[00] = Div/1, [01] = Div/2, [10] = Div/4. [11] = Div/8
Adjust TX divider bias current:
[00] = 25 uA, [01] = 37.5 uA, [10] = 50 uA, [11] = 62.5 uA
Modulator gain control: [0] = Default, [1] = High Gain
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Table 13. READBACK Mode Summary Serial interface Map
Bit
Register 0
RDBK
Bit0
Bit1
Bit2
Register Address
Register Address
Bit3
Bit4
Bit5
CHIP_ID
Bit6
Bit7
Bit8
Bit9
NU
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
R_SAT_ERR
N/C
VCO_TRIM
VCO_SEL
COUNT
MUX_COUNT
RB_REG
MUX_COUNT
RB_ENABLE
50
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ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
Table 14. Register 0 (Readback Only)
Register 0
Bit0
Bit Name
ADDR<0>
Reset Value
Description
0
0
0
1
0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Bit1
ADDR<1>
Bit2
ADDR<2>
Register Address Bits
Chip ID
Bit3
ADDR<3>
Bit4
ADDR<4>
Bit5
CHIP_ID<0>
Bit6
CHIP_ID<1>
Bit7
NU
Bit8
NU
Bit9
NU
Not Used
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
NU
NU
R_SAT_ERR
R-div saturation error for cal
COUNT<0>/NU
COUNT<1>/NU
COUNT<2>/VCO_TRIM<0>
COUNT<3>/VCO_TRIM<1>
COUNT<4>/VCO_TRIM<2>
COUNT<5>/VCO_TRIM<3>
COUNT<6>/VCO_TRIM<4>
COUNT<7>/VCO_TRIM<5>
COUNT<8>/VCO_SEL<0>
COUNT<9>/VCO_SEL<1>
COUNT<10>/VCO_SEL<2>
COUNT<11>
VCO frequency counter high when
MUX_COUNT = 0 and VCO_TEST_MODE = 1
VCO frequency counter low when
MUX_COUNT = 1 and VCO_TEST_MODE = 1
Autocal results for VCO_TRIM and VCO_SEL when
VCO_TEST_MODE = 0
COUNT<12>
COUNT<13>
COUNT<14>
COUNT<15>
COUNT<16>
COUNT<17>
MUX_COUNT
[0] = max freq count, [1] = min freq count
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Table 15. Register RDBK (Write Register for Readback)
RDBK
Bit0
Bit Name
ADDR<0>
ADDR<1>
ADDR<2>
ADDR<3>
ADDR<4>
N/C
Reset Value
Description
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
Bit1
Bit2
Register Address Bits
Bit3
Bit4
Bit5
Bit6
N/C
Bit7
N/C
Bit8
N/C
Bit9
N/C
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
MUX_COUNT
RB_REG<0>
RB_REG<1>
RB_REG<2>
RB_ENABLE
[0] = max freq count, [1] = min freq count
Three LSBs of the address for the register that is being read:
[001] = Register 1
[110] = Register 6
x
x
1
Puts device in Readback mode
52
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ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
8.5.1.1 BIAS SETTINGS
Optimum TRF7322 bias settings used in the performance measurements are shown in Table 16.
Table 16. Register Settings With Optimized Bias Set Used in the Performance Measurement.
TYPICAL OPERATING TYPICAL OPERATING TYPICAL OPERATING
LOW POWER MODE,
REGISTER
BITS
MODE [256MHz-2GHz], MODE [2GHz - 3GHz],
MODE [3GHz -
FRACTIONAL MODE
INT MODE
INT MODE
INT MODE
4.1GHz], INT MODE
REGISTER 1
REGISTER 1
REGISTER 1
REGISTER 1
REGISTER 1
REGISTER 1
RDIV
REF_INV
x
0
x
0
x
0
x
0
x
0
NEG_VCO
ICP
1
1
1
1
1
0
0
0
0
0
ICPDOUBLE
CAL_CLK_SEL
0
0
0
0
0
13
13
13
13
15
REGISTER 2
REGISTER 2
REGISTER 2
REGISTER 2
REGISTER 2
REGISTER 2
REGISTER 2
NINT
PLL_DIV_SEL
PRSC_SEL
VCO_SEL
x
x
x
x
x
0
1
x
x
x
x
x
0
1
x
x
x
x
x
0
1
x
x
x
x
x
0
1
x
x
x
x
x
0
1
VCO_SEL_MODE
CAL_ACC
EN_CAL
REGISTER 3
NFRAC
0
0
0
0
x
REGISTER 4
REGISTER 4
REGISTER 4
REGISTER 4
REGISTER 4
REGISTER 4
REGISTER 4
REGISTER 4
REGISTER 4
REGISTER 4
REGISTER 4
REGISTER 4
REGISTER 4
REGISTER 4
REGISTER 4
REGISTER 4
REGISTER 4
REGISTER 4
REGISTER 4
REGISTER 4
PWD_PLL
PWD_CP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
2
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
5
0
2
0
0
0
0
0
0
0
0
0
0
0
0
1
3
0
0
0
4
0
0
1
PWD_VCO
PWD_VCO_MUX
PWD _DIV124
PWD_PRESC
PWD_OUTBUF
PWD_LO_DIV
PWD_TX_DIV
PWD_MOD
EN_EXTVCO
EN_ISOURCE
LD_ANA_PREC
CP_TRISTATE
SPEEDUP
LD_DIG_PREC
MOD_ORD
DITH_SEL
DEL_SD_CLK
EN_FRAC_MODE
REGISTER 5
REGISTER 5
REGISTER 5
REGISTER 5
REGISTER 5
REGISTER 5
REGISTER 5
REGISTER 5
REGISTER 5
REGISTER 5
REGISTER 5
IB_MOD_GM
IB_MOD_LO
3
0
3
1
2
0
0
0
3
0
VCO_BIAS
15
2
15
2
15
2
15
2
15
2
VCOBUF_BIAS
OUTBUF_BIAS
VCOMUX_BIAS
VCO_CAL_IB
2
2
2
0
2
2
2
2
2
2
0
0
0
0
0
VCO_CAL_REF
VCO_AMPL_CTRL
VCO_VB_CTRL
EN_LD_ISOURCE
3
3
3
3
3
0
0
0
0
0
3
3
3
3
3
0
0
0
0
0
Copyright © 2014–2017, Texas Instruments Incorporated
53
TRF3722
ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
www.ti.com.cn
Table 16. Register Settings With Optimized Bias Set Used in the Performance Measurement. (continued)
TYPICAL OPERATING TYPICAL OPERATING TYPICAL OPERATING
LOW POWER MODE,
REGISTER
BITS
MODE [256MHz-2GHz], MODE [2GHz - 3GHz],
MODE [3GHz -
FRACTIONAL MODE
INT MODE
INT MODE
INT MODE
4.1GHz], INT MODE
REGISTER 6
REGISTER 6
REGISTER 6
REGISTER 6
REGISTER 6
REGISTER 6
REGISTER 6
REGISTER 6
REGISTER 6
REGISTER 6
REGISTER 6
REGISTER 6
VCO_TRIM
EN_LOCKDET
VCO_TEST_MODE
CAL_BYPASS
MUX_CTRL
x
0
0
0
1
0
4
x
2
x
1
0
x
0
0
0
1
0
4
x
2
x
1
0
x
0
0
0
1
0
4
x
2
x
1
0
x
0
0
0
1
0
4
x
0
x
0
0
x
0
0
0
5
0
7
x
2
x
1
0
ISOURCE_SINKB
ISOURCE_TRIM
LO_DIV_SEL
LO_DIV_BIAS
TX_DIV_SEL
TX_DIV_BIAS
GAIN_CTRL
54
Copyright © 2014–2017, Texas Instruments Incorporated
TRF3722
www.ti.com.cn
ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
Figure 135 shows a typical application schematic for the TRF3722.
BBI N IN
BBI P IN
C11
EXT VCO
R15
49.9
R16
49.9
4.7pF
5V or 3.3V
Supply
VCC_TNK
VCC_PLL
FB19
VCC_VCO
FB11
1K
1K
VCC_DIG
FB20
C40
1.0uF
C31
4.7pF
C47
0.1nF
C41
1.0uF
C32
4.7pF
C48
0.1nF
1K
VCC_MOD4
VCC_LO1
FB18
R41
VCC_LO2
1
2
VTUNE
200
C62
1.0uF
1K
VCC_LO2
FB21
LO OUTN
C39
1.0uF
C29
4.7pF
C46
0.1nF
VCC_MOD3
C12 47pF
1K
VCC_MOD2
VCC_MOD3
VCC_MOD1
VCC_MOD4
FB22
37
38
39
40
41
42
43
44
45
46
47
48
49
GND
24
NC4
23
LO_OUTN
LO_OUTP
GND
CP_OUT
VCC_PLL
GND
REFIN
GND
LE
DATA
CLK
PWRPAD
C64
0.1nF
C63
4.7pF
C52
1.0uF
R22
49.9
VCC_MOD4
1K
22
21
20
19
18
17
16
15
14
13
GND
VCC_MOD3
GND
GND
RFOUT
GND
VCC_MOD2
GND
VCC_MOD1
NC3
VCC_PLL
CP OUT
FB23
U1
C18
3.3V
Supply
RF OUT
VCC_LO_OUT
C27
10uF
C44
1.0uF
TRF3722
1K
4.7pF
C42
1.0uF
C55
4.7pF
C56
0.1nF
VCC_MOD2
FB17
LE
DATA
CLOCK
R26
49.9
1K
C54
0.1nF
C53
4.7pF
C38
1.0uF
FB24
C7
47pF
READ BACK
1K
VCC_VCO
FB10
LO OUTP
REFERENCE
PD
LD
VCC_MOD1
1K
VCC_LO_OUT
FB16
C60
1.0uF
VCC_DIG
1K
VCC_LO1
C25
10uF
C43
1.0uF
C37
1.0uF
C28
4.7pF
C45
0.1nF
R13
R12
49.9
49.9
BBQ N IN
BBQ P IN
Figure 135. TRF3722 Application Schematic
Copyright © 2014–2017, Texas Instruments Incorporated
55
TRF3722
ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
www.ti.com.cn
Typical Application (continued)
9.2.1 Design Requirements
Table 17 lists the pin termination requirements and interfacing for the circuit.
Table 17. Termination Requirements and Interfacing
PIN
NAME
DATA
RDBK
LD
DESCRIPTION
47
4WI data input: digital input, high impedance
2
3
Readback output; digital output pins can source or sink up to 8 mA of current
Lock detector digital output, as configured by MUX_CTRL
8,10,27,29
BBI_P, BBI_N, BBQ_P, In-phase and quadrature baseband differential baseband signals. Typical 0.25V common mode is
BBQ_N
needed
18
31
RFOUT
Modulator RF output: must be ac-coupled and can drive 50 Ω load
External local oscillator input: high impedance, normally ac-coupled. If unused terminate to 50 ohms load
Local oscillator output: open-collector output. A pull-up resistor is LO_OUT required, normally ac-coupled.
Reference clock input: high impedance, normally ac-coupled
Serial interface latch enable: digital input, high impedance
EXT_VCO
LO_OUTP, LO_OUTN
REFIN
38,39
44
46
LE
48
CLK
Serial interface clock input: digital input, high impedance
47
DATA
Serial interface data input: digital input, high impedance
56
Copyright © 2014–2017, Texas Instruments Incorporated
TRF3722
www.ti.com.cn
ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
9.2.2 Detailed Design Procedures: DAC to Modulator Interface Network
Digital-to-analog converter (DAC) can interface directly with the TRF3722 modulator. The common-mode voltage
of the DAC and the modulator baseband inputs should be properly maintained. With the proper interface
network, the common-mode voltage of the DAC can be translated to the proper common-mode voltage of the
modulator. The TRF3722 common-mode voltage is typically 0.25 V, and is ideally suited to interface with the
DAC3482/3484 (DAC348x) and DAC38J8x family. The interface network is shown in Figure 136.
50 W
50 W
50 W
50 W
DAC348x / DAC38J8X
0/90
S
~
50 W
50 W
50 W
50 W
TRF3722
Figure 136. DAC348x Interface with the TRF3722 Modulator
The DAC348x requires a load resistance of 25 Ω per branch to maintain its optimum voltage swing of 1-VPP
differential with a 20-mA max current setting. The load of the DAC is separated into two parallel 50-Ω resistors
placed on the input and output side of the low-pass filter. This configuration provides the proper resistive load to
the DAC while also providing a convenient 50-Ω source and load termination for the filter.
Copyright © 2014–2017, Texas Instruments Incorporated
57
TRF3722
ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
www.ti.com.cn
9.2.3 Application Curves: DAC34H84 with TRF3722 Modulator Performance
The cascaded combination of the DAC34H84 and TRF3722 modulator yields excellent system parameters
suitable for high-performance applications. Figure 137 and Figure 138 show 152.9 MHz IF adjacent channel
power ratio (ACPR) performance.
•
•
•
•
•
•
Mode integer
PFD: 3.2 MHz
Reference: 153.6 MHz
LO = 1689.6 MHz
IF = 152.9 MHz
RF= 1842.5 MHz
Figure 138. 152.9 MHz IF, 6 Carrier MC-GSM DAC34H84 +
TRF3722 ACPR Performance
Figure 137. 152.9 MHz IF, DAC34H84 + TRF3722 20 MHz
LTE ACPR
10 Power Supply Recommendations
The TRF3722 is powered by supplying a nominal 3.3 V and 5 V. It can also be powered using only 3.3V supply.
Proper RF bypassing should be placed close to each power supply pin. Ground pin connections should have at
least one ground via close to each ground pin to minimize ground inductance. The PowerPAD™ must be tied to
ground, preferably with the recommended ground via pattern to provide a good thermal conduction path to the
alternate side of the board and to provide a good RF ground for the device. (Refer to Layout Guidelines section
for additional information.)
58
Copyright © 2014–2017, Texas Instruments Incorporated
TRF3722
www.ti.com.cn
ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
11 Layout
11.1 Layout Guidelines
Layout of the application board significantly impacts the analog performance of the TRF3722 device. Noise and
high-speed signals should be prevented from leaking onto power-supply terminals or analog signals. The
TRF3722 device is fitted with a ground slug on the back of the package that must be soldered to the printed
circuit board (PCB) ground with adequate ground vias to ensure a good thermal and electrical connection. The
ground pins of the device can be directly tied to the ground slug pad for a low-inductance path to ground.
Additional ground vias may be added if space allows. Follow these recommendations:
•
Place supply decoupling capacitors physically close to the device, on the same side of the board. Isolate
supply terminals with a ferrite bead.
•
Maintain a continuous ground plane in the vicinity of the device and as return paths for all high-speed signal
lines. Place reference plane vias or decoupling capacitors near any signal line reference transition.
•
•
Power planes should not overlap each other or high-speed signal lines.
Isolate REFIN routing from loop filter lines, control lines, and other high-speed lines.
11.2 Layout Example
wC &5/
.ypass
ë//
/apacitors
Baseband
Terminations
ë//
PLL Loop
Filter
NC
GND
37
38
39
40
41
42
43
24
23
22
21
20
19
18
17
16
15
14
13
LO_OUTN
LO_OUTP
GND
VCC_MOD4
GND
[h hut
ë//
VCC_MOD3
GND
wC &5/
.ypass
/apacitors
bote: 9nsure good wC microstrip or stripline
traces are used to connect tꢀe external
components to tꢀe w9CLb, wC and [h output pins
CP_OUT
VCC_PLL
GND
ë//
GND
RFOUT
GND
wC hut
wC hut
/apacitor
w9CLb
REFIN 44
GND
ë//
VCC_MOD2
GND
5/ .locking
/apacitor
45
LE 46
DATA 47
CLK 48
wC &5/
.ypass
/apacitors
VCC_MOD1
NC
botes:
1ꢁ9nsure all components are connected to a
common wCꢂ5/ ground plane ꢃitꢀ plenty of vias
2ꢁ 9nsure a loꢃ impedance ë// plane is
connected to all ë// terminals
ë//
Baseband
Terminations
wC &5/
.ypass
/apacitors
Figure 139. Layout
版权 © 2014–2017, Texas Instruments Incorporated
59
TRF3722
ZHCSCN0B –MAY 2014–REVISED FEBRUARY 2017
www.ti.com.cn
12 器件和文档支持
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。请单击右上角的通知我进行注册，即可收到任意产品
信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
12.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.3 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
60
版权 © 2014–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TRF3722IRGZR
TRF3722IRGZT
ACTIVE
VQFN
VQFN
RGZ
48
48
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
TRF3722
IRGZ
ACTIVE
RGZ
NIPDAU
TRF3722
IRGZ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TRF3722IRGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RGZ 48
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
TRF3722IRGZR
2500
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
A
7.1
6.9
B
(0.1) TYP
7.1
6.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
PIN 1 INDEX AREA
(0.45) TYP
CHAMFERED LEAD
CORNER LEAD OPTION
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 5.5
5.15±0.1
(0.2) TYP
13
24
44X 0.5
12
25
SEE SIDE WALL
DETAIL
SYMM
2X
5.5
1
36
0.30
0.18
PIN1 ID
(OPTIONAL)
48X
48
37
SYMM
0.1
C A B
C
0.5
0.3
48X
0.05
SEE LEAD OPTION
4219044/D 02/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
5.15)
SYMM
(
48X (0.6)
37
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
25
12
21X (Ø0.2) VIA
TYP
24
13
2X (1.065)
2X (1.26)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219044/D 02/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
SYMM
(
1.06)
37
48X (0.6)
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(0.63)
2X
(1.26)
(R0.05)
TYP
25
12
24
13
2X
(1.26)
2X (0.63)
2X (5.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X
4219044/D 02/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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