TRF7964A_技术文档

TRF7964A

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SLOS787A –MAY 2012–REVISED JUNE 2012

MULTI-PROTOCOL FULLY INTEGRATED 13.56-MHz RFID

READER/WRITER IC

Check for Samples: TRF7964A

1 Introduction

1.1 Features

1

• Completely Integrated Protocol Handling for

ISO15693, ISO18000-3, ISO14443A/B, and

FeliCa

• Integrated Voltage Regulator Output for Other

System Components (MCU, Peripherals,

Indicators), 20 mA (Max)

• Integrated State Machine for ISO14443A

Anticollision (Broken Bytes) Operation

• Input Voltage Range: 2.7 VDC to 5.5 VDC

• Programmable Output Power: +20 dBm

(100 mW), +23 dBm (200 mW)

• Programmable Modulation Depth

• Dual Receiver Architecture With RSSI for

Elimination of "Read Holes" and Adjacent

Reader System or Ambient In-Band Noise

Detection

• Programmable Power Modes for Ultra Low-

Power System Design (Power Down <1 µA)

• Programmable I/O Voltage Levels From

1.8 VDC to 5.5 VDC

• Parallel or SPI Interface (With 128-Byte FIFO)

• Temperature Range: -40°C to 110°C

• 32-Pin QFN Package (5 mm x 5 mm)

• Programmable System Clock Frequency

Output (RF, RF/2, RF/4) from 13.56-MHz or

27.12-MHz Crystal or Oscillator

1.2 Applications

•

Public Transport or Event Ticketing

Passport or Payment (POS) Reader Systems

Product Identification or Authentication

Medical Equipment or Consumables

Access Control, Digital Door Locks

1.3 Description

The TRF7964A is an integrated analog front end and data-framing device for a 13.56-MHz RFID system.

Built-in programming options make it suitable for a wide range of applications for proximity and vicinity

identification systems.

Built-in user-configurable programming options make it suitable for a wide range of applications. The

TRF7964A is configured by selecting the desired protocol in the control registers. Direct access to all

control registers allows fine tuning of various reader parameters as needed.

Documentation, reference designs, EVM, and TI MCU (MSP430, ARM) source code are available.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

TRF7964A

SLOS787A –MAY 2012–REVISED JUNE 2012

www.ti.com

VDD_I/O

MUX

PHASE&

AMPLITUDE

DETECTOR

I/O_0

RSSI

(AUX)

LOGIC

GAIN

RX_IN1

RX_IN2

I/O_1

STATE

CONTROL

LOGIC

RF Level

Detector

I/O_2

RSSI

(EXTERNAL)

I/O_3

[CONTROL

REGISTERS&

COMMAND

LOGIC]

I/O_4

RSSI

(MAIN)

PHASE&

AMPLITUDE

DETECTOR

I/O_5

GAIN

FILTER

& AGC

I/O_6

DIGITIZER

DECODER

MCU

INTERFACE

VDD_PA

TX_OUT

VSS_PA

I/O_7

ISO

PROTOCOL

HANDLING

IRQ

SYS_CLK

DATA_CLK

VIN

TRANSMITTER ANALOG

FRONT END

128 BYTE

FIFO

BIT

FRAMING

SERIAL

CONVERSION

CRC & PARITY

VDD_A

BAND_GAP

VSS_A

VDD_RF

VSS_RF

EN

EN2

DIGITAL CONTROL

STATE MACHINE

ASK/OOK

MOD

VOLTAGE SUPPLY REGULATOR SYSTEMS

[SUPPLY REGULATORS , REFERENCE VOLTAGES ]

VDD_X

VSS

OSC_IN

CRYSTAL / OSCILLATOR

TIMING SYSTEM

VSS_D

OSC_OUT

Figure 1-1. Block Diagram

1.3.1 Detailed Description

RFID – Reader/Writer

The TRF7964A is a high performance 13.56-MHz HF RFID Transceiver IC composed of an integrated

analog front end (AFE) and a built-in data framing engine for ISO15693, ISO14443A, ISO14443B, and

FeliCa. This includes data rates up to 848 kbps for ISO14443 with all framing and synchronization tasks

on board (in default mode). This architecture enables the customer to build a complete cost-effective yet

high-performance multi-protocol 13.56-MHz RFID system together with a low-cost microcontroller (for

example, MSP430).

Other standards and even custom protocols can be implemented by using two of the Direct Modes that

the device offers. These Direct Modes (0 and 1) allow the user to fully control the analog front end (AFE)

and also gain access to the raw subcarrier data or the unframed but already ISO formatted data and the

associated (extracted) clock signal.

The receiver system has a dual input receiver architecture. The receivers also include various automatic

and manual gain control options. The received input bandwidth can be selected to cover a broad range of

input subcarrier signal options.

The received signal strength from transponders, ambient sources, or internal levels is available through

the RSSI register. The receiver output is selectable among a digitized subcarrier signal and any of the

integrated subcarrier decoders. The selected subcarrier decoder delivers the data bit stream and the data

clock as outputs.

The TRF7964A also includes a receiver framing engine. This receiver framing engine performs the CRC

or parity check, removes the EOF and SOF settings, and organizes the data in bytes for ISO14443-A/B,

ISO15693, and FeliCa protocols. Framed data is then accessible to the microcontroller (MCU) through a

128-byte FIFO register.

2

Introduction

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V_DD

V_{DD_X}

V_{DD_I/O}

TX_OUT

Matching

MCU

(MSP430 or ARM)

Parallel

or SPI

TRF7964A

RX_IN 1

RX_IN2

V_SS

V_IN

XIN

Supply: 2.7 V – 5.5 V

Crystal

13.56 MHz

Figure 1-2. Application Block Diagram

A parallel or serial interface (SPI) can be used for the communication between the MCU and the

TRF7964A reader. When the built-in hardware encoders and decoders are used, transmit and receive

functions use a 128-byte FIFO register. For direct transmit or receive functions, the encoders and

decoders can be bypassed so that the MCU can process the data in real time. The TRF7964A supports

data communication levels from 1.8 V to 5.5 V for the MCU I/O interface. The transmitter has selectable

output-power levels of 100 mW (+20 dBm) or 200 mW (+23 dBm) equivalent into a 50-Ω load when using

a 5-V supply.

The transmitter supports OOK and ASK modulation with selectable modulation depth. The TRF7964A also

includes a data transmission engine that comprises low-level encoding for ISO15693, ISO14443A/B and

FeliCa. Included with the transmit data coding is the automatic generation of Start Of Frame (SOF), End

Of Frame (EOF), Cyclic Redundancy Check (CRC), or parity bits.

Several integrated voltage regulators ensure a proper power-supply noise rejection for the complete

reader system. The built-in programmable auxiliary voltage regulator V_{DD_X}(pin 32), is able to deliver up to

20 mA to supply a microcontroller and additional external circuits within the reader system.

Table 1-1. Supported Protocols

Supported Protocols

ISO-14443A/B

FeliCa

ISO-15693,

ISO-18000-3

(Mode 1)

Device

212 kbps,

424 kbps

106 kbps

212 kbps

424 kbps

848 kbps

TRF7964A

√

1.4 Ordering Information

Packaged Devices⁽¹⁾

Package Type⁽²⁾

Transport Media

Quantity

TRF7964ARHBT

250

RHB-32

Tape and Reel

TRF7964ARHBR

3000

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Introduction

3

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1

Introduction .............................................. 1

1.1 Features ............................................. 1

1.2 Applications .......................................... 1

1.3 Description ........................................... 1

1.4 Ordering Information ................................. 3

Physical Characteristics ............................... 5

2.1 Terminal Functions .................................. 5

Electrical Specifications ............................... 8

3.1 Absolute Maximum Ratings .......................... 8

3.2 Recommended Operating Conditions ............... 8

3.3 Dissipation Ratings .................................. 8

3.4 Electrical Characteristics ............................ 9

5.3 Receiver – Analog Section ......................... 16

5.4 Receiver – Digital Section .......................... 18

5.5 Oscillator Section ................................... 23

5.6 Transmitter – Analog Section ...................... 24

5.7 Transmitter – Digital Section ....................... 25

5.8

Transmitter – External Power Amplifier and

2

3

Subcarrier Detector ................................. 26

5.9

TRF7964A IC Communication Interface ........... 26

5.10 Special Direct Mode for Improved MIFARE

Compatibility ........................................ 47

5.11 Direct Commands from MCU to Reader ........... 47

Register Description .................................. 51

6.1 Register Preset ..................................... 51

6.2 Register Overview .................................. 51

6.3 Detailed Register Description ...................... 52

System Design ......................................... 68

7.1 Layout Considerations .............................. 68

6

7

8

4

5

Application Schematic and Layout

Considerations ......................................... 10

4.1

TRF7964A Reader System Using Parallel

Microcontroller Interface ............................ 10

TRF7964A Reader System Using SPI With SS

4.2

Mode ................................................ 11

7.2

Impedance Matching TX_Out (Pin 5) to 50 Ω ...... 68

Detailed System Description ........................ 12

5.1 System Block Diagram ............................. 12

5.2 Power Supplies ..................................... 12

7.3 Reader Antenna Design Guidelines ................ 70

Revision History ....................................... 71

4

Contents

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2 Physical Characteristics

2.1 Terminal Functions

RHB PACKAGE

(TOP VIEW)

32

31

30

29

28

27

26

25

VDD_A

VIN

1

I/0_7

I/0_6

I/0_5

I/0_4

I/0_3

I/0_2

I/0_1

I/0_0

24

23

22

21

20

19

18

17

2

3

4

5

6

7

8

VDD_RF

VDD_PA

TX_OUT

VSS_PA

VSS_RX

RX_IN1

Pad

9

10

11

12

13

14

15

16

Figure 2-1. Pin Assignments

Physical Characteristics

5

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Table 2-1. Terminal Functions

TERMINAL

(1)

TYPE

DESCRIPTION

NAME

NO.

1

V_{DD_A}

V_IN

OUT

SUP

OUT

INP

Internal regulated supply (2.7 V to 3.4 V) for analog circuitry

External supply input to chip (2.7 V to 5.5 V)

2

V_{DD_RF}

V_{DD_PA}

3

Internal regulated supply (2.7 V to 5 V), normally connected to V_{DD_PA}(pin 4)

Supply for PA; normally connected externally to V_{DD_RF}(pin 3)

RF output (selectable output power, 100 mW or 200 mW, with V_DD= 5 V)

Negative supply for PA; normally connected to circuit ground

Negative supply for RX inputs; normally connected to circuit ground

Main RX input

4

TX_OUT

V_{SS_PA}

5

OUT

SUP

INP

6

V_{SS_RX}

7

RX_IN1

RX_IN2

V_SS

8

9

INP

Auxiliary RX input

10

11

SUP

OUT

Chip substrate ground

BAND_GAP

Bandgap voltage (V_BG= 1.6 V); internal analog voltage reference

Selection between ASK and OOK modulation (0 = ASK, 1 = OOK) for Direct Mode 0 or 1.

Can be configured as an output to provide the received analog signal output.

Interrupt request

ASK/OOK

IRQ

12

13

14

BID

OUT

INP

External data modulation input for Direct Mode 0 or 1

Subcarrier digital data output (see registers 0x1A and 0x1B)

Negative supply for internal analog circuits; connected to GND

Supply for I/O communications (1.8 V to V_IN) level shifter. V_INshould be never exceeded.

I/O pin for parallel communication

MOD

OUT

SUP

INP

V_{SS_A}

V_{DD_I/O}

I/O_0

I/O_1

15

16

17

18

BID

I/O pin for parallel communication

I/O_2

I/O_3

I/O_4

I/O_5

19

20

21

22

BID

TX_Enable (in Special Direct Mode)

I/O pin for parallel communication

TX_Data (in Special Direct Mode)

I/O pin for parallel communication

Slave Select signal in SPI mode

I/O pin for parallel communication

Data clock output in Direct Mode 1 and Special Direct Mode

I/O pin for parallel communication

I/O_6

I/O_7

23

24

BID

MISO for serial communication (SPI)

Serial bit data output in Direct Mode 1 or subcarrier signal in Direct Mode 0

I/O pin for parallel communication.

MOSI for serial communication (SPI)

Selection of power down mode. If EN2 is connected to V_IN, then V_{DD_X}is active during power

down mode 2 (for example, to supply the MCU).

EN2

25

26

INP

DATA_CLK

Data Clock input for MCU communication (parallel and serial)

If EN = 1 (EN2 = don't care) the system clock for MCU is configured. Depending on the crystal

that is used, options are as follows (see register 0x09):

SYS_CLK

27

OUT

13.56-MHz crystal: Off, 3.39 MHz, 6.78 MHz, or 13.56 MHz

27.12-MHz crystal: Off, 6.78 MHz, 13.56 MHz, or 27.12 MHz

If EN = 0 and EN2 = 1, then system clock is set to 60 kHz

Chip enable input (If EN = 0, then chip is in sleep or power-down mode).

Negative supply for internal digital circuits

Crystal or oscillator output

EN

28

29

30

INP

SUP

OUT

INP

V_{SS_D}

OSC_OUT

Crystal or oscillator input

OSC_IN

31

OUT

Crystal oscillator output

(1) SUP = Supply, INP = Input, BID = Bidirectional, OUT = Output

Physical Characteristics

6

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Table 2-1. Terminal Functions (continued)

TERMINAL

NAME

(1)

TYPE

DESCRIPTION

NO.

32

Internally regulated supply (2.7 V to 3.4 V) for digital circuit and external devices (for example,

MCU)

V_{DD_X}

OUT

SUP

Thermal Pad

PAD

Chip substrate ground

Physical Characteristics

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3 Electrical Specifications

(1) (2)

3.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

V_IN

I_IN

Input voltage range

Maximum current V_IN

-0.3 V to 6 V

150 mA

2 kV

HBM (Human-Body Model)

CDM (Charged-Device Model)

MM (Machine Model)

ESD

Electrostatic discharge rating

500 V

200 V

Any condition

140°C

T_J

Maximum operating virtual junction temperature

Storage temperature range

(3)

Continuous operation, long-term reliability

125°C

T_STG

-55°C to 150°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Operating Conditions are not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to substrate ground terminal V_SS

.

(3) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may

result in reduced reliability or lifetime of the device.

3.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.7

-40

TYP

5

MAX UNIT

V_IN

T_A

T_J

Operating input voltage

5.5

110

125

V

Operating ambient temperature

Operating virtual junction temperature

25

°C

3.3 Dissipation Ratings

POWER RATING⁽²⁾

_A≤ 25°C

2.7 W

(1)

PACKAGE

θ_JC

T

_A≤ 85°C

RHB (32 pin)

31°C/W

36.4°C/W

1.1 W

(1) This data was taken using the JEDEC standard high-K test PCB.

(2) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to increase substantially.

Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-

term reliability.

8

Electrical Specifications

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3.4 Electrical Characteristics

Typical operating conditions are TA = 25°C, V_IN= 5 V, Full-Power mode (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

All building blocks disabled, including supply-

voltage regulators; measured after 500-ms settling

time (EN = 0, EN2 = 0)

I_PD1

Supply current in Power Down Mode 1

0.5

5

µA

The SYS_CLK generator and V_{DD_X}remain active

to support external circuitry; measured after 100-ms

settling time (EN = 0, EN2 = 1)

Supply current in Power Down Mode 2 (Sleep

Mode)

I_PD2

120

200

µA

Oscillator running, supply-voltage regulators in low-

consumption mode (EN = 1, EN2 = x)

I_STBY

I_ON1

I_ON2

Supply current in stand-by mode

1.9

10.5

70

3.5

14

78

mA

Supply current without antenna driver current

Supply current – TX (half power)

Oscillator, regulators, RX and AGC active, TX is off

Oscillator, regulators, RX and AGC and TX active,

P_OUT= 100 mW

Oscillator, regulators, RX and AGC and TX active,

P_OUT= 200 mW

I_ON3

Supply current – TX (full power)

130

150

mA

V_POR

V_BG

Power-on reset voltage

Bandgap voltage (pin 11)

Input voltage at V_IN

1.4

1.5

2

2.6

1.7

V

Internal analog reference voltage

1.6

Regulated output voltage for analog circuitry (pin

1)

V_{DD_A}

V_IN= 5 V

3.1

3.5

3.4

3.8

V

V_{DD_X}

Regulated supply for external circuitry

Maximum output current of V_{DD_X}

Output voltage pin 32, V_IN= 5 V

Output current pin 32, V_IN= 5 V

Half-power mode, V_IN= 2.7 V to 5.5 V

Full-power mode, V_IN= 2.7 V to 5.5 V

3.8

20

12

6

V

I_{VDD_Xmax}

mA

8

4

(1)

R_RFOUT

Antenna driver output resistance

Ω

R_RFIN

RX_IN1 and RX_IN2 input resistance

4

10

20

kΩ

Maximum RF input voltage at RX_IN1 and

RX_IN2

V_{RF_INmax}

V_{RF_INmax}should not exceed V_IN

3.5

V_pp

f_SUBCARRIER= 424 kHz

1.4

2.1

2.5

3

Minimum RF input voltage at RX_IN1 and

RX_IN2 (input sensitivity)⁽²⁾

V_{RF_INmin}

mV_pp

f_SUBCARRIER= 848 kHz

f_{SYS_CLK}

f_C

SYS_CLK frequency

Carrier frequency

In power mode 2, EN = 0, EN2 = 1

Defined by external crystal

25

2

60

120

kHz

13.56

MHz

Time until oscillator stable bit is set (register

0x0F)⁽³⁾

t_CRYSTAL

f_{D_CLKmax}

V_IL

Crystal run-in time

3

8

ms

MHz

V

Depends on capacitive load on the I/O lines,

recommendation is 2 MHz⁽⁴⁾

Maximum DATA_CLK frequency⁽⁴⁾

Input voltage - logic low

10

0.2 x

V_{DD_I/O}

I/O lines, IRQ, SYS_CLK, DATA_CLK, EN, EN2

0.8 x

V_{DD_I/O}

V_IH

Input voltage threshold, logic high

V

R_OUT

Output resistance I/O_0 to I/O_7

Output resistance R_{SYS_CLK}

500

200

800

400

Ω

R_{SYS_CLK}

DATA_CLK time high or low, one half of

DATA_CLK at 50% duty cycle

t_LO/HI

Depends on capacitive load on the I/O lines⁽⁴⁾

250

62.5

200

50

ns

t_STE,LEAD

t_STE,LAG

Slave select lead time, slave select low to clock

Slave select lag time, last clock to slave Select

high

t_SU,SI

MOSI input data setup time

MOSI input data hold time

MISO input data setup time

MISO input data hold time

MISO output data valid time

15

30

ns

t_HD,SI

t_SU,SO

t_HD,SO

t_VALID,SO

DATA_CLK edge to MISO valid, C_L≤ 30 pF

50

75

(1) Antenna driver output resistance

(2) Measured with subcarrier signal at RX_IN1 or RX_IN2 and measured the digital output at MOD pin with register 0x1A bit 6 = 1.

(3) Depends on the crystal parameters and components

(4) Recommended DATA_CLK speed is 2 MHz; higher data clock depends on the capacitive load. Maximum SPI clock speed should not

exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output

resistance of 400 Ω (12-ns time constant when 30-pF load used).

Electrical Specifications

9

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4 Application Schematic and Layout Considerations

4.1 TRF7964A Reader System Using Parallel Microcontroller Interface

4.1.1 General Application Considerations

Figure 4-1 shows the most flexible TRF7964A application schematic. Both ISO15693, ISO14443 and

FeliCa systems can be addressed. Due to the low clock frequency on the DATA_CLK line, the parallel

interface is the most robust way to connect the TRF7964A with the MCU.

Figure 4-1 shows matching to a 50-Ω port, which allows connecting to a properly matched 50-Ω antenna

circuit or RF measurement equipment (for example, a spectrum analyzer or power meter).

4.1.2 Schematic

Figure 4-1 shows a sample application schematic for a parallel MCU interface.

OSC_OUT

3

JTAG

057-014-2

2

1

GND1OUT

IN GND2

C24 27pF

TDO/TDI

TDI

TMS

VCC

C23

27pF

OSC_IN

4

X4-1 -2

X4-3 -4

X4-5 -6

X4-7 -8

X4-9 -10

X4

X

TCK

GND

RST_NMI

GND

R4 100R

X4-11 4-12

X4-13 4-14

VCC

X

SMA-142-0701-801/806

X3

(+2.7VDC - 5.5VDC)

VIN

C26

C25

2.2uF

0.01uF

TP

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

1

VCC

SYS_CLK

C19

0.01uF

C20

GND

VCC

2

GND

C16

C15

0.01uF

C18

2.2uF

GND

C17

R5

47k

2.2uF

3

X2

RST_NMI

TCK

TMS

TDI

TDO/TDI

2.2uF

4

EN

0.01uF

TCK

5

TMS

RST_NMI

C1

GND

6

R6

10k

MC-921

GND

7

8

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

0.1uF

P4.7/TBCLK

P4.6/TBOUTH/ACLK

P4.5/TB2

VDD_A

VIN

I/O_7

I/O_6

I/O_5

I/O_4

GND

C6 10pF

9

C2

1500pF

C13

12pF

GND

10

11

12

13

14

15

16

17

18

19

20

TRF7964A

33

VDD_RF

VDD_PA

TX_OUT

VSS_PA

VSS_RX

RX_IN1

L3

1.5uH

P4.4/TB1

R3

0

L2

L1

P4.3/TB0

MOD

IRQ

ASK/OOK

GND(PAD) I/O_3

P4.2/TB2

R2

0

330nH

150nH

I/O_2

I/O_1

I/0_0

P4.1/TB1

C11 C10

8

C

C7 C4

R1

6.8k

C14

68pF

C12

12pF

1500pF

C3

GND

P4.0/TB0

1200pF

27pF 100pF 220pF

680pF

GND

C5

C9

GND GND

TXD

RXD

DATA_CLK

680pF

1200pF

GND

C21

0.01uF

GND

C22

2.2uF

GND

Figure 4-1. Application Schematic – Parallel MCU Interface

An MSP430F2370 (32kB Flash, 2kB RAM) is shown in Figure 4-1. Minimum MCU requirements depend

on application requirements and coding style. If only one ISO protocol or a limited command set of a

protocol needs to be supported, MCU Flash and RAM requirements can be significantly reduced. Be

aware that recursive inventory and anticollision commands require more RAM than single slotted

operations. For example, current reference firmware for ISO15693 (with host interface) is approximately

8kB, using 512B RAM; for all supported protocols (also with same host interface) the reference firmware is

approximately 12kB and uses a minimum of 1kB RAM. An MCU capable of running its GPIOs at

13.56 MHz is required for Direct Mode 0 operations.

10

Application Schematic and Layout Considerations

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4.2 TRF7964A Reader System Using SPI With SS Mode

4.2.1 General Application Considerations

Figure 4-2 shows the TRF7964A application schematic optimized for both ISO15693 and ISO14443

systems using the Serial Port Interface (SPI). Short SPI lines, proper isolation of radio frequency lines,

and a proper ground area are essential to avoid interference. The recommended clock frequency on the

DATA_CLK line is 2 MHz.

Figure 4-2 shows matching to a 50-Ω port, which allows connecting to a properly matched 50-Ω antenna

circuit or RF measurement equipment (for example, a spectrum analyzer or power meter).

4.2.2 Schematic

Figure 4-2 shows a sample application schematic for SPI with an SS mode MCU interface.

OSC_OUT

3

JTAG

2

1

GND1OUT

IN GND2

057-014-2

X4-1 -2

X4-3 -4

X4-5 -6

X4-7 -8

X4-9 -10

C24 27pF

TDO/TDI

TDI

TMS

TCK

GND

VCC

C23

27pF

OSC_IN

4

X4

X

GND

RST_NMI

X4-11 4-12

X4-13 4-14

R4 100R

VCC

(+2.7VDC - 5.5VDC)

VIN

X

SMA-142-0701-801/806

X3

C26

C25

2.2uF

0.01uF

TP

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

1

VCC

SYS_CLK

C19

C20

2.2uF

VCC

2

GND

X2

GND

C16

C15

C18

2.2uF

C17

R5

47k

3

0.01uF

RST_NMI

TCK

2.2uF

4

EN

0.01uF

GND

0.01uF

TCK

TMS

5

RST_NMI

C1

GND

TMS

6

R6

10k

MC-921

GND

TDI

7

8

TDO/TDI

1

24

23

22

21

20

19

18

17

0.1uF

P3.1

P4.7/TBCLK

P4.6/TBOUTH/ACLK

P4.5/TB2

VDD_A

VIN

I/O_7

I/O_6

I/O_5

I/O_4

GND

C6 10pF

2

3

4

5

6

7

8

9

P3.2

C2

1500pF

C13

12pF

TRF7964A

33

GND

10

11

12

13

14

15

16

17

18

19

20

P3.7

VDD_RF

VDD_PA

TX_OUT

VSS_PA

VSS_RX

RX_IN1

L3

1.5uH

P3.0

P4.4/TB1

R3

0

L2

L1

P3.6

P4.3/TB0

MOD

IRQ

ASK/OOK

VCC

GND(PAD) I/O_3

P4.2

P4.2/TB2

R2

0

330nH

150nH

I/O_2

I/O_1

I/0_0

C7

VDD_X

P4.1/TB1

C11 C10

8

C

C4

R1

6.8k

C14

68pF

C12

12pF

1500pF

C3

GND

P4.0/TB0

680pF

1200pF

27pF 100pF 220pF

GND

C5

GND

P3.0

P3.1

P3.2

C9

GND GND

TXD

RXD

DATA_CLK

680pF

1200pF

GND

C21

0.01uF

GND

C22

2.2uF

GND

Figure 4-2. Application Schematic – SPI With SS Mode MCU Interface

An MSP430F2370 (32kB Flash, 2kB RAM) is shown in Figure 4-2. Minimum MCU requirements depend

on application requirements and coding style. If only one ISO protocol or a limited command set of a

protocol needs to be supported, MCU Flash and RAM requirements can be significantly reduced and user

should be aware that recursive inventory and anticollision commands require more RAM than single

slotted operations. For example, current reference firmware for ISO15693 (with host interface) is

approximately 8kB, using 512B RAM and for all supported protocols (also with same host interface) the

reference firmware is approximately 12kB and uses a minimum of 1kB RAM. An MCU capable of running

its GPIOs at 13.56 MHz is required for Direct Mode 0 operations.

Application Schematic and Layout Considerations

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5 Detailed System Description

5.1 System Block Diagram

Figure 5-1shows a block diagram of the TRF7964A.

VDD_I/O

MUX

PHASE&

AMPLITUDE

DETECTOR

I/O_0

RSSI

(AUX)

LOGIC

GAIN

RX_IN1

RX_IN2

I/O_1

STATE

CONTROL

LOGIC

RF Level

Detector

I/O_2

RSSI

(EXTERNAL)

I/O_3

[CONTROL

REGISTERS&

COMMAND

LOGIC]

I/O_4

RSSI

(MAIN)

PHASE&

AMPLITUDE

DETECTOR

I/O_5

GAIN

FILTER

& AGC

I/O_6

DIGITIZER

DECODER

MCU

INTERFACE

VDD_PA

TX_OUT

VSS_PA

I/O_7

ISO

PROTOCOL

HANDLING

IRQ

SYS_CLK

DATA_CLK

VIN

TRANSMITTER ANALOG

FRONT END

128 BYTE

FIFO

BIT

FRAMING

SERIAL

CONVERSION

CRC & PARITY

VDD_A

BAND_GAP

VSS_A

VDD_RF

VSS_RF

EN

EN2

DIGITAL CONTROL

STATE MACHINE

ASK/OOK

MOD

VOLTAGE SUPPLY REGULATOR SYSTEMS

[SUPPLY REGULATORS , REFERENCE VOLTAGES ]

VDD_X

VSS

OSC_IN

CRYSTAL / OSCILLATOR

TIMING SYSTEM

VSS_D

OSC_OUT

Figure 5-1. System Block Diagram

5.2 Power Supplies

The TRF7964A positive supply input V_IN(pin 2) sources three internal regulators with output voltages

V_{DD_RF}, V_{DD_A}and V_{DD_X}. All regulators use external bypass capacitors for supply noise filtering and must

be connected as indicated in reference schematics. These regulators provide a high power supply reject

ratio (PSRR) as required for RFID reader systems. All regulators are supplied by V_IN(pin 2).

The regulators are not independent and have common control bits in register 0x0B for output voltage

setting. The regulators can be configured to operate in either automatic or manual mode (register 0x0B,

bit 7). The automatic regulator setting mode ensures an optimal compromise between PSRR and the

highest possible supply voltage for RF output (to ensure maximum RF power output). The manual mode

allows the user to manually configure the regulator settings.

5.2.1 Supply Arrangements

Regulator Supply Input: V_IN

The positive supply at V_IN(pin 2) has an input voltage range of 2.7 V to 5.5 V. V_INprovides the supply

input sources for three internal regulators with the output voltages V_{DD_RF}, V_{DD_A}, and V_{DD_X}. External

bypass capacitors for supply noise filtering must be used (per reference schematics).

NOTE

V_INmust be the highest voltage supplied to the TRF7964A.

12

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RF Power Amplifier Regulator: V_{DD_RF}

The V_{DD_RF}(pin 3) regulator is supplying the RF power amplifier. The voltage regulator can be set for

either 5-V or 3-V operation. External bypass capacitors for supply noise filtering must be used (per

reference schematics). When configured for 5-V manual-operation, the V_{DD_RF}output voltage can be set

from 4.3 V to 5 V in 100-mV steps. In 3-V manual-operation, the output can be programmed from 2.7 V to

3.4 V in 100-mV steps. The maximum output current capability for 5-V operation is 150 mA and for 3-V

operation is 100 mA.

Analog Supply Regulator: V_{DD_A}

Regulator V_{DD_A}(pin 1) supplies the analog circuits of the device. The output voltage setting depends on

the input voltage and can be set for 5-V and 3-V operation. When configured for 5-V manual-operation,

the output voltage is fixed at 3.4 V. External bypass capacitors for supply noise filtering must be used (per

reference schematics). When configured for 3-V manual-operation, the V_{DD_A}output can be set from 2.7 V

to 3.4 V in 100-mV steps (see Table 5-2).

Note: the configuration of V_{DD_A}and V_{DD_X}regulators are not independent from each other. The V_{DD_A}

output current should not exceed 20 mA.

Digital Supply Regulator: V_{DD_X}

The digital supply regulator V_{DD_X}(pin 32) provides the power for the internal digital building blocks and

can also be used to supply external electronics within the reader system. When configured for 3-V

operation, the output voltage can be set from 2.7 to 3.4 V in 100-mV steps. External bypass capacitors for

supply noise filtering must be used (per reference schematics).

Note: the configuration of the V_{DD_A}and V_{DD_X}regulators are not independent from each other. The V_{DD_X}

output current should not exceed 20 mA.

The RF power amplifier regulator (V_{DD_RF}), analog supply regulator (V_{DD_A}) and digital supply regulator

(V_{DD_X}) can be configured to operate in either automatic or manual mode described in Section 5.2.2. The

automatic regulator setting mode ensures an optimal compromise between PSRR and the highest

possible supply voltage to ensure maximum RF power output.

By default, the regulators are set in automatic regulator setting mode. In this mode, the regulators are

automatically set every time the system is activated by setting EN input High or each time the automatic

regulator setting bit, B7 in register 0x0B is set to a 1. The action is started on the 0 to 1 transition. This

means that, if the user wants to re-run the automatic setting from a state in which the automatic setting bit

is already high, the automatic setting bit (B7 in register 0x0B) should be changed: 1-0-1.

By default, the regulator setting algorithm sets the regulator outputs to a "Delta Voltage" of 250 mV below

V_IN, but not higher than 5 V for V_{DD_RF}and 3.4 V for V_{DD_A}and V_{DD_A}. The "Delta Voltage" in automatic

regulator mode can be increased up to 400 mV (for details, see bits B0 to B2 in register 0x0B).

Power Amplifier Supply: V_{DD_PA}

The power amplifier of the TRF7964A is supplied through V_{DD_PA}(pin 4). The positive supply pin for the RF

power amplifier is externally connected to the regulator output V_{DD_RF}(pin 3).

I/O Level Shifter Supply: V_{DD_I/O}

The TRF7964A has a separate supply input V_{DD_I/O}(pin 16) for the built-in I/O level shifter. The supported

input voltage ranges from 1.8 V to V_IN, not exceeding 5.5 V. Pin 16 is used to supply the I/O interface pins

(I/O_0 to I/O_7), IRQ, SYS_CLK, and DATA_CLK pins of the reader. In typical applications, V_{DD_I/O}is

directly connected to V_{DD_X}, while V_{DD_X}also supplies the MCU. This ensures that the I/O signal levels of

the MCU match the logic levels of the TRF7964A.

Negative Supply Connections: V_SS, V_{SS_TX}, V_{SS_RX}, V_{SS_A}, V_{SS_PA}

The negative supply connections V_{SS_X}of each functional block are all externally connected to GND.

Detailed System Description

13

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The substrate connection is V_SS(pin 10), the analog negative supply is V_{SS_A}(pin 15), the logic negative

supply is V_{SS_D}(pin 29), the RF output stage negative supply is V_{SS_PA}(pin 6), and the negative supply for

the RF receiver V_{SS_RX}(pin 7).

5.2.2 Supply Regulator Settings

The input supply voltage mode of the reader needs to be selected. This is done in the Chip Status Control

register (0x00). Bit 0 in register 0x00 selects between 5-V or 3-V input supply voltage. The default

configuration is 5 V, which reflects an operating supply voltage range of 4.3 V to 5.5 V. If the supply

voltage is below 4.3 V, the 3-V configuration should be used.

The various regulators can be configured to operate in automatic or manual mode. This is done in the

Regulator and I/O Control register (0x0B) as shown in Table 5-1 and Table 5-2.

Table 5-1. Supply Regulator Setting: 5-V System

(1)

Register

Address

(hex)

Option Bits Setting in Regulator Control Register

Comments

B7

B6

B5

B4

B3

B2

B1

B0

Automatic Mode (default)

0B

1

x

1

0

1

0

Automatic regulator setting 250-mV difference

Automatic regulator setting 350-mV difference

Automatic regulator setting 400-mV difference

0B

Manual Mode

0B

0

x

1

0

1

0

1

0

1

0

1

0

1

0

1

0

V_{DD_RF}= 5 V, V_{DD_A}= 3.4 V, V_{DD_X}= 3.4 V

V_{DD_RF}= 4.9 V, V_{DD_A}= 3.4 V, V_{DD_X}= 3.4 V

V_{DD_RF}= 4.8 V, V_{DD_A}= 3.4 V, V_{DD_X}= 3.4 V

V_{DD_RF}= 4.7 V, V_{DD_A}= 3.4 V, V_{DD_X}= 3.4 V

V_{DD_RF}= 4.6 V, V_{DD_A}= 3.4 V, V_{DD_X}= 3.4 V

V_{DD_RF}= 4.5 V, V_{DD_A}= 3.4 V, V_{DD_X}= 3.4 V

V_{DD_RF}= 4.4 V, V_{DD_A}= 3.4 V, V_{DD_X}= 3.4 V

V_{DD_RF}= 4.3 V, V_{DD_A}= 3.4 V, V_{DD_X}= 3.4 V

(1) x = Don't care

Table 5-2. Supply Regulator Setting: 3-V System

(1)

Register

Address

(hex)

Option Bits Setting in Regulator Control Register

Comments

B7

B6

B5

B4

B3

B2

B1

B0

Automatic Mode (default)

0B

1

x

1

0

1

0

Automatic regulator setting 250-mV difference

Automatic regulator setting 350-mV difference

Automatic regulator setting 400-mV difference

0B

Manual Mode

0B

0

x

1

0

1

0

1

0

1

0

1

0

1

0

1

0

V_{DD_RF}= 3.4 V, V_{DD_A}= 3.4 V, V_{DD_X}= 3.4 V

V_{DD_RF}= 3.3 V, V_{DD_A}= 3.3 V, V_{DD_X}= 3.3 V

V_{DD_RF}= 3.2 V, V_{DD_A}= 3.2 V, V_{DD_X}= 3.2 V

V_{DD_RF}= 3.1 V, V_{DD_A}= 3.1 V, V_{DD_X}= 3.1 V

V_{DD_RF}= 3.0 V, V_{DD_A}= 3.0 V, V_{DD_X}= 3.0 V

V_{DD_RF}= 2.9 V, V_{DD_A}= 2.9 V, V_{DD_X}= 2.9 V

V_{DD_RF}= 2.8 V, V_{DD_A}= 2.8 V, V_{DD_X}= 2.8 V

V_{DD_RF}= 2.7 V, V_{DD_A}= 2.7 V, V_{DD_X}= 2.7 V

(1) x = Don't care

14

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The regulator configuration function adjusts the regulator outputs by default to 250 mV below V_INlevel, but

not higher than 5 V for V_{DD_RF}, 3.4 V for V_{DD_A}and V_{DD_X}. This ensures the highest possible supply

voltage for the RF output stage while maintaining an adequate PSRR (power supply rejection ratio).

To further improve the PSRR, it is possible to increase the target voltage difference across V_{DD_X}and

V_{DD_A}from its default to 350 mV or even 400 mV (for details see Regulator and I/O Control register (0x0B)

definition in Table 5-1 and Table 5-2.)

5.2.3 Power Modes

The chip has several power states, which are controlled by two input pins (EN and EN2) and several bits

in the chip status control register (0x00) (see Table 5-3).

(1)

Table 5-3. Power Modes

Chip

Regulator

Control

Register

(0x0B)

Typical

Power

Out

Time

(From

Status

Control

Register

(0x00)

SYS_CLK

(13.56

MHz)

Typical

Current

(mA)

Trans-

mitter

SYS_CLK

(60 kHz)

Mode

EN2

EN

Receiver

V_{DD_X}

(dBm)

Mode 4 (Full Power)

at 5 VDC

approx. 20-

25 µs

X

1

21

20

31

30

07

ON

X

ON

105

68

23

17

20

14

Mode 4 (Full Power)

at 3.3 VDC

Mode 3 (Half Power)

at 5 VDC

approx. 20-

25 µs

82

Mode 3 (Half Power)

at 3.3 VDC

53

approx. 20-

25 µs

Mode 2 at 5 VDC

Mode 2 at 3.3 VDC

Mode 1 at 5 VDC

Mode 1 at 3.3 VDC

X

1

03

02

01

00

81

07

00

07

00

07

OFF

ON

X

ON

13

10

5

—

approx. 20-

25 µs

OFF

3

Standby Mode at 5

VDC

3

—

4.8 ms

Standby Mode at 3.3

VDC

X

1

0

1

0

80

X

00

X

OFF

ON

OFF

X

ON

2

Power Down Mode

2 (Sleep)

ON

OFF

0.120

<0.001

1.5 ms

Start

Power Down Mode

1 (Total PD)

X

OFF

(1) X = Don't care

Table 5-3 shows the configuration for the different power modes when using a 5-V or 3-V system supply.

The main reader enable signal is pin EN. When EN is set high, all of the reader regulators are enabled,

the 13.56-MHz oscillator is running and the SYS_CLK (output clock for external micro controller) is also

available.

The input pin EN2 has two functions:

•

A direct connection from EN2 to V_INto ensure the availability of the regulated supply V_{DD_X}and an

auxiliary clock signal (60 kHz, SYS_CLK) for an external MCU. This mode (EN = 0, EN2 = 1) is

intended for systems in which the MCU is also being supplied by the reader supply regulator (V_{DD_X}

)

and the MCU clock is supplied by the SYS_CLK output of the reader. This allows the MCU supply and

clock to be available during sleep mode.

•

EN2 enables the start-up of the reader system from complete power down (EN = 0, EN2 = 0). In this

case the EN input is being controlled by the MCU (or other system device) that is without supply

voltage during complete power down (thus unable to control the EN input). A rising edge applied to the

EN2 input (which has an approximately 1-V threshold level) starts the reader supply system and 13.56-

MHz oscillator (identical to condition EN = 1).

Detailed System Description

15

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When user MCU is controlling EN and EN2, a delay of 5 ms between EN and EN2 must be used. If the

MCU controls only EN, EN2 is recommended to be connected to either V_INor GND, depending on the

application MCU requirements for V_{DD_X}and SYS_CLK.

NOTE

Using EN = 1 and EN2 = 1 in parallel at start up should not be done as it can cause incorrect

operation.

This start-up mode lasts until all of the regulators have settled and the 13.56-MHz oscillator has stabilized.

If the EN input is set high (EN = 1) by the MCU (or other system device), the reader stays active. If the EN

input is not set high (EN = 0) within 100 µs after the SYS_CLK output is switched from auxiliary clock (60

kHz) to high-frequency clock (derived from the crystal oscillator), the reader system returns to complete

Power-Down Mode1. This option can be used to wake-up the reader system from complete Power Down

(PD Mode 1) by using a pushbutton switch or by sending a single pulse.

After the reader EN line is high, the other power modes are selected by control bits within the chip status

control register (0x00). The power mode options and states are listed in Table 5-3.

When EN is set high (or on rising edge of EN2 and then confirmed by EN = 1) the supply regulators are

activated and the 13.56-MHz oscillator started. When the supplies are settled and the oscillator frequency

is stable, the SYS_CLK output is switched from the auxiliary frequency of 60 kHz to the 13.56-MHz

frequency derived from the crystal oscillator. At this point, the reader is ready to communicate and perform

the required tasks. The MCU can then program the chip status control register 0x00 and select the

operation mode by programming the additional registers.

•

Stand-by Mode (bit 7 = 1 of register 0x00), the reader is capable of recovering to full operation in

100 µs.

Mode 1 (active mode with RF output disabled, bit 5 = 0 and bit 1 = 0 of register 0x00) is a low power

mode which allows the reader to recover to full operation within 25 µs.

Mode 2 (active mode with only the RF receiver active, bit 1 = 1 of register 0x00) can be used to

measure the external RF field (as described in RSSI measurements paragraph) if reader-to-reader

anticollision is implemented.

•

Modes 3 and 4 (active modes with the entire RF section active, bit 5 = 1 of register 0x00) are the

normal modes used for normal transmit and receive operations.

5.3 Receiver – Analog Section

5.3.1 Main and Auxiliary Receivers

The TRF7964A has two receiver inputs: RX_IN1 (pin 8) and RX_IN2 (pin 9). Each of the input is

connected to an external capacitive voltage divider to ensure that the modulated signal from the tag is

available on at least one of the two inputs. This architecture eliminates any possible communication holes

that may occur from the tag to the reader.

The two RX inputs (RX_IN1 and RX_IN2) are multiplexed into two receivers - the main receiver and the

auxiliary receiver. Only the main receiver is used for reception, the auxiliary receiver is used for signal

quality monitoring. Receiver input multiplexing is controlled by bit B3 in the Chip Status Control register

(address 0x00).

After startup, RX_IN1 is multiplexed to the main receiver which is composed of an RF envelope detection,

first gain and band-pass filtering stage, second gain and filtering stage with AGC. Only the main receiver

is connected to the digitizing stage which output is connected to the digital processing block. The main

receiver also has an RSSI measuring stage, which measures the strength of the demodulated signal

(subcarrier signal).

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The primary function of the auxiliary receiver is to monitor the RX signal quality by measuring the RSSI of

the demodulated subcarrier signal (internal RSSI). After startup, RX_IN2 is multiplexed to the auxiliary

receiver. The auxiliary receiver has an RF envelope detection stage, first gain and filtering with AGC stage

and finally the auxiliary RSSI block.

The default MUX setting is RX_IN1 connected to the main receiver and RX_IN2 connected to the auxiliary

receiver. To determine the signal quality, the response from the tag is detected by the "main" (pin RX_IN1)

and "auxiliary" (pin RX_IN2) RSSI. Both values measured and stored in the RSSI level register (address

0x0F). The MCU can read the RSSI values from the TRF7964A RSSI register and make the decision if

swapping the input- signals is preferable or not. Setting B3 in Chip Status Control register (address 0x00)

to 1 connects RX_IN1 (pin 8) to the auxiliary received and RX_IN2 (pin 9) to the main receiver. This

mechanism needs to be used to avoid reading holes.

The main and auxiliary receiver input stages are RF envelope detectors. The RF amplitude at RX_IN1 and

RX_IN2 should be approximately 3 VPP for a V_INsupply level greater than 3.3 V. If the V_INlevel is lower,

the RF input peak-to-peak voltage level should not exceed the V_INlevel.

5.3.2 Receiver Gain and Filter Stages

The first gain and filtering stage has a nominal gain of 15 dB with an adjustable band-pass filter. The

band-pass filter has programmable 3d-B corner frequencies between 110 kHz to 450 kHz for the high-

pass filter and 570 kHz to 1500 kHz for the low-pass filter. After the band-pass filter, there is another gain-

and-filtering stage with a nominal gain of 8 dB and with frequency characteristics identical to the first band-

pass stage.

The internal filters are configured automatically depending on the selected ISO communication standard in

the ISO Control register (address 0x01). If required, additional fine tuning can be done by writing directly

to the RX special setting registers (address 0x0A).

The main receiver also has a second receiver gain and digitizer stage which is included in the AGC loop.

The AGC loop is activated by setting the bit B2 = 1 in the Chip Status Control register (0x00). When

activated, the AGC continuously monitors the input signal level. If the signal level is significantly higher

than an internal threshold level, gain reduction is activated.

By default, the AGC is frozen after the first 4 pulses of the subcarrier signal. This prevents the AGC from

interfering with the reception of the remaining data packet. In certain situations, this AGC freeze is not

optimal, so it can be removed by setting B0 = 1 in the RX special setting register (address 0x0A).

Table 5-4. RX Special Setting Register (0x0A)

Bit

Function

Comments

B7

Bandpass from 110 kHz to 570 kHz

Appropriate for any 212-kHz subcarrier systems (for example, FeliCa)

Appropriate for 424-kHz subcarrier systems (for example, used in

ISO15693)

B6

B5

Bandpass from 200 kHz to 900 kHz

Bandpass from 450 kHz to 1.5 MHz

Bandpass from 100 kHz to 1.5 MHz

Appropriate for Manchester-coded 106-kbps 848-kHz subcarrier systems

(for example, used in ISO14443A)

Appropriate for highest bit rate (848 kbps) used in high-bit-rate ISO14443B.

Gain is reduced by 7 dB.

B4

B3

00 = no gain reduction

01 = gain reduction for 5 dB

10 = gain reduction for 10 dB

11 = gain reduction for 15 dB

Sets the RX digital gain reduction (changing the window of the digitizing

comparator)

B2

B1

AGC activation level change. From 5 times the minimum RX digitizing level

to 3 times the minimum digitizing level. The minimum RX digitizing level can

be adjusted by B2 and B3 (gain reduction)

0 = 5 times minimum digitizing level

1 = 3 times minimum digitizing level

AGC action is not limited in time or to the start of receive. AGC action can

be done any time during receive process. The AGC can only increase and,

therefore, clips on the peak RX level during the enable period. AGC level is

reset automatically at the beginning of each receive start frame.

0 = AGC freeze after 16 subcarrier edges

1 = AGC always on during receive

B0

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Table 5-4 shows the various settings for the receiver analog section. It is important to note that setting B4,

B5, B6, and B7 to 0 results to a band-pass characteristic of 240 kHz to 1.4 MHz, which is appropriate for

ISO14443B 106 kbps, ISO14443A/B data-rates of 212 kbps and 424 kbps and FeliCa 424 kbps.

5.4 Receiver – Digital Section

The output of the TRF7964A analog receiver block is a digitized subcarrier signal and is the input to the

digital receiver block. This block includes a Protocol Bit Decoder section and the Framing Logic section.

The protocol bit decoders convert the subcarrier coded signal into a serial bit stream and a data clock.

The decoder logic is designed for maximum error tolerance. This enables the decoder section to

successfully decode even partly corrupted subcarrier signals that otherwise would be lost due to noise or

interference.

In the framing logic section, the serial bit stream data is formatted in bytes. Special signals such as the

start of frame (SOF), end of frame (EOF), start of communication, and end of communication are

automatically removed. The parity bits and CRC bytes are also checked and removed. This "clean" data is

then sent to the 128 byte FIFO register where it can be read by the external microcontroller system.

Providing the data this way, in conjunction with the timing register settings of the TRF7964A means the

firmware developer has to know about much less of the finer details of the ISO protocols to create a very

robust application, especially in low cost platforms where code space is at a premium and high

performance is still required.

The start of the receive operation (successfully received SOF) sets the IRQ-flags in the IRQ and Status

Register (0x0C). The end of the receive operation is signaled to the external system MCU by setting pin

13 (IRQ) to high. When data is received in the FIFO, an interrupt is sent to the MCU to signal that there is

data to be read from the FIFO. The FIFO status register (0x1C) should be used to provide the number of

bytes that should be clocked out during the actual FIFO read.

Any error in the data format, parity, or CRC is detected and notified to the external system by an interrupt-

request pulse. The source condition of the interrupt request pulse is available in the IRQ status register

(0x0C). The main register controlling the digital part of the receiver is the ISO Control register (0x01). By

writing to this register, the user selects the protocol to be used. With each new write in this register, the

default presets are reloaded in all related registers, so no further adjustments in other registers are

needed for proper operation.

NOTE

If register setting changes are needed for fine tuning the system, they must be done after

setting the ISO Control register (0x01).

The framing section also supports the bit-collision detection as specified in ISO14443A. When a bit

collision is detected, an interrupt request is sent and a flag is set in the IRQ and Status Register (0x0C).

The position of the bit collision is written in two registers: Collision Position Register (0x0E) and partly in

Collision Position and Interrupt Mask Register (0x0D) (bits B6 and B7).

The collision position is presented as sequential bit number, where the count starts immediately after the

start bit. This means a collision in the first bit of a UID would give the value 00 0001 0000 in these

registers when their contents are combined after being read. (the count starts with 0 and the first 16 bits

are the command code and the Number of Valid Bits (NVB) byte)

The receive section also contains two timers. The RX wait time timer is controlled by the value in the RX

Wait Time Register (0x08). This timer defines the time interval after the end of the transmit operation in

which the receive decoders are not active (held in reset state). This prevents false detections resulting

from transients following the transmit operation. The value of the RX Wait Time Register (0x08) defines

the time in increments of 9.44 µs. This register is preset at every write to ISO Control Register (0x01)

according to the minimum tag response time defined by each standard.

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The RX no response timer is controlled by the RX No Response Wait Time Register (0x07). This timer

measures the time from the start of slot in the anticollision sequence until the start of tag response. If there

is no tag response in the defined time, an interrupt request is sent and a flag is set in the IRQ Status

Register (0x0C). This enables the external controller to be relieved of the task of detecting empty slots.

The wait time is stored in the register in increments of 37.76 µs. This register is also preset, automatically

for every new protocol selection.

The digitized output of the analog receiver is at the input of the digital portion of the receiver. This input

signal is the subcarrier coded signal, which is a digital representation of modulation signal on the RF

envelope.

The digital part of the receiver consists of two sections which partly overlap. The first section contains the

bit decoders for the various protocols. The bit decoders convert the subcarrier coded signal to a bit stream

and also the data clock. Thus the subcarrier coded signal is transformed to serial data and the data clock

is extracted. The decoder logic is designed for maximum error tolerance. This enables the decoders to

successfully decode even partly corrupted (due to noise or interference) subcarrier signals.

The second section contains the framing logic for the protocols supported by the bit decoder section. In

the framing section, the serial bit stream data is formatted in bytes. In this process, special signals like the

SOF (start of frame), EOF (end of frame), start of communication, end of communication are automatically

removed. The parity bits and CRC bytes are checked and also removed. The end result is "clean or raw"

data which is sent to the 128-byte FIFO register where it can be read out by the external microcontroller

system.

The start of the receive operation (successfully received SOF) sets the flags in the IRQ and Status

register. The end of the receive operation is signaled to the external system (MCU) by sending an interrupt

request (pin 13 IRQ). If the receive data packet is longer than 96 bytes, an interrupt is sent to the MCU

when the received data occupies 75% of the FIFO capacity to signal that the data should be removed

from the FIFO.

Any error in data format, parity or CRC is detected and the external system is made aware of the error by

an interrupt request pulse. The nature of the interrupt request pulse is available in the IRQ and Status

register (address 0x0C). The bit coding description of this register is shown in Section 6.3.3.1.

The main register controlling the digital part of the receiver is the ISO Control register (address 0x01). By

writing to this register, the user selects the protocol to be used. At the same time (with each new write in

this register) the default preset in all related registers is done, so no further adjustments in other registers

are needed for proper operation. Table 5-5 shows the coding of the ISO Control register (0x01).

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Table 5-5. Coding of the ISO Control Register

Bit

Signal Name

Function

Comments

1 = No RX CRC

0 = RX CRC

B7

rx_crc_n

Receiving without CRC

0 = output is subcarrier data

B6

B5

dir_mode

rfid

Direct mode type

RFID mode

1 = output is bit stream and clock from decoder selected by ISO bits

0 = RFID reader mode

1 = Reserved (should be set to 0)

B4

B3

B2

B1

B0

iso_4

iso_3

iso_2

iso_1

iso_0

RFID

See Table 5-6 for B0:B4 settings based on ISO protocol used by application.

Table 5-6. Coding of the ISO Control Register For RFID Mode (B5 = 0)

Iso_4

Iso_3

Iso_2

Iso_1

Iso_0

Protocol

Remarks

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

ISO15693 low bit rate, one subcarrier, 1 out of 4

ISO15693 low bit rate, one subcarrier, 1 out of 256

ISO15693 high bit rate, one subcarrier, 1 out of 4

ISO15693 high bit rate, one subcarrier, 1 out of 256

ISO15693 low bit rate, double subcarrier, 1 out of 4

ISO15693 low bit rate, double subcarrier, 1 out of 256

ISO15693 high bit rate, double subcarrier, 1 out of 4

ISO15693 high bit rate, double subcarrier, 1 out of 256

ISO14443A, bit rate 106 kbps

Default for RFID IC

RX bit rate when TX rate

different than RX rate (see

register 0x03)

0

1

0

1

ISO14443 A high bit rate 212 kbps

0

1

0

1

0

1

0

ISO14443 A high bit rate 424 kbps

ISO14443 A high bit rate 848 kbps

ISO14443B, bit rate 106 kbps

RX bit rate when TX rate

different than RX rate (see

register 0x03)

0

1

0

1

ISO14443 B high bit rate 212 kbps

0

1

0

1

0

1

0

1

0

1

0

1

0

1

ISO14443 B high bit rate 424 kbps

ISO14443 B high bit rate 848 kbps

Reserved

FeliCa 212 kbps

FeliCa 424 kbps

20

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The framing section also supports the bit collision detection as specified in ISO14443A. In the event of a

detected bit collision, an interrupt request is sent and flag set in the IRQ and Status registers. The position

of the bit collision is written in two registers: the Collision Position register (0x0E) and partly in the

Collision Position and Interrupt Mask register (0x0D), in which only the bits B7 and B6 are used for

collision position. The collision position is presented as sequential bit number, where the counting starts

immediately after the start bit. This means, the collision in the first bit of the UID would give value 00 0001

0000 in the collision position registers (the counting starts with 0 and the first 16 bits are the command

code and the NVB byte).

The receive part also contains two timers. The RX wait time timer setting is controlled by the value in the

RX Wait Time register (0x08). This timer defines the time after the end of transmit operation in which the

receive decoders are not active (held in reset state). This prevents any incorrect detections from occurring

as a result of transients following the transmit operation. The value of the RX Wait Time register defines

this time with increments of 9.44 µs. This register is preset at every write to the ISO Control register (0x01)

according to the minimum tag response time defined by each standard.

The RX no response timer setting is controlled by the RX No Response Wait Time register (0x07). This

timer measures the time from the start of slot in the anticollision sequence until the start of tag response. If

there is no tag response in the defined time, an interrupt request is sent and a flag is set in IRQ Status

Control register. This enables the external controller to be relieved of the task of detecting empty slots.

The wait time is stored in the register with increments of 37.76 µs. This register is also preset,

automatically, for every new protocol selection.

5.4.1 Received Signal Strength Indicator (RSSI)

The TRF7964A incorporates in total three independent RSSI building blocks: Internal Main RSSI, Internal

Auxiliary RSSI, and External RSSI. The internal RSSI blocks are measuring the amplitude of the

subcarrier signal; the External RSSI block measures the amplitude of the RF carrier signal at the receiver

input.

5.4.1.1 Internal RSSI – Main and Auxiliary Receivers

Each receiver path has its own RSSI block to measure the envelope of the demodulated RF signal

(subcarrier). Internal Main RSSI and Internal Auxiliary RSSI are identical however connected to different

RF input pins. The Internal RSSI is intended for diagnostic purposes to set the correct RX path conditions.

The Internal RSSI values can be used to adjust the RX gain settings or decide which RX path (Main or

Auxiliary) provides the greater amplitude and hence to decide if the MUX may need to be reprogrammed

to swap the RX input signal. The measuring system latches the peak value, so the RSSI level can be read

after the end of each receive packet. The RSSI register values are reset with every transmission (TX) by

the reader. This guarantees an updated RSSI measurement for each new tag response.

The Internal RSSI has 7 steps (3 bit) with a typical increment of approximately 4 dB. The operating range

is between 600 mV_PPand 4.2 V_PPwith a typical step size of approximately 600 mV. Both Internal Main

and Internal Auxiliary RSSI values are stored in the RSSI Levels and Oscillator Status register (0x0F). The

nominal relationship between the input RF peak level and the RSSI value is shown in Figure 5-2.

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7

6

5

4

3

2

1

0

0.25 0.5 0.75

1

1.25 1.5 1.75

2

2.25 2.5 2.75

3

3.25 3.5 3.75

4

4.25

Input RF Carrier Level in V_PP[V]

Figure 5-2. Digital Internal RSSI (Main and Auxiliary) Value vs RF Input Level in V_PP(V)

This RSSI measurement is done during the communication to the Tag; this means the TX must be on.

Bit1 in the Chip Status Control Register (0x00) defines if Internal RSSI or the External RSSI value is

stored in the RSSI Levels and Oscillator Status Register 0x0F. Direct command 0x18 is used to trigger an

Internal RSSI measurement.

5.4.1.2 External RSSI

The External RSSI is mainly used for test and diagnostic to sense the amplitude of any 13.56-MHz signal

at the receivers RX_IN1 input. The External RSSI measurement is typically done in active mode when the

receiver is on but transmitter output is off. The level of the RF signal received at the antenna is measured

and stored in the RSSI Levels and Oscillator Status register 0x0F. The relationship between the voltage at

the RX_IN1 input and the 3-bit code is shown in Figure 5-3.

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7

6

5

4

3

2

1

0

25

50

75

100

125

150

175

200

225

250

275

300

325

RF Input Voltage Level at RF_IN1 in mV_PP

Figure 5-3. Digital External RSSI Value vs RF Input Level in V_PP(mV)

The relation between the 3-bit code and the external RF field strength (A/m) sensed by the antenna must

be determined by calculation or by experiments for each antenna design. The antenna Q-factor and

connection to the RF input influence the result. Direct command 0x19 is used to trigger an Internal RSSI

measurement.

For clarity, to check the internal or external RSSI value independent of any other operation, the user must:

•

Set transmitter to desired state (on or off) using Bit 5 of Chip Status Control Register (0x00)

Set the receiver using direct command 0x17.

Check internal or external RSSI using direct commands 0x18 or 0x19, respectively. This action places

the RSSI value in the RSSI register

•

Read the RSSI register using direct command 0x0F; values range from 0x40 to 0x7F.

Repeat steps 1-4 as desired, as register is reset after it is read.

5.5 Oscillator Section

The 13.56-MHz or 27.12-MHz crystal (or oscillator) is controlled by the Chip Status Control Register

(0x00) and the EN and EN2 terminals. The oscillator generates the RF frequency for the RF output stage

as well as the clock source for the digital section. The buffered clock signal is available at pin 27

(SYS_CLK) for any other external circuits. B4 and B5 inside the Modulation and SYS_CLK Register

(0x09) can be used to divide the external SYS_CLK signal at pin 27 by 1, 2 or 4.

Typical start-up time from complete power down is in the range of 3.5 ms.

During Power Down Mode 2 (EN = 0, EN2 = 1) the frequency of SYS_CLK is switched to 60 kHz (typical).

The crystal needs to be connected between pin 31 and pin 32. The external shunt capacitors values for C₁

and C₂must be calculated based on the specified load capacitance of the crystal being used. The external

shunt capacitors are calculated as two identical capacitors in series plus the stray capacitance of the

TRF7964A and parasitic PCB capacitance in parallel to the crystal.

The parasitic capacitance (C_S, stray and parasitic PCB capacitance) can be estimated at 4 to 5 pF

(typical).

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As an example, using a crystal with a required load capacitance (C_L) of 18 pF, the calculation is shown in

Equation 1.

C₁= C₂= 2 × (C_L– C_S) = 2 × (18 pF – 4.5 pF) = 27 pF

(1)

A 27-pF capacitor must be placed on pins 30 and 31 to ensure proper crystal oscillator operation.

C_S

TRF7964A

C₁= C₂= 2 × (C_L– C_S) = 2 × (18 pF – 4.5 pF) = 27 pF

Pin 31

Pin 32

A 27-pF capacitor needs to be placed on pins 30 and 31

to ensure proper crystal oscillator operation.

Crystal

C₁

C₂

Figure 5-4. Crystal Block Diagram

Any crystal used with TRF7964A should have minimum characteristics shown in Table 5-7.

Table 5-7. Minimum Crystal Requirements

Parameter

Frequency

Specification

13.56 MHz or 27.12 MHz

Fundamental

Parallel

Mode of Operation

Type of Resonance

Frequency Tolerance

Aging

±20 ppm

< 5 ppm/year

-40°C to 85°C

50 Ω

Operation Temperature Range

Equivalent Series Resistance

As an alternative, an external clock oscillator source can be connected to Pin 31 to provide the system

clock; pin 32 can be left open.

5.6 Transmitter – Analog Section

The 13.56-MHz oscillator generates the RF signal for the PA stage. The power amplifier consists of a

driver with selectable output resistance of nominal 4 Ω or 8 Ω. The transmit power level is set by bit B4 in

the Chip Status Control Register (0x00). The transmit power levels are selectable between 100 mW (half

power) or 200 mW (full power) when configured for 5-V automatic operation. The transmit power levels

are selectable between 33 mW (half power) or 70 mW (full power) when configured for 3-V automatic

operation.

The ASK modulation depth is controlled by bits B0, B1, and B2 in the Modulator and SYS_CLK Control

Register (0x09). The ASK modulation depth range can be adjusted between 7% to 30% or 100% (OOK).

External control of the transmit modulation depth is possible by setting the ISO Control Register (0x01) to

direct mode. While operating the TRF7964A in direct mode, the transmit modulation is made possible by

selecting the modulation type ASK or OOK at pin 12. External control of the modulation type is made

possible only if enabled by setting B6 in the Modulator and SYS_CLK Control Register (0x09) to 1.

In normal operation mode, the length of the modulation pulse is defined by the protocol selected in the

ISO Control Register (0x01). With a high-Q antenna, the modulation pulse is typically prolonged, and the

tag detects a longer pulse than intended. For such cases, the modulation pulse length needs to be

corrected by using the TX Pulse Length Register (0x05).

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If the register contains all zeros, then the pulse length is governed by the protocol selection. If the register

contains a value other than 0x00, the pulse length is equal to the value of the register multiplied by

73.7 ns; therefore, the pulse length can be adjusted between 73.7 ns and 18.8 s in 73.7-ns increments.

5.7 Transmitter – Digital Section

The digital part of the transmitter is a mirror of the receiver. The settings controlled the ISO Control

Register (0x01) are applied to the transmitter just like the receiver. In the TRF7964A default mode the

TRF7964A automatically adds these special signals: start of communication, end of communication, SOF,

EOF, parity bits, and CRC bytes.

The data is then coded to modulation pulse levels and sent to the RF output stage modulation control unit.

Similar to working with the receiver, this means that the external system MCU only has to load the FIFO

with data and all the microcoding is done automatically, again saving the firmware developer code space

and time. Additionally, all of the registers used for transmit parameter control are automatically preset to

optimum values when a new selection is entered into the ISO Control register (0x01).

Note: FIFO must be reset before starting any transmission with Direct Command 0x0F.

There are two ways to start the transmit operation:

•

Load the number of bytes to be sent into registers 0x1D and 0x1E and load the data to be sent into the

FIFO (address 0x1F), followed by sending a transmit command (see Direct Commands section). The

transmission then starts when the transmit command is received.

Send the transmit command and the number of bytes to be transmitted first, and then start to send the

data to the FIFO. The transmission starts when first data byte is written into the FIFO.

NOTE

If the data length is longer than the FIFO, the TRF7964A notifies the external system MCU

when most of the data from the FIFO has been transmitted by sending an interrupt request

with a flag in the IRQ register to indicate a FIFO low or high status. The external system

should respond by loading the next data packet into the FIFO.

At the end of a transmit operation, the external system MCU is notified by interrupt request (IRQ) with a

flag in IRQ Register (0x0C) indicating TX is complete (example value = 0x80).

The TX Length registers also support incomplete byte transmission. The high two nibbles in register 0x1D

and the nibble composed of bits B4 through B7 in register 0x1E store the number of complete bytes to be

transmitted. Bit B0 in register 0x1E is a flag indicating that there are also additional bits to be transmitted

that do not form a complete byte. The number of bits is stored in bits B1 through B3 of the same register

(0x1E).

Some protocols have options, and there are two sublevel configuration registers to select the TX protocol

options.

•

ISO14443B TX Options register (0x02). This register controls the SOF and EOF selection and EGT

selection for the ISO14443B protocol.

•

ISO14443A High Bit Rate Options and Parity register (0x03). This register enables the use of different

bit rates for RX and TX operations in the ISO14443 high bit rate protocol and also selects the parity

method in the ISO14443A high bit rate protocol.

The digital section also has a timer. The timer can be used to start the transmit operation at a specified

time in accordance with a selected event.

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5.8 Transmitter – External Power Amplifier and Subcarrier Detector

The TRF7964A can be used in conjunction with an external TX power amplifier or external subcarrier

detector for the receiver path. In this case, certain registers must be programmed as shown here:

•

Bit B6 of the Regulator and I/O Control Register (0x0B) must be set to 1. This setting has two

functions: first, to provide a modulated signal for the transmitter if needed, and second, to configure the

TRF7964A receiver inputs for an external demodulated subcarrier input.

•

Bit B3 of the Modulation and SYS_CLK Control Register (0x09) must be set to 1 (see Section 6.3.2.8).

This function configures the ASK/OOK pin for either a digital or analog output (B3 = 0 enables a digital

output, B3 = 1 enables an analog output). The design of an external power amplifier requires detailed

RF knowledge. There are also readily designed and certified high-power HF reader modules on the

market.

5.9 TRF7964A IC Communication Interface

5.9.1 General Introduction

The communication interface to the reader can be configured in two ways: with a eight line parallel

interface (D0:D7) plus DATA_CLK, or with a three or four wire Serial Peripheral Interface (SPI). The SPI

interface uses traditional Master Out/Slave In (MOSI), Master In/Slave Out (MISO), IRQ, and DATA_CLK

lines. The SPI can be operated with or without using the Slave Select line.

These communication modes are mutually exclusive; that is, only one mode can be used at a time in the

application.

When the SPI interface is selected, the unused I/O_2, I/O_1, and I/O_0 pins must be hard-wired as shown

in Table 5-8. At power up, the TRF7964A samples the status of these three pins and then enters one of

the possible SPI modes.

The TRF7964A always behaves as the slave device, and the microcontroller (MCU) behaves as the

master device. The MCU initiates all communications with the TRF7964A, and the TRF7964A makes use

of the Interrupt Request (IRQ) pin in both parallel and SPI modes to prompt the MCU for servicing

attention.

Table 5-8. Pin Assignment in Parallel and Serial Interface Connection or Direct Mode

DATA_ CLK

I/O_7

Parallel

DATA_CLK

A/D[7]

Parallel (Direct Mode)

DATA_CLK

SPI With SS

DATA_CLK from master

MOSI⁽¹⁾= data in (reader in)

SPI Without SS

DATA_CLK from master

MOSI⁽¹⁾= data in (reader in)

(not used)

Direct mode, data out (subcarrier

or bit stream)

I/O_6

A/D[6]

A/D[5]

MISO⁽²⁾= data out (MCU out)

Direct mode, strobe – bit clock

out

I/O_5⁽³⁾

See

(3)

I/O_4

I/O_3

I/O_2

I/O_1

I/O_0

IRQ

A/D[4]

A/D[3]

(not used)

IRQ interrupt

SS – slave select⁽⁴⁾

(not used)

At VDD

(not used)

At VDD

A/D[2]

A/D[1]

At VDD

At V_SS

A/D[0]

At V_SS

IRQ interrupt

(1) MOSI = Master Out, Slave In

(2) MISO = Master In, Slave Out

(3) I/O_5 pin is used only for information when data is put out of the chip (for example, reading 1 byte from the chip). It is necessary first to

write in the address of the register (8 clocks) and then to generate another 8 clocks for reading out the data. The I/O_5 pin goes high

during the second 8 clocks. But for normal SPI operations, I/O_5 pin is not used.

(4) Slave_Select pin is active low

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Communication is initialized by

a

start condition, which is expected to be followed by an

Address/Command word (Adr/Cmd). The Adr/Cmd word is 8 bits long, and its format is shown in Table 5-

9.

Table 5-9. Address/Command Word Bit Distribution

Bit

Description

Bit Function

Address

Command

0 = address

1 = command

B7

Command control bit

0

1

0 = write

1 = read

B6

Read/Write

R/W

0

B5

B4

B3

B2

B1

B0

Continuous address mode

Address/Command bit 4

Address/Command bit 3

Address/Command bit 2

Address/Command bit 1

Address/Command bit 0

1 = Continuous mode

R/W

Adr 4

Adr 3

Adr 2

Adr 1

Adr 0

0

Cmd 4

Cmd 3

Cmd 2

Cmd 1

Cmd 0

The MSB (bit 7) determines if the word is to be used as a command or as an address. The last two

columns of Table 5-9 show the function of the separate bits if either address or command is written. Data

is expected once the address word is sent. In continuous-address mode (Cont. mode = 1), the first data

that follows the address is written (or read) to (from) the given address. For each additional data, the

address is incremented by one. Continuous mode can be used to write to a block of control registers in a

single stream without changing the address; for example, setup of the predefined standard control

registers from the MCU non-volatile memory to the reader. In non-continuous address mode (simple

addressed mode), only one data word is expected after the address.

Address Mode is used to write or read the configuration registers or the FIFO. When writing more than 12

bytes to the FIFO, the Continuous Address Mode should be set to 1.

The Command Mode is used to enter a command resulting in reader action (for example, initialize

transmission, enable reader, and turn reader on or off).

Examples of expected communications between an MCU and the TRF7964A are shown in the following

sections.

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5.9.1.1 Continuous Address Mode

Table 5-10. Continuous Address Mode

Start

Adr x

Data(x)

Data(x+1)

Data(x+2)

Data(x+3)

Data(x+4)

...

Data(x+n)

StopCont

Figure 5-5. Continuous Address Register Write Example Starting with Register 0x00 Using SPI With SS

Figure 5-6. Continuous Address Register Read Example Starting with Register 0x00 Using SPI With SS

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5.9.1.2 Noncontinuous Address Mode (Single Address Mode)

Table 5-11. Noncontinuous Address Mode (Single Address Mode)

Start

Adr x

Data(x)

Adr y

Data(y)

...

Adr z

Data(z)

StopSgl

Figure 5-7. Single Address Register Write Example of Register 0x00 Using SPI With SS

Figure 5-8. Single Address Register Read Example of Register 0x00 Using SPI With SS

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5.9.1.3 Direct Command Mode

Table 5-12. Direct Command Mode

Start

Cmd x

(Optional data or command)

Stop

Figure 5-9. Direct Command Example of Sending 0x0F (Reset) Using SPI With SS

The other Direct Command Codes from MCU to TRF7964A IC are described in Section 5.11.

5.9.1.4 FIFO Operation

The FIFO is a 128-byte register at address 0x1F with byte storage locations 0 to 127. FIFO data is loaded

in a cyclical manner and can be cleared by a reset command (0x0F) (see Figure 5-9 showing this Direct

Command).

Associated with the FIFO are two counters and three FIFO status flags. The first counter is a 7-bit FIFO

byte counter (bits B0 to B6 in register 0x1C) that tracks the number of bytes loaded into the FIFO. If the

number of bytes in the FIFO is n, the register value is n (number of bytes in FIFO register). For example, if

8 bytes are in the FIFO, the FIFO counter (Register 0x1C) has the hexadecimal value of 0x08 (binary

value of 00001000).

A second counter (12 bits wide) indicates the number of bytes being transmitted (registers 0x1D and

0x1E) in a data frame. An extension to the transmission-byte counter is a 4-bit broken-byte counter also

provided in register 0x1E (bits B0 to B3). Together these counters make up the TX length value that

determines when the reader generates the EOF byte.

FIFO status flags are as follows:

•

FIFO overflow (bit B7 of register 0x1C) – indicates that the FIFO has more than 128 bytes loaded

During transmission, the FIFO is checked for an almost-empty condition, and during reception for an

almost-full condition. The maximum number of bytes that can be loaded into the FIFO in a single

sequence is 128 bytes.

NOTE

The number of bytes in a frame, transmitted or received, can be greater than 128 bytes.

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During transmission, the MCU loads the TRF7964A IC's FIFO (or during reception the MCU removes data

from the FIFO), and the FIFO counter counts the number of bytes being loaded into the FIFO. Meanwhile,

the byte counter keeps track of the number of bytes being transmitted. An interrupt request is generated if

the number of bytes in the FIFO is less than 32 or greater than 96, so that MCU can send new data or

remove the data as necessary. The MCU also checks the number of data bytes to be sent, so as to not

surpass the value defined in TX length bytes. The MCU also signals the transmit logic when the last byte

of data is sent or was removed from the FIFO during reception. Transmission starts automatically after the

first byte is written into FIFO.

Figure 5-10. Example of Checking the FIFO Status Register Using SPI With SS

5.9.2 Parallel Interface Mode

In parallel mode, the start condition is generated on the rising edge of the I/O_7 pin while the CLK is high.

This is used to reset the interface logic. Figure 5-11 shows the sequence of the data, with an 8-bit address

word first, followed by data.

Communication is ended by:

•

The StopSmpl condition, where a falling edge on the I/O_7 pin is expected while CLK is high.

The StopCont condition, where the I/O_7 pin must have a successive rising and falling edge while CLK

is low to reset the parallel interface and be ready for the new communication sequence.

•

The StopSmpl condition is also used to terminate the direct mode.

Figure 5-11. Parallel Interface Communication With Simple Stop Condition (StopSmpl)

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Figure 5-12. Parallel Interface Communication with Continuous Stop Condition (StopCont)

Figure 5-13. Example of Parallel Interface Communication with Continuous Stop Condition

5.9.3 Reception of Air Interface Data

At the start of a receive operation (when SOF is successfully detected), B6 is set in the IRQ Status

register. An interrupt request is sent to the MCU at the end of the receive operation if the receive data

string was shorter than or equal to 8 bytes. The MCU receives the interrupt request, then checks to

determine the reason for the interrupt by reading the IRQ Status register (0x0C), after which the MCU

reads the data from the FIFO.

If the received packet is longer than 96 bytes, the interrupt is sent before the end of the receive operation

when the 96th byte is loaded into the FIFO (75% full). The MCU should again read the content of the IRQ

Status register to determine the cause of the interrupt request. If the FIFO is 75% full (as marked with flag

B5 in IRQ Status register and by reading the FIFO Status register), the MCU should respond by reading

the data from FIFO to make room for new incoming receive data. When the receive operation is finished,

the interrupt is sent and the MCU must check how many words are still present in the FIFO before it

finishes reading.

If the reader detects a receive error, the corresponding error flag is set (framing error, CRC error) in the

IRQ Status register, indicating to the MCU that reception was not completed correctly.

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5.9.4 Data Transmission to MCU

Before beginning data transmission, the FIFO should always be cleared with a reset command (0x0F).

Data transmission is initiated with a selected command (see Section 5.11). The MCU then commands the

reader to do a continuous write command (0x3D) starting from register 0x1D. Data written into register

0x1D is the TX Length Byte1 (upper and middle nibbles), while the following byte in register 0x1E is the

TX Length Byte2 (lower nibble and broken byte length) (see Table 6-29 and Table 6-30) . Note that the TX

byte length determines when the reader sends the end of frame (EOF) byte. After the TX length bytes are

written, FIFO data is loaded in register 0x1F with byte storage locations 0 to 127. Data transmission

begins automatically after the first byte is written into the FIFO. The loading of TX length bytes and the

FIFO can be done with a continuous-write command, as the addresses are sequential.

At the start of transmission, the flag B7 (IRQ_TX) is set in the IRQ Status register, and at the end of the

transmit operation, an interrupt is sent to inform the MCU that the task is complete.

5.9.5 Serial Interface Communication (SPI)

When an SPI interface is used, I/O pins I/O_2, I/O_1, and I/O_0 must be hard wired according to Table 5-

8. On power up, the TRF7964A looks for the status of these pins and then enters into one of two possible

SPI modes:

•

SPI with Slave Select

SPI without Slave Select

The choice of one of these modes over another should be predicated by the available GPIOs and the

desired control of the system.

The serial communications work in the same manner as the parallel communications with respect to the

FIFO, except for the following condition. On receiving an IRQ from the reader, the MCU reads the

TRF7964A IRQ Status register to determine how to service the reader. After this, the MCU must to do a

dummy read to clear the reader's IRQ status register. The dummy read is required in SPI mode because

the reader's IRQ status register needs an additional clock cycle to clear the register. This is not required in

parallel mode because the additional clock cycle is included in the Stop condition. When first establishing

communications with the TRF7964A, the SOFT_INIT (0x03) command should be sent first from the MCU

(see Table 5-13).

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The procedure for a dummy read is as follows:

1. Start the dummy read:

(a) When using slave select (SS): set SS bit low.

(b) When not using SS: start condition is when Data Clock is high (see Table 5-8).

2. Send address word to IRQ status register (0x0C) with read and continuous address mode bits set to 1

(see Table 5-8).

3. Read 1 byte (8 bits) from IRQ status register (0x0C).

4. Dummy-read 1 byte from register 0x0D (collision position and interrupt mask).

5. Stop the dummy read:

(a) When using slave select (SS): set SS bit high.

(b) When not using SS: stop condition when Data Clock is high.

Write Address

Byte (0x6C)

Read Data in

IRQ Status Register

Dummy Read

DATA

CLK

0

1

0

1

0

MOSI

MISO

No Data Transitions (All High/Low) No Data Transitions (All High/Low)

Ignore

Don't Care

B7 B6 B5 B4 B3 B2 B1 B0

SLAVE

SELECT

Figure 5-14. Procedure for Dummy Read

Figure 5-15. Example of Dummy Read Using SPI With SS

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5.9.5.1 Serial Interface Mode Without Slave Select (SS)

The serial interface without the slave select pin must use delimiters for the start and stop conditions.

Between these delimiters, the address, data, and command words can be transferred. All words must be 8

bits long with MSB transmitted first.

Start

Condition

Stop

Condition

Data_Clock

50 ns

b7

Data In

b6

b5

b4

b3

b2

b1

b0

Data Out

Figure 5-16. SPI Without Slave Select Timing Diagram

In this mode, a rising edge on data-in (I/O_7, pin 24) while SCLK is high resets the serial interface and

prepares it to receive data. Data-in can change only when SCLK is low and is taken by the reader on the

SCLK rising edge. Communication is terminated by the stop condition when the data-in falling edge occurs

during a high SCLK period.

5.9.5.2 Serial Interface Mode With Slave Select (SS)

The serial interface is in reset while the Slave Select signal is high. Serial data in (MOSI) changes on the

falling edge, and is validated in the reader on the rising edge, as shown in Figure 5-17. Communication is

terminated when the Slave Select signal goes high.

All words must be 8 bits long with the MSB transmitted first.

WRITE MODE

CKPH = 0, CKPL=0

Data Transition is on

READ MODE

CKPH = 0, CKPL=0

Data Transition is on

t_STE,LA

G

t_STE,LA

G

t_STE,LEAD

Data Clock rising edge

MOSI Valid on Data Clock Falling Edge

Data Clock rising edge

MISO Valid on Data Clock Falling Edge

1/f_UCxCLK

DATA

CLK

t_HD,SI

t_SU,SO

t_LO/HI

t_SU,SI

NO DATA TRANSITIONS

(ALL HIGH/LOW)

MOSI

MISO

b7

b6...b1

b0

t_HD,SO

t_VALID,SO

t_STE,DIS

DON’T CARE

b7

b6...

...b1

b0

Figure 5-17. SPI With Slave Select Timing Diagram

The read command is sent out on the MOSI pin, MSB first, in the first eight clock cycles. MOSI data

changes on the falling edge, and is validated in the reader on the rising edge, as shown in Figure 5-17.

During the write cycle, the serial data out (MISO) is not valid. After the last read command bit (B0) is

validated at the eighth rising edge of SCLK, after half a clock cycle, valid data can be read on the MISO

pin at the falling edge of SCLK. It takes eight clock edges to read out the full byte (MSB first). See

Section 3.4 for electrical specifications related to Figure 5-17.

The continuous read operation is shown in Figure 5-18.

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Write

Address Byte

Read

Data Byte 1

Read

Data Byte n

DATA_CLK

MOSI

No Data Transitions

(All High/Low)

No Data Transitions

(All High/Low)

B7 B6 B5 B4 B3 B2 B1 B0

MISO

Don't Care

B7 B6 B5 B4 B3 B2 B1 B0

SLAVE

SELECT

Figure 5-18. Continuous Read Operation Using SPI With Slave Select

Figure 5-19. Continuous Read of Registers 0x00 Through 0x05 Using SPI With SS

Performing Single Slot Inventory Command as an example is shown in Figure 5-20. Reader registers (in

this example) are configured for 5 VDC in and default operation. For full sequences for other settings and

protocols can be found here: http://www.ti.com/lit/zip/sloc240

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Figure 5-20. Inventory Command Sent From MCU to TRF7964A

The TRF7964A takes these bytes from the MCU and then send out Request Flags, Inventory Command

,and Mask over the air to the ISO15693 transponder. After these three bytes have been transmitted, an

interrupt occurs to indicate back to the reader that the transmission has been completed. In the example in

Figure 5-21, this IRQ occurs approximately 1.6 ms after the SS line goes high after the Inventory

command is sent out.

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Figure 5-21. IRQ After Inventory Command

The IRQ status register read (0x6C) yields 0x80, which indicates that TX is indeed complete. This is

followed by dummy clock and reset of FIFO with dummy clock. Then, if a tag is in the field and no error is

detected by the reader, a second interrupt is expected and occurs (in this example) approximately 4 ms

after first IRQ is read and cleared.

In the continuation of the example (see Figure 5-22), the IRQ Status Register is read using method

previously recommended, followed by a single read of the FIFO status register, which indicates that there

are at least 9 bytes to be read out.

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Figure 5-22. Read IRQ Status Register After Inventory Command

This is then followed by a continuous read of the FIFO. The first byte is (and should be) 0x00 for no error.

The next byte is the DSFID (usually shipped by manufacturer as 0x00), then the UID, shown here up to

the next most significant byte, the MFG code (shown as 0x07 (TI silicon)).

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Figure 5-23. Continuous Read of FIFO After Inventory Command

This is followed by another IRQ approximately 160 µs later, as there is still one byte in FIFO, the MSB of

the UID, which must be retrieved. IRQ register read shows RX is complete and FIFO register status shows

one byte available, as expected and it is the E0, indicating ISO15693 transponder.

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Figure 5-24. Second IRQ After Inventory Command

At this point it is good form to reset the FIFO and then read out the RSSI value of the tag. In this case the

transponder is very close to the antenna, so value of 0x7E is recovered.

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Figure 5-25. Reset FIFO and Read RSSI

5.9.6 Direct Mode

Direct mode allows the user to configure the reader in one of two ways. Direct Mode 0 (bit 6 = 0, as

defined in ISO Control register) allows the user to use only the front-end functions of the reader,

bypassing the protocol implementation in the reader. For transmit functions, the user has direct access to

the transmit modulator through the MOD pin (pin 14). On the receive side, the user has direct access to

the subcarrier signal (digitized RF envelope signal) on I/O_6 (pin 23).

Direct Mode 1 (bit 6 = 1, as defined in ISO Control register) uses the subcarrier signal decoder of the

selected protocol (as defined in ISO Control register). This means that the receive output is not the

subcarrier signal but the decoded serial bit stream and bit clock signals. The serial data is available on

I/O_6 (pin 23) and the bit clock is available on I/O_5 (pin 22). The transmit side is identical; the user has

direct control over the RF modulation through the MOD input. This mode is provided so that the user can

implement a protocol that has the same bit coding as one of the protocols implemented in the reader, but

needs a different framing format.

To select direct mode, the user must first choose which direct mode to enter by writing B6 in the ISO

Control register. This bit determines if the receive output is the direct subcarrier signal (B6 = 0) or the

serial data of the selected decoder. If B6 = 1, then the user must also define which protocol should be

used for bit decoding by writing the appropriate setting in the ISO Control register.

The reader actually enters the direct mode when B6 (direct) is set to 1 in the chip status control register.

Direct mode starts immediately. The write command should not be terminated with a stop condition (see

communication protocol), because the stop condition terminates the direct mode and clears B6. This is

necessary as the direct mode uses one or two I/O pins (I/O_6, I/O_5). Normal parallel communication is

not possible in direct mode. Sending a stop condition terminates direct mode.

Figure 5-26 shows the different configurations available in direct mode.

•

In mode 0, the reader is used as an AFE only, and protocol handling is bypassed.

In mode 1, framing is not done, but SOF and EOF are present. This allows for a user-selectable

framing level based on an existing ISO standard.

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•

In mode 2, data is ISO-standard formatted. SOF, EOF, and error checking are removed, so the

microprocessor receives only bytes of raw data through a 128-byte FIFO.

Analog Front End (AFE)

Direct Mode 0:

Raw RF Sub-Carrier

Data Stream

ISO Encoders/Decoders

14443A

14443B

15693

FeliCa

Direct Mode 1:

Raw Digital ISO Coded

Data Without

Protocol Frame

Packetization/Framing

Microcontroller

ISO Mode:

Full ISO Framing

and Error Checking

(Typical Mode)

Figure 5-26. User-Configurable Modes

The steps to enter Direct Mode are listed below, using SPI with SS communication method only as one

example, as Direct Modes are also possible with parallel and SPI without SS. The must enter Direct Mode

0 to accommodate non-ISO standard compliant card type communications. Direct Mode can be entered at

any time, so in the event a card type started with ISO standard communications, then deviated from the

standard after being identified and selected, the ability to go into Direct Mode 0 becomes very useful.

Step 1: Configure Pins I/O_0 to I/O_2 for SPI with SS

Step 2: Set Pin 12 of the TRF7964A (ASK/OOK pin) to 0 for ASK or 1 for OOK

Step 3: Program the TRF7964A registers

The following registers need to be explicitly set before going into the Direct Mode.

1. ISO Control register (0x01) to the appropriate standard

–

0x02 for ISO 15693 High Data Rate (26.48 kbps)

0x08 for ISO14443A (106 kbps)

0x1A for FeliCa 212 kbps

0x1B for FeliCa 424 kbps

2. Modulator and SYS_CLK Register (0x09) to the appropriate clock speed and modulation

–

0x21 for 6.78 MHz Clock and OOK (100%) modulation

0x20 for 6.78 MHz Clock and ASK 10% modulation

0x22 for 6.78 MHz Clock and ASK 7% modulation

0x23 for 6.78 MHz Clock and ASK 8.5% modulation

0x24 for 6.78 MHz Clock and ASK 13% modulation

0x25 for 6.78 MHz Clock and ASK 16% modulation

(See register 0x09 definition for all other possible values)

Example register setting for ISO14443A at 106 kbps:

•

ISO Control register (0x01) to 0x08

RX No Response Wait Time register (0x07) to 0x0E

RX Wait Time register (0x08) to 0x07

Modulator control register (0x09) to 0x21 (or any custom modulation)

RX Special Settings register (0x0A) to 0x20

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Step 4: Entering Direct Mode 0

The following registers need to be programmed to enter Direct Mode 0

1. Set bit B6 of the Modulator and SYS_CLK Control register (0x09) to 1.

2. Set bit B6 of the ISO Control (Register 01) to 0 for Direct Mode 0 (default its 0)

3. Set bit B6 of the Chip Status Control register (0x00) to 1 to enter Direct Mode

4. Send extra eight clock cycles (see Figure 5-27, this step is TRF7964A specific)

NOTE

–

It is important that the last write is not terminated with a stop condition. For SPI, this

means that Slave Select (I/O_4) stays low.

Sending a Stop condition terminates the Direct Mode and clears bit B6 in the Chip Status

Control register (0x00).

NOTE

Access to Registers, FIFO, and IRQ is not available during Direct Mode 0.

The reader enters the Direct Mode 0 when bit 6 of the Chip Status Control register (0x00) is set to a 1 and

stays in Direct Mode 0 until a stop condition is sent from the microcontroller.

NOTE

The write command should not be terminated with a stop condition (for example, in SPI

mode this is done by bringing the Slave Select line high after the register write), because the

stop condition terminates the direct mode and clears bit 6 of the Chip Status Control Register

(0x00), making it a 0.

Figure 5-27. Entering Direct Mode 0

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Step 5: Transmit Data Using Direct Mode

The application now has direct control over the RF modulation through the MOD input (see Figure 5-28).

TRF7964A

Microcontroller

Drive the MOD pin

according to the data coding

specified by the standard

MOD

(Pin 14)

Decode the subcarrier

information according

to the standard

I/O_6

(Pin 23)

Figure 5-28. Direct Control Signals

The microcontroller is responsible for generating data according to the coding specified by the particular

standard. The microcontroller must generate SOF, EOF, Data, and CRC. In direct mode, the FIFO is not

used and no IRQs are generated. See the applicable ISO standard to understand bit and frame

definitions. As an example of what the developer sees when using DM0 in an actual application, Figure 5-

29 is presented to clearly show the relationship between the MOD pin being controlled by the MCU and

the resulting modulated 13.56-MHz carrier signal.

Figure 5-29. TX Sequence Out in DM0

Step 6: Receive Data Using Direct Mode

After the TX operation is complete, the tag responds to the request and the subcarrier data is available on

pin I/O_6. The microcontroller needs to decode the subcarrier signal according to the standard. This

includes decoding the SOF, data bits, CRC, and EOF. The CRC then needs to be checked to verify data

integrity. The receive data bytes must be buffered locally.

As an example of the receive data bits and framing level according to the ISO14443A standard is shown

in Figure 5-30 (taken from ISO14443 specification and TRF7964A air interface).

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?

128/fc = 9.435 µs = t_b(106-kbps data rate)

64/fc = 4.719 µs = t_xtime

32/fc = 2.359 µs = t₁time

t_b= 9.44 µs

t_x= 4.72 µs

t₁= 2.48 µs

Sequence Y = Carrier for 9.44 µs

Sequence Z = Pause for 2 to 3 µs,

Carrier for Remainder of 9.44 µs

Figure 5-30. Receive Data Bits and Framing Level

Figure 5-31 is presented to clearly show an example of what the developer should expect on the I/O_6

line during the RX process while in Direct Mode 0.

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Figure 5-31. RX Sequence on I/O_6 in DM0 (Analog Capture)

Step 7: Terminating Direct Mode 0

After the EOF is received, data transmission is over, and Direct Mode 0 can be terminated by sending a

Stop Condition (in the case of SPI, make the Slave Select go high). The TRF7964A is returned to default

state.

5.10 Special Direct Mode for Improved MIFARE Compatibility

See the application report TRF7964A Firmware Design Hints (SLOA159).

5.11 Direct Commands from MCU to Reader

5.11.1 Command Codes

Table 5-13. Address/Command Word Bit Distribution

Command Code

0x00

Command

Comments

Idle

0x03

Software Initialization

Reset

Same as Power on Reset

0x0F

0x10

Transmission without CRC

Transmission with CRC

0x11

0x12

Delayed Transmission without CRC

Delayed Transmission with CRC

End of Frame/Transmit Next Time Slot

Block Receiver

0x13

0x14

ISO15693

0x16

0x17

Enable Receiver

0x18

Test external RF (RSSI at RX input with TX on)

Test internal RF (RSSI at RX input with TX off)

Receiver Gain Adjust

0x19

0x1A

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The command code values from Table 5-13 are substituted in Table 5-14, Bits 0 through 4. Also, the

most-significant bit (MSB) in Table 5-14 must be set to 1. ( Table 5-14 is same as Table 5-9, shown

here again for user clarity).

Table 5-14. Address/Command Word Bit Distribution

Bit

Description

Bit Function

Address

Command

0 = address

1 = command

B7

Command control bit

0

1

0 = write

1 = read

B6

Read/Write

R/W

0

B5

B4

B3

B2

B1

B0

Continuous address mode

Address/Command bit 4

Address/Command bit 3

Address/Command bit 2

Address/Command bit 1

Address/Command bit 0

1 = Continuous mode

R/W

Adr 4

Adr 3

Adr 2

Adr 1

Adr 0

0

Cmd 4

Cmd 3

Cmd 2

Cmd 1

Cmd 0

The MSB determines if the word is to be used as a command or address. The last two columns of

Table 5-14 show the function of each bit, depending on whether address or command is written.

Command mode is used to enter a command resulting in reader action (initialize transmission, enable

reader, and turn reader on or off).

5.11.1.1 Software Initialization (0x03)

This command starts a Power on Reset.

5.11.1.2 Reset (0x0F)

The reset command clears the FIFO contents and FIFO status register (0x1C). It also clears the register

storing the collision error location (0x0E).

5.11.1.3 Transmission With CRC (0x11)

The transmission command must be sent first, followed by transmission length bytes, and FIFO data. The

reader starts transmitting after the first byte is loaded into the FIFO. The CRC byte is included in the

transmitted sequence.

5.11.1.4 Transmission Without CRC (0x10)

Same as Section 5.11.1.3 with CRC excluded.

5.11.1.5 Delayed Transmission With CRC (0x13)

The transmission command must be sent first, followed by the transmission length bytes, and FIFO data.

The reader transmission is triggered by the TX timer.

5.11.1.6 Delayed Transmission Without CRC (0x12)

Same as Section 5.11.1.5 with CRC excluded.

5.11.1.7 Transmit Next Time Slot (0x14)

When this command is received, the reader transmits the next slot command. The next slot sign is defined

by the protocol selection.

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5.11.1.8 Block Receiver (0x16)

The block receiver command puts the digital part of receiver (bit decoder and framer) in reset mode. This

is useful in an extremely noisy environment, where the noise level could otherwise cause a constant

switching of the subcarrier input of the digital part of the receiver. The receiver (if not in reset) would try to

catch a SOF signal, and if the noise pattern matched the SOF pattern, an interrupt would be generated,

falsely signaling the start of an RX operation. A constant flow of interrupt requests can be a problem for

the external system (MCU), so the external system can stop this by putting the receive decoders in reset

mode. The reset mode can be terminated in two ways. The external system can send the enable receiver

command. The reset mode is also automatically terminated at the end of a TX operation. The receiver can

stay in reset after end of TX if the RX wait time register (0x08) is set. In this case, the receiver is enabled

at the end of the wait time following the transmit operation.

5.11.1.9 Enable Receiver (0x17)

This command clears the reset mode in the digital part of the receiver if the reset mode was entered by

the block receiver command.

5.11.1.10 Test Internal RF (RSSI at RX Input With TX ON) (0x18)

The level of the RF carrier at RF_IN1 and RF_IN2 inputs is measured. Operating range between 300 mV_P

and 2.1 V_P(step size is 300 mV). The two values are displayed in the RSSI levels register (0x0F). The

command is intended for diagnostic purposes to set correct RF_IN levels. Optimum RFIN input level is

approximately 1.6 V_Por code 5 to 6. The nominal relationship between the RF peak level and RSSI code

is shown in Table 5-15 and in Section 5.4.1.1.

NOTE

If the command is executed immediately after power-up and before any communication with

a tag is performed, the command must be preceded by Enable RX command. The Check RF

commands require full operation, so the receiver must be activated by Enable RX or by a

normal Tag communication for the Check RF command to work properly.

Table 5-15. Test Internal RF Peak Level to RSSI Codes

RF_IN1 [mV_PP

Decimal Code

Binary Code

]

300

1

600

2

900

3

1200

4

1500

5

1800

6

2100

7

001

010

011

001

101

011

111

5.11.1.11 Test External RF (RSSI at RX Input with TX OFF) (0x19)

This command can be used in active mode when the RF receiver is switched on but RF output is switched

off. This means bit B1 = 1 in Chip Status Control Register. The level of RF signal received on the antenna

is measured and displayed in the RSSI Levels register (0x0F). The relation between the 3 bit code and the

external RF field strength [A/m] must be determinate by calculation or by experiments for each antenna

type as the antenna Q and connection to the RF input influence the result. The nominal relation between

the RF peak to peak voltage in the RF_IN1 input and RSSI code is shown in Table 5-16 and in

Section 5.4.1.2.

NOTE

If the command is executed immediately after power-up and before any communication with

a tag is performed, the command must be preceded by an Enable RX command. The Check

RF commands require full operation, so the receiver must be activated by Enable RX or by a

normal Tag communication for the Check RF command to work properly.

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Table 5-16. Test External RF Peak Level to RSSI Codes

RF_IN1 [mV_PP

Decimal Code

Binary Code

]

40

1

60

2

80

3

100

4

140

5

180

6

300

7

001

010

011

001

101

011

111

5.11.1.12 Receiver Gain Adjust (0x1A)

This command should be executed when the MCU determines that no TAG response is coming and when

the RF and receivers are switched ON. When this command is received, the reader observes the digitized

receiver output. If more than two edges are observed in 100 ms, the window comparator voltage is

increased. The procedure is repeated until the number of edges (changes of logical state) of the digitized

reception signal is less than 2 (in 100 ms). The command can reduce the input sensitivity in 5-dB

increments up to 15 dB. This command ensures better operation in a noisy environment. The gain setting

is reset to maximum gain at EN = 0 and POR = 1.

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6 Register Description

6.1 Register Preset

After power-up and the EN pin low-to-high transition, the reader is in the default mode. The default

configuration is ISO15693, single subcarrier, high data rate, 1-out-of-4 operation. The low-level option

registers (0x02 to 0x0B) are automatically set to adapt the circuitry optimally to the appropriate protocol

parameters. When entering another protocol (by writing to the ISO Control register 0x01), the low-level

option registers (0x02 to 0x0B) are automatically configured to the new protocol parameters. After

selecting the protocol, it is possible to change some low-level register contents if needed. However,

changing to another protocol and then back, reloads the default settings, and so then the custom settings

must be reloaded.

The Clo0 and Clo1 register (0x09) bits, which define the microcontroller frequency available on the

SYS_CLK pin, are the only two bits in the configuration registers that are not cleared during protocol

selection.

6.2 Register Overview

Table 6-1. Register Definitions

Address

Register

Read/Write

Main Control Registers

0x00

Chip Status Control

ISO Control

R/W

0x01

Protocol Sub-Setting Registers

0x02

0x03

ISO14443B TX options

ISO14443A high bit rate options

TX timer setting, H-byte

R/W

0x04

0x05

TX timer setting, L-byte

0x06

TX pulse-length control

0x07

RX no response wait

0x08

RX wait time

0x09

Modulator and SYS_CLK control

RX Special Setting

0x0A

0x0B

Regulator and I/O control

Special Function Register, Preset 0x00

Adjustable FIFO IRQ Levels Register

0x10

0x11

0x14

Status Registers

0x0C

IRQ status

R

R/W

R

0x0D

0x0E

Collision position and interrupt mask register

Collision position

Test Registers

0x1A

Test Register. Preset 0x00

R/W

0x1B

FIFO Registers

0x1C

FIFO status

TX length byte1

TX length byte2

FIFO I/O register

R

0x1D

R/W

0x1E

0x1F

Register Description

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6.3 Detailed Register Description

6.3.1 Main Configuration Registers

6.3.1.1 Chip Status Control Register (0x00)

Table 6-2. Chip Status Control Register (0x00)

Function: Control of Power mode, RF on/off, AGC, AM/PM, Direct Mode

Default: 0x01, preset at EN = L or POR = H

Bit

Name

Function

1 = Standby Mode

0 = Active Mode

Description

Standby mode keeps all supply regulators, 13.56-MHz SYS_CLK oscillator

running. (typical start-up time to full operation 100 µs)

B7

stby

Active Mode (default)

Provides user direct access to AFE (Direct Mode 0) or allows user to add their

own framing (Direct Mode 1). Bit 6 of ISO Control register must be set by user

before entering Direct Mode 0 or 1.

1 = Direct Mode 0 or 1

B6

B5

B4

direct

rf_on

0 = Direct Mode 2 (default) Uses SPI or parallel communication with automatic framing and ISO decoders

1 = RF output active

Transmitter on, receivers on

Transmitter off

0 = RF output not active

TX_OUT (pin 5) = 8-Ω output impedance P = 100 mW (20 dBm) at 5 V,

P = 33 mW (+15 dBm) at 3.3 V

1 = half output power

0 = full output power

rf_pwr

TX_OUT (pin 5) = 4-Ω output impedance P = 200 mW (+23 dBm) at 5 V,

P = 70 mW (+18 dBm) at 3.3 V

1 = selects Aux RX input

0 = selects Main RX input

1 = AGC on

RX_IN2 input is used

B3

B2

pm_on

agc_on

RX_IN1 input is used

Enables AGC (AGC gain can be set in register 0x0A)

AGC block is disabled

0 = AGC off

1 = Receiver activated for

Forced enabling of receiver and TX oscillator. Used for external field

external field measurement measurement.

B1

B0

rec_on

vrs5_3

0 = Automatic Enable

Allows enable of the receiver by Bit 5 of this register (0x00)

1 = 5 V operation

0 = 3 V operation

Selects the V_INvoltage range

6.3.1.2 ISO Control Register (0x01)

Table 6-3. ISO Control Register (0x01)

Function: Controls the selection of ISO Standard protocol, Direct Mode and Receive CRC

Default: 0x02 (ISO15693 high bit rate, one subcarrier, 1 out of 4); it is preset at EN = L or POR = H

Bit

Name

Function

Description

0 = RX CRC (CRC is present in the response)

1 = no RX CRC (CRC is not present in the response)

B7

rx_crc_n

CRC Receive selection

0 = Direct Mode 0

1 = Direct Mode 1

B6

B5

dir_mode

rfid

Direct mode type selection

RFID / Reserved

0 = RFID Mode

1 = Reserved (should be set to 0)

RFID: See Table 6-4 for B0:B4 settings based on ISO protocol desired by

application

B4

B3

B2

B1

iso_4

iso_3

RFID

RFID: See Table 6-4 for B0:B4 settings based on ISO protocol desired by

application

RFID: See Table 6-4 for B0:B4 settings based on ISO protocol desired by

application

iso_2

RFID: See Table 6-4 for B0:B4 settings based on ISO protocol desired by

application

iso_1

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Table 6-3. ISO Control Register (0x01) (continued)

RFID: See Table 6-4 for B0:B4 settings based on ISO protocol desired by

application

B0

iso_0

RFID

Table 6-4. ISO Control Register ISO_x Settings, RFID Mode

ISO_4

ISO_3

ISO_2

ISO_1

ISO_0

Protocol

Remarks

0

1

0

1

0

1

0

1

0

1

0

1

0

ISO15693 low bit rate, 6.62 kbps, one subcarrier, 1 out of 4

ISO15693 low bit rate, 6.62 kbps, one subcarrier, 1 out of 256

ISO15693 high bit rate, 26.48 kbps, one subcarrier, 1 out of 4

ISO15693 high bit rate, 26.48 kbps, one subcarrier, 1 out of 256

ISO15693 low bit rate, 6.67 kbps, double subcarrier, 1 out of 4

ISO15693 low bit rate, 6.67 kbps, double subcarrier, 1 out of 256

ISO15693 high bit rate, 26.69 kbps, double subcarrier, 1 out of 4

Default for reader

ISO15693 high bit rate, 26.69 kbps, double subcarrier,

1 out of 256

0

1

(1)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

ISO14443A RX bit rate, 106 kbps

ISO14443A RX high bit rate, 212 kbps

ISO14443A RX high bit rate, 424 kbps

ISO14443A RX high bit rate, 848 kbps

ISO14443B RX bit rate, 106 kbps

ISO14443B RX high bit rate, 212 kbps

ISO14443B RX high bit rate, 424 kbps

ISO14443B RX high bit rate, 848 kbps

Reserved

RX bit rate

(1)

RX bit rate

Reserved

FeliCa 212 kbps

FeliCa 424 kbps

(1) For ISO14443A/B, when bit rate of TX is different than RX, settings can be done in register 0x02 or 0x03.

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6.3.2 Control Registers – Sub Level Configuration Registers

6.3.2.1 ISO14443B TX Options Register (0x02)

Table 6-5. ISO14443B TX Options Register (0x02)

Function: Selects the ISO subsets for ISO14443B – TX

Default: 0x00 at POR = H or EN = L

Bit

B7

B6

B5

Name

egt2

egt1

egt0

Function

Description

TX EGT time select MSB

TX EGT time select

Three bit code defines the number of etu (0-7) which separate two characters.

ISO14443B TX only

TX EGT time select LSB

1 = EOF→ 0 length 11 etu

0 = EOF→ 0 length 10 etu

B4

B3

B2

eof_l0

sof_l1

sof _l0

1 = SOF→ 1 length 03 etu

0 = SOF→ 1 length 02 etu

ISO14443B TX only

1 = SOF→ 0 length 11 etu

0 = SOF→ 0 length 10 etu

1 = EGT after each byte

0 = EGT after last byte is

omitted

B1

B0

l_egt

Reserved

6.3.2.2 ISO14443A High-Bit-Rate and Parity Options Register (0x03)

Table 6-6. ISO14443A High-Bit-Rate and Parity Options Register (0x03)

Function: Selects the ISO subsets for ISO14443A – TX

Default: 0x00 at POR = H or EN = L, and at each write to ISO Control register

Bit

B7

B6

Name

dif_tx_br

tx_br1

Function

Description

TX bit rate different than RX

bit rate enable

Valid for ISO14443A/B high bit rate

tx_br1 = 0, tx_br = 0 → 106 kbps

tx_br1 = 0, tx_br = 1 → 212 kbps

tx_br1 = 1, tx_br = 0 → 424 kbps

tx_br1 = 1, tx_br = 1 → 848 kbps

TX bit rate

B5

tx_br0

1 = parity odd except last

byte which is even for TX

B4

B3

parity-2tx

parity-2rx

For 14443A high bit rate, coding and decoding

1 = parity odd except last

byte which is even for RX

B2

B1

B0

Unused

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6.3.2.3 TX Timer High Byte Control Register (0x04)

Table 6-7. TX Timer High Byte Control Register (0x04)

Function: For Timings

Default: 0xC2 at POR = H or EN = L, and at each write to ISO Control register

Bit

Name

Function

Description

B7

tm_st1

Timer Start Condition

tm_st1 = 0, tm_st0 = 0 → beginning of TX SOF

tm_st1 = 0, tm_st0 = 1 → end of TX SOF

tm_st1 = 1, tm_st0 = 0 → beginning of RX SOF

tm_st1 = 1, tm_st0 = 1 → end of RX SOF

B6

tm_st0

Timer Start Condition

B5

B4

B3

B2

B1

B0

tm_lengthD

tm_lengthC

tm_lengthB

tm_lengthA

tm_length9

tm_length8

Timer Length MSB

Timer Length

Timer Length LSB

6.3.2.4 TX Timer Low Byte Control Register (0x05)

Table 6-8. TX Timer Low Byte Control Register (0x05)

Function: For Timings

Default: 0x00 at POR = H or EN = L, and at each write to ISO Control register

Bit

B7

B6

B5

B4

B3

B2

B1

B0

Name

Function

Timer Length MSB

Timer Length

Description

tm_length7

tm_length6

tm_length5

tm_length4

tm_length3

tm_length2

tm_length1

tm_length0

Defines the time when delayed transmission is started.

RX wait range is 590 ns to 9.76 ms (1 to 16383)

Step size is 590 ns

Timer Length

All bits low = timer disabled (0x00)

Timer Length

Preset 0x00 for all other protocols

Timer Length LSB

Register Description

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6.3.2.5 TX Pulse Length Control Register (0x06)

The length of the modulation pulse is defined by the protocol selected in the ISO Control register 0x01.

With a high Q antenna, the modulation pulse is typically prolonged, and the tag detects a longer pulse

than intended. For such cases, the modulation pulse length can be corrected by using the TX pulse length

register 0x06. If the register contains all zeros, then the pulse length is governed by the protocol selection.

If the register contains a value other than 0x00, the pulse length is equal to the value of the register in

73.7-ns increments. This means the range of adjustment can be 73.7 ns to 18.8 µs.

Table 6-9. TX Pulse Length Control Register (0x06)

Function: Controls the length of TX pulse

Default: 0x00 at POR = H or EN = L and at each write to ISO Control register.

Bit

B7

B6

B5

B4

B3

B2

B1

Name

Pul_p2

Pul_p1

Pul_p0

Pul_c4

Pul_c3

Pul_c2

Pul_c1

Function

Description

Pulse length MSB

The pulse range is 73.7 ns to 18.8 µs (1….255), step size 73.7 ns.

All bits low (00): pulse length control is disabled.

The following default timings are preset by the ISO Control register (0x01):

9.44 µs → ISO15693 (TI Tag-It HF-I)

11 µs → Reserved

2.36 µs → ISO14443A at 106 kbps

1.4 µs → ISO14443A at 212 kbps

B0

Pul_c0

Pulse length LSB

737 ns → ISO14443A at 424 kbps

442 ns → ISO14443A at 848 kbps; pulse length control disabled

6.3.2.6 RX No Response Wait Time Register (0x07)

The RX No Response timer is controlled by the RX NO Response Wait Time Register 0x07. This timer

measures the time from the start of slot in the anticollision sequence until the start of tag response. If there

is no tag response in the defined time, an interrupt request is sent and a flag is set in IRQ status control

register 0x0C. This enables the external controller to be relieved of the task of detecting empty slots. The

wait time is stored in the register in increments of 37.76 µs. This register is also preset, automatically, for

every new protocol selection.

Table 6-10. RX No Response Wait Time Register (0x07)

Function: Defines the time when "no response" interrupt is sent; only for ISO15693

Default: 0x0E at POR = H or EN = L and at each write to ISO Control register

Bit

B7

B6

B5

B4

B3

B2

B1

Name

Function

Description

NoResp7

NoResp6

NoResp5

NoResp4

NoResp3

NoResp2

NoResp1

No response MSB

Defines the time when "no response" interrupt is sent. It starts from the end of

TX EOF. RX no response wait range is 37.76 µs to 9628 µs (1 to 255), step

size is: 37.76 µs.

The following default timings are preset by the ISO Control register (0x01):

390 µs → Reserved

529 µs → for all protocols supported, but not listed here

604 µs → Reserved

755 µs → ISO15693 high data rate (TI Tag-It HF-I)

1812 µs → ISO15693 low data rate (TI Tag-It HF-I)

B0

NoResp0

No response LSB

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6.3.2.7 RX Wait Time Register (0x08)

The RX-wait-time timer is controlled by the value in the RX wait time register 0x08. This timer defines the

time after the end of the transmit operation in which the receive decoders are not active (held in reset

state). This prevents incorrect detections resulting from transients following the transmit operation. The

value of the RX wait time register defines this time in increments of 9.44 µs. This register is preset at

every write to ISO Control register 0x01 according to the minimum tag response time defined by each

standard.

Table 6-11. RX Wait Time Register (0x08)

Function: Defines the time after TX EOF when the RX input is disregarded for example, to block out electromagnetic disturbance

generated by the responding card.

Default: 0x1F at POR = H or EN = L and at each write toISO control register.

Bit

B7

B6

B5

B4

B3

B2

B1

Name

Rxw7

Rxw6

Rxw5

Rxw4

Rxw3

Rxw2

Rxw1

Function

Description

Defines the time after the TX EOF during which the RX input is ignored. Time

starts from the end of TX EOF.

RX wait range is 9.44 µs to 2407 µs (1 to 255), Step size 9.44 µs.

The following default timings are preset by the ISO Control register (0x01):

9.44 µs → FeliCa

RX wait time

66 µs → ISO14443A and B

180 µs → Reserved

B1

Rxw0

293 µs → ISO15693 (TI Tag-It HF-I)

Register Description

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6.3.2.8 Modulator and SYS_CLK Control Register (0x09)

The frequency of SYS_CLK (pin 27) is programmable by the bits B4 and B5 of this register. The frequency

of the TRF7964A system clock oscillator is divided by 1, 2 or 4 resulting in available SYS_CLK

frequencies of 13.56 MHz or 6.78 MHz or 3.39 MHz.

The ASK modulation depth is controlled by bits B0, B1 and B2. The range of ASK modulation is 7% to

30% or 100% (OOK). The selection between ASK and OOK (100%) modulation can also be done using

direct input OOK (pin 12). The direct control of OOK/ASK using OOK pin is only possible if the function is

enabled by setting B6 = 1 (en_ook_p) in this register (0x09) and the ISO Control Register (0x01, B6 = 1).

When configured this way, the MOD (pin 14) is used as input for the modulation signal.

Table 6-12. Modulator and SYS_CLK Control Register (0x09)

Function: Controls the modulation input and depth, ASK / OOK control and clock output to external system (MCU)

Default: 0x91 at POR = H or EN = L, and at each write to ISO control register, except Clo1 and Clo0.

Bit

Name

Function

Description

B7

27MHz

Enables 27.12-MHz crystal

Default = 1 (enabled)

Enable ASK/OOK pin (pin 12) for "on the fly change" between any preselected

ASK modulation as defined by B0 to B2 and OOK modulation:

1 = Enables external

selection of ASK or OOK

modulation

0 = Default operation as

defined in B0 to B2 (0x09)

B6

B5

en_ook_p

If B6 is 1, pin 12 is configured as follows:

1 = OOK modulation

0 = Modulation as defined in B0 to B2 (0x09)

SYS_CLK Output SYS_CLK Output

Clo1

Clo0

(if 13.56-MHz

(if 27.12-MHz

crystal is used)

SYS_CLK output frequency

MSB

crystal is used)

Clo1

0

1

0

1

0

1

Disabled

3.39 MHz

6.78 MHz

13.56 MHz

Disabled

6.78 MHz

13.56 MHz

27.12 MHz

SYS_CLK output frequency

LSB

B4

B3

Clo0

1 = Sets pin 12 (ASK/OOK)

as an analog output

0 = Default

For test and measurement purpose. ASK/OOK pin 12 can be used to monitor

the analog subcarrier signal before the digitizing with DC level equal to AGND.

en_ana

Pm2

Pm1

Pm0

Mod Type and %

ASK 10%

B2

B1

B0

Pm2

Pm1

Pm0

Modulation depth MSB

Modulation depth

0

1

0

1

0

1

0

1

0

1

0

1

0

1

OOK (100%)

ASK 7%

ASK 8.5%

ASK 13%

ASK 16%

Modulation depth LSB

ASK 22%

ASK 30%

58

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6.3.2.9 RX Special Setting Register (Address 0x0A)

Table 6-13. RX Special Setting Register (Address 0x0A)

Function: Sets the gains and filters directly

Default: 0x40 at POR = H or EN = L, and at each write to the ISO Control register 0x01. When bits B7, B6, B5 and B4 are all zero, the

filters are set for ISO14443B (240 kHz to 1.4 MHz).

Bit

B7

B6

Name

C212

C424

Function

Description

Bandpass 110 kHz to 570 kHz

Bandpass 200 kHz to 900 kHz

Appropriate for 212-kHz subcarrier system (FeliCa)

Appropriate for 424-kHz subcarrier used in ISO15693

Appropriate for Manchester-coded 848-kHz subcarrier used in ISO14443A

and B

B5

M848

Bandpass 450 kHz to 1.5 MHz

Bandpass 100 kHz to 1.5 MHz

Gain reduced for 18 dB

B4

B3

hbt

Appropriate for highest bit rate (848 kbps) used in high-bit-rate ISO14443

gd1

00 = Gain reduction 0 dB

01 = Gain reduction for 5 dB

10 = Gain reduction for 10 dB

11 = Gain reduction for 15 dB

Sets the RX gain reduction, and reduces sensitivity

B2

gd2

AGC activation level changed from five times the digitizing level to three

times the digitizing level.

1 = 3x

0 = 5x

B1

agcr

AGC activation level change

AGC action can be done any time during receive process. It is not limited

to the start of receive ("max hold").

1 = continuously – no time limit

B0

no-lim

AGC action is not limited in time

0 = 8 subcarrier pulses

The first four steps of the AGC control are comparator adjustment. The second three steps are real gain

reduction done automatically by AGC control. The AGC is turned on after TX.

The first gain and filtering stage following the RF envelope detector has a nominal gain of 15 and the 3-dB

band-pass frequencies are adjustable in the range from 100 kHz to 400 kHz for high pass and 600 kHz to

1.5 MHz for low pass. The next gain and filtering stage has a nominal gain of 8 and the frequency

characteristic identical to first stage. The filter setting is done automatically with internal preset for each

new selection of communication standard in ISO Control register (0x01). Additional corrections can be

done by directly writing into the RX Special Setting register 0x0A.

The second receiver gain stage and digitizer stage are included in the AGC loop. The AGC loop can be

activated by setting the bit B2 = 1 (agc-on) in Chip Status Control register 0x00. If activated the AGC

monitors the signal level at the input of digitizing stage. If the signal level is significantly higher than the

digitizing threshold level, the gain reduction is activated. The signal level, at which the action is started, is

by default five times the digitizing threshold level. It can be reduced to three times the digitizing level by

setting bit B1 = 1 (agcr) in RX Special Setting register (0x0A).

The AGC action is fast and it typically finishes after four subcarrier pulses. By default the AGC action is

blocked after first few pulses of subcarrier signal so AGC cannot interfere with signal reception during rest

of data packet. In certain cases, this is not optimal, so this blocking can be removed by setting B0 = 1

(no_lim) in RX Special Setting register (0x0A).

NOTE

The setting of bits B4, B5, B6 and B7 to zero selects bandpass characteristic of 240 kHz to

1.4 MHz. This is appropriate for ISO14443B, FeliCa protocol, and ISO14443A higher bit

rates 212 kbps and 424 kbps.

Register Description

59

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6.3.2.10 Regulator and I/O Control Register (0x0B)

Table 6-14. Regulator and I/O Control Register (0x0B)

Function: Control the three voltage regulators

Default: 0x87 at POR = H or EN = L

Bit

Name

Function

Description

0 = Manual settings; see B0

to B2 in Table 6-15 and

Table 6-16

1 = Automatic setting; see

Table 6-17 and Table 6-18

Auto system sets V_{DD_RF}= V_IN– 250 mV and V_{DD_A}= V_IN– 250 mV and

V_{DD_X}= V_IN– 250 mV, but not higher than 3.4 V.

B7

auto_reg

Internal peak detectors are disabled, receiver inputs (RX_IN1 and RX_IN2)

accept externally demodulated subcarrier. At the same time ASK/OOK pin 12

becomes modulation output for external TX amplifier.

Support for external power

amplifier

B6

B5

en_ext_pa

io_low

When B5 = 1, maintains the output driving capabilities of the I/O pins connected

to the level shifter under low voltage operation. Should be set 1 when V_{DD_I/O}

voltage is between 1.8 V to 2.7 V.

1 = enable low peripheral

communication voltage

B4

B3

B2

B1

B0

Unused

vrs2

No function

Default is 0.

Voltage set MSB voltage

set LSB

Vrs3_5 = L: V_{DD_RF}, V_{DD_A}, V_{DD_X}range 2.7 V to 3.4 V; see Table 6-15 through

Table 6-18

vrs1

vrs0

Table 6-15. Supply-Regulator Setting – Manual 5-V System

Option Bits Setting in Control Register

Register

Action

B7

B6

B5

B4

B3

B2

B1

B0

00

0B

1

5-V system

0

Manual regulator setting

1

0

1

0

1

0

1

0

1

0

1

0

1

0

V_{DD_RF}= 5 V, V_{DD_A}= 3.5 V, V_{DD_X}= 3.4 V

V_{DD_RF}= 4.9 V, V_{DD_A}= 3.5 V, V_{DD_X}= 3.4 V

V_{DD_RF}= 4.8 V, V_{DD_A}= 3.5 V, V_{DD_X}= 3.4 V

V_{DD_RF}= 4.7 V, V_{DD_A}= 3.5 V, V_{DD_X}= 3.4 V

V_{DD_RF}= 4.6 V, V_{DD_A}= 3.5 V, V_{DD_X}= 3.4 V

V_{DD_RF}= 4.5 V, V_{DD_A}= 3.5 V, V_{DD_X}= 3.4 V

V_{DD_RF}= 4.4 V, V_{DD_A}= 3.5 V, V_{DD_X}= 3.4 V

V_{DD_RF}= 4.3 V, V_{DD_A}= 3.5 V, V_{DD_X}= 3.4 V

Table 6-16. Supply-Regulator Setting – Manual 3-V System

Option Bits Setting in Control Register

Register

Action

B7

B6

B5

B4

B3

B2

B1

B0

00

0B

0

3-V system

0

Manual regulator setting

1

0

1

0

1

0

1

0

1

0

1

0

1

0

V_{DD_RF}= 3.4 V, V_{DD_A}and V_{DD_X}= 3.4 V

V_{DD_RF}= 3.3 V, V_{DD_A}and V_{DD_X}= 3.3 V

V_{DD_RF}= 3.2 V, V_{DD_A}and V_{DD_X}= 3.2 V

V_{DD_RF}= 3.1 V, V_{DD_A}and V_{DD_X}= 3.1 V

V_{DD_RF}= 3.0 V, V_{DD_A}and V_{DD_X}= 3.0 V

V_{DD_RF}= 2.9 V, V_{DD_A}and V_{DD_X}= 2.9 V

V_{DD_RF}= 2.8 V, V_{DD_A}and V_{DD_X}= 2.8 V

V_{DD_RF}= 2.7 V, V_{DD_A}and V_{DD_X}= 2.7 V

60

Register Description

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Table 6-17. Supply-Regulator Setting – Automatic 5-V System

Option Bits Setting in Control Register

Action

B7

B6

B5

B4

B3

B2

B1

B0

1

00

0B

5-V system

(1)

1

x

1

0

1

Automatic regulator setting 250-mV difference

Automatic regulator setting 350-mV difference

Automatic regulator setting 400-mV difference

x

0

(1) x = don't care

Table 6-18. Supply-Regulator Setting – Automatic 3-V System

Option Bits Setting in Control Register

Register

B7

Action

B6

B5

B4

B3

B2

B1

B0

0

00

3-V system

(1)

0B

1

x

1

0

1

Automatic regulator setting 250-mV difference

Automatic regulator setting 350-mV difference

Automatic regulator setting 400-mV difference

x

0

(1) x = don't care

6.3.3 Status Registers

6.3.3.1 IRQ Status Register (0x0C)

Table 6-19. IRQ Status Register (0x0C)

Function: Information available about TRF7964A IRQ and TX/RX status

Default: 0x00 at POR = H or EN = L, and at each write to the ISO Control Register 0x01. It is also automatically reset at the end of a read

phase. The reset also removes the IRQ flag.

Bit

Name

Function

Description

Signals that TX is in progress. The flag is set at the start of TX but the interrupt

request (IRQ = 1) is sent when TX is finished.

B7

Irq_tx

IRQ set due to end of TX

Signals that RX SOF was received and RX is in progress. The flag is set at the

start of RX but the interrupt request (IRQ = 1) is sent when RX is finished.

B6

B5

B4

Irg_srx

Irq_fifo

Irq_err1

IRQ set due to RX start

Signals the FIFO is 1/3 >

FIFO > 2/3

Signals FIFO high or low

Indicates receive CRC error only if B7 (no RX CRC) of ISO Control register is

set to 0.

CRC error

B3

B2

Irq_err2

Irq_err3

Parity error

Indicates parity error for ISO14443A

Indicates framing error

Byte framing or EOF error

Collision error for ISO14443A and ISO15693 single subcarrier. Bit is set if more

then 6 or 7 (as defined in register 0x01) are detected inside one bit period of

ISO14443A 106 kbps. Collision error bit can also be triggered by external

noise.

B1

B0

Irq_col

Collision error

No response within the "No-response time" defined in RX No-response Wait

Time register (0x07). Signals the MCU that next slot command can be sent.

Only for ISO15693.

Irq_noresp

No-response timeinterrupt

To reset (clear) the register 0x0C and the IRQ line, the register must be read. During Transmit the

decoder is disabled, only bits B5 and B7 can be changed. During Receive only bit B6 can be changed, but

does not trigger the IRQ line immediately. The IRQ signal is set at the end of Transmit and Receive

phase.

Register Description

61

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6.3.3.2 Collision Position Register (0x0D) and Interrupt Mask Register (0x0E)

Table 6-20. Collision Position Register (0x0D) and Interrupt Mask Register (0x0E)

Default: 0x3E at POR = H and EN = L. Collision bits reset automatically after read operation.

Bit

B7

B6

B5

B4

B3

Name

Col9

Function

Description

Bit position of collision MSB Supports ISO14443A

Bit position of collision

Col8

En_irq_fifo

En_irq_err1

En_irq_err2

Interrupt enable for FIFO

Interrupt enable for CRC

Interrupt enable for Parity

Default = 1

Interrupt enable for Framing

error or EOF

B2

B1

B0

En_irq_err3

En_irq_col

Default = 1

Default = 0

Interrupt enable for collision

error

Enables no-response

interrupt

En_irq_noresp

Table 6-21. Collision Position Register (0x0E)

Function: Displays the bit position of collision or error

Default: 0x00 at POR = H and EN = L. Automatically reset after read operation.

Bit

B7

B6

B5

B4

B3

B2

B1

B0

Name

Col7

Col6

Col5

Col4

Col3

Col2

Col1

Col0

Function

Description

Bit position of collision MSB

ISO14443A mainly supported, in the other protocols this register shows the bit

position of error. Either frame, SOF/EOF, parity or CRC error.

Bit position of collision LSB

62

Register Description

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6.3.3.3 RSSI Levels and Oscillator Status Register (0x0F)

Table 6-22. RSSI Levels and Oscillator Status Register (0x0F)

Function: Displays the signal strength on both reception channels and RF amplitude during RF-off state. The RSSI values are valid from

reception start till start of next transmission.

Bit

Name

Function

Description

B7

Unused

Crystal oscillator stable

indicator

B6

osc_ok

13.56-MHz frequency stable (≈200 µs)

MSB RSSI value of auxiliary

RX (RX_IN2)

B5

B4

B3

rssi_x2

rssi_x1

rssi_x0

Auxiliary channel is by default RX_IN2. The input can be swapped by B3 = 1

(Chip State Control register 0x00). If "swapped", the Auxiliary channel is

connected to RX_IN1 and, hence, the Auxiliary RSSI represents the signal level

at RX_IN2.

Auxiliary channel RSSI

MSB RSSI value of auxiliary

RX (RX_IN2)

MSB RSSI value of main

RX (RX_IN1)

B2

B1

B0

rssi_2

rssi_1

rssi_0

Active channel is default and can be set with option bit B3 = 0 of chip state

control register 0x00.

Main channel RSSI

LSB RSSI value of main RX

(RX_IN1)

RSSI measurement block is measuring the demodulated envelope signal (except in case of direct

command for RF amplitude measurement described later in direct commands section). The measuring

system is latching the peak value, so the RSSI level can be read after the end of receive packet. The

RSSI value is reset during next transmit action of the reader, so the new tag response level can be

measured. The RSSI levels calculated to the RF_IN1 and RF_IN2 are presented in Section 5.4.1.1 and

Section 5.4.1.2. The RSSI has 7 steps (3 bits) with 4-dB increment. The input level is the peak to peak

modulation level of RF signal measured on one side envelope (positive or negative).

6.3.3.4 Special Functions Register (0x10)

Table 6-23. Special Functions Register (0x10)

Function: User configurable options for ISO14443A specific operations

Bit

B7

B6

Name

Function

Description

Reserved

Disables parity checking for

ISO14443A

B5

B4

B3

B2

par43

0 = 18.88 µs

1 = 37.77 µs

next_slot_37us

Sp_dir_mode

4_bit_RX

Sets the time grid for next slot command in ISO15693

Bit stream transmit for

MIFARE at 106 kbps

Enables direct mode for transmitting ISO14443A data, bypassing the FIFO and

feeding the data bit stream directly onto the encoder.

0 = normal receive

1 = 4-bit receive

Enable 4-bit replay for example, ACK, NACK used by some cards; for example,

MIFARE Ultralight

0 = anticollision framing

(0x93, 0x95, 0x97)

1 = normal framing (no

broken bytes)

Disable anticollision frames for 14443A (this bit should be set to 1 after

anticollision is finished)

B1

B0

14_anticoll

col_7_6

0 = 7 subcarrier pulses

1 = 6 subcarrier pulses

Selects the number of subcarrier pulses that trigger collision error in the

14443A - 106 kbps

Register Description

63

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6.3.3.5 Special Functions Register (0x11)

Table 6-24. Special Functions Register (0x11)

Function: Indicate IRQ status for RX operations.

Bit

B7

B6

B5

B4

B3

B2

B1

Name

Function

Description

Reserved

Copy of the RX start signal

(Bit 6) of the IRQ Status

Register (0x0C)

Signals the RX SOF was received and the RX is in progress. IRQ when RX is

completed.

B0

irg_srx

6.3.3.6 Adjustable FIFO IRQ Levels Register (0x14)

Table 6-25. Adjustable FIFO IRQ Levels Register (0x14)

Function: Adjusts level at which FIFO indicates status by IRQ

Default: 0x00 at POR = H and EN = L

Bit

B7

B6

B5

B4

B3

Name

Function

Description

Reserved

Wlh_1

Reserved

Wlh_1

Wlh_0

IRQ Level

124

0

1

0

1

0

1

FIFO high IRQ level (during

RX)

120

112

96

B2

B1

B0

Wlh_0

Wll_1

Wll_0

Wll_1

Wll_0

IRQ Level

0

1

0

1

0

1

4

8

16

32

FIFO low IRQ level (during

TX)

64

Register Description

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6.3.4 Test Registers

6.3.4.1 Test Register (0x1A)

Table 6-26. Test Register (0x1A) (for Test or Direct Use)

Default: 0x00 at POR = H and EN = L.

Bit

B7

B6

Name

Function

Subcarrier Input

Description

OOK Pin becomes decoder digital input

OOK_Subc_In

MOD_Subc_Out Subcarrier Output

MOD Pin becomes receiver subcarrier output

Direct TX modulation and

RX reset

B5

B4

B3

MOD_Direct

o_sel

MOD pin becomes input for TX modulation control by the MCU

o_sel = L: Second Stage output used for analog out and digitizing

o_sel = H: Second Stage output used for analog out and digitizing

First stage output selection

Second stage gain -6 dB,

HP corner frequency/2

low2

First stage gain -6 dB, HP

corner frequency/2

B2

B1

B0

low1

zun

Input followers test

AGC test, AGC level is

seen on rssi_210 bits

Test_AGC

6.3.4.2 Test Register 0x1B

Table 6-27. Test Register (0x1B) (for Test or Direct Use)

Default: 0x00 at POR = H and EN = L. When a test_dec or test_io is set IC is switched to test mode. Test Mode persists until a stop

condition arrives. At stop condition the test_dec and test_io bits are cleared.

Bit

B7

B6

B5

B4

B3

B2

B1

B0

Name

Function

Description

test_rf_level

RF level test

test_io1

test_io0

test_dec

clock_su

I/O test

Not implemented

Decoder test mode

Coder clock 13.56 MHz

For faster test of coders

Register Description

65

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6.3.5 FIFO Control Registers

6.3.5.1 FIFO Status Register (0x1C)

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Table 6-28. FIFO Status Register (0x1C)

Function: Number of bytes available to be read from FIFO (= N number of bytes, in hexadecimal)

Bit

B7

B6

B5

B4

B3

B2

B1

B0

Name

Foverflow

Fb6

Function

FIFO overflow error

FIFO bytes fb[6]

FIFO bytes fb[5]

FIFO bytes fb[4]

FIFO bytes fb[3]

FIFO bytes fb[2]

FIFO bytes fb[1]

FIFO bytes fb[0]

Description

Bit is set when FIFO has more than 128 bytes presented to it

Fb5

Fb4

Fb3

Fb2

Bits B0:B6 indicate how many bytes that are in the FIFO to be read out (= N

number of bytes, in hex)

Fb1

Fb0

66

Register Description

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6.3.5.2 TX Length Byte1 Register (0x1D), TX Length Byte2 Register (0x1E)

Table 6-29. TX Length Byte1 Register (0x1D)

Function: High 2 nibbles of complete, intended bytes to be transferred through FIFO

Register default is set to 0x00 at POR and EN = 0. It is also automatically reset at TX EOF

Bit

Name

Function

Description

Number of complete byte

bn[11]

B7

Txl11

Number of complete byte

bn[10]

B6

B5

B4

B3

B2

B1

B0

Txl10

Txl9

Txl8

Txl7

Txl6

Txl5

Txl4

High nibble of complete, intended bytes to be transmitted

Number of complete byte

bn[9]

Number of complete byte

bn[8]

Number of complete byte

bn[7]

Number of complete byte

bn[6]

Middle nibble of complete, intended bytes to be transmitted

Number of complete byte

bn[5]

Number of complete byte

bn[4]

Table 6-30. TX Length Byte2 Register (0x1E)

Function: Low nibbles of complete bytes to be transferred through FIFO; Information about a broken byte and number of bits to be

transferred from it

Default: 0x00 at POR and EN = 0. It is also automatically reset at TX EOF

Bit

Name

Function

Description

Number of complete byte

bn[3]

B7

Txl3

Number of complete byte

bn[2]

B6

B5

B4

B3

B2

Txl2

Txl1

Txl0

Bb2

Bb1

Low nibble of complete, intended bytes to be transmitted

Number of complete byte

bn[1]

Number of complete byte

bn[0]

Broken byte number of bits

bb[2]

Broken byte number of bits Number of bits in the last broken byte to be transmitted.

bb[1]

It is taken into account only when broken byte flag is set.

Broken byte number of bits

bb[0]

B1

B0

Bb0

Bbf

Broken byte flag

B0 = 1, indicates that last byte is not complete 8 bits wide.

Register Description

67

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7 System Design

7.1 Layout Considerations

Keep all decoupling capacitors as close to the IC as possible, with the high-frequency decoupling

capacitors (10 nF) closer than the low-frequency decoupling capacitors (2.2 µF).

Place ground vias as close as possible to the ground side of the capacitors and reader IC pins to minimize

possible ground loops.

It is not recommend to use any inductor sizes below 0603, as the output power can be compromised. If

smaller inductors are necessary, output performance must be confirmed in the final application.

Pay close attention to the required load capacitance of the crystal, and adjust the two external shunt

capacitors accordingly. Follow the recommendations of the crystal manufacturer for those values.

There should be a common ground plane for the digital and analog sections. The multiple ground sections

or islands should have vias that tie the different sections of the planes together.

Ensure that the exposed thermal pad at the center of the reader IC is properly laid out. It should be tied to

ground to help dissipate any heat from the package.

All trace line lengths should be made as short as possible, particularly the RF output path, crystal

connections, and control lines from the reader to the microprocessor. Proper placement of the TRF7964A,

microprocessor, crystal, and RF connection/connector help facilitate this.

Avoid crossing of digital lines under RF signal lines. Also, avoid crossing of digital lines with other digital

lines when possible. If the crossings are unavoidable, 90° crossings should be used to minimize coupling

of the lines.

Depending on the production test plan, consider possible implementations of test pads or test vias for use

during testing. The necessary pads or vias should be placed in accordance with the proposed test plan to

enable easy access to those test points.

If the system implementation is complex (for example, if the RFID reader module is a subsystem of a

greater system with other modules (Bluetooth, WiFi, microprocessors, and clocks), special considerations

should be taken to ensure that there is no noise coupling into the supply lines. If needed, special filtering

or regulator considerations should be used to minimize or eliminate noise in these systems.

For more information/details on layout considerations, see the TRF796x HF-RFID Reader Layout Design

Guide (SLOA139).

7.2 Impedance Matching TX_Out (Pin 5) to 50 Ω

The output impedance of the TRF7964A when operated at full power out setting is nominally 4 + j0 (4 Ω

real). This impedance must be matched to a resonant circuit and TI recommends matching circuit from

4 Ω to 50 Ω, as commercially available test equipment (for example, spectrum analyzers, power meters,

and network analyzers) are 50-Ω systems. An impedance-matching reference circuit can be seen in

Figure 7-1 and Figure 7-2. This section explains how the values were calculated.

Starting with the 4-Ω source, the process of going from 4 Ω to 50 Ω can be represented on a Smith Chart

simulator (available from http://www.fritz.dellsperger.net/). The elements are combined where appropriate

(see Figure 7-1).

68

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Figure 7-1. Impedance Matching Circuit

This yields the Smith Chart Simulation shown in Figure 7-2.

Figure 7-2. Smith Chart Simulation

System Design

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Resulting power out can be measured with a power meter or spectrum analyzer with power meter function

or other equipment capable of making a "hot" measurement. Observe maximum power input levels on test

equipment and use attenuators whenever available to avoid damage to equipment. Expected output

power levels under various operating conditions are shown in Table 6-2.

7.3 Reader Antenna Design Guidelines

For HF antenna design considerations using the TRF7964A, see these documents:

•

Antenna Matching for the TRF7960 RFID Reader (SLOA135)

TRF7960TB HF RFID Reader Module User's Guide (SLOU297)

70

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8 Revision History

Revision

Comments

SLOS787

Initial release

SLOS787A

Section 3.3, Corrected Power Rating for T_A≤ 25°C.

Revision History

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interface.ti.com

logic.ti.com

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TRF7964A
厂家：	TEXAS INSTRUMENTS
描述：	MULTI-PROTOCOL FULLY INTEGRATED 13.56-MHz RFID READER/WRITER IC 多协议完全集成的13.56MHz RFID读/写器IC
文件：	总76页 (文件大小：3009K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TRF7964A [TI]

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