TS2PCIE2212ZAHRG1 [TI]
PCI Express™ SIGNAL SWITCH; 的PCI Express ™信号开关
| 型号： | TS2PCIE2212ZAHRG1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PCI Express™ SIGNAL SWITCH |
| 文件： | 总12页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TS2PCIE2212
PCI Express™ SIGNAL SWITCH
www.ti.com
SCDS209–JUNE 2006
FEATURES
•
Offers Bandwidth Allocation of PCI Express™
Signal Using Two-Lane 1:2
Multiplexer/Demultiplexer
•
•
•
Excellent Differential Skew (5 ps Max)
Minimal Propagation Delay
ESD Performance Tested Per JESD 22
•
•
•
•
•
•
Vcc Operating Range From 1.7 V to 1.9 V
Supports Data Rates of 2.5 Gbps
– 2000-V Human-Body Model
(A114-B, Class II)
Port-Port Crosstalk (–39 dB at 1.25 GHz)
OFF Port Isolation (–38 dB at 1.25 GHz)
Low ON-State Resistance (10 Ω Typ)
Low Input/Output Capacitance (3.5 pF Typ)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
The TS2PCIE2212 can be used to muxltiplex/demultiplex two PCI Express™ lanes, each representing
differential pairs of receive (RX) and transmit (TX) signals. The switch operates at the PCI Express bandwidth
standard of 2.5-Gbps signal-processing speed. The device is composed of two banks, with each bank
accommodating two sources (source A and source B) and two destinations (destination A and destination B).
When a logic-level low is applied to the control (CTRL) pin, source A is connected to destination A and source B
is connected to destination B. When a logic-level high is applied to CTRL, source A is connected to destination
B, while source B and destination A are open.
ORDERING INFORMATION
TA
PACKAGE
Tape and reel
ORDERABLE PART NUMBER
TOP-SIDE MARKING
0°C to 85°C
BGA – ZAH
TS2PCIE2212ZAHR
ZAH PACKAGE
(BOTTOM VIEW)
5 mm
J
H
G
F
5 mm
E
D
C
B
A
1
2 7 8 9
3 4 5 6
TERMINAL ASSIGNMENTS
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
CTRL0
TxSB:0P
GND
TxSA:0P
TxSA:0N
GND
VDD
TxDA:0P
TxDA:0N
TxDB:0P
GND
NC
RxSA:0P
TxSB:0N
TxDB:0N
RxDA:0P
RxSA:0N
RxSB:0N
VDD
RxDA:0N
RxDB:0N
VDD
RxSB:0P
GND
RxDB:0P
GND
TxSA:1P
TxSA:1N
TxSB:1N
GND
TxDA:1N
TxDB:1N
GND
TxDA:1P
G
H
J
TxSB:1P
NC
RxSA:1N
RxSB:1N
RXSB:1P
VDD
GND
RxDB:1N
RXDB:1P
RxDA:1N
TxDB:1P
CTRL1
RxSA:1P
RxDA:1P
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PCI Express is a trademark of PCI-SIG.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TS2PCIE2212
PCI Express™ SIGNAL SWITCH
www.ti.com
SCDS209–JUNE 2006
PIN DESCRIPTION
NAME
FUNCTION
TxSA:nP, TxSA:nN
RxSA:nP, RxSA:nN
TxSB:nP, TxSB:nN
RxSB:nP, RxSB:nN
TxDA:nP, TxDA:nN
RxDA:nP, RxDA:nN
TxDB:nP, TxDB:nN
RxDB:nP, RxDB:nN
CTRL0
Source A transmit pair
Source A receive pair
Source B transmit pair
Source B receive pair
Destination A transmit pair
Destination A receive pair
Destination B transmit pair
Destination B receive pair
Control signal for bank 0
Control signal for bank 1
Positive supply voltage
Ground (0 V)
CTRL1
VDD
GND
NC
No internal connection
LOGIC DIAGRAM
CTRL0
2
2
TxSA:0
TxDA:0
2
2
2
2
TxSB:0
RxSA:0
TxDB:0
RxDA:0
2
2
2
2
RxDB:0
TxDA:1
RxSB:0
TxSA:1
2
2
2
2
TxSB:1
RxSA:1
TxDB:1
RxDA:1
2
2
RxSB:1
CTRL1
RxDB:1
2
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TS2PCIE2212
PCI Express™ SIGNAL SWITCH
www.ti.com
SCDS209–JUNE 2006
FUNCTION TABLE
CTRLn
FUNCTION
L
SA:n = DA:n, SB:n = DB:n
H
SA:n = DB:n, DA:n = open, SBin = open
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
2.5
UNIT
V
VDD
VIN
VI/O
IIK
Supply voltage range
Control input voltage range(2)(3)
Switch I/O voltage range(2)(3)(4)
Control input clamp current
I/O port clamp current
2.5
V
2.5
V
VIN < 0 and VI/O < 0
VIN < 0 and VI/O < 0
50
mA
mA
mA
mA
°C/W
°C
II/OK
II/O
50
ON-state switch current(5)
±100
±100
TBD
150
Continuous current through VDD or GND
Package thermal impedance(6)
Storage temperature range
θJA
Tstg
–65
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) VI and VO are used to denote specific conditions for VI/O
(5) II and IO are used to denote specific conditions for II/O
.
.
(6) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
MIN
1.7
TYP
MAX UNIT
VDD
VIH
VIL
VIO
TA
Supply voltage
1.8
1.9
V
V
High-level control input voltage
Low-level control input voltage
Data input/output voltage
Operating free-air temperature
CTRL
CTRL
0.65 VDD
0.35 VDD
VDD
V
0
0
V
85
°C
3
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TS2PCIE2212
PCI Express™ SIGNAL SWITCH
www.ti.com
SCDS209–JUNE 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
TA = 0°C to 85°C
PARAMETER
TEST CONDITIONS
UNIT
MIN TYP
MAX
–1.8
VIK
IIN
Control inputs
Control inputs
VDD = 1.7 V,
VDD = 1.9 V,
IIN = –18 mA
V
VIN = VDD or GND
±1
µA
VO = 0 to 1.9 V,
VI = 0,
IOZ
VDD = 1.9 V,
Switch OFF
±5
µA
µA
VDD = 1.9 V,
VIN = VDD or GND,
ICC
Cin
II/O = 0,
Switch ON or OFF
160
300
Control inputs
VDD = 1.9 V,
VI/O = 0 V,
VIN = VDD or GND
Switch OFF
Switch ON
0.5
1.4
3.5
10
1.0
1.5
4
pF
pF
pF
CIO(OFF) SB or DA port
CIO(ON)
VI/O = 0 V,
VDD = 1.7 V,
VDD = 1.7 V,
VDD = 1.7 V,
VI = 0 V,
IO = 10 mA
14
17
5
ron
Ω
Ω
VI = 1.5 V,
IO = –10 mA
12
∆ron(flat)
IO = 10 mA,
VI = 1.5 V ± 0.4 V
2.5
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
TA = 0°C to 85°C
PARAMETER
DESCRIPTION
TEST CONDITIONS
UNIT
MIN
TYP
2.5
MAX
DR
tpd
tsk
Data rate per TX or RX pair
Propagation delay, Sx to Dx
Intra-pair skew
Gbps
ps
See Figure 7
250
f =1.25 GHz, See Figure 7
See Figure 6
5
5
ps
ten (tPZL, tPZH
)
Switch turn-on delay, CTRL to DA
Switch turn-off delay, CTRL to DA
ns
tdis (tPLZ, tPHZ
)
See Figure 6
2.5
ns
f =1.25 GHz, RLOAD = 50 Ω,
See Figure 1
ILOSS
Differential insertion loss
Differential return loss
–2.5
–9.5
–2
–3.2
dB
dB
dB
dB
dB
f =1.25 GHz, RLOAD = 50 Ω,
See Figure 2
RLOSS
ILOSS(CM)
OIFF
–7.2
f =1.25 GHz, RLOAD = 50 Ω,
See Figure 3
Common-mode insertion loss
Differential OFF isolation
Differential crosstalk
f =1.25 GHz, RLOAD = 50 Ω,
See Figure 4
–33
–33
–38
–39
f =1.25 GHz, RLOAD = 50 Ω,
See Figure 5
XTALK
4
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TS2PCIE2212
PCI Express™ SIGNAL SWITCH
www.ti.com
SCDS209–JUNE 2006
OPERATING CHARACTERISTICS
0
−1
−2
−3
−4
−5
0
−5
−10
−15
−20
−25
−6
0.01
0.10
1.00
10.00
0.01
0.10
1.00
10.00
Frequency (GHz)
Frequency (GHz)
Figure 1. Differential Insertion Loss vs Frequency
Figure 2. Differential Return Loss vs Frequency
0
−2
0
−20
−40
−60
−80
−4
−6
−8
−10
−12
0.01
0.10
1.00
10.00
0.01
0.10
1.00
10.00
Frequency (GHz)
Frequency (GHz)
Figure 3. Common-Mode Insertion Loss vs Frequency
Figure 4. Differential OFF Isolation vs Frequency
0
−20
−40
−60
−80
0.01
0.10
1.00
10.00
Frequency (GHz)
Figure 5. Differential Crosstalk vs Frequency
5
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TS2PCIE2212
PCI Express™ SIGNAL SWITCH
www.ti.com
SCDS209–JUNE 2006
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
V
DD
Input Generator
V
IN
CTRL
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
2 × V
DD
Input Generator
50 Ω
S1
Open
R
L
V
I
V
O
SA
GND
V
G2
C
L
R
L
(see Note A)
S1
2 × V
V
I
C
V
∆
R
V
TEST
L
L
CC
t
/t
1.8 V ± 0.1 V
1.8 V ± 0.1 V
100 Ω
100 Ω
GND
No Load
No Load
0.3 V
0.3 V
PLZ PZL
DD
t
/t
GND
V
DD
PHZ PZH
Output Control
V
DD
(V
IN
)
V /2
DD
V /2
DD
Output
0 V
Waveform 1
t
t
PLZ
PZL
S1 at 2 y V
DD
V
V
OH
(see Note B)
V
/2
DD
V
V
+ 0.3 V
OL
OL
t
t
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
− 0.3 V
OH
V
DD
/2
OL
(see Note B)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
t
t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PHZ
PZH
are the same as t
en
Figure 6. Test Circuit and Voltage Waveforms
6
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TS2PCIE2212
PCI Express™ SIGNAL SWITCH
www.ti.com
SCDS209–JUNE 2006
PARAMETER MEASUREMENT INFORMATION
V
DD
TS2PCIE2212
A1
V
(1)
DD
T1
CTRL0
GND
Sx:nP
Dx:nP
Input
Generator
V
V
100 Ω
I
O
Sx:nN Dx:nN
(1)
TEST PATH
T1
SA:n = DA:n, SB:n = DB:n
GND
SA:n = DB:n, DA:n = open
V
DD
(1) T1 is an external terminal.
V
+ 400 mV
− 400 mV
COM
Input
Waveform
V
COM
V
COM
V
COM
OH
t
t
PLH
PHL
V
Output
Waveform
V
CRS
V
CRS
V
OL
V
V
= 1.5 V
COM
is the cross point of the differential signal.
– t
CRS
t
= |t
|
PHLn
sk
PLHn
Figure 7. Test Circuit for Propagation Delay and Intra-Pair Skew
7
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TS2PCIE2212
PCI Express™ SIGNAL SWITCH
www.ti.com
SCDS209–JUNE 2006
PARAMETER MEASUREMENT INFORMATION (continued)
V
DD
TS2PCIE2212
A1
V
DD
CTRL0
GND
SA:nP
SA:nN
DA:nP
DA:nN
50 Ω
50 Ω
Network
Analyzer
SB:nP
SB:nN
DB:nP
DB:nN
50 Ω
50 Ω
VNA
MEASUREMENT
TEST
Differential insertion loss
Differential return loss
S
21
S
S
11
Common-mode insertion loss
21
Figure 8. Differential Insertion Loss, Differential Return Loss,
and Common-Mode Insertion Loss Test Circuit
8
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TS2PCIE2212
PCI Express™ SIGNAL SWITCH
www.ti.com
SCDS209–JUNE 2006
PARAMETER MEASUREMENT INFORMATION (continued)
V
DD
TS2PCIE2212
A1
V
DD
(1)
T1
CTRL0
GND
TxSA:0P
TxSA:0N
TxDA:0P
TxDA:0N
A6
B6
A4
B4
50 Ω
50 Ω
Network
Analyzer
TxSB:0P
TxSB:0N
TxDB:0P
TxDB:0N
A2
B3
A8
B7
50 Ω
50 Ω
(1)
TEST
T1
Differential crosstalk
GND
Differential OFF isolation
V
DD
(1) T1 is an external terminal.
Figure 9. Differential Crosstalk and OFF Isolation Test Circuit
9
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Nov-2008
PACKAGING INFORMATION
Orderable Device
TS2PCIE2212ZAHR
TS2PCIE2212ZAHRG1
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
NFBGA
ZAH
48
3000
Pb-Free
(RoHS)
SNAGCU
Level-3-260C-168 HR
NFBGA
ZAH
48
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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