TS3A5017PW [TI]
14-OHM DUAL SP4T ANALOG SWITCH 3.3-V/2.5-V DUAL 4:1 ANALOG MULTIPLEXER/DEMULTIPLEXER; 14欧姆双SP4T模拟开关3.3 -V / 2.5 V双4 ： 1模拟复用器/解复用器
| 型号： | TS3A5017PW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 14-OHM DUAL SP4T ANALOG SWITCH 3.3-V/2.5-V DUAL 4:1 ANALOG MULTIPLEXER/DEMULTIPLEXER |
| 文件： | 总20页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCDS188 – JANUARY 2005
Description
Features
D
D
D
D
D
D
D
Isolation in the Powered-Down Mode, V = 0
+
The TS3A5017 is a dual single-pole quadruple-throw
(4:1) analog switch that is designed to operate from
2.3 V to 3.6 V. This device can handle both digital and
Low ON-State Resistance (10 W)
Low Charge Injection
analog signals, and signals up to V can be transmitted
+
Excellent ON-State Resistance Matching
Low Total Harmonic Distortion (THD)
2.3-V to 3.6-V Single-Supply Operation
in either direction.
Applications
D
D
D
D
Sample-and-Hold Circuit
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Battery-Powered Equipment
Audio and Video Signal Routing
Communication Circuits
D
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
SOIC, SSOP, TSSOP, OR TVSOP PACKAGE
(TOP VIEW)
Summary of Characteristics
Logic
Control
Logic
Control
V = 3.3 V, T = 25°C
1
2
3
4
5
6
+
A
1EN
IN2
16
15
14
13
12
11
V
+
2EN
IN1
Dual Analog
MUX/DEMUX
(4:1 MUX/DEMUX)
1S
4
Configuration
2S
4
1S
3
Number of channels
2
11 Ω
1S
2
1S
1
2S
3
ON-state resistance (r
)
on
2S
2S
2
ON-state resistance match (∆r
)
on
1 Ω
10
9
7
8
1D
1
ON-state resistance flatness (r
)
7 Ω
on(flat)
2D
GND
Turn-on/turn-off time (t /t
)
5 ns/1.5 ns
5 pC
ON OFF
Charge injection (Q )
C
FUNCTION TABLE
Bandwidth (BW)
165 MHz
−48 dB at 10 MHz
−49 dB at 10 MHz
0.21%
D TO S
S TO D
EN
IN2
IN1
OFF isolation (O
ISO
)
Crosstalk (X
)
TALK
L
L
L
L
H
L
L
L
H
L
D = S
D = S
D = S
D = S
OFF
1
2
3
4
Total harmonic distortion (THD)
Leakage current (I /I
)
0.1 µA
D(OFF) S(OFF)
H
H
X
Power-supply current (I )
+
2.5 µA
H
X
Package option
16-pin SOIC, SSOP,
TSSOP, or TVSOP
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢍꢝ ꢏ ꢊꢋ ꢓ ꢀꢒ ꢏ ꢎ ꢊ ꢃꢀꢃ ꢞꢟ ꢠꢡ ꢢ ꢣꢤ ꢥꢞꢡꢟ ꢞꢦ ꢧꢨ ꢢ ꢢ ꢩꢟꢥ ꢤꢦ ꢡꢠ ꢪꢨꢫ ꢬꢞꢧ ꢤꢥꢞ ꢡꢟ ꢭꢤ ꢥꢩꢕ ꢍꢢ ꢡꢭꢨ ꢧꢥꢦ
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ꢍꢢ ꢡ ꢭꢨꢧ ꢥ ꢞꢡ ꢟ ꢪꢢ ꢡ ꢧ ꢩ ꢦ ꢦ ꢞꢟ ꢲ ꢭꢡ ꢩ ꢦ ꢟꢡꢥ ꢟꢩ ꢧꢩ ꢦꢦ ꢤꢢ ꢞꢬ ꢱ ꢞꢟꢧ ꢬꢨꢭ ꢩ ꢥꢩ ꢦꢥꢞ ꢟꢲ ꢡꢠ ꢤꢬ ꢬ ꢪꢤ ꢢ ꢤꢣ ꢩꢥꢩ ꢢ ꢦꢕ
Copyright 2005, Texas Instruments Incorporated
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www.ti.com
SCDS188 – JANUARY 2005
ORDERING INFORMATION
(1)
T
PACKAGE
ORDERABLE PART NUMBER
TS3A5017RGYR
TS3A5017D
TOP-SIDE MARKING
A
QFN − RGY
SOIC − D
Tape and reel
Tube
YA017
TS3A5017
YA017
Tape and reel
Tape and reel
Tube
TS3A5017DR
SSOP (QSOP) − DBQ
TSSOP − PW
TS3A5017DBQR
TS3A5017PW
−40°C to 85°C
YA017
Tape and reel
Tape and reel
TS3A5017PWR
TVSOP − DGV
TS3A5017DGVR
YA017
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
(1)(2)
Absolute Minimum and Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
−0.5
−0.5
−50
MAX
4.6
UNIT
V
(3)
V
Supply voltage range
+
(3)(4)
Analog voltage range
V , V
S
4.6
V
D
I
K
Analog port diode current
On-state switch current
Digital input voltage range
Digital input clamp current
V , V < 0
mA
mA
V
S
D
I , I
S
V , V = 0 to 7 V
−128
−0.5
−50
128
4.6
D
S
D
(3)(4)
V
I
IK
+
I
I
I
V < 0
I
mA
mA
mA
Continuous current through V
100
+
Continuous current through GND
−100
GND
D package
73
82
DB package
DGV package
DW package
(5)
θ
Package thermal impedance
°C/W
°C
JA
120
108
150
T
stg
Storage temperature range
−65
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified
is not implied.
(2)
(3)
(4)
(5)
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
All voltages are with respect to ground, unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
2
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ꢆ ꢈ ꢉW ꢊꢋꢃ ꢌ ꢁꢍ ꢈ ꢀ ꢃꢎꢃ ꢌꢏ ꢐ ꢁ ꢑꢒ ꢀꢓ ꢔ
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SCDS188 – JANUARY 2005
(1)
Electrical Characteristics for 3.3-V Supply
V
+
= 3 V to 3.6 V, T = −40°C to 85°C (unless otherwise noted)
A
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
SYMBOL
T
A
V
+
TYP
Analog Switch
Analog signal
range
V , V
0
V
+
V
D
S
25°C
11
1
12
14
ON-state
resistance
0 ≤ V ≤ V ,
Switch ON,
See Figure 13
S
+
r
3 V
3 V
Ω
on
I
D
= −32 mA,
Full
ON-state
resistance match
between
25°C
2
3
V
I
= 2.1 V,
= −32 mA,
Switch ON,
See Figure 13
S
D
∆r
on
Ω
Ω
Full
channels
ON-state
resistance
flatness
25°C
Full
7
9
10
0 ≤ V ≤ V ,
Switch ON,
See Figure 13
S
+
r
3 V
on(flat)
I
D
= −32 mA,
V
V
= 1 V, V = 3 V,
D
25°C
Full
−0.1
−0.2
0.05
0.1
0.2
S
Switch OFF,
See Figure 14
or
I
3.6 V
0 V
S(OFF)
S
= 3 V, V = 1 V,
S
D
OFF leakage
current
µA
µA
25°C
−1
−5
0.5
1
5
V
S
V
D
= 0 to 3.6 V,
= 3.6 V to 0,
Switch OFF,
See Figure 14
I
SPWR(OFF)
Full
V
D
V
D
= 1 V, V = 3 V,
S
25°C
−0.1
−0.2
0.05
0.1
0.2
Switch OFF,
See Figure 14
or
I
3.6 V
0 V
D(OFF)
D
Full
= 3 V, V = 3 V,
S
OFF leakage
current
25°C
−1
−5
0.5
1
5
V
D
V
S
= 0 to 3.6 V,
= 3.6 V to 0,
Switch OFF,
See Figure 14
I
DPWR(OFF)
Full
S
V
= 1 V, V = Open,
D
25°C
Full
−0.1
−0.2
−0.1
−0.2
0.05
0.1
0.2
0.1
0.2
S
Switch ON,
See Figure 15
ON leakage
current
or
I
3.6 V
µA
µA
S(ON)
V
= 3 V, V = Open,
S
D
D
D
V
= 1 V, V = Open,
S
25°C
Full
0.05
Switch ON,
See Figure 15
ON leakage
current
or
I
3.6 V
D(ON)
V
D
= 3 V, V = Open,
S
(2)
Digital Control Inputs (IN1, IN2, EN)
Input logic high
Input logic low
V
Full
Full
2
0
5.5
0.8
1
V
V
IH
V
IL
25°C
Full
−1
−1
0.05
Input leakage
current
I
, I
IH IL
V = 5.5 V or 0
I
3.6 V
µA
1
(1)
(2)
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
All unused digital inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application report, Implications
+
of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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www.ti.com
SCDS188 – JANUARY 2005
(1)
Electrical Characteristics for 3.3-V Supply (continued)
V
+
= 3 V to 3.6 V, T = −40°C to 85°C (unless otherwise noted)
A
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
SYMBOL
T
V
TYP
5
A
+
Dynamic
25°C
Full
3.3 V
1
1
9.5
V
R
= 2 V,
= 300 Ω,
C = 35 pF,
L
D
L
Turn-on time
t
ns
ON
See Figure 17
C = 35 pF,
L
3 V to 3.6 V
3.3 V
10.5
25°C
Full
0.5
0.5
1.5
3.5
V
R
= 2 V,
= 300 Ω,
D
Turn-off time
t
ns
OFF
See Figure 17
3 V to 3.6 V
4.5
L
V
C
= 0, R
= 0.1 nF,
= 0
GEN
L
GEN
Charge injection
Q
See Figure 22
25°C
25°C
25°C
25°C
3.3 V
3.3 V
3.3 V
3.3 V
5
19
pC
pF
pF
pF
C
S
V
S
= V or GND,
+
C
C
See Figure 16
See Figure 16
See Figure 16
S(OFF)
D(OFF)
OFF capacitance
Switch OFF,
D
V = V or GND,
D +
Switch OFF,
4.5
25
OFF capacitance
S
V
S
= V or GND,
+
C
S(ON)
D(ON)
ON capacitance
Switch ON,
D
V
D
= V or GND,
+
C
See Figure 16
See Figure 16
See Figure 18
25°C
25°C
25°C
25°C
25°C
25°C
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
25
2
pF
pF
ON capacitance
Switch ON,
Digital input
capacitance
C
V = V or GND,
I
I
+
R
= 50 Ω,
L
Bandwidth
OFF isolation
Crosstalk
BW
165
−48
−49
−74
MHz
dB
Switch ON,
R
= 50 Ω,
Switch OFF,
See Figure 19
L
O
ISO
f = 10 MHz,
R
= 50 Ω,
Switch ON,
See Figure 20
L
X
dB
TALK
f = 10 MHz,
Crosstalk
Adjacent
R
= 50 Ω,
Switch ON,
See Figure 21
L
X
dB
TALK(ADJ)
f = 10 MHz,
Total harmonic
distortion
R
C
= 600 Ω,
= 50 pF,
f = 20 Hz to 20 kHz,
See Figure 23
L
L
THD
25°C
3.3 V
0.21
2.5
%
Supply
25°C
7
Positive supply
current
I
+
V = V or GND,
I
Switch ON or OFF
3.6 V
µA
+
Full
10
(1)
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
4
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ꢆ ꢈ ꢉW ꢊꢋꢃ ꢌ ꢁꢍ ꢈ ꢀ ꢃꢎꢃ ꢌꢏ ꢐ ꢁ ꢑꢒ ꢀꢓ ꢔ
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SCDS188 – JANUARY 2005
(1)
Electrical Characteristics for 2.5-V Supply
V
+
= 2.3 V to 2.7 V, T = −40°C to 85°C (unless otherwise noted)
A
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
SYMBOL
T
A
V
+
TYP
Analog Switch
Analog signal
range
V , V
0
V
+
V
D
S
25°C
20.5
1
22
24
ON-state
resistance
0 ≤ V ≤ V ,
Switch ON,
See Figure 13
S
+
r
2.3 V
2.3 V
Ω
on
I
D
= −24 mA,
Full
ON-state
resistance match
between
25°C
2
3
V
I
= 1.6 V,
= −24 mA,
Switch ON,
See Figure 13
S
D
∆r
on
Ω
Ω
Full
channels
ON-state
resistance
flatness
25°C
Full
16
18
20
0 ≤ V ≤ V ,
Switch ON,
See Figure 13
S
+
r
2.3 V
on(flat)
I
D
= −24 mA,
V
V
= 0.5 V, V = 2.2 V,
D
25°C
Full
−0.1
−0.2
0.05
0.1
0.2
S
Switch OFF,
See Figure 14
or
I
2.7 V
0 V
S(OFF)
S
= 2.2 V, V = 0.5 V,
S
D
OFF leakage
current
µA
µA
25°C
−1
−5
0.5
1
5
V
S
V
D
= 0 to 3.6 V,
= 3.6 V to 0,
Switch OFF,
See Figure 14
I
SPWR(OFF)
Full
V
D
V
D
= 0.5 V, V = 2.2 V,
S
25°C
−0.1
−0.2
0.05
0.1
0.2
Switch OFF,
See Figure 14
or
I
2.7 V
0 V
D(OFF)
D
Full
= 2.2 V, V = 0.5 V,
S
OFF leakage
current
25°C
−1
−5
0.5
1
5
V
D
V
S
= 0 to 5.5 V,
= 5.5 V to 0,
Switch OFF,
See Figure 14
I
DPWR(OFF)
Full
S
V
= 0.5 V, V = Open,
D
25°C
Full
−0.1
−0.2
−0.1
−0.2
0.05
0.1
0.2
0.1
0.2
S
Switch ON,
See Figure 15
ON leakage
current
or
I
2.7 V
µA
µA
S(ON)
V
= 2.2 V, V = Open,
S
D
D
D
V
= 0.5 V, V = Open,
S
25°C
Full
0.05
Switch ON,
See Figure 15
ON leakage
current
or
I
2.7 V
D(ON)
V
D
= 2.2 V, V = Open,
S
(2)
Digital Control Inputs (IN1, IN2)
Input logic high
Input logic low
V
Full
Full
1.7
0
5.5
0.7
1
V
V
IH
V
IL
25°C
Full
−1
−1
0.05
Input leakage
current
I
, I
IH IL
V = 5.5 V or 0
I
2.7 V
µA
1
(1)
(2)
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
All unused digital inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application report, Implications
+
of Slow or Floating CMOS Inputs, literature number SCBA004.
5
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆ ꢇ
ꢆꢈ ꢉW ꢊ ꢋ ꢃꢌ ꢁꢍ ꢈ ꢀ ꢃꢎ ꢃꢌ ꢏꢐ ꢁ ꢑꢒ ꢀ ꢓꢔ
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SCDS188 – JANUARY 2005
(1)
Electrical Characteristics for 2.5-V Supply (continued)
V
+
= 2.3 V to 2.7 V, T = −40°C to 85°C (unless otherwise noted)
A
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
SYMBOL
T
V
TYP
5
A
+
Dynamic
25°C
Full
2.5 V
1.5
1
8
V
R
= 1.5 V,
= 300 Ω,
C = 35 pF,
L
D
L
Turn-on time
t
ns
ON
See Figure 17
C = 35 pF,
L
2.3 V to 2.7 V
2.5 V
10
25°C
Full
0.3
0.3
2
4.5
V
R
= 1.5 V,
= 300 Ω,
D
Turn-off time
t
ns
OFF
See Figure 17
2.3 V to 2.7 V
6
L
V
C
= 0, R
= 0.1 nF,
= 0
GEN
L
GEN
Charge injection
Q
See Figure 22
25°C
25°C
25°C
25°C
2.5 V
2.5 V
2.5 V
2.5 V
pC
pF
pF
pF
C
S
V
S
= V or GND,
+
C
C
See Figure 16
See Figure 16
See Figure 16
18.5
45
S(OFF)
D(OFF)
NC(ON)
OFF capacitance
Switch OFF,
D
V = V or GND,
D +
Switch OFF,
OFF capacitance
S
V
S
= V or GND,
+
C
24
ON capacitance
Switch ON,
D
V
= V or GND,
D
+
C
See Figure 16
See Figure 16
See Figure 18
25°C
25°C
25°C
25°C
25°C
25°C
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
3.3 V
24
2
pF
pF
D(ON)
ON capacitance
Switch ON,
Digital input
capacitance
C
I
V = V or GND,
I
+
R
= 50 Ω,
L
Bandwidth
OFF isolation
Crosstalk
BW
165
−48
−49
−74
MHz
dB
Switch ON,
R
= 50 Ω,
Switch OFF,
See Figure 19
L
O
ISO
f = 10 MHz,
R
= 50 Ω,
Switch ON,
See Figure 20
L
X
dB
TALK
f = 10 MHz,
Crosstalk
Adjacent
R
= 50 Ω,
Switch ON,
See Figure 21
L
X
dB
TALK(ADJ)
f = 10 MHz,
Total harmonic
distortion
R
C
= 600 Ω,
= 50 pF,
f = 20 Hz to 20 kHz,
See Figure 23
L
L
THD
25°C
2.5 V
0.29
2.5
%
Supply
25°C
7
Positive supply
current
I
+
V = V or GND,
I
Switch ON or OFF
2.7 V
µA
+
Full
10
(1)
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
6
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SCDS188 – JANUARY 2005
TYPICAL PERFORMANCE
12
10
18
T
A
= 25_C
16
14
12
10
8
855C
255C
V
+
= 2.5 V
8
6
4
2
0
6
V
+
= 3.3 V
4
–405C
2
0
0
1
2
3
4
0.0
0.5
1.0
1.5
V
2.0
(V)
2.5
3.0
3.5
V
COM
(V)
COM
Figure 1. r vs V
Figure 2. r vs V
(V = 3.3 V)
on
COM
on
COM +
18
16
14
12
10
8
40
I
NC(ON)
COM(ON)
I
30
20
10
0
I
NO(ON)
855C
255C
I
COM(OFF)
I
NC(OFF)
6
4
2
I
–405C
NO(OFF)
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
−40
25
(°C)
85
T
A
V
(V)
COM
Figure 4. Leakage Current vs Temperature
(V = 5.5 V)
Figure 3. r vs V
(V = 5 V)
+
on
COM
+
4.5
9
8
7
6
5
4
3
2
1
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
= 3.3 V
= 2.5 V
t
+
ON
V
+
t
OFF
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
2.0
2.5
3.0
(V)
3.5
4.0
V
COM
(V)
V
+
Figure 5. Charge-Injection (Q ) vs V
Figure 6. t
and t
vs Supply Voltage
C
COM
ON
OFF
7
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SCDS188 – JANUARY 2005
TYPICAL PERFORMANCE
5.0
4.5
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
t
ON
V
IH
V
IL
t
OFF
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
−40
25
85
V
(V)
+
T
(5C)
A
Figure 8. Logic-Level Threshold vs V
Figure 7. t
and t
vs Temperature (V = 5 V)
+
ON
OFF
+
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
−2
−4
−6
−8
−10
−12
0.1
0.1
1
10
100
1000
1
10
Frequency (MHz)
100
1000
Frequency (MHz)
Figure 10. OFF Isolation and Crosstalk vs
Figure 9. Bandwidth (Gain vs Frequency)
Frequency (V = 5 V)
+
(V = 5 V)
+
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.25
0.20
0.15
0.10
0.05
0.00
−40
25
85
10
100
1000
10 K
100 K
T
(5C)
A
Frequency (Hz)
Figure 12. Power-Supply Current vs
Figure 11. Total Harmonic Distortion vs
Frequency
Temperature (V = 3.6 V)
+
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SCDS188 – JANUARY 2005
PIN DESCRIPTION
PIN
NUMBER
NAME
DESCRIPTION
1
2
1EN
IN2
Enable (active low)
Digital control pin to connect D to S
Analog I/O
3
1S
4
1S
3
1S
2
1S
1
4
Analog I/O
5
Analog I/O
6
Analog I/O
7
1D
GND
2D
Common
8
Ground
9
Common
10
11
12
13
14
15
16
2S
2S
2S
2S
Analog I/O
1
2
3
4
Analog /O
Analog I/O
Analog I/O
IN1
Digital control pin to connect D to S
Enable (active low)
Power supply
2EN
V
+
9
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SCDS188 – JANUARY 2005
PARAMETER DESCRIPTION
SYMBOL
DESCRIPTION
V
Voltage at D
Voltage at S
D
S
V
r
Resistance between D and S ports when the channel is ON
Difference of r between channels in a specific device
on
∆r
on
on
r
Difference between the maximum and minimum value of r in a channel over the specified range of conditions
on
on(flat)
S(OFF)
I
Leakage current measured at the S port, with the corresponding channel (S to D) in the OFF state
I
Leakage current measured at the S port, under powered down mode, V = 0
+
SPWR(OFF)
I
Leakage current measured at the S port, with the corresponding channel (S to D) in the ON state and the output (D) open
Leakage current measured at the D port, with the corresponding channel (D to S) in the OFF state
S(ON)
I
D(OFF)
I
Leakage current measured at the D port, under powered down mode, V = 0
+
DPWR(OFF)
I
Leakage current measured at the D port, with the corresponding channel (D to S) in the ON state and the output (S) open
Minimum input voltage for logic high for the control input (IN, EN)
Maximum input voltage for logic low for the control input (IN, EN)
Voltage at the control input (IN, EN)
D(ON)
V
IH
IL
I
V
V
I , I
IH IL
Leakage current measured at the control input (IN, EN)
Turn-on time for the switch. This parameter is measured under the specified range of conditions and by the propagation delay
between the digital control (IN) signal and analog output (D or S) signal when the switch is turning ON.
t
ON
Turn-off time for the switch. This parameter is measured under the specified range of conditions and by the propagation delay
between the digital control (IN) signal and analog output (D or S) signal when the switch is turning OFF.
t
OFF
Charge injection is a measurement of unwanted signal coupling from the control (IN) input to the analog (S or D) output. This is
measured in coulomb (C) and measured by the total charge induced due to switching of the control input.
Q
C
Charge injection, Q = C × ∆V , C is the load capacitance, and ∆V is the change in analog output voltage.
C
L
D
L
D
C
C
C
C
C
Capacitance at the S port when the corresponding channel (S to D) is OFF
Capacitance at the S port when the corresponding channel (S to D) is ON
Capacitance at the D port when the corresponding channel (D to S) is OFF
Capacitance at the D port when the corresponding channel (D to S) is ON
Capacitance of control input (IN)
S(OFF)
S(ON)
D(OFF)
D(ON)
I
OFF isolation of the switch is a measurement of OFF-state switch impedance. This is measured in dB in a specific frequency,
with the corresponding channel (S to D) in the OFF state.
O
ISO
Crosstalk is a measurement of unwanted signal coupling from an ON channel to an adjacent ON channel (1S to 2S ). This is
measured in a specific frequency and in dB.
1
1
X
TALK
BW
Bandwidth of the switch. This is the frequency in which the gain of an ON channel is −3 dB below the DC gain.
Total harmonic distortion describes the signal distortion caused by the analog switch. This is defined as the ratio of root mean
square (RMS) value of the second, third, and higher harmonic to the absolute magnitude of the fundamental harmonic.
THD
I
+
Static power-supply current with the control (IN) pin at V or GND
+
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SCDS188 – JANUARY 2005
PARAMETER MEASUREMENT INFORMATION
V
+
V
S1
S
1
D
V
D
+
Channel ON
V
S2-S4 S -S
2
4
VD * VS2*S4 or VS1
r
+
W
on
ID
IN or EN
I
D
V
I
V = V or V
IH IL
I
+
GND
Figure 13. ON-State Resistance (r
)
on
V
+
V
S1
S
1
OFF-State Leakage Current
Channel OFF
D
V
D
+
V
S2-S4
S -S
+
2
4
V = V or V
I
IH
IL
V
S1
or V
and
= 0 to V
S2-S4 +
IN or EN
V
I
V
D
= V to 0
+
+
GND
Figure 14. OFF-State Leakage Current (I
, I
I
)
D(OFF) S(OFF), NO(OFF
V
+
S
1
V
S1
D
ON-State Leakage Current
Channel ON
V
D
+
V
S -S
S2-S4
2
4
V = V or V
I IH IL
IN or EN
V
I
+
GND
Figure 15. ON-State Leakage Current (I
, I
)
D(ON) S(ON)
11
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SCDS188 – JANUARY 2005
V
+
V
S1
S
1
Capacitance
Meter
V
= V or GND
+
BIAS
V
S2-S4
S -S
2
4
V = V or V
I
IH IL
V
D
D
Capacitance is measured at S1,
S2-S4, D, and IN inputs during
ON and OFF conditions.
V
BIAS
V
I
IN or EN
GND
Figure 16. Capacitance (C , C
, C
, C
, C
)
I
D(OFF) D(ON) S(OFF) S(ON)
V
+
TEST
R
L
C
L
V
S1
S
1
t
300 Ω
300 Ω
35 pF
35 pF
ON
D
(3)
V
D
(2)
C
L
R
L
t
S -S
2
OFF
4
V
I
V
0
Logic
Input
(V )
I
+
50%
50%
IN or EN
(2)
C
Logic
(1)
L
GND
Input
t
t
ON
OFF
Switch
Output
90%
90%
(V
S1
)
(1)
(2)
(3)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t < 5 ns, t < 5 ns.
O
r
f
C
includes probe and jig capacitance.
L
See Electrical Characteristics for V .
D
Figure 17. Turn-On (t ) and Turn-Off Time (t
)
ON
OFF
V
+
Network Analyzer
50 W
V
S1
S
1
Channel ON: S to D
1
V
D
V = V or GND
D
I
+
S -S
Source
Signal
2
4
Network Analyzer Setup
IN or EN
V
I
Source Power = 0 dBm
50 W
(632-mV P-P at 50-W load)
+
GND
DC Bias = 350 mV
Figure 18. Bandwidth (BW)
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ꢎ
ꢃ
ꢌꢏ
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ꢚ
ꢋ
ꢌꢀ
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SCDS188 – JANUARY 2005
V
+
Network Analyzer
50 W
Channel OFF: S to D
V = V or GND
V
S1
S
1
I
+
V
D
D
Source
Signal
50 W
S -S
2
4
Network Analyzer Setup
IN or EN
Source Power = 0 dBm
(632-mV P-P at 50-W load)
V
I
50 W
+
GND
DC Bias = 350 mV
Figure 19. OFF Isolation (O
)
ISO
V
+
Network Analyzer
Channel ON: S to D
1
50 W
V
V
Channel OFF: S -S to D
S
S1
2
4
1
V
D
V = V or GND
I
+
Source
Signal
S -S
2
S2-S4
4
Network Analyzer Setup
IN or EN
50 W
V
+
I
50 W
Source Power = 0 dBm
(632-mV P-P at 50-W load)
GND
DC Bias = 350 mV
Figure 20. Crosstalk (X
)
TALK
V
+
Network Analyzer
50 W
V
1S
1
1S
Channel ON: S to D
1
1D
2D
Source
Signal
2S
1
V
2S
Network Analyzer Setup
50 W
IN or EN
Source Power = 0 dBm
(632 mV P-P at 50 W load)
V
I
50 W
+
DC Bias = 350 mV
GND
Figure 21. Adjacent Crosstalk
13
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ꢈ
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ꢎ
ꢃ
ꢌ
ꢏꢐ
ꢚ
ꢋ
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ꢒ
ꢍ
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ꢛ
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SCDS188 – JANUARY 2005
V
IH
V
+
Logic
Input
OFF
ON
OFF
V
(V
I)
IL
R
GEN
S
1
D
V
D
+
V
D
∆V
D
V
GEN
S -S
2
4
(1)
C
L
IN or EN
V
= 0 to V
= 0
= 0.1 nF
GEN
+
V
I
R
C
GEN
L
Logic
(2)
GND
Q
= C × ∆V
D
C
L
Input
V = V or V
I
IH IL
(1)
(2)
C
includes probe and jig capacitance.
L
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t < 5 ns, t < 5 ns.
O
r
f
Figure 22. Charge Injection (Q )
C
V = V or V
IH
Channel ON: D to S
= V P-P
I
IL
V
f
= 20 Hz to 20 kHz
SOURCE
+
SOURCE
V /2
+
V
+
Audio Analyzer
R
L
10 mF
S
1
10 mF
Source
Signal
D
(1)
C
L
600 W
S -S
2
4
600 W
IN or EN
V
I
+
GND
600 W
(1)
C
L
includes probe and jig capacitance.
Figure 23. Total Harmonic Distortion (THD)
14
PACKAGE OPTION ADDENDUM
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30-Aug-2005
PACKAGING INFORMATION
Orderable Device
TS3A5017D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TS3A5017DBQR
TS3A5017DBQRE4
TS3A5017DE4
SSOP/
QSOP
DBQ
DBQ
D
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
SOIC
TVSOP
TVSOP
SOIC
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TS3A5017DGVR
TS3A5017DGVRE4
TS3A5017DR
DGV
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TS3A5017DRE4
TS3A5017PW
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TS3A5017PWE4
TS3A5017PWR
TS3A5017PWRE4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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