TS5USBC400YFPT [TI]
具有 16V 过压保护功能的双路 2:1 USB 2.0 多路复用器/多路信号分离器或单端交叉点开关 | YFP | 12 | 0 to 70;
| 型号： | TS5USBC400YFPT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 16V 过压保护功能的双路 2:1 USB 2.0 多路复用器/多路信号分离器或单端交叉点开关 | YFP | 12 | 0 to 70 开关 输出元件 复用器 |
| 文件： | 总30页 (文件大小：1279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TS5USBC400
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
具有 16-V 过压保护功能的TS5USBC400双路 2:1 USB 2.0 多路复用器/多
路信号分离器
1 特性
3 说明
1
•
•
•
•
•
•
•
•
•
•
电源范围：2.3V 至 5.5V
TS5USBC400 是一种双向低功耗双端口高速 USB 2.0
模拟开关，具有针对 USB Type-C™系统的集成保护功
能。该器件配置为双路 2:1 或 1:2 开关，并经过了优
化，能够应对 USB Type-C™ 系统中的 USB 2.0 D+/-
线路。
差分 2:1 或 1:2 开关/多路复用器
公共引脚上具有 0V 至 16V 过压保护 (OVP)
VCC = 0V 时具有断电保护
较低的 RON（最大值为 9Ω）
典型带宽为 1.1GHz
TS5USBC400 在 I/O 引脚上的保护功能可承受高达
16V 的电压，并配备自动关闭电路来保护开关后面的
系统组件。
典型的 CON 为 4.5pF
低功耗禁用模式
1.8V 兼容型逻辑输入
TS5USBC400 采用小型 12 引脚 DSBGA 封装，使其
成为移动应用和空间受限型 应用中的杂音问题。中对
于高效率、高电源密度和稳健性的需求。
ESD 保护性能超出 JESD 22 标准
–
2000V 人体模型 (HBM)
•
•
•
TS5USBC400：标准温度范围为
0°C 至 70°C
器件信息(1)
TS5USBC400I：工业温度范围为
-40°C 至 85°C
器件型号
封装
封装尺寸（标称值）
TS5USBC400
TS5USBC400I
DSBGA (12)
1.582mm × 1.182mm
小型 DSBGA 封装
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
2 应用
•
•
•
•
移动设备
台式机/笔记本电脑
平板电脑
使用 USB Type-C™ 或 Micro-B 连接器的任何场合
简化电路原理图
USB
Connector
TS5USBC400
UART
USB
D1+
VCC
OVP
D2+
D1-
D2-
SEL1
USB
SEL2
Logic
Control
OE
FLT
GND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SCDS374
TS5USBC400
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
目录
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 16
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application .................................................. 17
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Dynamic Characteristics ........................................... 7
6.7 Timing Requirements................................................ 7
6.8 Typical Characteristics.............................................. 8
Parameter Measurement Information .................. 9
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
9
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 20
12 器件和文档支持 ..................................................... 21
12.1 文档支持................................................................ 21
12.2 社区资源................................................................ 21
12.3 商标....................................................................... 21
12.4 静电放电警告......................................................... 21
12.5 Glossary................................................................ 21
13 机械、封装和可订购信息....................................... 22
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (September 2017) to Revision A
Page
•
Added ICC Active supply current and Supply current during OVP condition to the Electrical Specification table .................. 4
2
Copyright © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com.cn
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
5 Pin Configuration and Functions
YFP Package
12-Pin DSBGA
Top View
1
2
3
4
A
SEL1
VCC
D2+
D+
D-
FLT
SEL2
D2-
GND
D1+
OE
B
C
D1-
Pin Functions
PIN
I/O
DESCRIPTION
NAME
SEL1
D+
NO.
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
C4
I
I/O
I/O
O
Switch select1 (Active high)
Data switch input (Differential +)
Data switch input (Differential –)
D–
FLT
VCC
SEL2
GND
OE
Fault indicator output pin (Active low) - open drain
Supply Voltage
PWR
I
Switch select2 (Active high)
Ground
GND
I
Output enable (Active low)
D2+
D2–
D1+
D1–
I/O
I/O
I/O
I/O
Data switch output 2 (Differential +)
Data switch output 2 (Differential -)
Data switch output 1 (Differential +)
Data switch output 1 (Differential -)
Copyright © 2017, Texas Instruments Incorporated
3
TS5USBC400
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
(2)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
UNIT
VCC
VI/O
VI/O
VI
Supply voltage(3)
6
18
6
V
V
V
V
V
Input/Output DC voltage (D+, D-)(3)
Input/Output DC voltage (D1+/D1-, D2+/D2-)
Digital input voltage (SEL1, SEL2, OE)
Digital output voltage (FLT)
(3)
6
VO
6
Input-output port diode current (D+, D-,
D1+, D1-, D2+, D2-)
IK
VIN < 0
VI < 0
–50
–50
mA
mA
Digital logic input clamp current (SEL1,
IIK
(3)
SEL2, OE)
ICC
Continuous current through VCC
Continuous current through GND
Storage temperature
100
150
mA
mA
°C
IGND
Tstg
–100
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
5.5
18
UNIT
VCC
Supply voltage
2.3
0
V
V
VI/O (D+, D-)
Analog input/output voltage
VI/O (D1, D1-, D2+, D2-)
0
3.6
5.5
5.5
50
V
VI
Digital input voltage (SEL1, SEL2, OE)
Digital output voltage (FLT)
0
V
VO
0
V
II/O (D+, D-, D1+, D1-, D2+, D2-)
Analog input/output port continuous current
Digital output current
-50
mA
mA
ºC
ºC
ºC
IOL
TA
TA
TJ
3
Operating free-air temperature (TS5USBC400) Standard
Operating free-air temperature (TS5USBC400I) Industrial
Junction temperature
0
–40
–40
70
85
125
4
Copyright © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com.cn
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
6.4 Thermal Information
TS5USBC400
(1)
THERMAL METRIC
YFP
12 PINS
91.8
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
°C/W
0.8
22.8
0.5
ψJB
Junction-to-board characterization parameter
23.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard), VCC = 2.3 V to 5.5 V, GND = 0V, Typical values are at VCC
=
3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY
VCC
Power supply voltage
Active supply current
2.3
5.5
V
OE = 0 V
SEL1, SEL2 = 0 V, 1.8 V or VCC
0 V < VI/O < 3.6 V
72
80
100
µA
ICC
OE = 0 V
Supply current during OVP condition SEL1, SEL2 = 0 V, 1.8 V or VCC
VI/O > VPOS_THLD
120
10
µA
µA
OE = 1.8 V or VCC
Standby powered down supply
SEL1 = 0 V, 1.8 V, or VCC
ICC_PD
2.2
current
SEL2 = 0 V, 1.8 V, or VCC
DC Characteristics
VI/O = 0.4 V
RON
ON-state resistance
ISINK = 8 mA
Refer to ON-State Resistance Figure
5.6
0.07
0.07
9
0.3
0.4
Ω
Ω
Ω
VI/O = 0.4 V
ISINK = 8 mA
Refer to ON-State Resistance Figure
ON-state resistance match between
channels
ΔRON
VI/O = 0 V to 0.4 V
ISINK = 8 mA
Refer to ON-State Resistance Figure
RON (FLAT)
ON-state resistance flatness
I/O pin OFF leakage current
ON leakage current
VD± = 0 V or 3.6 V
VCC = 2.3 V to 5.5 V
VD1±or VD2+/- = 3.6 V or 0 V
Refer to Off Leakage Figure
-1
-1
1.2
6
µA
IOFF
VD± = 0 V or 16 V
VCC = 2.3 V to 5.5 V
VD1± or VD2+/- = 0 V
165
1.2
200
6
µA
µA
Refer to Off Leakage Figure
VD± = 0 V or 3.6 V
VD1± and VD2+/- = high-Z
Refer to On Leakage Figure
ION
-1
Digital Characteristics
VIH
VIL
Input logic high
SEL1, SEL2, OE
SEL1, SEL2, OE
1.4
V
V
Input logic low
0.5
0.4
FLT
IOL = 3 mA
VOL
Output logic low
V
IIH
IIL
Input high leakage current
Input low leakage current
SEL1, SEL2, OE = 1.8 V, VCC
SEL1, SEL2, OE = 0 V
-1
-1
1
5
5
μA
μA
±0.2
Copyright © 2017, Texas Instruments Incorporated
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TS5USBC400
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
Electrical Characteristics (continued)
TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard), VCC = 2.3 V to 5.5 V, GND = 0V, Typical values are at VCC
=
3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Internal pull-down resistor on digital
input pins
RPD
CI
6
MΩ
SEL1, SEL2 = 0 V, 1.8 V or VCC
f = 1 MHz
Digital input capacitance
3.4
pF
Protection
VOVP_TH
OVP positive threshold
4.5
75
4.8
5.2
V
VOVP_HYST
OVP threshold hysteresis
230
425
mV
VD± = 0 to 18 V
tRISE and tFALL(10% to 90 %) = 100 ns
RL = Open
Switch on or off
0
0
9.6
9.0
V
V
OE = 0 V
Maximum voltage to appear on D1±
and D2± pins during OVP scenario
VCLAMP_V
VD± = 0 to 18 V
tRISE and tFALL(10% to 90 %) = 100 ns
RL = 50Ω
Switch on or off
OE = 0 V
RPU = 10 kΩ to VCC (FLT)
CL = 35 pF
Refer to OVP Timing Diagram Figure
tEN_OVP
OVP enable time
0.6
1.5
3
5
μs
μs
RPU = 10 kΩ to VCC (FLT)
CL = 35 pF
tREC_OVP
OVP recovery time
Refer to OVP Timing Diagram Figure
6
Copyright © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com.cn
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
6.6 Dynamic Characteristics
TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard), VCC = 2.3 V to 5.5V, GND = 0V, Typical values are at VCC
=
3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VD+/- = 0 or 3.3 V,
MIN
TYP
MAX UNIT
OE = VCC
D+, D- off capacitance
Switch OFF
1.2
3.5
6.2
pF
f = 240 MHz
COFF
VD+/- = 0 or 3.3 V,
OE = VCC or OE = 0V with SEL1,
SEL2 (switch not selected)
f = 240 MHz
D1+, D1-, D2+, D2- off
capacitance
Switch OFF or
not selected
1.2
1.4
3.5
4.5
-90
6.2
6.2
pF
pF
dB
VD+/- = 0 or 3.3 V,
f = 240 MHz
CON
IO pins ON capacitance
Switch ON
RL = 50 Ω
CL = 5 pF
f = 100 kHz
Switch OFF
Refer to Off Isolation Figure
OISO
Differential off isolation
RL = 50 Ω
CL = 5 pF
f = 240 MHz
Switch OFF
-22
dB
Refer to Off Isolation Figure
RL = 50 Ω
CL = 5 pF
f = 100 kHz
Refer to Crosstalk Figure
XTALK
BW
Channel to Channel crosstalk
Bandwidth
Switch ON
Switch ON
-90
1.1
dB
RL = 50 Ω; Refer to BW and
GHz
Insertion Loss Figure
RL = 50 Ω
ILOSS
Insertion loss
Switch ON
-0.7
dB
f = 240 MHz; Refer to BW and
Insertion Loss Figure
6.7 Timing Requirements
TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard), VCC = 2.3 V to 5.5V, GND = 0V, Typical values are at VCC
=
3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN NOM
MAX UNIT
VD+/- = 0.8 V
Refer to Tswitch Timing Figure
Switching time between channels
(SEL1, SEL2 to output)
tswitch
ton
0.45
1.2
250
1
µs
µs
µs
RL = 50 Ω,
CL = 5 pF,
VCC = 2.3 V to 5.5 V
VD+/- = 0.8 V
Refer to Ton and Toff Figure
Device turn on time (OE to output)
Device turn off time (OE to output)
100
VD+/- = 0.8 V
Refer to Ton and Toff Figure
toff
0.35
RL = 50 Ω,
CL = 1 pF,
VCC = 2.3 V to 5.5 V
VD+/- = 0.4 V
Refer to Tsk Figure
Skew of opposite transitions of
same output (between D+ and D-)
tSK(P)
9
50
ps
ps
RL = 50 Ω,
CL = 5 pF,
VCC = 2.3 V to 5.5 V
VD+/- = 0.4 V
Refer to Tpd Figure
tpd
Propagation delay
130
180
版权 © 2017, Texas Instruments Incorporated
7
TS5USBC400
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
6.8 Typical Characteristics
8
7.5
7
6.5
6
5.5
5
4.5
4
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
VIN, Input Voltage (V)
D001
VCC = 3.3 V
TA = 25°C
图 1. ON-Resistance vs Input Voltage
8
版权 © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com.cn
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
7 Parameter Measurement Information
V
VD+/-
ISINK
Switch
Channel ON, RON = V/ISINK
图 2. ON-State Resistance (RON
)
VDX+/-
VD+/-
A
A
Switch
图 3. Off Leakage
VD+/-
A
Switch
图 4. On Leakage
VD1+/-
VD2+/-
VD+/-
SEL
CL
RL
RL
CL
VSEL
1.8 V
0 V
1.8 V
0 V
0.8 V
1.2 V
1.2 V
0.8 V
VSEL
tSWITCH
VD1+/-
VSEL
tSWITCH
VD2+/-
tSWITCH
tSWITCH
VD+/-
VD+/-
0 V
80 %
80 %
20 %
20 %
0 V
Copyright © 2017, Texas Instruments Incorporated
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2) CL includes probe and jig capacitance.
图 5. tSWITCH Timing
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TS5USBC400
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
Parameter Measurement Information (接下页)
2.3 V
VCC
VD+/-
1.8 V
0 V
VOE
0.8 V
1.2 V
CL
RL
OE
tON
tOFF
10 %
VD+/-
0 V
90 %
VDX+/-
VOE
Copyright © 2017, Texas Instruments Incorporated
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2) CL includes probe and jig capacitance.
图 6. tON, tOFF for OE
Network Analyzer
Switch
50 O
D+
D-
50 O
Source
Signal
50 O
50 O
Source
Signal
50 O
50 O
Copyright © 2017, Texas Instruments Incorporated
图 7. Off Isolation
Network Analyzer
50 ꢀ
Switch
D+
D-
50 ꢀ
Source
Signal
50 ꢀ
50 ꢀ
50 ꢀ
50 ꢀ
Copyright © 2017, Texas Instruments Incorporated
图 8. Cross Talk
10
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TS5USBC400
www.ti.com.cn
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
Parameter Measurement Information (接下页)
Network Analyzer
Switch
50 ꢀ
D+
50 ꢀ
Source
Signal
50 ꢀ
D-
50 ꢀ
Source
Signal
50 ꢀ
50 ꢀ
Copyright © 2017, Texas Instruments Incorporated
图 9. BW and Insertion Loss
18 V
0 V
VD+/-
OE
VPOS_THLD
VD+/-
CL
RL
tEN_OVP
FLT
tREC_OVP
VOE
VCC
0 V
10 %
10 %
Copyright © 2017, Texas Instruments Incorporated
图 10. tEN_OVP and tDIS_OVP Timing Diagram
Switch
D+/-
50 ꢀ
0.4 V
0 V
VD+/-
50 %
50 %
50 ꢀ
tPD
50 %
tPD
0.4 V
0 V
VDX+/-
50 %
Copyright © 2017, Texas Instruments Incorporated
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2) CL includes probe and jig capacitance.
图 11. tPD
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ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
Parameter Measurement Information (接下页)
Switch
0.4 V
D+
D-
50 O
50 O
VD+/-
VDX+
VDX-
0 V
50 O
50 O
0.4 V
50 %
50 %
0 V
0.4 V
0 V
tSK
tSK
50 %
50 %
Copyright © 2017, Texas Instruments Incorporated
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2) CL includes probe and jig capacitance.
图 12. tSK
12
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TS5USBC400
www.ti.com.cn
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
8 Detailed Description
8.1 Overview
The TS5USBC400 is a bidirectional low-power dual port, high-speed, USB 2.0 analog switch with integrated
protection for USB Type-C systems. The device is configured as a dual 2:1 or 1:2 switch and is optimized for
handling the USB 2.0 D+/- lines in a USB Type-C system as shown in 图 13.
图 13. USB Type-C Connector Pinout
The TS5USBC400 also works in traditional USB systems that need protection from fault conditions such as
automotive and applications that require higher voltage charging. The device maintains excellent signal integrity
through the optimization of both RON and BW while protecting the system with 0 V to 16 V OVP protection. The
OVP implementation is designed to protect sensitive system components behind the switch that cannot survive a
fault condition where VBUS is shorted the D+ and D- pins on the connector.
8.2 Functional Block Diagram
VCC
SEL1
6 Mꢀ
SEL2
Control
Logic
FLT
6 Mꢀ
OE
6 Mꢀ
VOVP
OVP
D1+
D+
D1-
D2+
D-
D2-
Switches
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8.3 Feature Description
8.3.1 Powered-off Protection
When the TS5USBC400 is powered off the I/Os of the device remain in a high-Z state. The crosstalk, off-
isolation, and leakage remain within the Electrical Specifications.
This prevents errant voltages from reaching the rest of the system and maintains isolation when the system is
powering up.
8.3.2 Overvoltage Protection
The OVP of the TS5USBC400 is designed to protect the system from D+/- shorts to VBUS at the USB and USB
Type-C connector. 图 14 depicts a moisture short that would cause 16 V to appear on an existing USB solution
that could pass through the device and damage components behind the device.
VBUS
SBU2
D-
VBUS
CC1
D+
UART
USB
Existing Solutions
D+
D1+
D2+
D1-
D-
D
D-
D2-
CC
SBU1
VBUS
USB
16 V
VBU
Copyright © 2017, Texas Instruments Incorporated
图 14. Existing Solution Being Damaged by a Short, 16 V
The TS5USBC400 will open the switches and protect the rest of the system by blocking the 16 V as depicted in .
14
版权 © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com.cn
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
Feature Description (接下页)
16 V doesn‘t reach
rest of system
VBUS
SBU2
D-
VBUS
UART
USB
CC1
D+
D1+
D+
D-
D2+
D1-
D
D-
D2-
CC
SBU1
VBUS
USB
16 V
VBU
Copyright © 2017, Texas Instruments Incorporated
图 15. Protecting During a 16-V Short
图 16 is a waveform showing the voltage on the pins during an over-voltage scenario.
16 V
VOVP_THLD
D+/-
0 V
D1/D2
0 V
FLT
图 16. Overvoltage Protection Waveform, 16 V
版权 © 2017, Texas Instruments Incorporated
15
TS5USBC400
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
8.4 Device Functional Modes
8.4.1 Pin Functions
表 1. Function Table
OE
H
L
SEL1
SEL2
D- Connection
High-Z
D+ Connection
X
L
X
L
High-Z
D- to D1-
D- to D1-
D- to D2-
D- to D2-
D+ to D1+
D+ to D2+
D+ to D1+
D+ to D2+
L
L
H
L
L
H
H
L
H
16
版权 © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com.cn
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
There are many USB applications in which the USB hubs or controllers have a limited number of USB I/Os or
need to route signals from a single USB connector. The TS5USBC400 solution can effectively expand the limited
USB I/Os by switching between multiple USB buses to interface them to a single USB hub or controller or route
signals from on connector to two different locations. With independent control of the two switches using SEL1
and SEL2, TS5USBC400 can be used to cross switch single ended signals.
9.2 Typical Application
TS5USBC400 USB/UART switch. The TS5USBC400 is used to switch signals between the USB path, which
goes to the baseband or application processor, or the UART path, which goes to debug port. The TS5USBC400
has internal 6-MΩ pull-down resistors on SEL1, SEL2, and OE. The pull-down on SEL1 and SEL2 pins ensure
the D1+/D1- channel is selected by default. The pull-down on OE enables the switch when power is applied.
USB
Connector
V
CC
100 nF
UART
USB
VCC
OVP
D1+
D2+
D1-
D2-
SEL1
SEL2
USB
Logic
Control
OE
FLT
GND
Copyright © 2017, Texas Instruments Incorporated
图 17. Typical TS5USBC400 Application
9.2.1 Design Requirements
Design requirements of USB 1.0,1.1, and 2.0 standards must be followed. The TS5USBC400 has internal 6-MΩ
pulldown resistors on SEL1, SEL2, and OE, so no external resistors are required on the logic pins. The internal
pull-down resistor on SEL1 and SEL2 pins ensures the D1+ and D1- channels are selected by default. The
internal pull-down resistor on OE enables the switch when power is applied to VCC.
9.2.2 Detailed Design Procedure
The TS5USBC400can be properly operated without any external components. However, TI recommends that
unused pins must be connected to ground through a 50-Ω resistor to prevent signal reflections back into the
device. TI does recommend a 100nF bypass capacitor placed close to TS5USBC400 VCC pin.
版权 © 2017, Texas Instruments Incorporated
17
TS5USBC400
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
Typical Application (接下页)
9.2.3 Application Curves
0.4
0.2
0.0
0.4
0.2
0.0
-0.2
-0.4
-0.2
-0.4
1.0
0.0
0.5
1.5
2.0
1.0
0.0
0.5
1.5
2.0
Time (ns)
Time (ns)
图 18. High Speed Eye Diagram With TS5USBC400
图 19. High Speed Eye Diagram Without TS5USBC400
10 Power Supply Recommendations
Power to the device is supplied through the VCC pin and must follow the USB 1.0, 1.1, and 2.0 standards. TI
recommends placing a 100nF bypass capacitor as close to the supply pin VCC as possible to help smooth out
lower frequency noise to provide better load regulation across the frequency spectrum.
18
版权 © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com.cn
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
11 Layout
11.1 Layout Guidelines
1. Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the
D± traces.
2. The high-speed D± must match and be no more than 4 inches long; otherwise, the eye diagram performance
may be degraded. A high-speed USB connection is made through a shielded, twisted pair cable with a
differential characteristic impedance. In layout, the impedance of D+ and D– traces must match the cable
characteristic differential impedance for optimal performance.
3. Route the high-speed USB signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points on twisted
pair lines; through-hole pins are not recommended.
4. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
5. Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices or ICs that use or duplicate clock signals.
6. Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable,
then the stub must be less than 200 mm.
7. Route all high-speed USB signal traces over continuous GND planes, with no interruptions.
8. Avoid crossing over anti-etch, commonly found with plane splits.
9. Due to high frequencies associated with the USB, a printed circuit board with at least four layers is
recommended; two signal layers separated by a ground and power layer as shown in 图 20.
Signal 1
GND Plane
Power Plane
Signal 2
图 20. Four-Layer Board Stack-Up
The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layer must
be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or power
plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing the
number of signal vias reduces EMI by reducing inductance at high frequencies.
版权 © 2017, Texas Instruments Incorporated
19
TS5USBC400
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
11.2 Layout Example
Example 4 layer PCB Stackup
Top Layer 1 (Signal1)
Inner Layer 2 (GND)
Inner Layer 3 (VCC)
Bottom Layer 4 (Signal2)
Via to layer 2 (GND)
Via to layer 3 (VCC)
Via to layer 4 (Signal)
D+
D-
FLT#
OE#
SEL1
A1
A3
B4
C4
A2
A2
Place near VCC pin.
B2
SEL2
C2
B3
VCC
B1
GND
C1
C3
D2-
D1+
D1-
D2+
图 21. Layout Example
20
版权 © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com.cn
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
•
USB 2.0 电路板设计及布线指南
应用报告《高速布局指南》
《高速接口布局指南》
12.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.3 商标
E2E is a trademark of Texas Instruments.
USB Type-C is a trademark of USB Implementers Forum.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2017, Texas Instruments Incorporated
21
TS5USBC400
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。
22
版权 © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com.cn
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
PACKAGE OUTLINE
YFP0012-C01
DSBGA - 0.5 mm max height
S
C
A
L
E
8
.
0
0
0
DIE SIZE BALL GRID ARRAY
1.612
1.552
B
A
BALL A1
CORNER
1.212
1.152
C
0.5 MAX
SEATING PLANE
0.05 C
0.19
0.13
BALL TYP
1.2 TYP
SYMM
C
B
0.8
TYP
SYMM
0.4 TYP
A
1
2
3
4
0.25
0.21
12X
0.015
0.4
TYP
C A B
4223498/B 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
版权 © 2017, Texas Instruments Incorporated
23
TS5USBC400
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
www.ti.com.cn
EXAMPLE BOARD LAYOUT
YFP0012-C01
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
12X ( 0.23)
1
2
3
4
A
(0.4) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:50X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
( 0.23)
METAL
EXPOSED
EXPOSED
METAL
METAL
(
0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4223498/B 04/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
24
版权 © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com.cn
ZHCSGS1A –SEPTEMBER 2017–REVISED SEPTEMBER 2017
EXAMPLE STENCIL DESIGN
YFP0012-C01
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
12X ( 0.25)
1
2
3
4
A
B
(0.4) TYP
SYMM
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:50X
4223498/B 04/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
版权 © 2017, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TS5USBC400IYFPR
TS5USBC400IYFPT
TS5USBC400YFPR
TS5USBC400YFPT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DSBGA
DSBGA
DSBGA
DSBGA
YFP
YFP
YFP
YFP
12
12
12
12
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
0 to 70
USB4
USB4
USB4
USB4
SNAGCU
SNAGCU
SNAGCU
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Mar-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TS5USBC400IYFPR
TS5USBC400IYFPT
TS5USBC400YFPR
TS5USBC400YFPT
DSBGA
DSBGA
DSBGA
DSBGA
YFP
YFP
YFP
YFP
12
12
12
12
3000
250
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
1.32
1.32
1.32
1.32
1.72
1.72
1.72
1.72
0.62
0.62
0.62
0.62
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Mar-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TS5USBC400IYFPR
TS5USBC400IYFPT
TS5USBC400YFPR
TS5USBC400YFPT
DSBGA
DSBGA
DSBGA
DSBGA
YFP
YFP
YFP
YFP
12
12
12
12
3000
250
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
20.0
20.0
20.0
20.0
3000
250
Pack Materials-Page 2
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
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Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
TS5USBC402
具有 20V 过压保护功能的双路 2:1 USB 2.0 多路复用器/多路信号分离器或单端交叉点开关Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TS5USBC402IYFPR
具有 20V 过压保护功能的双路 2:1 USB 2.0 多路复用器/多路信号分离器或单端交叉点开关 | YFP | 12 | -40 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TS5USBC402IYFPT
具有 20V 过压保护功能的双路 2:1 USB 2.0 多路复用器/多路信号分离器或单端交叉点开关 | YFP | 12 | -40 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TS5USBC402YFPR
具有 20V 过压保护功能的双路 2:1 USB 2.0 多路复用器/多路信号分离器或单端交叉点开关 | YFP | 12 | 0 to 70Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TS5USBC402YFPT
具有 20V 过压保护功能的双路 2:1 USB 2.0 多路复用器/多路信号分离器或单端交叉点开关 | YFP | 12 | 0 to 70Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TS5USBC41
具有 20V/24V OVP 功能的双路 2:1 USB 2.0 多路复用器/多路信号分离器或单端交叉点开关Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TS5USBC410IYFFR
具有 20V/24V OVP 功能的双路 2:1 USB 2.0 多路复用器/多路信号分离器或单端交叉点开关 | YFF | 12 | -40 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TS5USBC410IYFFT
具有 20V/24V OVP 功能的双路 2:1 USB 2.0 多路复用器/多路信号分离器或单端交叉点开关 | YFF | 12 | -40 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TS5USBC410YFFR
具有 20V/24V OVP 功能的双路 2:1 USB 2.0 多路复用器/多路信号分离器或单端交叉点开关 | YFF | 12 | 0 to 70Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TS5USBC410YFFT
具有 20V/24V OVP 功能的双路 2:1 USB 2.0 多路复用器/多路信号分离器或单端交叉点开关 | YFF | 12 | 0 to 70Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TS5USBC412IYFFR
具有 20V/24V OVP 功能的双路 2:1 USB 2.0 多路复用器/多路信号分离器或单端交叉点开关 | YFF | 12 | -40 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TS5USBC412IYFFT
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