TS5USBC412IYFFT [TI]
具有 20V/24V OVP 功能的双路 2:1 USB 2.0 多路复用器/多路信号分离器或单端交叉点开关 | YFF | 12 | -40 to 85;
| 型号： | TS5USBC412IYFFT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 20V/24V OVP 功能的双路 2:1 USB 2.0 多路复用器/多路信号分离器或单端交叉点开关 | YFF | 12 | -40 to 85 开关 复用器 |
| 文件： | 总30页 (文件大小：1424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TS5USBC41
ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
具有 20V/24V 过压保护功能的 TS5USBC41 双路 2:1 USB 2.0 多路复用器
/多路信号分离器或单端交叉开关
1 特性
2 应用
1
•
•
电源电压范围为 2.3V 至 5.5V
•
•
•
•
移动设备
差动 2:1 或 1:2 开关/多路复用器或灵活的双路单端
交叉开关
台式机/笔记本电脑
平板电脑
•
在公共引脚上提供 0V 至 20V (TS5USBC410) 和
24V (TS5USBC412) 过压保护 (OVP) 功能
使用 USB Type-C™ 或 Micro-B 连接器的任何场合
•
•
•
VCC = 0V 时具有断电保护
3 说明
较低的 RON（最大值为 9Ω）
TS5USBC41 是一款双向低功耗双端口高速 USB 2.0
模拟开关，具有针对 USB Type-C™系统的集成保护功
能。该器件可配置为一个 2:1 或 1:2 开关。该器件经过
优化，可用于 USB Type-C™ 系统中的 USB 2.0 D+/-
线路。
典型带宽为 1.1GHz (TS5USBC410) 和 1.2GHz
(TS5USBC412)
•
CON 典型值为 2.7pF (TS5USBC410) 和 2.5pF
(TS5USBC412)
•
•
•
低功耗禁用模式
I/O 引脚上的 TS5USBC41 保护功能可承受最高 20V
(TS5USBC410) 或 24V (TS5USBC412) 的电压，且会
通过自动关闭电路来保护该开关后面的系统组件。
1.8V 兼容型逻辑输入
ESD 保护性能超出 JESD 22 标准
–
2000V 人体放电模型 (HBM)
•
•
•
TS5USBC410 和 TS5USBC412：0°C 至 70°C 的
标准温度范围
TS5USBC41 采用小型 12 引脚 DSBGA 封装，使其成
为移动应用和空间受限型 应用。
TS5USBC410I 和 TS5USBC412I：-40°C 至 85°C
的工业温度范围
器件信息(1)
器件型号
封装
封装尺寸（标称值）
小型 DSBGA 封装
TS5USBC410
TS5USBC410I
TS5USBC412
TS5USBC412I
DSBGA (12)
1.638mm × 1.238mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
简化原理图
USB
Connector
UART
USB
D1+
VCC
OVP
D2+
D1-
D2-
SEL1
USB
SEL2
Logic
Control
OE
FLT
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SCDS377
TS5USBC41
ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
www.ti.com.cn
目录
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 17
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application .................................................. 18
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Dynamic Characteristics ........................................... 8
6.7 Timing Requirements................................................ 8
6.8 Typical Characteristics.............................................. 9
Parameter Measurement Information ................ 10
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
9
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 21
12 器件和文档支持 ..................................................... 22
12.1 文档支持................................................................ 22
12.2 接收文档更新通知 ................................................. 22
12.3 社区资源................................................................ 22
12.4 商标....................................................................... 22
12.5 静电放电警告......................................................... 22
12.6 术语表 ................................................................... 22
13 机械、封装和可订购信息....................................... 22
7
8
4 修订历史记录
Changes from Revision A (May 2018) to Revision B
Page
•
更改了器件状态：将预告信息 更改成了生产数据 ................................................................................................................... 1
2
Copyright © 2018, Texas Instruments Incorporated
TS5USBC41
www.ti.com.cn
ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
5 Pin Configuration and Functions
YFF Package
12-Pin DSBGA
Top View
1
2
3
4
A
B
C
SEL1
VCC
D2+
D+
Dœ
FLT
SEL2
GND
D1+
OE
D2œ
D1œ
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NO.
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
C4
NAME
SEL1
D+
I
I/O
I/O
O
Switch select1. Refer to 表 1.
Data switch input (Differential +).
Data switch input (Differential –)
D–
FLT
VCC
SEL2
GND
OE
Fault indicator output pin (Active low) - open drain
Supply Voltage
PWR
I
Switch select2. Refer to 表 1.
Ground
GND
I
Output enable (Active low). Refer to 表 1.
Data switch output 2 (Differential +)
Data switch output 2 (Differential -)
Data switch output 1 (Differential +)
Data switch output 1 (Differential -)
D2+
D2–
D1+
D1–
I/O
I/O
I/O
I/O
Copyright © 2018, Texas Instruments Incorporated
3
TS5USBC41
ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
(2)
MIN
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-50
MAX
6
UNIT
V
VCC
VI/O
VI/O
VI/O
VI
Supply voltage(3)
Input/Output DC voltage (D+, D-) (TS5USBC412, TS5USBC412I)(3)
Input/Output DC voltage (D+, D-) (TS5USBC410, TS5USBC410I)(3)
Input/Output DC voltage (D1+/D1-, D2+/D2-)(3)
28
24
6
V
V
V
Digital input voltage (SEL1, SEL2, OE)
6
V
VO
Digital output voltage (FLT)
6
V
IK
Input-output port diode current (D+, D-, D1+, D1-, D2+, D2-) when VIN < 0
mA
mA
mA
mA
°C
(3)
IIK
Digital logic input clamp current (SEL1, SEL2, OE) when VI < 0
-50
ICC
IGND
Tstg
Continuous current through VCC
Continuous current through GND
Storage temperature
100
150
-100
-65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwisespecified.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
5.5
24
UNIT
V
VCC
Supply voltage
2.3
0
VI/O (D+, D-)
Analog input/output voltage (TS5USBC412, TS5USBC412I)
Analog input/output voltage (TS5USBC410, TS5USBC410I)
Analog input/output voltage
V
VI/O (D+, D-)
0
20
V
VI/O (D1, D1-, D2+, D2-)
0
3.6
5.5
5.5
V
VI
Digital input voltage (SEL1, SEL2, OE)
Digital output voltage (FLT)
0
V
VO
0
V
II/O (D+, D-, D1+, D1-, D2+,
D2-)
Analog input/output port continuous current
-50
0
50
3
mA
mA
ºC
IOL
Digital output current
Operating free-air temperature (Standard)
(TS5USBC410, TS5USBC412)
TA
70
Operating free-air temperature (Industrial)
(TS5USBC410I, TS5USBC412I)
TA
TJ
–40
–40
85
ºC
ºC
Junction temperature
125
4
Copyright © 2018, Texas Instruments Incorporated
TS5USBC41
www.ti.com.cn
ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
6.4 Thermal Information
Device
(1)
THERMAL METRIC
YFF
12 PINS
91.8
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
°C/W
0.8
22.8
0.5
ψJB
Junction-to-board characterization parameter
23.0
(1) For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application
report.
6.5 Electrical Characteristics
TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard),VCC = 2.3 V to 5.5 V, GND = 0 V, Typical values are at VCC
=
3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER
OE = 0 V
SEL1, SEL2 = 0 V, 1.8 V or
VCC
ICC-ACTIVE
Active supply current.
9
22
µA
0 V < VI/O < 3.6 V
OE = 0 V
SEL1, SEL2 = 0 V, 1.8 V or
VCC
VI/O > VPOS_THLD
ICC-OVP
Supply current during OVP condition.
Standby powered down supply current
10
2
35
6
μA
OE = 1.8 V or VCC
SEL1 = 0 V, 1.8 V, or VCC
SEL2 = 0 V, 1.8 V, or VCC
ICC_PD
DC Characteristics
µA
VI/O = 0.4 V
ISINK = 8 mA
Refer to ON-State Resistance
Figure
RON
ON-state resistance
5.6
0.075
0.1
9
0.48
0.4
Ω
Ω
Ω
VI/O = 0.4 V
ISINK = 8 mA
Refer to ON-State Resistance
Figure
ON-state resistance match between
channels
ΔRON
VI/O = 0 V to 0.4 V
ISINK = 8 mA
Refer to ON-State Resistance
Figure
RON (FLAT)
ON-state resistance flatness
I/O pin OFF leakage current
OE = H
VD± = 0 V or 3.6 V
VCC = 2.3 V to 5.5 V
VD1±or VD2± = 3.6 V or 0 V
Refer to Off Leakage Figure
IOFF
-4
-0.5
140
0.1
4
0.5
µA
µA
µA
OE = H
VD± = 20-V
VCC = 2.3 V to 5.5 V
VD1± or VD2± = 0 V
Refer to Off Leakage Figure
D1/D2+/- pin OFF leakage current
during OVP scenario on D+/-
IOFF-20V
OE = H
VD± = 20-V
VCC = 2.3 V to 5.5 V
VD1± or VD2± = 0 V
Refer to Off Leakage Figure
D+/- pin OFF leakage current during OVP
scenario
IOFF-20V-DP/N
150
180
Copyright © 2018, Texas Instruments Incorporated
5
TS5USBC41
ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
www.ti.com.cn
Electrical Characteristics (continued)
TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard),VCC = 2.3 V to 5.5 V, GND = 0 V, Typical values are at VCC
=
3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
OE = H
MIN
TYP
MAX
UNIT
VD± = 24-V
D1/D2 +/- pin OFF leakage current during
OVP scenario on D+/-.
IOFF-24V
VCC = 2.3 V to 5.5 V
VD1± or VD2± = 0 V
Refer to Off Leakage Figure
-0.5
0.5
µA
OE = H
VD± = 0 V or 24-V
VCC = 2.3 V to 5.5 V
VD1± or VD2± = 0 V
Refer to Off Leakage Figure
D+/- pin OFF leakage current during OVP
scenario.
IOFF-24V-DPN
220
250
270
7.5
µA
µA
VD± = 0 V or 3.6 V
VD1± and VD2+/- = high-Z
Refer to On Leakage Figure
ION
ON leakage current.
-5.5
1.4
0.25
Digital Characteristics
VIH
VIL
Input logic high
SEL1, SEL2, OE
SEL1, SEL2, OE
V
V
Input logic low
0.5
0.4
FLT
IOL = 3 mA
VOL
Output logic low
V
IIH
IIL
Input high leakage current
Input low leakage current
SEL1, SEL2, OE = 1.8 V, VCC
SEL1, SEL2, OE = 0 V
-1
-1
1
5
5
μA
μA
±0.2
Internal pull-down resistor on digital input
pins
RPD
6
MΩ
SEL1, SEL2 = 0 V, 1.8 V or
VCC
CI
Digital input capacitance
4
pF
f = 1 MHz
Protection
VOVP_TH
OVP positive threshold
4.4
4.8
5.2
V
VOVP_HYST
OVP threshold hysteresis
125
250
440
mV
VD± = 0 to 24 V
tRISE and tFALL(10% to 90 %) =
100 ns
RL = Open
Switch on or off
OE = 0 V
Maximum voltage to appear on D1± and
D2± pins during OVP scenario
(TS5USBC412, TS5USBC412I)
VCLAMP_V
VCLAMP_V
VCLAMP_V
VCLAMP_V
11.2
10.8
10.8
9.8
V
V
V
V
VD± = 0 to 24 V
tRISE and tFALL(10% to 90 %) =
100 ns
RL = 50Ω
Switch on or off
OE = 0 V
Maximum voltage to appear on D1± and
D2± pins during OVP scenario
(TS5USBC412, TS5USBC412I)
VD± = 0 to 20 V
tRISE and tFALL(10% to 90 %) =
100 ns
RL = Open
Switch on or off
OE = 0 V
Maximum voltage to appear on D1± and
D2± pins during OVP scenario
(TS5USBC410, TS5USBC410I)
VD± = 0 to 20 V
tRISE and tFALL(10% to 90 %) =
100 ns
RL = 50Ω
Switch on or off
OE = 0 V
Maximum voltage to appear on D1± and
D2± pins during OVP scenario
(TS5USBC410, TS5USBC410I)
6
Copyright © 2018, Texas Instruments Incorporated
TS5USBC41
www.ti.com.cn
ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
Electrical Characteristics (continued)
TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard),VCC = 2.3 V to 5.5 V, GND = 0 V, Typical values are at VCC
=
3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VD± = 0 to 24 V
MIN
TYP
MAX
UNIT
tRISE and tFALL(10% to 90 %) =
100 ns
RL = Open CL = 10pF
Switch on or off
OE = 0 V
Maximum OVP transient duration above
5 V (TS5USBC412, TS5USBC412I).
VCLAMP_T
VCLAMP_T
VCLAMP_T
VCLAMP_T
75
100
ns
ns
ns
ns
VD± = 0 to 24 V
tRISE and tFALL(10% to 90 %) =
100 ns
RL = 50Ω CL = 10pF
Switch on or off
OE = 0 V
Maximum OVP transient duration above
5 V
(TS5USBC412, TS5USBC412I)
68
64
55
95
100
95
VD± = 0 to 20 V
tRISE and tFALL(10% to 90 %) =
100 ns
RL = Open CL = 10pF
Switch on or off
OE = 0 V
Maximum OVP transient duration above
5 V
(TS5USBC410, TS5USBC410I)
VD± = 0 to 20 V
tRISE and tFALL(10% to 90 %) =
100 ns
RL = 50Ω CL = 10pF
Switch on or off
OE = 0 V
Maximum OVP transient duration above
5 V
(TS5USBC410, TS5USBC410I)
RPU = 10 kΩ to VCC (FLT)
CL = 35 pF
Refer to OVP Timing Diagram
Figure
tEN_OVP
OVP enable time
3
5
μs
μs
RPU = 10 kΩ to VCC (FLT)
CL = 35 pF
Refer to OVP Timing Diagram
Figure
tREC_OVP
OVP recovery time
Copyright © 2018, Texas Instruments Incorporated
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TS5USBC41
ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
www.ti.com.cn
6.6 Dynamic Characteristics
TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard),VCC = 2.3 V to 5.5V, GND = 0V, Typical values are at VCC = 3.3
V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VD+/- = 0 or 3.3 V,
MIN
TYP
MAX UNIT
OE = VCC
D+, D- off capacitance
Switch OFF
1.2
1.6
3.2
pF
f = 240 MHz
COFF
VD+/- = 0 or 3.3 V,
OE = VCC or OE = 0V with SEL1,
SEL2 (switch not selected)
f = 240 MHz
D1+, D1-, D2+, D2- off
capacitance
Switch OFF or
not selected
1.2
1.5
3.0
pF
IO pins ON capacitance
(TS5USBC412, TS5USBC412I)
VD+/- = 0 or 3.3 V,
f = 240 MHz
CON
CON
Switch ON
Switch ON
2.0
2.0
2.5
2.7
3.9
4
pF
pF
IO pins ON capacitance
(TS5USBC410, TS5USBC410I)
VD+/- = 0 or 3.3 V,
f = 240 MHz
RL = 50 Ω
CL = 5 pF
f = 100 kHz
Refer to Off Isolation Figure
Switch OFF
Switch OFF
Switch ON
-95
-25
-90
dB
dB
dB
OISO
Differential off isolation
RL = 50 Ω
CL = 5 pF
f = 240 MHz
Refer to Off Isolation Figure
RL = 50 Ω
CL = 5 pF
f = 100 kHz
XTALK
Channel to Channel crosstalk
Refer to Crosstalk Figure
Bandwidth
(TS5USBC412, TS5USBC412I)
RL = 50 Ω; Refer to BW and
Insertion Loss Figure
BW
BW
Switch ON
Switch ON
1.2
1.1
GHz
GHz
Bandwidth
(TS5USBC410, TS5USBC410I)
RL = 50 Ω; Refer to BW and
Insertion Loss Figure
RL = 50 Ω
ILOSS
Insertion loss
Switch ON
-0.8
dB
f = 240 MHz; Refer to BW and
Insertion Loss Figure
6.7 Timing Requirements
TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard),VCC = 2.3 V to 5.5V, GND = 0V, Typical values are atVCC = 3.3
V, TA = 25°C, (unless otherwisenoted)
PARAMETER
TEST CONDITIONS
MIN NOM
MAX UNIT
VD+/- = 0.8 V
Refer to Tswitch Timing Figure
tSWITC Switching time between channels
0.8
2.5
250
1
µs
µs
µs
(SEL1, SEL2 to output)
H
RL = 50 Ω,
CL = 5 pF,
VCC = 2.3 V to 5.5 V
VD+/- = 0.8 V
Refer to Ton and Toff Figure
Device turn on time (OE to
output).
tON
84
VD+/- = 0.8 V
Refer to Ton and Toff Figure
tOFF
Device turn off time (OE to output)
0.75
RL = 50 Ω,
CL = 1 pF,
VCC = 2.3 V to 5.5 V
Skew of opposite transitions of
same output (between D+ and D-
).
VD+/- = 0.4 V
Refer to Tsk Figure
tSK(P)
11
50
ps
ps
f - 240 MHz
VD+/- = 0.4 V
RL = 50 Ω,
CL = 5 pF,
tPD
Propagation delay.
150
230
Refer to Tpd Figure
VCC = 2.3 V to 5.5 V
8
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TS5USBC41
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ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
6.8 Typical Characteristics
8
7.5
7
0.6
0.55
0.5
0.45
0.4
6.5
6
0.35
0.3
0.25
0.2
5.5
5
0.15
0.1
VCC = 2.3 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 5.5 V
4.5
4
0.05
0
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
VIN, Input Voltage (V)
D001
Voltage on Dê (V)
D001
VCC = 3.3 V
图 1. ON-Resistance vs Input Voltage
TA = 25°C
图 2. IOFF Leakage Current vs Voltage on D±
1
2
Supply Voltage
1
VCC = 2.3 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 5.5 V
0.1
0.1
0.01
0.001
0.01
0.001
Supply Voltage
VCC = 2.3 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 5.5 V
0.0001
2E-5
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
Voltage on D1ê or D2ê (V)
Voltage on Dê or D1ê or D2ê (V)
D002
D003
图 3. IOFF Leakage Current vs Voltage on D1± or D2±
图 4. ION Leakage Current vs Voltage on D± or D1± or D2±
版权 © 2018, Texas Instruments Incorporated
9
TS5USBC41
ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
www.ti.com.cn
7 Parameter Measurement Information
V
VD+/-
ISINK
Switch
Channel ON, RON = V/ISINK
图 5. ON-State Resistance (RON
)
VDX+/-
VD+/-
A
A
Switch
图 6. Off Leakage
VD+/-
A
Switch
图 7. On Leakage
VD1+/-
VD2+/-
VD+/-
SEL
CL
RL
RL
CL
VSEL
1.8 V
0 V
1.8 V
0 V
0.8 V
1.2 V
1.2 V
0.8 V
VSEL
tSWITCH
VD1+/-
VSEL
tSWITCH
VD2+/-
tSWITCH
tSWITCH
VD+/-
0 V
VD+/-
0 V
80 %
80 %
20 %
20 %
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2) CL includes probe and jig capacitance.
图 8. tSWITCH Timing
10
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TS5USBC41
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ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
Parameter Measurement Information (接下页)
2.3 V
VCC
VD+/-
1.8 V
0 V
VOE
0.8 V
1.2 V
CL
RL
OE
tON
tOFF
10 %
VD+/-
0 V
90 %
VDX+/-
VOE
(1) All input pulses are supplied by generators having the following characteristics: PRR = 10 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2) CL includes probe and jig capacitance.
图 9. tON, tOFF for OE
Network Analyzer
Switch
50 O
D+
D-
50 O
Source
Signal
50 O
50 O
Source
Signal
50 O
50 O
图 10. Off Isolation
Network Analyzer
50 ꢀ
Switch
D+
50 ꢀ
Source
Signal
50 ꢀ
D-
50 ꢀ
50 ꢀ
50 ꢀ
图 11. Cross Talk
版权 © 2018, Texas Instruments Incorporated
11
TS5USBC41
ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
www.ti.com.cn
Parameter Measurement Information (接下页)
Network Analyzer
Switch
50 ꢀ
D+
50 ꢀ
Source
Signal
50 ꢀ
D-
50 ꢀ
Source
Signal
50 ꢀ
50 ꢀ
图 12. BW and Insertion Loss
20 / 24 V
0 V
VD+/-
OE
VPOS_THLD
VD+/-
CL
RL
tEN_OVP
FLT
tREC_OVP
VOE
VCC
0 V
10 %
10 %
图 13. tEN_OVP and tDIS_OVP Timing Diagram
Switch
D+/-
50 ꢀ
0.4 V
VD+/-
50 %
50 %
0 V
0.4 V
0 V
50 ꢀ
tPD
50 %
tPD
VDX+/-
50 %
(1) All input pulses are supplied by generators having the following characteristics: PRR = 240 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2) CL includes probe and jig capacitance.
图 14. tPD
12
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TS5USBC41
www.ti.com.cn
ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
Parameter Measurement Information (接下页)
Switch
0.4 V
D+
D-
50 O
50 O
VD+/-
VDX+
VDX-
0 V
50 O
50 O
0.4 V
50 %
50 %
0 V
0.4 V
0 V
tSK
tSK
50 %
50 %
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2) CL includes probe and jig capacitance.
图 15. tSK
版权 © 2018, Texas Instruments Incorporated
13
TS5USBC41
ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TS5USBC41 is a bidirectional low-power dual port, high-speed, USB 2.0 analog switch with integrated
protection for USB Type-C systems. The device is configured as a dual 2:1 or 1:2 switch and is optimized for
handling the USB 2.0 D+/- lines in a USB Type-C system as shown in 图 16.
图 16. USB Type-C Connector Pinout
The TS5USBC41 also works in traditional USB systems that need protection from fault conditions such as
automotive and applications that require higher voltage charging. The device maintains excellent signal integrity
through the optimization of both RON and BW while protecting the system with 20 V (TS5USBC410) and 24 V
(TS5USBC412) OVP protection. The OVP implementation is designed to protect sensitive system components
behind the switch that cannot survive a fault condition where VBUS is shorted to the D+ and D- pins on the
connector.
8.2 Functional Block Diagram
VCC
SEL1
6 Mꢀ
SEL2
Control
Logic
FLT
6 Mꢀ
OE
6 Mꢀ
VOVP
OVP
D1+
D+
D1-
D2+
D-
D2-
Switches
14
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TS5USBC41
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ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
8.3 Feature Description
8.3.1 Powered-off Protection
When the TS5USBC41 is powered off the I/Os of the device remain in a high-Z state. The crosstalk, off-isolation,
and leakage remain within the Electrical Specifications.
This prevents errant voltages from reaching the rest of the system and maintains isolation when the system is
powering up.
8.3.2 Overvoltage Protection
The OVP of the TS5USBC41 is designed to protect the system from D+/- shorts to VBUS at the USB and USB
Type-C connector. 图 17 depicts a moisture short that would cause high voltage (20 V for TS5USBC410 or 20 V
for TS5USBC412) to appear on an existing USB solution that could pass through the device and damage
components behind the device.
VBUS
SBU2
D-
VBUS
CC1
D+
UART
USB
Existing Solutions
D+
D1+
D2+
D1-
D-
D
D-
D2-
CC
SBU1
VBUS
USB
20 V / 24 V
VB
图 17. Existing Solution Being Damaged by a Short
版权 © 2018, Texas Instruments Incorporated
15
TS5USBC41
ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
www.ti.com.cn
Feature Description (接下页)
The TS5USBC41 will open the switches and protect the rest of the system by blocking the 20 V / 24 V as
depicted in 图 18.
20 V / 24 V doesn‘t
reach rest of system
VBUS
SBU2
D-
VBUS
CC1
D+
UART
USB
D1+
D+
D-
D2+
D1-
D
D-
D2-
CC
SBU1
VBUS
USB
20 V / 24 V
VBU
图 18. Protecting During a 20-V / 24-V Short
图 19 is a waveform showing the voltage on the pins during an over-voltage scenario.
20 V / 24 V
VOVP_THLD
D+/-
0 V
D1/D2
0 V
FLT
图 19. Overvoltage Protection Waveform
16
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TS5USBC41
www.ti.com.cn
ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
8.4 Device Functional Modes
8.4.1 Pin Functions
表 1. Function Table
OE
H
L
SEL1
SEL2
D- Connection
D+ Connection
High-Z
X
L
X
L
High-Z
D- to D1-
D- to D1-
D- to D2-
D- to D2-
D+ to D1+
D+ to D2+
D+ to D1+
D+ to D2+
L
L
H
L
L
H
H
L
H
版权 © 2018, Texas Instruments Incorporated
17
TS5USBC41
ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
www.ti.com.cn
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
There are many USB applications in which the USB hubs or controllers have a limited number of USB I/Os or
need to route signals from a single USB connector. The TS5USBC41 solution can effectively expand the limited
USB I/Os by switching between multiple USB buses to interface them to a single USB hub or controller or route
signals from on connector to two different locations. With independent control of the two switches using SEL1
and SEL2, TS5USBC41 can be used to cross switch single ended signals.
9.2 Typical Application
TS5USBC41 USB/UART switch. The TS5USBC41 is used to switch signals between the USB path, which goes
to the baseband or application processor, or the UART path, which goes to debug port. The TS5USBC41 has
internal 6-MΩ pull-down resistors on SEL1, SEL2, and OE. The pull-down on SEL1 and SEL2 pins ensure the
D1+/D1- channel is selected by default. The pull-down on OE enables the switch when power is applied.
USB
Connector
V
CC
100 nF
UART
USB
VCC
OVP
D1+
D2+
D1-
D2-
SEL1
SEL2
USB
Logic
Control
OE
FLT
GND
图 20. Typical Application
9.2.1 Design Requirements
Design requirements of USB 1.0,1.1, and 2.0 standards must be followed. The TS5USBC41 has internal 6-MΩ
pulldown resistors on SEL1, SEL2, and OE, so no external resistors are required on the logic pins. The internal
pull-down resistor on SEL1 and SEL2 pins ensures the D1+ and D1- channels are selected by default. The
internal pull-down resistor on OE enables the switch when power is applied to VCC.
9.2.2 Detailed Design Procedure
The TS5USBC41 can be properly operated without any external components. However, TI recommends that
unused pins must be connected to ground through a 50-Ω resistor to prevent signal reflections back into the
device. TI does recommend a 100-nF bypass capacitor placed close to TS5USBC41 VCC pin.
18
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TS5USBC41
www.ti.com.cn
ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
Typical Application (接下页)
9.2.3 Application Curves
0.4
0.2
0.0
0.4
0.2
0.0
-0.2
-0.4
-0.2
-0.4
1.0
0.0
0.5
1.5
2.0
1.0
0.0
0.5
1.5
2.0
Time (ns)
Time (ns)
图 22. High Speed Eye Diagram Without TS5USBC41
图 21. High Speed Eye Diagram With TS5USBC41
10 Power Supply Recommendations
Power to the device is supplied through the VCC pin and must follow the USB 1.0, 1.1, and 2.0 standards. TI
recommends placing a 100 nF bypass capacitor as close to the supply pin VCC as possible to help smooth out
lower frequency noise to provide better load regulation across the frequency spectrum.
版权 © 2018, Texas Instruments Incorporated
19
TS5USBC41
ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
1. Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the
D± traces.
2. The high-speed D± must match and be no more than 4 inches long; otherwise, the eye diagram performance
may be degraded. A high-speed USB connection is made through a shielded, twisted pair cable with a
differential characteristic impedance. In layout, the impedance of D+ and D– traces must match the cable
characteristic differential impedance for optimal performance.
3. Route the high-speed USB signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points on twisted
pair lines; through-hole pins are not recommended.
4. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
5. Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices or ICs that use or duplicate clock signals.
6. Avoid stubs on the high-speed USB signals due to signal reflections. If a stub is unavoidable, then the stub
must be less than 200 mm.
7. Route all high-speed USB signal traces over continuous GND planes, with no interruptions.
8. Avoid crossing over anti-etch, commonly found with plane splits.
9. Due to high frequencies associated with the USB, a printed circuit board with at least four layers is
recommended; two signal layers separated by a ground and power layer as shown in 图 23.
Signal 1
GND Plane
Power Plane
Signal 2
图 23. Four-Layer Board Stack-Up
The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layer must
be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or power
plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing the
number of signal vias reduces EMI by reducing inductance at high frequencies.
20
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TS5USBC41
www.ti.com.cn
ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
11.2 Layout Example
Example 4 layer PCB Stackup
Top Layer 1 (Signal1)
Inner Layer 2 (GND)
Inner Layer 3 (VCC)
Bottom Layer 4 (Signal2)
Via to layer 2 (GND)
Via to layer 3 (VCC)
Via to layer 4 (Signal)
D+
D-
FLT#
SEL1
A1
A3
A2
A2
Place near VCC pin.
B2
SEL2
C2
B3
VCC
OE#
B4
B1
GND
C4
C1
C3
D2-
D1+
D1-
D2+
图 24. Layout Example
版权 © 2018, Texas Instruments Incorporated
21
TS5USBC41
ZHCSHY0B –MARCH 2018–REVISED JUNE 2018
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
•
《USB 2.0 电路板设计和布局指南》
《高速布局指南》应用报告
《高速接口布局指南》
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
USB Type-C is a trademark of USB Implementers Forum.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查看左侧的导航栏。
22
版权 © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TS5USBC410IYFFR
TS5USBC410IYFFT
TS5USBC410YFFR
TS5USBC410YFFT
TS5USBC412IYFFR
TS5USBC412IYFFT
TS5USBC412YFFR
TS5USBC412YFFT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
YFF
YFF
YFF
YFF
YFF
YFF
YFF
YFF
12
12
12
12
12
12
12
12
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
0 to 70
TU41
TU41
TU41
TU41
TU41
TU41
TU41
TU41
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Dec-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TS5USBC410IYFFR
TS5USBC410IYFFR
TS5USBC410IYFFT
TS5USBC410IYFFT
TS5USBC410YFFR
TS5USBC410YFFT
TS5USBC412IYFFR
TS5USBC412IYFFT
TS5USBC412YFFR
TS5USBC412YFFT
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
YFF
YFF
YFF
YFF
YFF
YFF
YFF
YFF
YFF
YFF
12
12
12
12
12
12
12
12
12
12
3000
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
1.38
1.38
1.38
1.38
1.38
1.38
1.38
1.38
1.38
1.38
1.76
1.76
1.76
1.76
1.76
1.76
1.76
1.76
1.76
1.76
0.77
0.77
0.77
0.77
0.77
0.77
0.77
0.77
0.77
0.77
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
250
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Dec-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TS5USBC410IYFFR
TS5USBC410IYFFR
TS5USBC410IYFFT
TS5USBC410IYFFT
TS5USBC410YFFR
TS5USBC410YFFT
TS5USBC412IYFFR
TS5USBC412IYFFT
TS5USBC412YFFR
TS5USBC412YFFT
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
YFF
YFF
YFF
YFF
YFF
YFF
YFF
YFF
YFF
YFF
12
12
12
12
12
12
12
12
12
12
3000
3000
250
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
250
3000
250
3000
250
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0012
DSBGA - 0.625 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
0.625 MAX
C
SEATING PLANE
0.05 C
BALL TYP
0.30
0.12
0.8 TYP
0.4 TYP
D
C
B
SYMM
1.2
TYP
D: Max = 1.628 mm, Min =1.568 mm
E: Max = 1.228 mm, Min =1.168 mm
A
0.4 TYP
1
2
3
0.3
12X
0.015
0.2
SYMM
C A
B
4222191/A 07/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YFF0012
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
12X ( 0.23)
(0.4) TYP
1
2
A
B
C
SYMM
D
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
(
0.23)
METAL
(
0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4222191/A 07/2015
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information,
see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
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EXAMPLE STENCIL DESIGN
YFF0012
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
12X ( 0.25)
1
2
3
A
(0.4) TYP
B
SYMM
METAL
TYP
C
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4222191/A 07/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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