TS5V330DR [TI]
QUAD SPDT WIDE BANDWIDTH VIDEO SWITCH WITH LOW ON STATE RESISTANCE; 具有低导通电阻四路SPDT高带宽视频开关
| 型号： | TS5V330DR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUAD SPDT WIDE BANDWIDTH VIDEO SWITCH WITH LOW ON STATE RESISTANCE |
| 文件： | 总17页 (文件大小：358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCDS164A – MAY 2004 − REVISED MAY 2004
D, DBQ, OR PW PACKAGE
(TOP VIEW)
D
Low Differential Gain and Phase
(D = 0.64%, D = 0.1 Degrees Typ)
G
P
D
D
D
D
D
D
D
D
D
D
D
Wide Bandwidth (BW = 300 MHz Min)
Low Crosstalk (X = −63 dB Typ)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
EN
S1
S2
D
S1
S2
D
IN
CC
TALK
S1
S2
D
S1
S2
D
A
A
A
B
B
B
Low Power Consumption
(I = 3 µA Max)
D
CC
D
Bidirectional Data Flow, With Near-Zero
Propagation Delay
D
C
C
Low ON-State Resistance (r = 3 Ω Typ)
on
GND
C
V
Operating Range From 4.5 V to 5.5 V
CC
I
Supports Partial-Power-Down Mode
off
Operation
RGY PACKAGE
(TOP VIEW)
Data and Control Inputs Provide
Undershoot Clamp Diode
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
1
16
15
14
13
12
11
10
S1
S2
D
2
EN
S2
A
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
3
A
D
4
S2
A
D
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
S1
S2
D
5
D
B
D
6
S1
B
C
7
S2
B
C
− 1000-V Charged-Device Model (C101)
8
9
D
Suitable for Both RGB and
Composite-Video Switching
description/ordering information
The TI TS5V330 video switch is a 4-bit 1-of-2 multiplexer/demultiplexer with a single switch-enable (EN) input.
When EN is low, the switch is enabled and the D port is connected to the S port. When EN is high, the switch
is disabled and the high-impedance state exists between the D and S ports. The select (IN) input controls the
data path of the multiplexer/demultiplexer.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
QFN − RGY
SOIC − D
Tape and reel
Tube
TS5V330RGYR
TS5V330D
TE330
TS5V330
TE330
Tape and reel
TS5V330DR
TS5V330DBQR
TS5V330PW
−40°C to 85°C
SSOP (QSOP) − DBQ Tape and reel
Tube
TSSOP − PW
TE330
Tape and reel
TS5V330PWR
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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ꢞ ꢝ ꢜ ꢗꢥ ꢜ ꢚꢥ ꢩ ꢜ ꢚꢚ ꢜ ꢗ ꢝꢪꢦ ꢊꢚ ꢙ ꢥꢠꢟ ꢝꢖꢙꢗ ꢢꢚ ꢙꢟ ꢡꢞ ꢞꢖ ꢗꢫ ꢥꢙꢡ ꢞ ꢗꢙꢝ ꢗꢡ ꢟꢡ ꢞꢞ ꢜꢚ ꢖꢤ ꢪ ꢖꢗꢟ ꢤꢠꢥ ꢡ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢋꢌ ꢀ ꢑ ꢔ ꢒꢋ ꢒꢐ ꢎ ꢁꢀꢈꢀꢍ ꢕꢍ ꢁ ꢌ ꢁꢀꢈꢐ ꢓꢍ
SCDS164A – MAY 2004 − REVISED MAY 2004
description/ordering information (continued)
Low differential gain and phase make this switch ideal for composite and RGB video applications. This device
has wide bandwidth and low crosstalk, making it suitable for high-frequency applications as well.
This device is fully specified for partial-power-down applications using I . The I feature ensures that
off
off
damaging current will not backflow through the device when it is powered down. This switch maintains isolation
during power off.
To ensure the high-impedance state during power up or power down, EN should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
FUNCTION TABLE
INPUTS
INPUT/OUTPUT
D
FUNCTION
EN
IN
L
L
L
S1
S2
Z
D port = S1 port
D port = S2 port
Disconnect
H
X
H
PIN DESCRIPTIONS
PIN NAME
DESCRIPTION
Analog video I/Os
Analog video I/Os
Select input
S1, S2
D
IN
EN
Switch-enable input
2
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SCDS164A – MAY 2004 − REVISED MAY 2004
PARAMETER DEFINITIONS
PARAMETER
DESCRIPTION
r
Resistance between the D and S ports, with the switch in the ON state
on
I
Output leakage current measured at the D and S ports, with the switch in the OFF state
Short-circuit current measured at the I/O pins
OZ
I
OS
V
IN
Voltage at the IN pin
V
EN
Voltage at the EN pin
C
Capacitance at the control (EN, IN) inputs
IN
C
Capacitance at the analog I/O port when the switch is OFF
Capacitance at the analog I/O port when the switch is ON
Minimum input voltage for logic high for the control (EN, IN) inputs
Minimum input voltage for logic low for the control (EN, IN) inputs
Hysteresis voltage at the control (EN, IN) inputs
OFF
C
ON
V
IH
V
IL
V
hys
V
I/O and control (EN, IN) inputs diode clamp voltage
Voltage applied to the D or S pins when D or S is the switch input
Voltage applied to the D or S pins when D or S is the switch output
Input high leakage current of the control (EN, IN) inputs
Input low leakage current of the control (EN, IN) inputs
Current into the D or S pins when D or S is the switch input
Current into the D or S pins when D or S is the switch output
IK
V
I
V
O
I
IH
I
IL
I
I
I
O
I
off
Output leakage current measured at the D or S ports, with V = 0
CC
t
Propagation delay measured between 50% of the digital input to 90% of the analog output when switch is turned ON
Propagation delay measured between 50% of the digital input to 90% of the analog output when switch is turned OFF
Frequency response of the switch in the ON state measured at −3 dB
ON
t
OFF
BW
Unwanted signal coupled from channel to channel. Measured in −dB. X
crosstalk.
= 20 log V /V This is a nonadjacent
I.
TALK
O
X
TALK
O
Off isolation is the resistance (measured in −dB) between the input and output with the switch OFF.
IRR
Magnitude variation between analog input and output pins when the switch is ON and the dc offset of composite-video
signal varies at the analog input pin. In the NTSC standard, the frequency of the video signal is 3.58 MHz, and dc offset is
from 0 to 0.714 V.
D
G
Phase variation between analog input and output pins when the switch is ON and the dc offset of composite-video signal
varies at the analog input pin. In the NTSC standard, the frequency of the video signal is 3.58 MHz, and dc offset is from 0
to 0.714 V.
D
P
I
Static power-supply current
CC
I
Variation of I for a change in frequency in the control (EN, IN) inputs
CC
CCD
∆I
This is the increase in supply current for each control input that is at the specified voltage level, rather than V
or GND.
CC
CC
3
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SCDS164A – MAY 2004 − REVISED MAY 2004
functional diagram (positive logic)
4
2
3
S1
S2
D
A
A
A
7
5
6
D
B
S1
S2
B
B
9
11
10
S1
S2
D
C
C
C
12
14
13
D
D
S1
S2
D
D
1
IN
Control
Logic
15
EN
4
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SCDS164A – MAY 2004 − REVISED MAY 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IN
I/O
IK IN
I/O port clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/OK I/O
ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Continuous current through V
I/O
or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 5): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
(see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
(see Note 5): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 6): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground, unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. V and V are used to denote specific conditions for V
I/O
.
I
O
4. I and I are used to denote specific conditions for I .
I
O
I/O
5. The package thermal impedance is calculated in accordance with JESD 51-7.
6. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 7)
MIN
4
MAX
5.5
5.5
0.8
2
UNIT
V
V
V
V
Supply voltage
CC
IH
IL
High-level control input voltage (EN, IN)
Low-level control input voltage (EN, IN)
Analog I/O voltage
2
V
0
V
V
0
V
ANALOG
T
A
Operating free-air temperature
−40
85
°C
NOTE 7: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
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ꢋꢌ ꢀ ꢑ ꢔ ꢒꢋ ꢒꢐ ꢎ ꢁꢀꢈꢀꢍ ꢕꢍ ꢁ ꢌ ꢁꢀꢈꢐ ꢓꢍ
SCDS164A – MAY 2004 − REVISED MAY 2004
electrical characteristics over recommended operating free-air temperature range, V
(unless otherwise noted)
= 5 V 10%
CC
†
PARAMETER
TEST CONDITIONS
I = −18 mA
IN
MIN TYP
MAX
UNIT
V
V
V
EN, IN
EN, IN
EN, IN
EN, IN
V
= 4.5 V,
−1.8
IK
CC
150
mV
µA
hys
I
I
V
V
= 5.5 V,
= 5.5 V,
V
IN
V
IN
V
O
and V
and V
= V
CC
1
1
IH
CC
EN
= GND
µA
IL
CC
EN
= 0 to 5.5 V,
‡
§
I
I
V
V
= 5.5 V,
= 5.5 V,
Switch OFF
Switch ON
1
µA
OZ
CC
V = 0,
I
V
= 0.5 V ,
CC
O
50
mA
OS
CC
V = 0,
I
I
I
V
V
V
= 0,
V
= 0 to 5.5 V,
= 0,
V = 0
I
1
3
µA
µA
off
CC
CC
CC
O
= 5.5 V,
= 5.5 V,
I
Switch ON or OFF
CC
I/O
∆I
EN, IN
One input at 3.4 V,
D and S ports open,
f = 1 MHz
Other inputs at V
CC
or GND
2.5
mA
CC
V
CC
V
EN
= 5.5 V,
= GND,
mA/
MHz
I
V
IN
input switching 50% duty cycle
0.25
CCD
C
C
EN, IN
D port
S port
V
or V
= 0,
3.5
6
pF
IN
IN EN
f = 1 MHz,
Outputs open
V = 0,
I
Switch OFF
Switch ON
pF
OFF
4
f = 1 MHz,
Outputs open
C
r
V = 0,
I
14
pF
ON
¶
V = 1 V,
I
I
I
= 13 mA,
= 26 mA,
R
R
= 75 Ω
= 75 Ω
3
7
7
O
L
L
V
CC
= 4.5 V
Ω
on
V = 2 V,
I
10
O
V , V , I , and I refer to I/O pins.
I
O
I
O
†
‡
§
¶
All typical values are at V
= 5 V (unless otherwise noted), T = 25°C.
CC
A
For I/O ports, I
The I
OS
includes the input leakage current.
test is applicable to only one ON channel at a time. The duration of this test is less than one second.
OZ
Measured by the voltage drop between the D and S terminals at the indicated current through the switch. ON-state resistance is determined by
the lower of the voltages of the two (D or S) terminals.
switching characteristics over recommended operating free-air temperature range,
= 5 V 10%, R = 75 Ω, C = 20 pF (unless otherwise noted) (see Figure 5)
V
CC
L
L
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
TYP
MAX
UNIT
t
D
D
2.5
1.1
6
6
ns
ns
S
S
ON
t
OFF
dynamic characteristics over recommended operating free-air temperature range, V
(unless otherwise noted)
= 5 V 10%
CC
†
PARAMETER
TEST CONDITIONS
f = 3.58 MHz, see Figure 6
f = 3.58 MHz, see Figure 6
MIN TYP
MAX
UNIT
%
#
D
D
R
R
R
R
R
= 150 Ω,
0.64
0.1
G
L
L
L
L
L
#
= 150 Ω,
Deg
MHz
dB
P
BW
= 150 Ω, see Figure 7
= 150 Ω,
300
X
TALK
f = 10 MHz,
R
= 10 Ω, see Figure 8
IN
−63
−60
O
= 150 Ω,
f = 10 MHz, see Figure 9
dB
IRR
†
#
All typical values are at V
= 5 V (unless otherwise noted), T = 25°C.
A
CC
D
and D are expressed in absolute magnitude.
G
P
6
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SCDS164A – MAY 2004 − REVISED MAY 2004
OPERATING CHARACTERISTICS
0
0
0.08
0.0
−0.1
0.07
−1
−10
Differential Phase
0.06
−0.2
−2
−3
Phase
−0.3
−20
−30
−40
−50
−60
0.05
0.04
0.03
0.02
−0.4
−0.5
−4
−5
−0.6
−0.7
−0.8
−0.9
−1.0
Differential Gain
Gain
0.01
0.00
−6
−7
−0.01
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
− V
1
1
10
100
1000
V
BIAS
Frequency − MHz
Differential Phase at 0.714, 0.056 Degree
Differential Gain at 0.714, −0.63%
Phase at −3-dB Frequency, 35 Degrees
Gain −3 dB at 460 MHz
Figure 1. Gain/Phase vs Frequency
Figure 2. Differential Gain/Phase vs V
BIAS
160
0
250
200
150
0
−10
−20
140
120
100
−10
−20
−30
−40
−50
−60
−70
−80
−90
−30
−40
Phase
80
60
40
20
0
−50
−60
Phase
100
50
0
Off Isolation
Crosstalk
−70
−80
−90
1
10
100
Frequency − Mhz
1000
1
100
10
1000
Frequency − MHz
Phase at 10 MHz, −90.4 Degrees
Crosstalk at 10 MHz, −63.9 dB
Phase at 10 MHz, 88.5 Degrees
Off Isolation at 10 MHz, −60 dB
Figure 3. Off Isolation vs Frequency
Figure 4. Crosstalk vs Frequency
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃꢄ ꢄ ꢅ
ꢆꢇ ꢈ ꢉ ꢁꢊ ꢉꢀ ꢋꢌ ꢉꢍ ꢎꢏꢈ ꢐꢉꢋ ꢌ ꢉ ꢀꢑ ꢃ ꢌ ꢉꢍ ꢒ ꢁꢋ ꢌ ꢀꢓ ꢑ
ꢋꢌ ꢀ ꢑ ꢔ ꢒꢋ ꢒꢐ ꢎ ꢁꢀꢈꢀꢍ ꢕꢍ ꢁ ꢌ ꢁꢀꢈꢐ ꢓꢍ
SCDS164A – MAY 2004 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
Input Generator
V
IN
IN
50 Ω
50 Ω
V
G1
S1
DUT
EN
V
V
V
S1
O
D
C
L
S2
R
(see Note A)
L
S2
R
V
S1
V
S2
C
V
CC
TEST
L
L
5 V 0.5 V
5 V 0.5 V
75
75
20
20
GND
3 V
3 V
t
ON
GND
5 V 0.5 V
5 V 0.5 V
75
75
20
20
GND
3 V
3 V
t
OFF
GND
TEST CIRCUIT
50% 50%
Output
Control
(V
3 V
0 V
)
IN
t
t
ON
OFF
Analog Output
Waveform
V
OH
90%
90%
(V
O
)
0 V
VOLTAGE WAVEFORMS
AND t TIMES
t
ON
OFF
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
C. The outputs are measured one at a time, with one transition per measurement.
Figure 5. Test Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄ ꢄꢅ
ꢆ ꢇꢈꢉ ꢁꢊ ꢉꢀ ꢋ ꢌꢉꢍ ꢎꢏꢈꢐꢉꢋ ꢌ ꢉꢀ ꢑ ꢃꢌ ꢉꢍꢒ ꢁ ꢋꢌ ꢀꢓ ꢑ
ꢋ ꢌꢀ ꢑ ꢔ ꢒ ꢋ ꢒ ꢐꢎꢁꢀꢈꢀ ꢍ ꢕꢍꢁ ꢌ ꢁꢀꢈ ꢐꢓ ꢍ
SCDS164A – MAY 2004 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
V
BIAS
BIAS
Network Analyzer
(HP8753ES)
Sawtooth
Waveform Generator
P1
P2
V
CC
S1
A
D
A
R
= 150 Ω
L
IN
DUT
V
IN
EN
V
EN
NOTE A: For additional information on measurement method, refer to the TI application report, Measuring Differential Gain and Phase, literature
number SLOA040.
Figure 6. Test Circuit for Differential Gain/Phase Measurement
Differential gain and phase are measured at the output of the ON channel. For example, when V = 0, V = 0, and
IN
EN
D is the input, the output is measured at S1 .
A
A
HP8753ES setup
Average = 20
RBW = 300 Hz
ST = 1.381 s
P1 = −7 dBM
CW frequency = 3.58 MHz
sawtooth waveform generator setup
V
= 0 to 1 V
BIAS
Frequency = 0.905 Hz
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃꢄ ꢄ ꢅ
ꢆꢇ ꢈ ꢉ ꢁꢊ ꢉꢀ ꢋꢌ ꢉꢍ ꢎꢏꢈ ꢐꢉꢋ ꢌ ꢉ ꢀꢑ ꢃ ꢌ ꢉꢍ ꢒ ꢁꢋ ꢌ ꢀꢓ ꢑ
ꢋꢌ ꢀ ꢑ ꢔ ꢒꢋ ꢒꢐ ꢎ ꢁꢀꢈꢀꢍ ꢕꢍ ꢁ ꢌ ꢁꢀꢈꢐ ꢓꢍ
SCDS164A – MAY 2004 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
Network Analyzer
(HP8753ES)
V
BIAS
P1
P2
V
CC
D
S1
A
A
R
= 150 Ω
L
IN
DUT
V
IN
EN
V
EN
Figure 7. Test Circuit for Frequency Response (BW)
Frequency response is measured at the output of the ON channel. For example, when V = 0, V
= 0, and D is
IN
EN
A
the input, the output is measured at S1 . All unused analog I/O ports are left open.
A
HP8753ES setup
Average = 4
RBW = 3 kHz
V
= 0.35 V
BIAS
ST = 2 s
P1 = 0 dBM
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄ ꢄꢅ
ꢆ ꢇꢈꢉ ꢁꢊ ꢉꢀ ꢋ ꢌꢉꢍ ꢎꢏꢈꢐꢉꢋ ꢌ ꢉꢀ ꢑ ꢃꢌ ꢉꢍꢒ ꢁ ꢋꢌ ꢀꢓ ꢑ
ꢋ ꢌꢀ ꢑ ꢔ ꢒ ꢋ ꢒ ꢐꢎꢁꢀꢈꢀ ꢍ ꢕꢍꢁ ꢌ ꢁꢀꢈ ꢐꢓ ꢍ
SCDS164A – MAY 2004 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
Network Analyzer
V
BIAS
(HP8753ES)
P1
P2
V
CC
D
S1
A
A
†
50 Ω
IN
R
= 150 Ω
L
V
IN
DUT
EN
V
EN
D
S1
B
B
R
= 10 Ω
R = 150 Ω
L
IN
†
A 50-Ω termination resistor is needed for the network analyzer.
Figure 8. Test Circuit for Crosstalk (X
)
TALK
Crosstalk is measured at the output of the nonadjacent ON channel. For example, when V = 0, V
= 0, and D
A
IN
EN
is the input, the output is measured at S1 . All unused analog input (D) ports and output (S) ports are connected to
B
GND through 10-Ω and 50-Ω pulldown resistors, respectively.
HP8753ES setup
Average = 4
RBW = 3 kHz
V
= 0.35 V
BIAS
ST = 2 s
P1 = 0 dBM
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃꢄ ꢄ ꢅ
ꢆꢇ ꢈ ꢉ ꢁꢊ ꢉꢀ ꢋꢌ ꢉꢍ ꢎꢏꢈ ꢐꢉꢋ ꢌ ꢉ ꢀꢑ ꢃ ꢌ ꢉꢍ ꢒ ꢁꢋ ꢌ ꢀꢓ ꢑ
ꢋꢌ ꢀ ꢑ ꢔ ꢒꢋ ꢒꢐ ꢎ ꢁꢀꢈꢀꢍ ꢕꢍ ꢁ ꢌ ꢁꢀꢈꢐ ꢓꢍ
SCDS164A – MAY 2004 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
Network Analyzer
(HP8753ES)
V
BIAS
P1
P2
V
CC
D
S1
A
A
R
R
= 150 Ω
= 150 Ω
L
IN
DUT
V
IN
S2
A
EN
†
50 Ω
L
V
EN
†
A 50-Ω termination resistor is needed for the network analyzer.
Figure 9. Test Circuit for Off Isolation (O
)
IRR
Off-isolation is measured at the output of the OFF channel. For example, when V = V , V
= 0, and D is the
A
IN
CC EN
input, the output is measured at S1 . All unused analog input (D) ports are left open, and output (S) ports are
A
connected to GND through 50-Ω pulldown resistors.
HP8753ES setup
Average = 4
RBW = 3 kHz
V
= 0.35 V
BIAS
ST = 2 s
P1 = 0 dBM
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃꢄ ꢅꢆꢂ ꢄꢇ ꢈ ꢄꢉꢄ
MSOI004E JANUARY 1995 − REVISED MAY 2002
DBQ (R−PDSO−G**)
PLASTIC SMALL−OUTLINE PACKAGE
0.012 (0,30)
0.008 (0,20)
0.025 (0,64)
24
0.005 (0,13)
13
0.157 (3,99) 0.244 (6,20)
0.150 (3,81) 0.228 (5,80)
0.008 (0,20) NOM
Gauge Plane
1
12
A
0.010 (0,25)
0°−8°
0.035 (0,89)
0.016 (0,40)
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
PINS **
16
20
24
28
DIM
0.197
(5,00)
0.344
(8,74)
0.344
(8,74)
0.394
(10,01)
A MAX
A MIN
0.189
(4,80)
0.337
(8,56)
0.337
(8,56)
0.386
(9,80)
M0−137
VARIATION
D
AB
AD
AE
AF
4073301/F 02/2002
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO−137.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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