TSB15LV01IPFC [TI]
VIDEO SIGNAL PROCESSOR WITH IEEE 1394 LINK LAYER CONTROLLER; 符合IEEE 1394链路层控制器视频信号处理器
| 型号： | TSB15LV01IPFC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | VIDEO SIGNAL PROCESSOR WITH IEEE 1394 LINK LAYER CONTROLLER |
| 文件： | 总74页 (文件大小：415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢆꢊ ꢋ ꢌ ꢍ ꢁ ꢊꢎ ꢏ ꢐꢑ ꢒ ꢓꢍ ꢔꢌ ꢕꢕꢍꢓ ꢖ ꢊꢗꢘ ꢉ ꢙꢙ ꢙꢚ ꢃꢛꢜꢝ ꢅꢊꢏꢞ
ꢅ ꢐꢟ ꢌꢓ ꢠ ꢍ ꢏꢗ ꢓꢍ ꢑꢑꢌ ꢓ
Data Manual
2002
Mixed Signal Products
SLLS425A
IMPORTANT NOTICE
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Copyright 2002, Texas Instruments Incorporated
Contents
Section
Title
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
1.1
1.2
1.3
1.4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
2
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
2.1
1394 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
Isochronous Versus Asynchronous Protocols . . . . . . . . . . . 2–1
Packet Format/Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
1394 Serial Bus Management Capabilities . . . . . . . . . . . . . 2–6
PHY/Link Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Enabling the Transmission of Video . . . . . . . . . . . . . . . . . . . 2–7
2.2
Sensor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
2.2.1
2.2.2
2.2.3
CCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
Analog Front End Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
CCD/AFE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
2.3
2.4
STAT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
Motor Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
2.4.1
2.4.2
2.4.3
Motor Driver Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
Positioning System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
Pushbutton Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
2.5
2.6
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
Video Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
2.6.7
2.6.8
2.6.9
2.6.10
2.6.11
De-Mosaicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
Brightness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
Gain and Exposure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
Sharpness and Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28
White Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29
Gamma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29
YUV Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29
Antiblooming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30
Backlight Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30
White Spot Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30
Test Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
3
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
3.1
3.2
1394 Node Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Top-Level Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
iii
3.3
Register Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
3.3.1
3.3.2
3.3.3
1394 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Inquiry Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Control and Configuration Registers . . . . . . . . . . . . . . . . . . . 3–14
4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4.1
Absolute Maximum Ratings Over Operating Free-Air
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4.2
4.3
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Electrical Characteristics Over Recommended Ranges of
Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . 4–2
5
6
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
List of Illustrations
Figure
Title
Page
2–1 Top-Level Sensor Interface Signal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
2–2 TLV990 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
2–3 AFE Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
2–4 Sensor Interface Timing for ICX098/LZ24BP Sensor, Full Frame . . . . . . . . 2–13
2–5 Sensor Interface Timing for ICX084 Sensor, Full Frame . . . . . . . . . . . . . . . . 2–14
2–6 Sensor Interface Timing for TC237 Sensor, Full Frame . . . . . . . . . . . . . . . . . 2–15
2–7 Sensor Interface Timing for ICX098/LZ24BP Sensor,
Start of Frame Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
2–8 Sensor Interface Timing for ICX084 Sensor, Start of Frame . . . . . . . . . . . . . 2–17
2–9 Sensor Interface Timing for TC237 Sensor, Start of Frame . . . . . . . . . . . . . 2–18
2–10 Sensor Interface Timing for ICX098/LZ24BP/ICX084 Sensor,
Start of Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19
2–11 Sensor Interface Timing for TC237 Sensor, Start of Line . . . . . . . . . . . . . . 2–20
2–12 Sensor Interface Timing for All Sensors, Horizontal Drive . . . . . . . . . . . . . 2–21
2–13 STATn Motor Select Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
2–14 Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
2–15 Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
2–16 Gain and Exposure Automatic and Manual Controls . . . . . . . . . . . . . . . . . . 2–28
2–17 TSB15LV01 Built-In Test Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
3–1 TSB15LV01 Root Directory Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
iv
List of Tables
Table
Title
Page
2–1 Isochronous Data Block Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
2–2 Data Payload Per Isochronous Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
2–3 Video Data Payload Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
2–4 Data Structure for Y, R, G, and B Data Components . . . . . . . . . . . . . . . . . . . 2–4
2–5 Data Structure for U and V Data Components . . . . . . . . . . . . . . . . . . . . . . . . 2–4
2–6 Asynchronous Quadlet Write Request Packet Format . . . . . . . . . . . . . . . . . . 2–4
2–7 Asynchronous Block Write Request Packet Format . . . . . . . . . . . . . . . . . . . . 2–5
2–8 Asynchronous Quadlet Read Request Packet Format . . . . . . . . . . . . . . . . . 2–6
2–9 Asynchronous Block Read Request Packet Format . . . . . . . . . . . . . . . . . . . . 2–6
2–10 Approved CCD Sensors and Recommended Drivers . . . . . . . . . . . . . . . . . 2–8
2–11 Values Transmitted to AFE via Serial Interface . . . . . . . . . . . . . . . . . . . . . . . 2–11
2–12 AFE Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
2–13 ICX098/LZ24BP Full Frame Timing Parameters . . . . . . . . . . . . . . . . . . . . . . 2–13
2–14 ICX084 Full Frame Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
2–15 TC237 Full Frame Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
2–16 ICX098/LZ24BP Frame Start Timing Parameters . . . . . . . . . . . . . . . . . . . . . 2–16
2–17 ICX084 Frame Start Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
2–18 TC237 Frame Start Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
2–19 ICX098/LZ24BP/ICX084 Line Start Timing Parameters . . . . . . . . . . . . . . . 2–19
2–20 TC237 Line Start Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
2–21 Horizontal Drive Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
2–22 Status Terminal Functions Determined by STATn Register Fields . . . . . . . 2–22
2–23 Stepper Drive Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
2–24 EEPROM Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
2–25 CCD Sensor Processing Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
2–26 Backlight Compensation Hot Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30
3–1 TSB15LV01 Register Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
3–2 1394 Address Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
3–3 Top-Level Memory Map: 1394 Memory (Core CSRs) . . . . . . . . . . . . . . . . . . 3–2
3–4 Top-Level Memory Map: 1394 Memory (Device Configuration ROM) . . . . . 3–3
3–5 Top-Level Memory Map: Inquiry Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
3–6 Top-Level Memory Map: Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
3–7 Top-Level Memory Map: Configuration Registers . . . . . . . . . . . . . . . . . . . . . . 3–5
3–8 Implemented Core CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
3–9 Serial-Bus-Dependent CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
3–10 Base Configuration ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
3–11 Node_Unique_ID Leaf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
v
3–12 Unit Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
3–13 Unit-Dependent Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
3–14 Vendor Name Leaf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
3–15 Model Name Leaf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
3–16 Video Format Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
3–17 Video Format Register Proper Values for TSB15LV01 . . . . . . . . . . . . . . . . 3–8
3–18 Video Format Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
3–19 Video Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
3–20 Video Mode Proper Values for TSB15LV01 . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
3–21 Video Mode Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
3–22 Video Frame Rate Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
3–23 Video Frame Rate Proper Values for TSB15LV01 . . . . . . . . . . . . . . . . . . . . 3–10
3–24 Video Frame Rate Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
3–25 Memory Map for Basic Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
3–26 Basic Function Register Proper Values for TSB15LV01 . . . . . . . . . . . . . . . 3–11
3–27 Field Descriptions for Basic Function Register . . . . . . . . . . . . . . . . . . . . . . . 3–11
3–28 Memory Map for Feature Presence Registers . . . . . . . . . . . . . . . . . . . . . . . 3–12
3–29 Feature Presence Registers Proper Values for TSB15LV01 . . . . . . . . . . . 3–12
3–30 Field Descriptions for Feature Presence Registers . . . . . . . . . . . . . . . . . . . 3–12
3–31 Memory Map for Feature Elements Inquiry Registers . . . . . . . . . . . . . . . . . 3–13
3–32 Feature Elements Registers Proper Values for TSB15LV01 . . . . . . . . . . . . 3–14
3–33 Field Descriptions for Feature Elements Registers . . . . . . . . . . . . . . . . . . . 3–14
3–34 Camera Initialize Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
3–35 Camera Initialize Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 3–15
3–36 Memory Map for Camera Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
3–37 Field Descriptions for Camera Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
3–38 Memory Map for Feature Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
3–39 Field Descriptions for Feature Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
3–40 Configuration Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19
3–41 Field Descriptions for Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . 3–20
vi
1 Introduction
The TSB15LV01 is a video signal processor integrated with a 1394 link layer controller. It is designed to be the center
of a host-controlled, full-motion color camera when coupled with a 1394 PHY, CCD sensor and driver, analog front
end, and an external EEPROM device. A camera based on the TSB15LV01 is compliant with the IEEE 1394a
standard and the 1394 Trade Association’s Digital Camera specification, Draft 1.04.
The TSB15LV01 offers the advantage of 24-bit true-color digital video processing. This gives superior video quality
at higher sustained data rates. Isochronous transfer of the video data and asynchronous control of the camera are
accomplished via the 1394 high-speed serial bus, operating at data rates of up to 400 Mbits/s. This bus allows
noncompressed full-motion digital video at rates of 30 frames/sec. Use of this serial connection eliminates the need
for expensive video capture cards. The chipset supports the YUV 4:1:1, YUV 4:2:2, YUV 4:4:4, and RGB 24-bit
formats.
The video signal processor (VSP) portion of the device incorporates proprietary digital image processing techniques,
implemented with an advanced digital signal processing (DSP) ASIC. These techniques enable a camera to achieve
excellent color accuracy and resolution. The use of a custom advanced CMOS ASIC process allows for both the
advanced digital image processing techniques and for advanced color space conversion. This allows the multiple
output formats required for a multipurpose video conferencing camera. Use of this advanced, low-power CMOS
process also enables the camera to be powered by a notebook computer operating on battery power. The device is
designed to work with CCDs that have a pixel resolution of 640(H) y 480(V). This resolution meets the VGA square
pixel standards.
The 1394 link layer controller is capable of up to 400 Mbits/s operation and is compatible with both the IEEE
1394–1995 and 1394a standards. The TSB15LV01 implements all registers and address space required by the 1394
Trade Association’s Digital Camera specification, Draft 1.04 (hereafter referred to as the Digital Camera
Specification).
The device supports packet speeds of up to 400 Mbits/s, but the maximum bandwidth consumed by the device is
200 Mbits/s. This means that a TSB15LV01-based camera leaves at least 200 Mbits/s available to other functions.
With its balance of features and low cost, a system based on TSB15LV01 is well-suited for applications such as:
•
•
•
•
•
•
•
•
•
•
PC Video Camera
Video Conferencing
Video Capture
Still Picture Capture
Set-Top Boxes
Video Phone
Gaming
Webcam
Robotics
Security
1–1
1.1 Features
•
•
•
Compatible With 1394 Trade Association’s Digital Camera Specification, Draft 1.04
1394a Link Layer Controller With 400 Mbits/s Capability
Support for Several CCD Sensors
–
–
–
Sony ICX084AK, ICX098AK
Sharp LZ24BP
Texas Instruments TC237
•
•
Integrated CCD (Charge-Coupled Device) and CDS (Correlated Double Sampling) Pulse Timer With
Programmable Pulse Skew
Video Controls
–
–
–
–
–
–
–
Brightness (Auto/Manual)
Exposure (Auto/Manual)
Sharpness (Manual)
Saturation (Manual)
White Balance (Auto/Manual)
Gamma (Manual)
Backlight Compensation (Manual)
•
•
•
•
Three Stepper Motor Controls for Focus/Zoom/Tilt or Other Motorized Functions
EEPROM Interface
Programmable Status/Test Terminals
Seamlessly Connects to TI’s 1394 Physical Layer Devices
1–2
1.2 Functional Block Diagram
CCD Interface;
Analog Front End (AFE)
Video Data Interface
Analog Front End (AFE)
Serial Interface
AFE Sample/Hold and
Black Clamp Interface
Timing
Generator
Pipelined Video
Signal Processor
Controls:
RGB / YUV
and Quadlet
Data Formatter
Motor
Gain White Balance
Gamma
Motor
Control
Interface
Brightness
Saturation
Sharpness
STAT
Interface
Control
Data
Master
Controller
FIFO Buffer
Feature
Control/
Configure
EEPROM
Interface
ASYNC Command
Processor
Register RAM
Host
Interface
Data
Mover
CFR
ASYNC
FIFO
Link Core
1394 Link Layer
1394 PHY I/F
1–3
1.3 Terminal Assignments
TQFP PACKAGE
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
VCC
CLAMP
LREQ
PG1
SCLK
VCC
CTL0
CTL1
GND
D0
D1
D2
D3
VCC
D4
D5
D6
D7
GND
STAT0
STAT1
STAT2
1
2
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SV
SR
NC
3
4
5
OBCLP
6
GND
7
SERIAL_CS
SERIAL_DATA
SERIAL_CLK
NC
8
TSB15LV01PFC
TSB15LV01IPFC
(TQFP)
9
10
11
12
13
14
15
16
17
18
19
20
GND
ADCLK
VCC
PIXEL_DATA9
PIXEL_DATA8
PIXEL_DATA7
PIXEL_DATA6
PIXEL_DATA5
TEST_SE_IN
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC – No internal connection
1–4
1.4 Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Analog Front End (AFE) Interface
ADCLK
13
O
ADC clock. Triggers the AFE’s analog/digital converter to sample the amplifier output, and clocks the
digital data out of the AFE to the TSB15LV01.
CLAMP
OBCLP
2
6
O
O
Pulse that instructs AFE to electrically clamp the ac-coupled pixel pulse to a fixed reference voltage.
Optical Black Clamp pulse. Instructs the AFE to clamp its ADC output to a digital black reference value.
Samples occur during the black pixel portion of the CCD’s image signal.
PIXEL_DATA9–
PIXEL_DATA0
15–19,
22–26
I
Data bus that inputs processed video data from the AFE’s analog/digital converter. PIXEL_DATA_IN9 is
the MSB of these 10 bits.
SERIAL _CS
8
O
Serial interface chip select. Allows programming of AFE control registers. Signifies the beginning of data
transmission on SERIAL_DATA.
SERIAL _DATA
SERIAL _CLK
SR
9
10
4
O
O
O
Serial interface digital data input. Allows programming of AFE control registers.
Serial interface clock. Allows programming of AFE control registers. Clocks data out of SERIAL_DATA.
CCD reset-pedestal sampling pulse. Triggers the AFE to sample the reset pedestal of the pixel pulse
received from the CCD image sensor.
SV
3
O
O
CCD video data sampling pulse. Triggers the AFE to sample the data pedestal of the pixel pulse received
from the CCD image sensor.
CCD Interface
ABD_XSUB
35
Image area clear bias. Goes high to clear the image area. This pulse performs an electronic shutter
function, controlling the integration time of the CCD image. Performed at the beginning of every frame.
ABSP_XSG
H2
32
37
29
39
O
O
O
O
Antiblack smear. Goes low to increase the pixel well size during parallel transfer.
Horizontal transfer 2. Horizontal charge transfer control for CCD.
IAG_XV3
RST_RG
Image-area gate/vertical transfer 3. Charge transfer control for CCD.
Reset gate. Reset pulse for the CCD’s charge-detection amplifier, generated for every pixel moved out of
the CCD.
SAG_XV1
SRG_H1
XV2
34
38
33
O
O
O
Storage-area gate/vertical transfer 1. Charge transfer control for CCD.
Serial register gate/horizontal transfer 1. Horizontal charge transfer control for CCD.
Vertical transfer 2. Charge transfer control for CCD.
PHY Interface
CTL1,
CTL0
55
56
I/O Control 1 and control 0 of the PHY-link control bus.
D[7..0]
45–48, I/O Data signals of the PHY-link data bus. Data is expected on D0-D1 at 100 Mbits/s, D0-D3 at 200 Mbits/s,
50–53
and D0-D7 at 400 Mbits/s. D0 is the MSB.
LREQ
RESET
SCLK
60
I/O Makes bus requests and accesses to the PHY.
62
I
I
Reset, active low. The asynchronous reset to the link controller.
System clock. SCLK is a 49.152-MHz clock supplied by the PHY.
EEPROM Interface
58
EEPROM_CS
EEPROM_SCLK
EEPROM_SI
66
64
65
68
O
O
O
I
EEPROM chip select.
EEPROM serial data clock.
EEPROM serial data output.
EEPROM_SO
EEPROM serial data input.
1–5
TERMINAL
NAME
I/O
DESCRIPTION
NO.
Motor Control Interface
IR_SIG
75
I
Position feedback from infrared detectors on motorized mechanisms. Applies to the stepper motor
currently selected by the STATn terminals.
MOTOR_MINUS
MOTOR_PLUS
PHASE2_B
73
74
77
I
I
Negative pushbutton input. Applies to the stepper motor currently selected by the STATn terminals.
Positive pushbutton input. Applies to the stepper motor currently selected by the STATn terminals.
O
Drive signal for stepper motors, phase 2, signal B. Applies to the stepper motor currently selected by the
STATn terminals.
PHASE2_A
PHASE1_B
PHASE1_A
78
79
80
O
O
O
Drive signal for stepper motors, phase 2, signal A. Applies to the stepper motor currently selected by the
STATn terminals.
Drive signal for stepper motors, phase 1, signal B. Applies to the stepper motor currently selected by the
STATn terminals.
Drive signal for stepper motors, phase 1, signal A. Applies to the stepper motor currently selected by the
STATn terminals.
Miscellaneous Interface
CAM_POWER
28
72
O
I
Power switch. Toggles with bit in CAMERA_POWER_CNTL register, which is low upon device power up.
Used to instruct system power supply to enter power saving mode.
EN
Regulatorenable. Whenlow, thedevicesupplypowerregulatorisactive. Shouldbekeptlowduringnormal
operation.
GND
7, 12,
21, 36,
44, 54,
61, 76
Connect to ground.
NC
5, 11
59, 69
41
No connect
No connect
PG1, PG2
STAT2
STAT1
STAT0
I/O Status signals
42
43
TEST_SE_IN
TESTMODE
20
63
I
I
Factory test terminal. Connect to ground.
Factory test terminal. Connect to ground.
Power/Ground
VCC_CORE
VCC
30,70
Connect to 3.3 V.
Connect to 3.3 V.
1, 14,
27, 40,
49, 57,
67
VDD_CAP
31,71
Mid-supply. Connect to ground through a 0.1-µF capacitor.
1–6
2 Detailed Description
2.1 1394 Interface
The 1394 interface is used to connect the camera to external devices using the IEEE 1394 serial bus. This bus is
currently capable of speeds up to 400 Mbits/s and provides adequate bandwidth in which to transmit a quality
uncompressed video signal. It is assumed that the reader has a moderate level of familiarity with the 1394 serial bus.
The TSB15LV01 serves as the application, transaction, and link layers of a 1394 node. This greatly simplifies
implementation of the 1394 node, since only the physical layer remains to be implemented. This can be accomplished
by placing a 1394 PHY, such as the TSB41LV01, between the TSB15LV01 and the 1394 connector. The 1394
interface on the TSB15LV01 provides a glueless interface to the PHY.
Note that while the device supports s400 1394 packets, the maximum bandwidth consumed by the device is
200 Mbits/s. This means that a TSB15LV01-based camera leaves at least 200 Mbits/s available to other functions,
assuming all devices on the bus use s400 packets.
This section is not designed to be a tutorial on 1394. It is assumed that the reader has a basic knowledge of the 1394
serial bus. For more information on the 1394 bus, see the 1394 standard.
2.1.1 Isochronous Versus Asynchronous Protocols
There are two types of packets used in the 1394 link layer: isochronous and asynchronous. The TSB15LV01 uses
isochronous packets to send video data to the bus and asynchronous packets to exchange control/status information
with the bus.
An isochronous transaction delivers a consistent amount of data that is transferred at regular 125-µs intervals, with
simplified addressing. Reception of an acknowledge packet is not required. Allocated flows of isochronous data are
referred to as channels. Because the packets are assured to be delivered regularly, a constant data rate is achieved,
making it ideal for video. In order to assure this bandwidth, a node must first request allocation of the bus resources
from the node serving as the bus manager. The TSB15LV01 expects this to be performed by the node receiving the
video data, referred to as the host node. The TSB15LV01 is capable of being an isochronous talker. However, it is
not capable of listening to a channel of isochronous data. It is capable of transmitting isochronous data on channels
0 to 15 only.
An asynchronous transaction delivers a variable amount of data to a specific address. An acknowledge packet must
be received from the designated target node, assuring delivery of the packet. This protocol allows packets to be sent
without any prior permission or allocation. However, isochronous packets receive priority in order to maintain a
consistent data rate. The TSB15LV01 is capable of sending and receiving asynchronous packets with a payload of
up to 32 quadlets per packet. All request packets received by the device are answered with a response packet. If a
request packet is received between a request and its corresponding response packet, the device acknowledges that
packet with a busy acknowledge code.
2.1.2
Packet Format/Protocol
2.1.2.1 Isochronous Packet Format/Protocol
All video data sent from the camera is done so using isochronous communication. Before data can be sent, the node
residing in the host must first request allocation of bus resources from the node serving as the bus manager. It must
then configure the TSB15LV01’s control and configuration registers. After the first CCD image integration cycle that
follows completion of configuration, the camera will begin to send video data.
The full isochronous packet structure is shown in Table 2–1. This packet structure is defined by the 1394 standard.
2–1
Table 2–1. Isochronous Data Block Packet Format
0–7
8–15
16–23
24–31
tCode sy
data_length
tg
channel
header_CRC
data payload quadlet 1
data payload quadlet 2
.
.
.
last quadlet of data payload (padded with zeroes if necessary)
data_CRC
The fields are defined as:
•
•
•
•
•
data_length The number of bytes in the data payload field
tg
The tag field is set to zero
channel
tCode
sy
The isochronous channel number, as programmed in the ISO_CHANNEL_CNTL register
The transaction code. The code for an isochronous data block transaction is 1010b.
Synchronization value. For the first isochronous packet of a frame, this is set to 0001b.
For all other isochronous packets, this is set to zero.
•
data payload Contains the digital video information
Isochronous data is formatted differently for each video transfer mode. Table 2–2 lists all supported transfer modes.
For each mode, the table lists the total number of bits representing a single pixel. It also gives the data payload per
packet for each mode, in terms of lines, pixels, and quadlets. The payload varies for each frame rate.
Every video component, Y, U, V, R, G, and B, has 8-bit data.
Table 2–2. Data Payload Per Isochronous Packet
FRAME RATE (Frame per Second)
MODE
VIDEO FORMAT
30
15
7.5
3.75
Mode_0
160 x 120 YUV(4:4:4)
24 bits/pixel
1/2 L
80 P
60 Q
1 L
1/4 L
40 P
30 Q
1/2 L
160 P
80 Q
1 L
1/8 L
20 P
15 Q
1/4 L
80 P
Mode_1
Mode_2
Mode_3
Mode_4
Mode_5
320 x 240 YUV(4:2:2)
16 bits/pixel
1/8 L
40 P
320 P
160 Q
40 Q
1/2 L
320 P
120 Q
1/2 L
320 P
160 Q
1/2 L
320P
240Q
1/2 L
320 P
80 Q
20 Q
1/4 L
160 P
60 Q
1/4 L
160 P
80 Q
1/4 L
160P
120Q
1/4 L
160 P
40 Q
†
2 L
640 x 480 YUV(4:1:1)
12 bits/pixel
1280 P
480 Q
640 P
240 Q
†
1 L
640 x 480 YUV(4:2:2)
16 bits/pixel
640 P
320 Q
†
1 L
640 x 480 RGB
24 bits/pixel
640 P
480 Q
1 L
†
2 L
640 x 480 Y (Mono)
8 bits/pixel
1280P
320 Q
640 P
160 Q
†
Requires s200 or faster packet speed, as programmed in the ISO_CHANNEL/SPEED_CNTL
register. The others can use s100 as well.
Key: L: Lines/packet
P: Pixel/packet
Q: Quadlet/packet
2–2
2.1.2.2 Isochronous Video Payload
Each transfer mode requires a different data format structure, each defining how the pixels are combined to build
32-bit quadlets. Table 2–3 shows the payload structure for each mode, with the quadlets broken down into individual
bytes. This data payload structure is slightly different for every video mode. In the table, N is the number of
pixels/packet, as shown in Table 2–2.
Table 2–3. Video Data Payload Structure
0–7
8 –15
16–23
24–31
YUV (4:4:4) format (Mode_0)
U
Y
V
Y
V
U
V
U
Y
U
Y
V
0
1
2
0
1
3
0
2
3
1
2
3
.
.
.
.
.
.
.
.
.
.
.
.
U
Y
V
Y
V
U
V
U
Y
U
Y
V
N-4
N-3
N-2
N-4
N-3
N-1
N-4
N-2
N-1
N-3
N-2
N-1
YUV (4:2:2) format (Mode_1, Mode_3)
U
U
U
Y
Y
Y
V
Y
0
2
4
0
2
4
0
2
4
1
3
5
V
Y
V
Y
.
.
.
.
.
.
.
.
.
.
.
.
U
U
U
Y
Y
Y
V
V
V
Y
Y
Y
N-6
N-4
N-2
N-6
N-4
N-2
N-6
N-4
N-2
N-5
N-3
N-1
YUV (4:1:1) format (Mode_2)
U
Y
Y
Y
Y
V
Y
V
0
Y
4
Y
7
0
2
5
0
3
4
1
4
6
U
Y
.
.
.
.
.
.
.
.
.
.
.
.
U
Y
Y
Y
Y
V
Y
U
Y
V
Y
Y
N-8
N-6
N-3
N-8
N-5
N-4
N-7
N-4
N-2
N-8
N-4
N-1
RGB format (Mode_4)
R
G
B
G
B
R
0
1
2
0
1
3
0
2
3
1
2
3
B
R
G
R
G
B
.
.
.
.
.
.
.
.
.
.
.
.
R
G
B
G
B
R
B
R
G
R
G
B
N-4
N-3
N-2
N-4
N-2
N-1
N-4
N-2
N-1
N-3
N-2
N-1
2–3
Table 2–3. Video Data Payload Structure (Continued)
0–7
8 –15
16–23
24–31
Y (Mono) format (Mode_5)
Y
Y
Y
V
U
Y
Y
Y
0
4
1
5
2
6
3
7
.
.
.
.
.
.
.
.
.
.
.
.
Y
Y
Y
V
U
Y
Y
Y
N-8
N-4
N-7
N-3
N-6
N-2
N-5
N-1
Table 2–4 shows the data structure for Y, R, G, and B video data components. All components are unsigned 8-bit
values.
Table 2–4. Data Structure for Y, R, G, and B Data Components
SIGNAL LEVEL (Decimal)
DATA (Hexadecimal)
Highest
255
254
:
0xFF
0xFE
:
1
0x01
0x00
Lowest
0
Table 2–5 shows the data structure for U and V video data components. Both components are signed 8-bit values.
Table 2–5. Data Structure for U and V Data Components
SIGNAL LEVEL (Decimal)
DATA (Hexadecimal)
Highest(+)
127
126
:
0xFF
0xFE
:
1
0x81
0x80
0x7F
:
Lowest
0
–1
:
–127
–128
0x01
0x00
Highest(–)
2.1.2.3 Asynchronous Packet Format/Protocol
Asynchronous packets are used to read status information from the TSB15LV01 and write control information to it.
These packets are formatted as defined by the 1394 standard. All reads and writes should correlate with the memory
maps as shown in section 3, Address Space.
Asynchronous reads and writes can be performed either as quadlets or as blocks. Blocks can be read in sizes of up
to 32 quadlets per packet. The structure of a quadlet write request packet is shown in Table 2–6, while the structure
of a block write request packet is shown in Table 2–7.
Table 2–6. Asynchronous Quadlet Write Request Packet Format
0–7
8–15
destination_ID
source_ID
16–23
24–31
tCode
destination_offset
tl
rt
pri
destination_offset
quadlet data
header_CRC
2–4
The fields are defined as:
•
•
destination_ID 10-bit busID concatenated with 6-bit nodeID
tl Transaction label, specified by the host that identifies this transaction. This optional value is
returned in the response packet.
•
•
•
•
•
•
•
rt Retry code. Indicates whether this packet is an attempted retry and defines retry protocol.
tCode Transaction code. The code for an asynchronous write request for quadlet data is 0000b.
pri Not used.
source_ID Identifies host node by specifying its bus and physical ID
destination_offset Address location within TSB15LV01 address space
quadlet_data Contains the value being written to the addressed location
header_CRC CRC value for the header
Table 2–7. Asynchronous Block Write Request Packet Format
0–7
8–15
destination_ID
16–23
24–31
tCode
destination_offset
tl
rt
pri
source_ID
destination_offset
extended_tcode (0000)
data_length
header_CRC
data block
.
.
.
last quadlet of data block
The fields are defined as:
•
•
destination_ID 10 bit busID concatenated with 6-bit nodeID.
tl Transaction label, specified by the host that identifies this transaction. This optional value is returned
in the response packet.
•
•
•
•
•
•
•
•
•
•
rt Retry code. Indicates whether this packet is an attempted retry and defines retry protocol.
tCode Transaction code. The code for an asynchronous write request for block data is 0001b.
pri Not used.
source_ID Identifies host node by specifying its bus and physical ID
destination_offset Address location within TSB15LV01 address space
data length Specifies the amount of data being sent in the data field. Maximum size is 128 bytes.
extended_tcode Reserved during write request packets
header_CRC CRC value for the header
data_field Contains the value being written to the addressed location
data_CRC CRC value for the data field
ThestructureofaquadletreadrequestpacketisshowninTable2–8, whilethestructureofablockreadrequestpacket
is shown in Table 2–9.
2–5
Table 2–8. Asynchronous Quadlet Read Request Packet Format
0–7
8–15
destination_ID
source_ID
16–23
24–31
tCode
destination_offset
tl
rt
pri
destination_offset
header_CRC
The fields are defined as:
•
•
destination_ID 10-bit busID concatenated with 6-bit nodeID
tl Transaction label is specified by the host that identifies this transaction. This optional value is
returned in the response packet.
•
•
•
•
•
•
rt Retry code. Indicates whether this packet is an attempted retry and defines retry protocol.
tCode Transaction code. The code for an asynchronous read request for quadlet data is 0100b.
pri Not used.
source_ID Identifies host node by specifying its bus and physical ID
destination_offset Address location within TSB15LV01 address space
header_CRC CRC value for the header
Table 2–9. Asynchronous Block Read Request Packet Format
0–7
8–15
destination_ID
16–23
24–31
tCode
destination_offset
tl
rt
pri
source_ID
destination_offset
extended_tcode (0000h)
header_CRC
data_length
The fields are defined as:
•
•
destination_ID 10-bit busID concatenated with 6-bit nodeID.
tl Transaction label is specified by the host that identifies this transaction. This value is reflected in the
response packet that corresponds to this request packet.
•
•
•
•
•
•
•
•
rt. Retry code. Indicates whether this packet is an attempted retry and defines retry protocol.
tCode Transaction code. The code for an asynchronous read request for block data is 0101b.
pri Not used
source_ID Identifies host node by specifying its bus and physical ID
destination_offset Address location within TSB15LV01 address space
data_length Specifies the amount of data being sent in the data field. Maximum size is 128 bytes.
extended_transaction_code Reserved during write request packets
header_CRC CRC value for the header
2.1.3 1394 Serial Bus Management Capabilities
Nodes on the 1394 bus may be called on to serve in a number of bus management roles following a bus reset event.
The TSB15LV01 is not designed to serve as the isochronous resource manager, a full bus manager, or the cycle
master. The contents of the configuration ROM should reflect this level of capability.
2–6
2.1.4 PHY/Link Interface
The PHY/link interface consists of the signals that connect the TSB15LV01, which serves as the link layer of the 1394
node, to a physical layer device, or PHY. This interface carries all data, control, and status information that is
transferred between the two layers.
To take full advantage of the TSB15LV01’s capabilities, a 400-Mbits/s PHY device should be used, such as TI’s
TSB41LV01.
2.1.4.1 Principles of Operation
The TSB15LV01 PHY/link interface consists of the SCLK, CTL0-CTL1, D0-D7, LREQ, and RESET terminals. The
PHY’s SYSCLK terminal provides a 49.152-MHz interface clock to the TSB15LV01’s SCLK terminal. All control and
data signals are synchronized to, and sampled on, the rising edge of SYSCLK.
The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data
between the PHY and TSB15LV01.
The D0-D7 terminals form a bidirectional data bus, which is used to transfer status information, control information,
or packet data between the devices. In s100 operation only the D0 and D1 terminals are used; in s200 operation only
the D0-D3 terminals are used; and in s400 operation all D0-D7 terminals are used for data transfer. When the PHY
is in control of the D0-D7 bus, unused Dn terminals are driven low during s100 and s200 operations. When the
TSB15LV01 is in control of the D0-D7 bus, unused Dn terminals are ignored by the PHY.
The LREQ terminal is used by the TSB15LV01 to send serial service requests to the PHY in order to request access
to the serial-bus for packet transmission.
The PHY normally controls the CTL0-CTL1 and D0-D7 bidirectional buses. The TSB15LV01 is allowed to drive these
buses only after it has been granted permission to do so by the PHY. There are three operations that may occur on
the PHY-link interface: link service request, data transmit, and data receive. The TSB15LV01issues a service request
when it wants to request the PHY to gain control of the 1394 serial bus in order to transmit a packet.
The PHY may initiate a status transfer autonomously. The PHY initiates a receive operation whenever a packet is
received from the 1394 serial bus. The PHY initiates a transmit operation after winning control of the serial bus
following a bus request by the TSB15LV01. The transmit operation is initiated when the PHY grants control of the
interface to the TSB15LV01.
For details on how the PHY/link interface operates, consult the 1394 specification.
2.1.5 Enabling the Transmission of Video
2.1.5.1 Enabling Isochronous Video Streaming
To enable the streaming of isochronous video data, the function control registers must be configured properly, as
described in section 3.3.3.1.2. The last register to be written should be the CAMERA_POWER_CNTLregister, which
asserts the CAM_POWER terminal (activating the CCD circuitry, if the signal is utilized), begins processing data from
the AFE interface, and begins transmitting isochronous data.
2.1.5.2 Enabling One-Shot Video Transmission
Alternatively to transmitting an isochronous stream of video data, the one-shot feature can be utilized. With this
feature, a single frame is sent using the same isochronous packet structure. It is activated by asserting the one_shot
field of the ONE_SHOT_CNTL register. Note that in order to use this feature, isochronous video streaming should
be disabled via the ISO_EN_CNTL register.
When the feature is activated, the device automatically powers up the camera, activates isochronous transmission,
sends a single image, then deactivates isochronous data and powers down the camera.
2.2 Sensor Interface
The TSB15LV01 obtains its raw video data from a charge-coupled device (CCD) sensor. This information is sent to
an analog front end (AFE) that amplifies the analog video information provided by the CCD, performs correlated
double sampling (CDS) and gain, and converts it to a digital format recognizable by the TSB15LV01.
2–7
Figure 2-1 shows the top-level signal flow in the sensor interface.
Drive Signals
CCD Drivers
CCD
Sensor
Pixel
Pulses
CCD I/F
Sample/Hold I/F
Black Clamp I/F
TSB15LV01
AFE
Serial I/F
Video Data I/F
Figure 2–1. Top-Level Sensor Interface Signal Flow
2.2.1 CCD Interface
2.2.1.1 General Description
The video data is sourced by a CCD sensor. The TSB15LV01 contains a CCD timing generator for the approved
sensors. Some of these signals must pass through a driver circuit to undergo voltage shifting.
Because the timing of the CCD interface is closely integrated with the timing of the analog front end, this topic is
discussed jointly in section 2.2.3, CCD/AFE Timing.
2.2.1.2 Configuring for Different CCD Sensors
The TSB15LV01 is designed to be used with several different CCD sensors and contains the necessary logic to drive
each of them. The ccd_sel field of the AFE_SETUP_CNFG register must be set to the correct value, identified in
section 3.3.3.2, Configuration Registers. If this field selects the TC237 CCD, field color_bw of
VIDEO_OPTIONS_CNFG register must also be set to black and white, since this is a black and white sensor.
Otherwise, it should be set to color.
2.2.1.3 External Pulse Drivers
As with nearly all CCD applications, the TSB15LV01 requires use of a dedicated driver chip for the vertical drive
pulses. This device performs level-shifting to high-voltage rails, as well as some logic functions. Table 2–10 shows
the approved sensors with their recommended driver devices.
Table 2–10. Approved CCD Sensors and Recommended Drivers
SENSOR
DRIVER
Sony CXD1267AN
Sony ICX084AK 1/3” color sensor
Sony ICX098AK 1/4” color sensor
Sharp LZ24BP 1/4” color sensor
TI TC237 1/3” black and white sensor
Sony CXD1267AN
Sony CXD1267AN or Sharp LR36685N
TI TMC57253
In addition, an external driver for horizontal pulses is required in order to drive the capacitive load of the CCD sensor.
A CMOS inverter device is recommended, such as the TI SN74LVCU04A.
2.2.2 Analog Front End Interface
Circuitry must be used in a TSB15LV01-based system that processes the pixel pulses received from the CCD and
converts them to digital data readable by the TSB15LV01. This circuit is referred to as the analog front end (AFE).
The TSB15LV01 is designed to be used with the TLV990 AFE device.
2–8
2.2.2.1 AFE Function
Figure 2-2 shows the block diagram of the TLV990.
AVDD1–5
CLVDO CLCCD CLREF
RPD RBD RMD
INT. REF.
DV
DD
DIV
DD
OE
D0
Clamp
1.2 V REF
Three
State
Latch
CDS/
MUX
10-Bit
ADC
PGA
10
CCDIN
Σ
Σ
D9
VIDEOIN
RESET
CLK
Optical
Black
Pixel Limits
8-Bit
ADC
8-Bit
ADC
PGA
Regulator
SV
Timing
and
SR
Control
Logic
BLKG
OBCLP
STBY
ADDOS
Offset
Register
Offset
Register
Digital
Averager/
Filter
10-Bit
ADC
DAC
REG
DACO1
DACO2
SCKP
CS
8-Bit
DAC
DAC
REG
Serial
Port
SCLK
SDIN
VSS
DGND
DIGND
AGND1–5
Figure 2–2. TLV990 Block Diagram
At the beginning of each image line, the AFE resets the dc bias of the incoming video data. It then performs correlated
double sampling (CDS), which effectively extracts the video data from the pixel pulse and removes the most
significant forms of noise. It then enters a programmable gain array (PGA) prior to conversion to digital form via a
10-bit analog/digital converter (ADC).
Before and after the PGA are offset correction circuits that maximize dynamic range of the video signal. The one prior
to the PGA is considered the coarse adjustment offset, while the one after the PGA is considered the fine adjustment
offset. These offset values are based either on the internal black clamping process or on values received from the
TSB15LV01 via the serial interface, depending on the brightness mode. Digital/analog converters (DACs) in the AFE
circuitry decode these values and apply them to the video signal flow. The TLV990 also contains a number of other
registers that control operation of the device, which the TSB15LV01 is able to program.
The TSB15LV01 contains an interface to the AFE that is divided into four sections. The first is the sample/hold
interface, which provides the timing signals necessary for sampling of the pixel pulses. The second is the black
clampinginterface. Thethirdistheserialinterface, whichprogramscontrolvaluesintotheAFE. Thefourthisthevideo
data interface, which is a 10-bit parallel port that receives the video from the ADC after it has been converted.
2–9
2.2.2.2 Sample/Hold Interface
This interface provides the signals necessary for dc bias clamping and correlated double sampling (CDS) of the CCD
pixel pulse.
The AFE should be capacitively coupled to the CCD output signal. At the beginning of each image line, the AFE must
clampthissignaltoareferencevoltage, therebyproperlysettingthedcbiasoftheincomingvideodata. Toaccomplish
this, the TSB15LV01 sends the CLAMP terminal low. This occurs during the CCD’s dummy pixel output, prior to the
active data pixels. CLAMP is held low only for a few pixels, but due to very low leakage current from this node, the
clamped bias holds for the duration of the line.
During the active pixels portion of the line, reset pedestal and video data pedestal of the pixel pulses are sampled.
The data pedestal is subtracted from the reset pedestal prior to amplification. The SR signal supplies the sampling
pulse for the reset pedestal, while SV supplies the sampling pulse for the video data pedestal.
2.2.2.3 Black Clamping Interface
The dc offset is directly related to the brightness of the image. The dc offset can be controlled automatically or
manually. When the TSB15LV01 is configured for autobrightness, it utilizes the black clamping feature of the TLV990.
In autobrightness mode, the AFE uses an internal feedback loop to adjust the offset. It adjusts the black pixels until
they match a digital value received from the TSB15LV01 via the serial interface. When the TSB15LV01 sends the
OBCLP terminal low, the AFE begins to acquire the digital pixel values produced by the ADC, average them, and
compare them to the black reference value. If the values are not equal, the AFE attempts to make them equal by
altering the fine adjustment offset value, which changes the offset that is summed with the signal prior to the ADC.
Ifthenecessaryadjustmentisoutofrangeforthefineoffset, theAFEcanusethecoarseadjustment. Theadjustments
are applied until the pixel data equals the black reference value.
The TSB15LV01 sends the OBCLP pulse during a time in which it knows the selected CCD is sending its black pixels.
The number of lines per image and the number of pixels per line that should be sampled are stored in internal
registers, programmed by the TSB15LV01 from the lines_smpl and pix_smpl fields, respectively, of the
VIDEO_OPTIONS_CNFG register.
See section 2.6.6, Brightness, for more information on dc offset control.
2.2.2.4 Serial Interface
The TLV990 contains several control registers. The serial interface of the TSB15LV01 provides a means of
programming these values. Table 2–11 shows the values that are transmitted from the TSB15LV01 to the TLV990.
2–10
Table 2–11. Values Transmitted to AFE via Serial Interface
Source Within the TSB15LV01
TLV990 Target Register
Covered in Section…
Gain/exposure control loop (auto mode)
PGA register
2.6.8, Gain and Exposure
2.6.7, Anti-Blooming
GAIN_CNTL register (manual mode)
Blooming_value field of DAC_OFFSET_CNFG register
Brightness control loop (auto mode)
User DAC1 register
Coarse dc offset DAC register
BRIGHTNESS_CNTL register (manual mode)
Brightness control loop (auto mode)
Fine dc offset DAC register
Optical black level register
2.6.6, Brightness
BRIGHTNESS_CNTL register (manual mode)
Offset_level field of DAC_OFFSET_CNFG register
Lines_smpl field of AFE_SETUP_CNFG register
pixels_smpl field of AFE_SETUP_CNFG register
Optical black calibration register
Gain and offset (brightness) sources depend on whether the respective modes are manual or automatic.
The lines_smpl and pix_smpl fields of AFE_SETUP_CNFG register control the lines per image, and pixels per line,
respectively, that are to be averaged (see section 2.2.2.3, Black Clamping Interface, for more information). The
offset_level field of the DAC_OFFSET_CNFG register is the digital black reference value to which the dc offset is
normalized.
The TLV990 contains two general purpose DACs with external outputs. One of these, DAC1, can be used to convert
a digital code (sourced from the TSB15LV01’s DAC_OFFSET_CNFG register) to an analog signal, which can be
routed to the sensor for use in antiblooming. The second DAC, DAC2, is generally not utilized, but can be controlled
from the TSB15LV01 as well.
See the TLV990 data sheet (literature number SLAS298) for more information about the target registers.
The timing of the AFE serial interface is shown in Figure 2–3. Table 2–12 shows the AFE interface timing parameters.
S_CLK
S_CS
S_DATA
t
h
t
su
t
cl
Figure 2–3. AFE Serial Interface Timing
Table 2–12. AFE Interface Timing Parameters
MIN
TYP
82
MAX
UNIT
ns
t
su
t
cl
t
h
164
82
ns
ns
In Figure 2-3, two words are being written by the TSB15LV01 to the AFE. Each word represents a value being written
to an AFE register address. The number of values written depends on the mode. For example, if autoexposure is
being used, different parameters are being programmed to the AFE than if the mode is manual.
2–11
2.2.2.5 Video Data Interface
A 10-bit parallel interface is used to move the video data from the AFE ADC to the TSB15LV01. Data is clocked in
with ADCLK.
2.2.3 CCD/AFE Timing
2.2.3.1 General Description
The timing of these interfaces takes into consideration two asynchronous, periodic events. The first event is the
integration of light in the sensor, which occurs at a frequency dictated by the camera’s frame rate. The second event
is the beginning of a 1394 isochronous cycle, which determines when video data is transmitted from the TSB15LV01.
The TSB15LV01 reconciles these two events in a way that produces optimal video quality while minimizing the
amount of memory necessary to store the pixel data.
When the integration cycle is complete, the pixel charges are transferred out of the active region of the sensor. For
the TC237, which is a full frame transfer CCD, this is the parallel transfer of charge from the image area to the storage
area. For the other sensors, which are interline CCDs, this is the transfer of charge to the vertical shift registers.
Several dummy/black lines are subsequently clocked and processed by the AFE.
At this point, timing waits for the next 1394 isochronous cycle. As data is clocked out onto the serial bus, more data
is needed and therefore clocked out of the sensor and into the TSB15LV01. This method of processing reconciles
the two asynchronous, periodic events. It also minimizes the size of the internal FIFO needed to buffer the data
stream, since data is only taken from the CCD as it is needed.
The data is packetized on the bus such that there is a period of time between frames in which no data remains to be
clocked out of the sensor, and no data is being transferred on the serial bus. During such periods of inactivity, the
TSB15LV01 may clock pixels out of the serial register while ignoring the resulting processed data from the AFE. This
results in lines of blank dummy pixels being clocked out of the CCD at regular intervals. This action is taken because
extended idle periods can allow the CCD serial register to accumulate dark current. Clocking these pixels also keeps
a constant dc level at the AFE ac-coupling capacitor.
Figures 2-4 through 2-12 show the sensor interface for each approved sensor. For each sensor, there are four views
shown. The first view contains the timing for the acquisition and transfer of a full frame of video. The second view is
a magnified portion of the start frame. The third view is a magnified portion of the start of a line, while the fourth view
is a magnified portion of the horizontal drive pulses. In some cases, the pulses are identical for the different sensor
options, so they are consolidated under a single figure. In all figures, the mode is YUV 4:1:1 640 x 480, at 30 frames
per second, with minimum exposure time.
Note that these signals are intended to be processed by one of the recommended driver devices before reaching the
CCD. In addition to level-shifting, these devices perform logic on the signals. Therefore, the signals at the sensor are
different than the ones shown in Figures 2-4 through 2-12.
2–12
t
frame
ABD_XSUB
ABSP_XSG
SAG/XV1
XV2
IAG/XV3
SRG/H1
H2
RST
CLAMP
OBCLP
SR
SV
ADCLK
Figure 2–7
Figure 2–4. Sensor Interface Timing for ICX098/LZ24BP Sensor, Full Frame
Table 2–13. ICX098/LZ24BP Full Frame Timing Parameters
MIN
TYP
MAX
UNIT
t
Frame period (@ 30 frames per sec.)
33.3
ms
frame
2–13
t
frame
ABD_XSUB
ABSP_XSG
SAG/XV1
XV2
IAG/XV3
SRG/H1
H2
RST
CLAMP
OBCLP
SR
SV
ADCLK
Figure 2–8
Figure 2–5. Sensor Interface Timing for ICX084 Sensor, Full Frame
Table 2–14. ICX084 Full Frame Timing Parameters
MIN
TYP
MAX
UNIT
t
Frame period (@ 30 frames per second)
33.3
ms
frame
2–14
t
frame
ABD_XSUB
ABSP_XSG
SAG/XV1
XV2
IAG/XV3
SRG/H1
H2
RST
CLAMP
OBCLP
SR
SV
ADCLK
Figure 2–9
Figure 2–6. Sensor Interface Timing for TC237 Sensor, Full Frame
Table 2–15. TC237 Full Frame Timing Parameters
MIN
TYP
MAX
UNIT
t
Frame period (@ 30 frames per second)
33.3
ms
frame
Figures 2-7 through 2-9 depict the start of a frame. Each block of pulses on the horizontal drive signals following the
pulse on ABSP_XSG represents a line of video data. The gap between the fourth and fifth lines is the waiting period
for the next 1394 isochronous cycle. Because the integration cycle is asynchronous with the 1394 isochronous cycle,
this gap continually changes in length.
2–15
t
26 Pulses
expo
t
xh
ABD_XSUB
ABSP_XSG
SAG/XV1
XV2
IAG/XV3
SRG/H1
H2
RST
CLAMP
OBCLP
SR
SV
ADCLK
Waiting for Next 1394
Isochronous Cycle
Figure 2–10
Lines of Video
Figure 2–7. Sensor Interface Timing for ICX098/LZ24BP Sensor, Start of Frame Data
Table 2–16. ICX098/LZ24BP Frame Start Timing Parameters
MIN
TYP
MAX
UNIT
µs
t
t
ABD_XSUB hold
Exposure time
11
xh
292
µs
expo
2–16
t
26 Pulses
expo
t
xh
ABD_XSUB
ABSP_XSG
SAG/XV1
XV2
IAG/XV3
SRG/H1
H2
RST
CLAMP
OBCLP
SR
SV
ADCLK
Waiting for Next 1394
Isochronous Cycle
Figure 2–10
42 µs
Lines of Video
Figure 2–8. Sensor Interface Timing for ICX084 Sensor, Start of Frame
Table 2–17. ICX084 Frame Start Timing Parameters
MIN
TYP
11
MAX
UNIT
µs
t
t
ABD_XSUB hold
Exposure time
xh
292
µs
expo
2–17
t
expo
t
xh
ABD_XSUB
ABSP_XSG
SAG/XV1
XV2
IAG/XV3
SRG/H1
H2
RST
CLAMP
OBCLP
SR
SV
ADCLK
42 s
Waiting for Next 1394
Isochronous Cycle
523
Pulses
Figure 2–11
Lines of Video
Figure 2–9. Sensor Interface Timing for TC237 Sensor, Start of Frame
Table 2–18. TC237 Frame Start Timing Parameters
MIN
TYP
MAX
UNIT
µs
t
t
ABD_XSUB/ABSP_XSG hold
Exposure time
11
xh
294
µs
expo
t
Parallel transfer duration
42
µs
ptd
2–18
t
xv1h
t
xv2h
t
t
xv3h
xv2d
t
t
hd
xv3d
ABD_XSUB
ABSP_XSG
SAG/XV1
XV2
IAG/XV3
SRG/H1
H2
RST
CLAMP
OBCLP
SR
SV
ADCLK
Figure 2–12
t
cd
t
od
t
ch
t
oh
Figure 2–10. Sensor Interface Timing for ICX098/LZ24BP/ICX084 Sensor, Start of Line
Table 2–19. ICX098/LZ24BP/ICX084 Line Start Timing Parameters
MIN
TYP
2.7
MAX
UNIT
µs
µs
µs
ns
t
t
t
t
t
t
t
t
t
t
SAG/XV1 hold time
xv1h
xv2h
xv3h
xv2d
xv3d
hd
XV2 hold time
2.7
IAG/XV3 hold time
2.7
XV2 delay time
900
900
350
280
652
1.3
IAG/XV3 delay time
ns
Horizontal drive delay following line transfer
CLAMP delay following start of horizontal drive
CLAMP hold time
ns
ns
cd
ns
ch
Time between OBCLP and end of line
OBCLP hold time
µs
ns
od
160
oh
2–19
t
hd
t
xv1h
ABD_XSUB
ABSP_XSG
SAG/XV1
XV2
IAG/XV3
SRG/H1
H2
RST
CLAMP
OBCLP
SR
SV
ADCLK
t
cd
Figure 2–12
t
oh
t
xv3h
t
od
t
ch
Figure 2–11. Sensor Interface Timing for TC237 Sensor, Start of Line
Table 2–20. TC237 Line Start Timing Parameters
MIN
TYP
MAX
UNIT
ns
t
t
t
t
t
t
t
SAG/XV1 hold time
820
810
1.8
xv1h
xv3h
hd
IAG/XV3 hold time
ns
Horizontal drive delay following line transfer
CLAMP delay following start of horizontal drive
CLAMP hold time
µs
40
ns
cd
244
488
1.056
ns
ch
Time between clamp and OBCLP
OBCLP hold time
ns
od
µs
oh
Figure 2–12 depicts the horizontal drive pulses. Note that this diagram reflects the timing when all fields in the
CCD_PULSE_CNFG and CCD_PULSE_CNFG registers are set to 00. This is the nominal position. Table 2–21
shows the horizontal drive timing parameters.
2–20
t
t
h1lw
h1hw
ABD_XSUB
ABSP_XSG
SAG/XV1
XV2
IAG/XV3
SRG/H1
H2
RST
CLAMP
OBCLP
SR
SV
ADCLK
t
t
svh
rh
t
srh
t
t
ahw
alw
Figure 2–12. Sensor Interface Timing for All Sensors, Horizontal Drive
Table 2–21. Horizontal Drive Timing Parameters
MIN
TYP
MAX
UNIT
ns
t
t
t
t
t
t
t
SRG/H1 high width
SRG/H1 low width
RST hold time
40
40
20
20
20
40
40
h1hw
h1lw
rh
ns
ns
SR hold time
ns
srh
SV hold time
ns
svh
ahw
alw
ADCLK high width
ADCLK low width
ns
ns
2.2.3.2 Pulse Tuning
Maintaining maximum dynamic range of the CCD image requires that the AFE’s CDS clamp and sample pulses
correspond perfectly to the analog output of the CCD, and thus to the CCD clock pulses as well. This means that after
a camera has been built, the CCD/AFE drive pulses need to be tuned into their proper positions.
Signals that need to be adjusted include RST, H2, SRG/H1, SR, SV, and ADCLK. For each of these signals, a field
exists in the CCD_PULSE_CNFG and CDS_PULSE_CNFG registers. These 6-bit fields contain values that
represent the amount of delay relative to the nominal position. Each field has a maximum value of 3 F, which
corresponds to approximately 16 to 18 ns.
2.3 STAT Interface
Three status terminals are provided: STAT0, STAT1, and STAT2. These terminals can be configured to provide
different functions. The function of a STATn terminal is changed by writing a new signal code into the corresponding
field of the STATUS_CNFG register.
When one or more of the terminals is configured as a signal input, the host can read the input value by reading the
st_stat field of the STATUS_CNFG register. Similarly, when one or more of the terminals is configured as a signal
output, the host can change its value by writing to the st_stat field.
The functions provided by the STAT interface are shown in Table 2–22.
2–21
Table 2–22. Status Terminal Functions Determined by STATn Register Fields
SIGNAL
CODE
I/O
SIGNAL
STAT0
0
1
2
I
Signalinput. Configures this terminal as an input that can be read from the host via the 1394 serial bus. The input value can be
found in bit 0 of the st_stat field of the STATUS_CNFG register.
O
O
Signal output. Configures this terminal such that it outputs the value of bit 0 in the st_stat field of the STATUS_CNFG register,
which can be written to by the host.
Cycle_out. This is the link’s cycle clock. It is based on the timer controls and the cycle-start messages received from the 1394
bus cyclemaster.
3
4
5
6
7
O
O
O
O
O
ITF_Empty. This signal is high when the ITF (isochronous transfer FIFO) is empty.
Line sync pulse. Pulses at the start of every horizontal line
Clamping pulse
Active region pulse. Vertical sync signal that pulses once per image frame.
Focus motor select. Writing this value to the STAT0 register tells the TSB15LV01 that a motor is present that will derive its
control from the FOCUS_CNTL register.
STAT1
0
1
I
Signalinput. Configures this terminal as an input that can be read from the host via the 1394 serial bus. The input value can be
found in bit 1 of the st_stat field of the STATUS_CNFG register.
O
Signal output. Configures this terminal such that it outputs the value of bit 1 in the st_stat field of the STATUS_CNFG Register,
which can be written to by the host.
2
3
O
O
Cycle_start. Isochronous cycle start indicator. Signals the beginning of an isochronous cycle by pulsing for one clock period.
Cycle_Done. When high, an arbitration gap has been detected on the 1394 bus after the reception of a cycle-start packet. This
indicates that the isochronous cycle is over.
4
5
6
7
O
O
O
O
Line sync pulse. Pulses at the start of every horizontal line.
Iso_Enable. Indicates that isochronous 1394 packet transmission has been activated.
Active region pulse. Vertical sync signal that pulses once per image frame.
Zoom motor select. Writing this value to the STAT1 register tells the TSB15LV01 that a motor is present that will derive its
control from the ZOOM_CNTL register.
STAT2
0
1
I
Signalinput. Configures this terminal as an input that can be read from the host via the 1394 serial bus. The input value can be
found in bit 2 of the st_stat field of the STATUS_CNFG register.
O
Signal output. Configures this terminal such that it outputs the value of bit 2 in the st_stat field of the STATUS_CNFG register,
which can be written to by the host.
2
3
O
O
Dm_Rdy. Indicates that a 1394 isochronous stream is ready to be sent on the next iso cycle.
While high, indicates that a valid video line is being clocked out of the CCD. If low, indicates that dummy lines are being
clocked out.
4
5
6
7
O
O
O
O
Line sync pulse. Pulses at the start of every horizontal line
6-MHz clock
Active region pulse. Vertical sync signal that pulses once per image frame
Iris motor select. Writing this value to the STAT2 register tells the TSB15LV01 that a motor is present that will derive its control
from the IRIS_CNTL register.
2–22
2.4 Motor Control Interface
The TSB15LV01 provides control for three stepper motors that can be used for focus, zoom, and iris functions.
Steppers provide exact, high-tolerance control.
Note also that while the interface provides for focus, zoom, and iris motors, any motor with a similar function can be
attached to those interfaces, such as pan or tilt.
2.4.1 Motor Driver Timing
Only one set of drivers is provided, and control of the motors is multiplexed. The STAT0, STAT1, and STAT2 terminals,
when configured for stepper motors as discussed in section 2.3 STAT Interface, select which motor is being
controlled. When
a
STATn terminal goes low, all motor terminal signals (PHASEx_n, IR_SIG,
MOTOR_PLUS/MINUS) are intended for the motor corresponding to the STATn terminal in question.
If only one STATn terminal is configured as a motor select, that terminal is held low continually, while the others
perform the function for which they were programmed. If more than one STATn terminal is configured as a motor
select, their outputs alternately pulse low. For example, if two motors are being used, each STATn terminal is active
half the time. If three motors are being used, each STATn terminal is active one third the time. This is shown in
Figure 2–13.
STAT0
(Enables Focus Motor)
STAT1
(Enables Zoom Motor)
STAT2
(Enables Iris Motor)
PHASE_xn
MOTOR_PLUS/MINUS
TERMINALS
FOCUS
POSITION
ZOOM
POSITION
IRIS
POSITION
New Value Written to
ZOOM_CNTL Register
Pushbuttons For Focus
and Zoom are Pressed
Simultaneously
Device Power Up
Figure 2–13. STATn Motor Select Pulses
In Figure 2-13, each pulse in the last three lines does not indicate a signal pulse, but rather a movement in the position
of the motors. Also, the pulses for phase_xn are not literal. The pulses actually driven are as defined by the stepper
drive table used by the TSB15LV01, shown in Table 2–23.
2–23
Table 2–23. Stepper Drive Table
MOTOR DRIVE TERMINAL
PHASE1_A
PHASE1_B
PHASE2_A
PHASE2_B
STEP 1
STEP 2
STEP 3
STEP 4
1
0
0
1
0
1
1
0
1
1
0
0
0
0
1
1
The table shows values for the forward direction. The values are driven in a cyclical pattern when the motor is to be
driven forward. The values are driven cyclically in reverse when the motor is to be moved backwards.
The default state for the drive terminals is high, resulting in the outgoing value of 1111. It is intended that the outputs
will be used as inputs to an inverting drive circuit; therefore, the default state of the stepper drive windings is that both
ends are grounded. As a result, the motor and driver assembly only draw current when actively stepping in one
direction or another.
Note that only one STATn terminal is needed per motor, such that if less than three motors are being used, the
remaining STATn terminals can be used for other functions.
2.4.2 Positioning System
Positioning for the steppers is based on a linear scale from 000h to 3FFh (10 bit). Upon power up of the device, it
seeks to align the physical motor position with the initial starting value stored in the corresponding field of the
MOTOR_POS_CNFG register (ir_zoom, ir_focus, or ir_iris fields). To do this, the device first moves the stepper to
a physical reference point indicated by the IR_SIG terminal. IR_SIG is assumed to have a position feedback signal
attached to it, such as an infrared sensor. This point is likely near the beginning or end of the mechanism’s motion.
If the IR_SIG terminal is high when the device powers up, it indicates that the mechanism is in a position beyond the
position reference. The TSB15LV01 steps the mechanism down until the terminal goes low. If the terminal is already
low at power up, the motor steps the mechanism up until the terminal goes high, and then steps it back one.
After each motor has been positioned at its reference, the TSB15LV01 associates those positions with the values in
the corresponding fields of the MOTOR_POS_CNFG register. Using these values as starting points, it moves each
motor to the position indicated in the value field of the feature control register corresponding to that motor
(ZOOM_CNTL, FOCUS_CNTL, or IRIS_CNTL). For example, a camera can be preset to focus at a certain distance.
After the TSB15LV01 has realigned the motor at the beginning or end of the focus mechanism movement, it moves
the motor to the predetermined focus setting.
Subsequently, any value written to the feature control registers that is not equal to the current position will cause the
motor to step toward that value. Each incremental value written to the register represents one step the motor moves.
When the motor position matches the value in the feature control register, the stepper shuts off, and the windings are
grounded. Power up and movement of the motor can be seen in Figure 2–13.
Initial positioning of the motors following power up occurs in sequential order, with the first motor pulling itself into
position, then the second motor, and then the third. After this, all motor step sequences are multiplexed, which
effectively causes the motors to move simultaneously.
2.4.3 Pushbutton Interface
The MOTOR_PLUS and MOTOR_MINUS terminals are designed as pushbutton inputs. Driving one of these
terminals high causes the value field of the current motor’s feature control register to increment or decrement
accordingly. In response, the corresponding motor moves forward or backward. Holding one of these inputs high will
cause the motor to step continuously.
The motor to which activity on MOTOR_PLUS/MINUS is applied is determined by which motor select (STATn
terminal) is currently low. If only one motor is used, only one motor select is present, allowing pushbuttons to be
attached directly to the terminals.
2–24
If more than one motor is being used, it is necessary to multiplex them. As a result of the alternating STATn pulses,
the switches are scanned on a periodic basis. There is no need for a debounce circuit, because the buttons are
scanned at a fixed rate of approximately 30 Hz.
2.5 EEPROM Interface
An external EEPROM with serial port interface (SPI) interface is required for TSB15LV01 operation. The entire
address space of the TSB15LV01 accessible from the 1394 bus is stored there. The EEPROM must provide 4096
bits of memory, such as a 512 × 8 configuration. The interface is designed to be used with the Atmel AT25040 or Xicor
X25040. It utilizes a four-wire interface consisting of a chip select, an input, an output, and a clock.
The 1394 bus uses 48-bit addresses. Since this is too large of a contiguous address space for most conventional
EEPROMs, the TSB15LV01 converts these addresses into an 8-bit form called the internal address. The conversion
is shown in section 3, Address Space.
All registers are stored in the external EEPROM device. However, upon power up of the TSB15LV01, the feature
control registers and the configuration registers are copied from the EEPROM into registers resident in the
TSB15LV01 device. This includes all address space between F0F00800h and F0F00F24h. From that moment on,
1394 bus accesses to this address space apply to the registers in the TSB15LV01. For address space outside this
range, bus accesses are executed on the EEPROM device. As a result, the role of the EEPROM with respect to these
registers is to store default values, these values are saved when power is removed from the device. The values in
the TSB15LV01 registers are never written back to the EEPROM by the TSB15LV01 device, and the bus is not
capable of changing them since all normal run-time bus accesses to this memory space operate on the TSB15LV01.
This allows for the loading of power up initialization values into the EEPROM.
However, it is possible to write values to the EEPROM for any address location once a value of 12345678h has been
written to the write_protect_control field of the EEPROM_CNFG register. This value is known as the write-protect
control code. Once this control code has been written to the device, all register space accesses will operate upon
the EEPROM. Writes operate on both the EEPROM and the TSB15LV01. Reads operate on the EEPROM only. This
mechanism provides a way to program new initialization values.
Figures 2–14 and 2–15 show the read and write timing (Table 2-24) associated with the TSB15LV01 EEPROM
interface.
T
cssu
T
csd
EEPROM_CS
EEPROM_SCLK
EEPROM_SI
T
CL
0
1
2
3
4
5
6
7
8
7
9
6
10 11 12 13 14 15 16 17 18 19 20 21 22
INSTRUCTION
8
BYTE ADDRESS
5
4
3
2
1
0
9th BIT of ADDRESS
DATA OUT
HIGH IMPEDANCE
EEPROM_SO
7
6
5
4
3
2
1
0
MSB
Figure 2–14. Read Timing
2–25
T
cssu
T
csd
EEPROM_CS
EEPROM_SCLK
EEPROM_SI
T
CL
0
1
2
3
4
5
6
7
8
7
9
6
10 11 12 13 14 15 16 17 18 19 20 21 22 23
INSTRUCTION
8
BYTE ADDRESS
DATA IN
5
4
3
2
1
0
7
6
5
4
3
2
1
0
9th BIT of ADDRESS
HIGH IMPEDANCE
EEPROM_SO
Figure 2–15. Write Timing
Table 2–24. EEPROM Interface Timing Parameters
MIN
TYP
652
652
MAX
UNIT
ns
t
t
t
EEPROM CS setup time
EEPROM CS delay time
Clock period
cssu
csd
cl
ns
1.304
µs
2.6 Video Signal Processor
After the CCD image data is received from the AFE, it is processed by the video signal processor (VSP). The core
of the VSP is a digital signal processor (DSP) that conducts numerous essential algorithms, discussed in the sections
below.
Most of the video processing features present in the TSB15LV01 are included as part of the digital camera
specification. As such, they are controllable via the feature control registers (see section 3.3.3.1.3, Feature Control
Registers). A few others are specific to the TSB15LV01 and can be controlled with the TSB15LV01 configuration
registers.
2.6.1 De-Mosaicing
The CCD image data is comprised of individual component pixels, each of which is pure red, green, or blue. The VSP
de-mosaics them, a process in which they are grouped to form composite pixels that fit the RGB standard.
Several adjustments can be made in the configuration registers that affect how the sensor data is compiled into the
RGB image frame. These are shown in Table 2–25.
Table 2–25. CCD Sensor Processing Adjustments
ADJUSTMENT
COMMENT
H-Center and V-Center fields of
CCD_OPTICS_CNFG register
The TSB15LV01 receives an image size greater than 640 x 480 pixels from the CCD. These fields
determine which 640 x 480 rectangle is processed and transmitted to the host.
pix_shp fields of
VIDEO_OPTIONS_CNFG register
Determines whether component pixels are grouped as squares or as L-shaped pieces. L-shaped pixels
give a higher resolution image than square pixels but can create a jagged edge effect.
Additional information for each of these adjustments can be found in section 3.3.3.2, Configuration Registers.
2–26
2.6.2 Brightness
The brightness of the image is directly related to the DC offset of the image data in the AFE. This feature can be
controlled automatically or manually.
When brightness is configured for automatic control via the BRIGHTNESS_CNTL register, the TSB15LV01 utilizes
the TLV990’s black clamping feature. This feature sets the offset at the beginning of every image frame, adjusting
it so that the black pedestal is equal to the value stored in the offset_level field of the DAC_OFFSET_CNFG register.
(See section 2.2.2.3, Black Clamping Interface, for more information.)
Brightness can also be controlled by setting the offset manually. If the TSB15LV01’s auto-brightness feature is
disabled, it divides the value field of the BRIGHTNESS_CNTL register into coarse (most significant eight bits) and
fine (least significant eight bits) and sends those values directly to the AFE.
If autobrightness is used, there are two parameters sent to TLV990 that affect how black clamping is performed. Both
are found in the AFE_SETUP_CNFG register. The first, found in the lines_smpl field, informs the TLV990 how many
lines per image should be included in the black clamp averaging. The second, found in the pix_smpl field, informs
the TLV990 how many samples per line should be included in the averaging. The TLV990 datasheet can provide more
information on the use of these values.
2.6.3 Gain and Exposure
Gain refers to the gain stage of the AFE, while exposure refers to the CCD image integration time. These parameters
canbeconfiguredmanuallyusingtheircorrespondingfeaturecontrolregisters, GAIN_CNTLandEXPOSURE_CNTL
(Figure 2-16).
Alternatively, they can be controlled automatically using an internal feedback loop. This loop samples 4048 pixels
within an image and calculates the average pixel luminance. It compares this value with the value stored in the
auto-expo field of the AUTO_ADJ_CNFG register, adjusting the gain and exposure time accordingly.
A control input to this block, stored in the expo_delta field of the AUTO_ADJ_CNFG register, regulates the speed at
which adjustments are made to the algorithmic filter. This value must be adjusted to provide adequate damping for
the feedback loop.
2–27
AFE
PGA
Clamp
and
CDS
Coarse
Offset
Adjust
CCD/
Driver
Fine
+
Offset
Adjust
A/D
–
Gain
Black
Clamp
Control
TSB15LV01
Pixel
Saturation
Simulator
∑
SHUTTER_CNTL register –
value field
(backlight compensation)
Algorithmic
Comparator
Adjustment
with Digital
Filter
AUTO_ADJ_CNFG register –
expo_deltafield
AUTO_ADJ_CNFG register –
–expo_ref field
(used with auto gain/exposure)
Gain
Serial
Encoder
GAIN_CNTL register –
value field
EXPOSURE_CNTL register –
CCD Pulse
Generator
value field
Image Clear Pulse
(ABD_XSUB)
(used with manual gain exposure)
Figure 2–16. Gain and Exposure Automatic and Manual Controls
The location of the sampled pixels is dictated by the backlight compensation feature, described in section 2.6.9.
Gainandexposurehaveasimilareffectontheimage. Inotherwords, theeffectofareductioningaincanbecountered
by a proportional increase in exposure, and vice versa. Therefore, there are many combinations of gain and exposure
settings that produce a similar image.
High gain settings can amplify any noise that may have been introduced to the analog signal, prior to or during its
conversion to digital. Because of this, the autogain/exposure loop generally seeks to keep gain as low as possible,
adjusting the exposure parameter to properly expose the image. Gain is increased when the exposure parameter
alone is not sufficient to produce a proper exposure.
2.6.4 Sharpness and Saturation
Processing on the sharpness and saturation parameters is performed by the VSP. They are adjustable within
reasonable boundaries by altering values in their corresponding feature control registers.
The sharpness control utilizes a continuous extrapolation filter, providing smooth sharpness control. Saturation refers
to color saturation, as opposed to saturation of a CCD charge.
2–28
2.6.5 White Balance
This feature alters the degree to which red and blue CCD component pixels are weighted to form composite pixels.
Green is considered constant. White balance often needs to be adjusted when image lighting changes. For example,
when white balance has been configured for incandescent lighting, it will need adjustment if taken to an area with
fluorescent or natural lighting. This is because the spectral content of these light sources differs from incandescent
light.
White balance can be adjusted manually or automatically, selectable in the WHITE_BALANCE_CNTL register. If the
featureissetasmanual, itcorrespondsdirectlywiththevalueinthatregister. Thehostcanthenalterthewhitebalance
value as it wishes. For example, it could implement its own autobalance feature.
If the feature is set as automatic, an internal adjustment is used. This algorithm assumes that all incoming colors have
a relatively equal amount of red, green, and blue, and makes small, iterative adjustments to the white balance. This
provides very good white balance in most situations without necessitating manual adjustments. However, if red or
blue is dominant in the image for a moderate period of time, the assumption is incorrect, and the image will begin to
noticeably discolor.
2.6.6 Gamma
Gamma correction can be implemented to compensate for nonlinearities in cathode ray tubes, which in most cases
is the device that is used to display the image. It is possible to turn this feature off, since some high-end CRTs are
capable of providing their own gamma correction.
The gamma correction implemented by the TSB15LV01 incorporates a correction factor equivalent to the 0.45 analog
gamma standard.
2.6.7 YUV Conversion
If the transfer mode is one that uses the YUV color space, the VSP converts the RGB pixels into YUV.
RGB to YUV color space conversion for gamma-corrected, fully-saturated RGB video is:
Y = 0.257 R + 0.504 G + 0.098 B + 16
Cb = -0.148 R - 0.291 G + 0.439 B + 128
Cr = 0.439 R - 0.368 G - 0.071 B + 128
This matrix is approximated in the TSB15LV01, which processes video data as 8-bit digital values, by fractionalizing
the coefficients with respect to 8 bits:
Y = (66/256) R + (129/256) G + (25/256) B + 16
Cb = - ( 38/256) R - (74/256) G + (112/256) B + 128
Cr = (112/256) R - (94/256) G - ( 18/256) B + 128
This approximation introduces less than one least significant bit of error.
2–29
2.6.8 Antiblooming
Blooming occurs when a CCD pixel becomes saturated and overflows into surrounding pixels. This can appear on
the image display as discoloration or bright speckles. CCD sensors usually have a means of allowing a cutoff level
to be set, above which charge is not allowed to exceed. Setting this antiblooming level just below the saturation level
prevents charge overflow.
The Sony ICX084, Sony ICX098, and the Sharp LZ24BP perform this function internally. The TI TC237, however,
requires the level to be set externally. To provide this voltage reference, one of the general-purpose DACs on the AFE
can be utilized. The TSB15LV01 designates DAC1 as the antiblooming DAC. The DAC output can be used to set the
TC237 antiblooming level.
The antiblooming feature must be activated by setting the bloom_en field of the DAC_OFFSET_CNFGregister. Once
this has been done, the value of the blooming_value field of the DAC_OFFSET_CNFG register will be sent to the
TLV990. This will set the antiblooming voltage level for the CCD sensor. The value of the other general-purpose DAC,
DAC2, can be set as well via the DAC2_en and DAC2_value fields of the same corresponding registers.
2.6.9 Backlight Compensation
The TSB15LV01 provides a way to compensate for situations in which a forefront object appears dark due to
excessive light in the background. This is accomplished by extracting more gain/exposure samples from image
regions in which the intended object resides (see 2.6.3, Gain and Exposure). Hot regions for which this feature can
be activated include those shown in Table 2–26.
Table 2–26. Backlight Compensation Hot Regions
VALUES OF
SHUTTER_CNTL
HOT REGION
REGISTER
0
1
2
Matrix (No compensation). Pixel samples are evenly spaced.
Circle. All the pixel samples are taken from a circle in the center of the image. The region is 128 pixels wide.
Circle, averaged. Half the samples are taken inside the same circle as circle mode, half the samples are taken outside
the circle.
3
Head and Shoulders. All the pixel samples are taken from a region that would be occupied by a person sitting in front
of the camera.
4
5
6
Top third. All the pixel samples are taken from the top third of the image.
Bottom third. All the pixel samples are taken from the bottom third of the image.
Middle third. All the pixel samples are taken from the middle third of the image.
The hot region for backlight compensation is selected by the SHUTTER_CNTL register. As shown in Table 2–26, the
feature can be disabled, causing the gain/exposure loop samples to be evenly distributed throughout the image.
2.6.10 White Spot Compensation
CCD sensors occasionally have nonuniformities that cause some pixels to build a charge significantly greater than
the light that is activating them, due to leakage current in the pixel. In a black and white sensor, this causes white spots
that appear out of place. In a color sensor, it can result in discoloration or speckles.
The TSB15LV01 can be configured to compensate for this error using one of two built-in filters. The first filter is a
medianfilter. Foreverypixel, themedianfilterconsidersitsvalueandthepixelsoneithersideandreplacestheoriginal
pixel with the median of the three. This removes any single-pixel abnormalities from the pixel stream. The other filter
is the nonlinear interpolation filter. It compares a pixel to the ones before and after it. If it is significantly different, such
that it exceeds a preset threshold, it is thrown out and replaced by the average of the two surrounding pixels.
Alternatively, white spot compensation can be disabled.
The white spot compensation filter is chosen by the filter field of the CCD_OPTICS_CNFG register. The threshold
for how deviant a pixel is allowed to be before it is discarded by the nonlinear interpolation filter is determined by the
value of the filter_limit field, also in the CCD_OPTICS_CNFG register.
2–30
The tradeoff in using one of these filters lies in the fact that the filters are indiscriminate in discarding single-pixel
abnormalities. Single-pixel abnormalities may be noise, or they may be a valid part of the image. As a result, the filters
remove white spots but also result in some degradation of the image due to some loss of spacial high-frequency
response. The median filter is more extreme in this regard. The nonlinear interpolation filter has an amplitude
threshold that defines how extreme the abnormality must be before it is discarded, giving the user more control of
the tradeoff.
The median filter is more effective in removing white spots, but if it has an adverse effect on the sharpness of the
image, it may be desirable to use the nonlinear interpolation filter and adjust the filter limit, or disable the filter
altogether.
2.6.11 Test Pattern
The TSB15LV01 can send a continuous image consisting of color bars and linear ramps. The test pattern is activated
using the test_en field of the TEST_CNFG register. It is shown in Figure 2–17.
Figure 2–17. TSB15LV01 Built-In Test Pattern
The upper portion of the test pattern consists of solid vertical bars of white, yellow, cyan, green, magenta, red, blue,
and black (in order, as shown in Figure 2–17). The bottom portion consists of horizontal bars of white, red, green,
and blue, with luminance increasing from left to right. The luminance value increases by one every two pixels (RGB
640 x 480 mode).
The test pattern image is subject to changes in saturation, white balance, sharpness, and gamma control. It is not
affected by changes in gain, brightness, exposure, or backlight compensation.
The test pattern is useful during camera development for determining whether image problems are originating after
the VSP (1394 interface) or before it (sensor interface). That is, it can verify functionality between the host and the
TSB15LV01 device, isolating image problems to the CCD or AFE interface.
2–31
2–32
3 Address Space
The address space for the TSB15LV01 is divided into four areas. The first consists of registers and ROM required
for any 1394 node, called 1394 memory. The second area consists of registers that reflect the level of capability of
the digital camera, known as the inquiry registers. These registers are required by the Digital Camera Specification.
Both 1394 memory and the inquiry registers are considered read-only. The third and fourth areas consist of registers
that can be read for camera status or written to for camera control. These are called the control registers and
configuration registers. The control registers are dictated by the Digital Camera Specification, while the configuration
registers are unique to the TSB15LV01.
Table 3–1 gives a summary of the various register groupings referred to throughout this document.
Table 3–1. TSB15LV01 Register Groupings
REGISTER GROUP NAME
1394 registers
DESCRIPTION
Registers required for 1394 nodes.
REQUIRED BY
DOCUMENTATION
Section 3.3.1
1394 Standard
Inquiry registers
Registers that describe the capability of the digital camera, Digital Camera
allowing host to determine availability of features provided for by Specification
the Digital Camera Specification.
Section 3.3.2
Control registers
Registersthatcontrolbasiccamerafeatures, suchasframerate, Digital Camera
Section 3.3.3.1
output format, and video parameters.
Specification
Configuration registers
Registers that control unique TSB15LV01 features and TSB15LV01-specific Section 3.3.3.2
functions.
The TSB15LV01 provides a memory map consistent with v1.04 of the 1394 Digital Camera Specification, and
implements most of the features provided for by that document. There are a few features that are not implemented.
This functionality should always be indicated in the inquiry registers. Recommended values are provided in Section
3.3.2. The inquiry registers themselves are always valid, since their function is to tell the host which features are valid
and which are not, and since they are read-only by definition. The only registers that are disabled for nonsupported
features are control registers.
3.1 1394 Node Memory Architecture
To understand the memory allocation of the TSB15LV01, it is useful to first understand the addressing structure for
1394 nodes in general. 1394 addresses consist of the components shown in Table 3–2.
Table 3–2. 1394 Address Components
COMPONENT
Bus ID
LENGTH
10 bits
6 bits
COMMENT
Identifies the 1394 bus
Node ID
Identifies the node within the bus
Destination offset
48 bits
Identifies the address within the node
The values of the first two components are environment-dependent. Note that address values shown throughout
section 3 consist only of the 48-bit destination offset. In the case of the TSB15LV01, locations in “1394 memory” have
abasedestinationoffsetofFFFFF0000000h. Incontrast, theinquiry, control, andconfigurationregistershaveabase
destination offset of FFFF F0F0 0000h. Various registers are determined by adding an additional offset value to the
destination offset.
Thememoryspaceofatypical1394nodeconsistsofasmallcollectionofregistersthatexistatfixedaddresses, called
initial register space, and a number of dynamic memory structures called directories and leaves. Directories contain
information and pointers to more directories and leaves. Leaves are blocks of memory that contain information but
do not point to other directories or leaves.
3–1
These elements form a tree structure. A certain amount of freedom is granted to the developer of the 1394 node,
allowing a variety of structures within the architecture guidelines. The root node for this structure exists in part of the
initial register space, called the root directory. The root directory tree allotted in the TSB15LV01 is shown in
Figure 3–1.
Root Directory
Node Unique ID Leaf
Unit Directory
Unit Dependent
Directory
Vendor
Name
Leaf
Model
Name Leaf
Figure 3–1. TSB15LV01 Root Directory Tree
TheTSB15LV01memorystructureisbasedonthisdynamicconceptbutassumesthatallmemorylocationsarefixed.
Although all the components are present, including initial register space, root directory tree, and the appropriate
pointers, these structures are assigned a fixed memory location. All memory locations can be legally addressed by
their fixed addresses without needing to derive them from the corresponding base address and offset. (The
exceptionsto this rule are the vendor and model name leaves, discussed in section 3.3.1.2, Configuration ROM). This
scheme provides efficient usage of EEPROM memory.
Because this memory structure is implemented in EEPROM, it is the responsibility of the system designer to ensure
that it exists according to the maps shown in section 3. See section 2.5, EEPROM Interface, for more information.
3.2 Top-Level Memory Maps
The tables below give a top-level map of the TSB15LV01 address space. Along with the 1394 bus address, aninternal
address is given. This is the address scheme used inside the TSB15LV01 and also in interfacing with the EEPROM
(see sections entitled Physical Location of Register Data and EEPROM Interface for more information).
Table 3–3. Top-Level Memory Map: 1394 Memory (Core CSRs)
1394 BUS
ADDRESS
INTERNAL
ADDRESS
FFFF F000 0000
FFFF F000 0004
FFFF F000 0008
FFFF F000 000C
FFFF F000 0010
FFFF F000 0014
FFFF F000 0018
FFFF F000 001C
FFFF F000 0200
FFFF F000 0204
FFFF F000 0208
FFFF F000 020C
FFFF F000 0210
0
1
2
3
5
6
8
9
10
11
12
3–2
Table 3–4. Top-Level Memory Map: 1394 Memory (Device Configuration ROM)
1394 BUS
ADDRESS
INTERNAL
ADDRESS
REGISTER NAME
FFFF F000 0400
FFFF F000 0404
FFFF F000 0408
FFFF F000 040C
FFFF F000 0410
FFFF F000 0414
FFFF F000 0418
FFFF F000 041C
FFFF F000 0420
FFFF F000 0424
FFFF F000 0428
FFFF F000 042C
FFFF F000 0430
FFFF F000 0434
FFFF F000 0438
FFFF F000 043C
FFFF F000 0440
FFFF F000 0444
FFFF F000 0448
FFFF F000 044C
FFFF F000 0450
FFFF F000 0454
FFFF F000 0458
FFFF F000 045C
FFFF F000 0460
FFFF F000 0464
FFFF F000 0468
FFFF F000 046C
FFFF F000 0470
FFFF F000 0474
FFFF F000 0478
FFFF F000 047C
FFFF F000 0480
FFFF F000 0484
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
BUS INFO BLOCK
ROOT DIRECTORY
NODE UNIQUE
UNIT DIRECTORY
UNIT DEPENDENT DIRECTORY
VENDOR NAME LEAF
MODEL NAME LEAVES
3–3
Table 3–5. Top-Level Memory Map: Inquiry Registers
1394 BUS
ADDRESS
INTERNAL
ADDRESS
REGISTER NAME
FFFF F0F0 0000
FFFF F0F0 0100
64
65
CAMERA INITIALIZATION
FORMAT_INQ
FFFF F0F0 0180
FFFF F0F0 0200
FFFF F0F0 0204
FFFF F0F0 0208
FFFF F0F0 020C
FFFF F0F0 0210
FFFF F0F0 0214
FFFF F0F0 0400
66
67
68
69
70
71
72
73
VIDEO_MODE_INQ
RATE_INQ
BASIC_FUNC_INQ
FEATURE_HI_INQ
FEATURE_LO_INQ
BRIGHTNESS_INQ
EXPOSURE_INQ
SHARPNESS_INQ
WHITE_BAL_INQ
HUE_INQ
FFFF F0F0 0404
FFFF F0F0 0408
FFFF F0F0 0500
FFFF F0F0 0504
FFFF F0F0 0508
FFFF F0F0 050C
FFFF F0F0 0510
FFFF F0F0 0514
FFFF F0F0 0518
FFFF F0F0 051C
FFFF F0F0 0520
FFFF F0F0 0524
FFFF F0F0 0528
FFFF F0F0 0580
FFFF F0F0 0584
FFFF F0F0 0588
74
75
76
77
78
79
80
81
82
83
84
85
111
87
88
89
SATURATION_INQ
GAMMA_INQ
SHUTTER_INQ
GAIN_INQ
IRIS_INQ
FOCUS_INQ
ZOOM_INQ
PAN_INQ
TILT_INQ
3–4
Table 3–6. Top-Level Memory Map: Control Registers
1394 BUS
ADDRESS
INTERNAL
ADDRESS
REGISTER NAME
FFFF F0F0 0600
FFFF F0F0 0604
FFFF F0F0 0608
FFFF F0F0 060C
FFFF F0F0 0610
FFFF F0F0 0614
FFFF F0F0 0618
FFFF F0F0 061C
FFFF F0F0 0620
FFFF F0F0 0624
FFFF F0F0 0800
FFFF F0F0 0804
FFFF F0F0 0808
FFFF F0F0 080C
FFFF F0F0 0810
FFFF F0F0 0814
FFFF F0F0 0818
FFFF F0F0 081C
FFFF F0F0 0820
FFFF F0F0 0824
FFFF F0F0 0828
FFFF F0F0 0880
FFFF F0F0 0884
FFFF F0F0 0888
90
91
CUR_V_FRM_RATE_CNTL
CUR_V_MODE_CNTL
CUR_V_FORMAT_CNTL
ISO_CHANNEL/SPEED_CNTL
CAMERA_POWER_CNTL
ISO_EN_CNTL
92
93
94
95
96
RESERVED
97
ONE_SHOT_CNTL
RESERVED
98
99
RESERVED
100
101
102
103
104
105
106
107
108
109
110
112
113
114
BRIGHTNESS_CNTL
EXPOSURE_CNTL
SHARPNESS_CNTL
WHITE_BAL_CNTL
RESERVED
SATURATION_CNTL
GAMMA_CNTL
SHUTTER_CNTL (BACKLIGHT COMPENSATION)
GAIN_CNTL
IRIS_CNTL
FOCUS_CNTL
ZOOM_CNTL
RESERVED
RESERVED
Table 3–7. Top-Level Memory Map: Configuration Registers
1394 BUS
ADDRESS
INTERNAL
ADDRESS
REGISTER NAME
FFFF F0F0 0F00
FFFF F0F0 0F04
FFFF F0F0 0F08
FFFF F0F0 0F0C
FFFF F0F0 0F10
FFFF F0F0 0F14
FFFF F0F0 0F18
FFFF F0F0 0F1C
FFFF F0F0 0F20
FFFF F0F0 0F24
127
116
117
118
119
120
121
122
123
124
EEPROM_CNFG
TEST_CNFG
CCD_PULSE_CNFG
CDS_PULSE_CNFG
AUTO_ADJ_CNFG
DAC_OFFSET_CNFG
CCD_OPTICS_CNFG
STATUS_CNFG
VIDEO_OPTIONS_CNFG
MOTOR_POSITION_CNFG
3.3 Register Detail
3.3.1 1394 Memory
The following sections define the CSR (Command and Status register) and ROM locations implemented in the
TSB15LV01. For more information on the way 1394 CSR architectures are implemented, see section 3.1, 1394 Node
Memory Architecture, and the 1394a specification.
3–5
3.3.1.1 Implemented Core CSRs
The TSB15LV01 implements the following core CSRs, defined in the IEEE 1212-1991 standard (upon which the 1394
standard is based). These are shown in Table 3–8.
Table 3–8. Implemented Core CSRs
Offset
0-7
8-15
16-23
24-31
FFFF F000 0000h
FFFF F000 0004h
FFFF F000 0008h
FFFF F000 000Ch
FFFF F000 0010h
FFFF F000 0014h
FFFF F000 0018h
FFFF F000 001Ch
STATE_CLEAR
STATE_SET
NODE_IDS
RESET_START
SPLIT_TIMEOUT_HI
SPLIT_TIMEOUT_LO
The TSB15LV01 implements the following serial-bus-dependent CSRs, defined by the 1394 standard. These are
shown in Table 3–9.
Table 3–9. Serial-Bus-Dependent CSRs
Offset
0-7
8-15
16-23
CYCLE_TIME
24-31
FFFF F000 0200h
FFFF F000 0204h
FFFF F000 0208h
FFFF F000 020Ch
FFFF F000 0210h
BUSY_TIMEOUT
3.3.1.2 Configuration ROM
The TSB15LV01 implements Configuration ROM defined in the IEEE 1212-1991 standard, shown in Table 3–10.
Table 3–10. Base Configuration ROM
NAME
Offset
0-7
04h
8-15
crc_length
33h (3)
16-23
24-31
FFFF F000 0400h
FFFF F000 0404h
rom_crc_value
31h (1)
39h (9)
max_rec
34h (4)
FFFF F000 0408h 0 0 1 0
FFFF F000 040Ch
rsv
FFh
rsrv
chip_id_hi
Bus info block
node_vendor_id
FFFF F000 0410h
chip_id_lo
FFFF F000 0414h
0004h
CRC
module_vendor_ID value
FFFF F000 0418h
FFFF F000 041Ch
FFFF F000 0420h
FFFF F000 0424h
03h
Root directory
06h
0Dh
11h
module_sw_version (070198h)
Node_Unique_ID indirect_offset (000002h)
unit_directory offset (000004h)
Note that the last two quadlets of Table 3–10 are entries that point to a leaf and a directory, respectively. The leaves
are shown in Table 3–11 and Table 3–12.
Table 3–11. Node_Unique_ID Leaf
NAME
Offset
0-7
8-15
16-23
24-31
FFFF F000 0428h
FFFF F000 042Ch
FFFF F000 0430h
0002h
node_vendor_ID
chip_id_lo
CRC
Node_ Unique_ID leaf
chip_id_hi
3–6
Table 3–12. Unit Directory
NAME
Offset
0-7
8-15
16-23
24-31
FFFF F000 0434h
FFFF F000 0438h
FFFF F000 043Ch
FFFF F000 0440h
0003h
CRC
12h
13h
D4h
unit_spec_ID (=0x00A02D)
unit_sw_version (=0x000100)
unit_dependent_directory offset
Unit directory
The last quadlet of the unit directory in Table 3–12 contains an offset to another directory, shown below in Table 3–13.
Table 3–13. Unit-Dependent Directory
NAME
Offset
0-7
8-15
16-23
24-31
FFFF F000 0444h
FFFF F000 0448h
FFFF F000 044Ch
FFFF F000 0450h
unit_dep_info_length
CRC
40h
81h
82h
command_regs_base
vendor_name_leaf
model_name_leaf
Unit-dependent directory
In the unit-dependent directory, command_regs_base points to the base address of the inquiry, control, and
configuration registers (FFFF F0F0 0000h). It is expressed in terms of quadlets, relative to the base address of initial
register space (FFFF F000 0000h).
Two leaves are provided that should contain ASCII strings representing the camera vendor and model names. These
are referred to as the vendor name leaf and model name leaf. The unit-dependent directory also contains pointers
totheseleaves. Vendor_name_leafspecifiesthenumberofquadletsfromtheaddressofthevendor_name_leafentry
(FFFF F000 044Ch) to the address of the vendor name leaf. Model_name_leaf specifies the number of quadlets from
the address of the model_name_leaf entry (FFFF F000 0450h) to the address of the model name leaf.
The format of the vendor and model name leaves is shown in Table 3–14 and Table 3–15.
Table 3–14. Vendor Name Leaf
NAME
Offset
0-7
8-15
16-23
00 0000h
char_2
24-31
FFFF F000 0454h
FFFF F000 0458h
FFFF F000 045Ch
FFFF F000 0460h
leaf_length
CRC
00h
Vendor name leaf
0000 0000h
char_0
char_1
char_3
Table 3–15. Model Name Leaf
NAME
Offset
0-7
8-15
16-23
24-31
FFFF F000 0464h
FFFF F000 0468h
FFFF F000 046Ch
FFFF F000 0470h
FFFF F000 0474h
FFFF F000 047Ch
FFFF F000 0480h
FFFF F000 0480h
leaf_length
CRC
00h
00 0000h
Model name leaf
0000 0000h
char_0
char_4
char_8
char_1
char_5
char_2
char_6
…
char_3
char_7
Model name leaf
…
char + n – 3
char_n – 2
char_n – 1
NUL
NUL
Notice that these leaves have length that varies according to the length of the ASCII strings. A total of 13 quadlets
is provided for these two leaves. Because each leaf contains a three-quadlet header, seven quadlets are available
for ASCII characters. These seven quadlets can be appropriated in any way between the two name leaves, providing
that the directory length field in each leaf reflects the appropriation. Also, the vendor_name_leaf and
model_name_leaf fields in the unit-dependent directory leaf must point to their appropriate leaves. This is especially
important for the model name leaf, since its address can move depending on the length of the vendor name leaf.
3–7
3.3.2 Inquiry Registers
The Digital Camera Specification provides for a wide variety of features a vendor can choose to implement. However,
a compliant camera must include a series of registers that indicate exactly which of the standard features are
supported. These inquiry registers also provide some basic information about the way in which the camera supports
these features, such as whether an automatic control exists.
These values are determined during camera system development and must be written to the EEPROM when
cameras are built. TheTSB15LV01supportsthemajorityoffeaturesprovidedundertheDigitalCameraSpecification.
Note that setting these values does not change any camera functionality. It only changes what the host perceives the
capability of the camera to be.
The inquiry registers have a base destination offset of FFFF F0F0 0000h. In the tables that follow, all listed offsets
are specified in bytes, relative to this base address. Most fields serve as Boolean flags that indicate availability of the
feature, with a 1 indicating availability. Other types of fields are marked accordingly.
3.3.2.1 Video Format Inquiry Register
The video format describes the format of the video information being transmitted by the TSB15LV01 across the 1394
serial bus. The only formatsupportedbyv1.04ofthedigitalcameraspecificationisVGAnon-compresseddata, which
has a maximum of 640 x 480 resolution. Space is reserved for future expansion to other formats.
Table 3–16. Video Format Memory Map
NAME
OFFSET
0–7
8–15
16–23
24–31
FORMAT_INQ
100h
Format_x
Rsrv
Table 3–17. Video Format Register Proper Values for TSB15LV01
NAME
OFFSET
0–7
8–15
16–23
24–31
FORMAT_INQ
100h
1
XXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Table 3–18. Video Format Field Descriptions
FIELD NAME
BITS
0
DESCRIPTION
VGA noncompressed format. (Maximum 640 x 480)
Reserved for other formats
Format_0
Format_x
Reserved
1..7
8..31
Reserved (all zero)
3–8
3.3.2.2 Video Mode Inquiry Registers
The video mode describes the type of data output by the digital camera. These modes correspond with those
described in section 2.1.2.1, Isochronous Packet Format/Protocol.
The base address is FFFF F0F0 0000h. All listed offsets are specified in bytes, relative to this base address. All fields
are Boolean flags; a 1 indicates availability.
Table 3–19. Video Mode Memory Map
NAME
OFFSET
0–7
8–15
16–23
24–31
VIDEO_MODE_INQ_0
100h
Rsrv
(640 × 480 VGA Format)
VIDEO_MODE_INQ_0 184h..19Fh
Reserved for other formats
Table 3–20. Video Mode Proper Values for TSB15LV01
NAME
OFFSET
0–7
8–15
16–23
24–31
VIDEO_MODE_INQ_0
(640 × 480 VGA Format)
100h
1 1 1 1 1 1 XX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
VIDEO_MODE_INQ_0 184h..19Fh
Table 3–21. Video Mode Field Descriptions
FIELD NAME
Mode_0
Mode_1
Mode_2
Mode_3
Mode_4
Mode_5
Mode_x
BITS
DESCRIPTION
160 × 120 YUV(4:4:4) Mode (24 bit/pixel)
320 × 240 YUV(4:2:2) Mode (16 bit/pixel)
640 × 480 YUV(4:1:1) Mode (12 bit/pixel)
640 × 480 YUV(4:2:2) Mode (16 bit/pixel)
640 × 480 RGB Mode (24 bit/pixel)
640 × 480 Y (Mono) Mode (8 bit/pixel)
Reserved for other modes
0
1
2
3
4
5
6..7
8..31
Reserved
Reserved (all zero)
3.3.2.3 Video Frame Rate Inquiry Registers
These registers describe the availability of the various frame rates for the digital camera. A separate register is
provided for each combination of format and mode, and this relationship is shown in Table 3–22.
The base address is FFFF F0F0 0000h. All listed offsets are specified in bytes, relative to this base address. All fields
are Boolean flags; a 1 indicates availability.
3–9
Table 3–22. Video Frame Rate Memory Map
NAME
OFFSET
0–7
8–15
16–23
24–31
RATE_INQ_0
200h
Rsrv
(160 × 120 YUV (4:4:4))
RATE_INQ_1
(320 × 240 YUV (4:2:2))
204h
208h
20Ch
Rsrv
Rsrv
Rsrv
RATE_INQ_2
(320 × 240 YUV (4:1:1))
RATE_INQ_3
(640 × 480 YUV (4:2:2))
RATE_INQ_4
(640 × 480 RGB)
210h
214h
Rsrv
Rsrv
RATE_INQ_5
(640 × 480 Mono)
Table 3–23. Video Frame Rate Proper Values for TSB15LV01
NAME
OFFSET
200h
0-7
1
8-15
16-23
24-31
RATE_INQ_0
RATE_INQ_1
RATE_INQ_2
RATE_INQ_3
RATE_INQ_4
RATE_INQ_5
X
X
X
X
X
X
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
XXX
XXX
XXX
XXX
XXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
204h
1
208h
1
20Ch
210h
1
1
214h
1
0 XX
Table 3–24. Video Frame Rate Field Descriptions
FIELD NAME
BITS
0
DESCRIPTION
FrameRate_0
FrameRate_1
FrameRate_2
FrameRate_3
FrameRate_4
FrameRate_5
FrameRate_x
FrameRate_y
Reserved
Reserved
3.75 fps
7.5 fps
15 fps
1
2
3
4
30 fps
5
60 fps
5..7
6..7
6..31
Reserved for another frame rate
Reserved for another frame rate
Reserved (all zero)
3–10
3.3.2.4 Basic Function Inquiry Register
This register describes the availability of some top-level features.
The base address is FFFF F0F0 0000h. The listed offset is specified in bytes, relative to this base address. All fields
are Boolean flags; a 1 indicates availability.
Table 3–25. Memory Map for Basic Function Register
NAME
OFFSET
0–7
8–15
16–23
24–31
BASIC_FUNC_INQ
400h
Rsrv
Rsrv
Table 3–26. Basic Function Register Proper Values for TSB15LV01
NAME
OFFSET
0–7
8–15
16–23
24–31
0000
BASIC_FUNC_INQ
400h
XXXXXXXX
XXXXXXXX
1 X X 1 XXXX XXXX
Table 3–27. Field Descriptions for Basic Function Register
FIELD NAME
Reserved
BITS
0..15
16
DESCRIPTION
Reserved
cam_power_inq
Reserved
Camera process power on/off capability
Reserved
17..18
19
one_shot_inq
Reserved
One shot transmission capability
Reserved
20..27
28..31
memory_channel
Maximum memory channel number (N) Memory channel number
0 = Factory setting memory
1 = Memory Ch 1
2 = Memory Ch 2
:
N = Memory Ch N
If 0000, user memory is not available.
3–11
3.3.2.5 Feature Presence Inquiry Registers
These registers indicate the availability of some low level features.
The base address is FFFF F0F0 0000h. All listed offsets are specified in bytes, relative to this base address. All fields
are Boolean flags; a 1 indicates availability.
Table 3–28. Memory Map for Feature Presence Registers
NAME
OFFSET
0–7
8–15
16–23
24–31
FEATURE_HI_INQ
404h
Rsrv
FEATURE_LO_INQ
408h
Rsrv
Table 3–29. Feature Presence Registers Proper Values for TSB15LV01
NAME
OFFSET
404h
0–7
1 1 1 1 0 1 1 1 1 ? ? XXXXX
? 0 0 XXXXX XXXXXXX
8–15
16–23
24–31
FEATURE_HI_INQ
FEATURE_LO_INQ
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
408h
Table 3–30. Field Descriptions for Feature Presence Registers
FIELD NAME
Brightness
Exposure
Sharpness
White_Balance
Hue
BITS
DESCRIPTION
Brightness control
0
1
Exposure control
Sharpness control
White Balance control
Hue control
2
3
4
Saturation
Gamma
Shutter
5
Saturation control
Gamma control
6
†
7
Shutter control
Gain
8
Gain control
‡
Iris
9
Iris control
‡
Focus
10
Focus control
11..31 Reserved
‡
Zoom control
Zoom
Pan
Tilt
0
1
2
Pan control
Tilt control
3..31 Reserved
†
‡
On the TSB15LV01, the shutter register controls the backlight
compensation feature.
The proper setting of these bits depends on whether the designer has
implemented focus, zoom, and iris motorized controls on the camera.
3.3.2.6 Feature Elements Inquiry Registers
These registers indicate the availability of features provided in the Digital Camera Specification. All registers are
supported except hue, pan, and tilt, and this is reflected in the proper values in Table 3–31. (Note that pan and tilt
features can still be supported, as described in section 2.4, Motor Control Interface).
3–12
The base address is FFFF F0F0 0000h. All listed offsets are specified in bytes, relative to this base address. All fields
are Boolean flags; a 1 indicates availability.
Table 3–31. Memory Map for Feature Elements Inquiry Registers
NAME
OFFSET
0–7
8–15
16–23
24–31
BRIGHTNESS_INQ
500h
min_value
max_value
EXPOSURE_INQ
SHARPNESS_INQ
WHITE_BAL_INQ
504h
508h
50Ch
min_value
min_value
min_value
max_value
max_value
max_value
HUE_INQ
510h
514h
min_value
min_value
max_value
max_value
SATURATION_INQ
GAMMA_INQ
518h
min_value
max_value
†
SHUTTER_INQ
51Ch
520h
min_value
min_value
max_value
max_value
GAIN_INQ
‡
IRIS_INQ
524h
528h
580h
min_value
min_value
min_value
max_value
max_value
max_value
‡
FOCUS_INQ
‡
ZOOM_INQ
PAN_INQ
TILT_INQ
584h
588h
min_value
min_value
max_value
max_value
†
‡
On the TSB15LV01, the shutter register controls the backlight compensation feature
The proper setting of these bits depends on whether the designer has implemented focus, zoom, and iris motorized
mechanisms on the camera, and the individual characteristics of those mechanisms.
3–13
Table 3–32. Feature Elements Registers Proper Values for TSB15LV01
NAME
OFFSET
500h
504h
508h
50Ch
510h
514h
518h
51Ch
520h
524h
528h
580h
584h
588h
0-7
1
8-15
16-23
24-31
BRIGHTNESS_INQ
EXPOSURE_INQ
SHARPNESS_INQ
WHITE_BAL_INQ
HUE_INQ
1
1
1
1
0
1
1
1
1
?
?
?
0
0
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
0
0
0
0
X
0
0
0
0
0
0
0
X
X
1
1
0
1
X
0
0
0
0
0
0
0
X
X
1
1
1
1
X
1
1
1
1
1
1
1
X
X
000
000
000
000
XXX
000
000
000
000
???
???
???
XXX
XXX
1FF
1FF
0FF
0FF
1
1
1
X
1
XXX
0FF
001
007
0FF
???
???
???
XXX
XXX
SATURATION_INQ
GAMMA_INQ
1
†
SHUTTER_INQ
GAIN_INQ
1
1
‡
IRIS_INQ
1
‡
FOCUS_INQ
1
‡
ZOOM_INQ
PAN_INQ
TILT_INQ
1
X
X
†
‡
On the TSB15LV01, the shutter register controls the backlight compensation feature
The proper setting of these bits depends on whether the designer has implemented focus, zoom, and iris motorized
mechanisms on the camera, and the individual characteristics of those mechanisms.
Table 3–33. Field Descriptions for Feature Elements Registers
FIELD NAME
BITS
DESCRIPTION
Presence
0
1..3
4
Presence of this feature
Reserved
§
Capability of reading the value of this feature
ReadOut
On/Off
5
Capability of switching this feature on and off
Auto mode (in which the feature is controlled automatically by camera)
Manual mode (in which the feature is controlled directly by user)
MIN Value for this feature control
Auto
6
Manual
7
MIN_Value
MAX_Value
8..19
20..31
MAX Value for this feature control
§
All control values in manual mode can be read. Values cannot be read during auto modes.
3.3.3 Control and Configuration Registers
These registers are used to control the digital camera, as well as allowing the host to read camera status. The control
registers are required by the Digital Camera Specification. They control some of the basic camera operations, such
as frame rate, output format, and video parameters. The configuration registers are unique to the TSB15LV01. They
allow the user to configure features unique to the TSB15LV01 and fine-tune its interface with supporting components.
As with the inquiry registers, the control and configuration registers have a base destination offset of FFFF F0F0
0000h. In the tables that follow, all listed offsets are specified in bytes, relative to this base address.
3.3.3.1 Control Registers
As stated earlier, all features provided for by the digital camera specification are listed.
3–14
3.3.3.1.1 Camera Initialize Register
This register is not used on the TSB15LV01.
Table 3–34. Camera Initialize Register Memory Map
NAME
OFFSET
0–7
8–15
16–23
24–31
INITIALIZE
000h
Rsrv
Table 3–35. Camera Initialize Register Field Descriptions
FIELD CODE
BITS
DESCRIPTION
Rsrv
0..31
Reserved (all zero)
3.3.3.1.2 Function Control Registers
These registers control the basic functionality of the camera. The base address is FFFF F0F0 0000h. All listed offsets
are specified in bytes, relative to this base address.
Table 3–36. Memory Map for Camera Registers
NAME
OFFSET
0–7
8–15
16–23
24–31
CUR_V_FRM_RATE_CNTL
600h
Rsrv
Rsrv
Rsrv
CUR_V_MODE_CNTL
604h
608h
CUR_V_FORMAT_CNTL
ISO_CHANNEL/SPEED_CNTL
60Ch
Rsrv
CAMERA_POWER_CNTL
ISO_EN_CNTL
610h
614h
Rsrv
Rsrv
RSRV
618h
61Ch
Rsrv
Rsrv
ONE_SHOT_CNTL
RSRV
620h..
624h
Rsrv
3–15
Table 3–37. Field Descriptions for Camera Registers
DESCRIPTION
FIELD NAME
Frame_rate
Video_mode
Video_format
Iso_chnl
BITS
0..2
0..2
0..2
0..3
4..5
6..7
Current frame rate (FrameRate_0 .. FrameRate_7)
Current video mode (Mode_0 .. Mode_7)
Current video format (Format_0 .. Format_7)
1394 isochronous channel number for video data transmission (0-15)
Reserved
Iso_speed
1394 isochronous transmit speed code
0 = s100
1 = s200
2 = s400
Cam_power
0
This register determines the on/off status of the TSB15LV01. It also directly controls the CAM_POWER terminal of
the device, which can be used to control power to the CCD.
1 = power up camera
0 = power down camera.
Iso_Enable
One_shot
0
0
1 = start isochronous transmission of video data
0 = stop isochronous transmission of video data
1 = only one frame of video data is transmitted. Self-cleared after transmission. Ignored if ISO_EN_CNTL (field
iso_en) = 1.
3–16
3.3.3.1.3 Feature Control Registers
These registers control features pertaining to video processing and motor control.
The base address is FFFF F0F0 0000h. All listed offsets are specified in bytes, relative to this base address.
Table 3–38. Memory Map for Feature Control Registers
NAME
OFFSET
0–7
8–15
16–23
24–31
Value
BRIGHTNESS_CNTL
800h
Rsrv
Rsrv
Rsrv
Rsrv
Rsrv
EXPOSURE_CNTL
SHARPNESS_CNTL
WHITE_BAL_CNTL
804h
508h
80Ch
Value
Value
Rsrv
U_Value
V_Value
RSRV
510h
814h
Rsrv
SATURATION_CNTL
Rsrv
Rsrv
Rsrv
Value
Value
GAMMA_CNTL
818h
Rsrv
†
SHUTTER_CNTL
81Ch
820h
Rsrv
Rsrv
Rsrv
Rsrv
Value
Value
GAIN_CNTL
IRIS_CNTL
824h
828h
Rsrv
Rsrv
Rsrv
Rsrv
Value
Value
FOCUS_CNTL
RSRV
82Ch..
87CH
Rsrv
ZOOM_CNTL
580h
Rsrv
Rsrv
Value
RSRV
884h..
8FCH
Rsrv
†
On the TSB15LV01, the shutter register controls the backlight compensation feature.
3–17
Table 3–39. Field Descriptions for Feature Registers
FIELD NAME
BITS
DESCRIPTION
Presence
0
Presence of this feature should match the value in the corresponding feature control inquiry register.
0 : Not available
1 : Available
Reserved
ON_OFF
1..5
6
Reserved
If this field is written to, it turns the feature on or off (1 or 0, respectively). If this field is read, it indicates the on/off
status of the feature. (As the inquiry registers indicate, this feature is not enabled for any of the controls in the
TSB15LV01.)
A_M_Mode
7
Indicates whether an automatic mode is active for this feature. Writing to this field changes the mode status.
Reading from it indicates the mode status.
0 : Manual
1 : Auto
8..19
Reserved.
Value
20..31
Value associated with the feature. If a value is written to this field while A_M_Mode indicates auto mode, this
field is ignored. If readout capability for this feature is not available as indicated by the corresponding feature
elements inquiry register, the value read from this address has no meaning.
U_Value
V_Value
8..19
U-Value. Target U-value for white balance. If a value is written when A_M_Mode indicates auto mode, this field
is ignored. If readout capability for this feature is not available (see Feature Elements Inquiry Register), the
value read from this address has no meaning.
20..31
V-Value. Target U-value for white balance. If a value is written when A_M_Mode indicates auto mode, this field
is ignored. If readout capability for this feature is not available (see Feature Elements Inquiry Register), the
value read from this address has no meaning.
3–18
3.3.3.1.4 Configuration Registers
These registers control features and enhancements that are unique to the TSB15LV01. Most of these features have
been addressed in prior sections of this document when applicable.
Table 3–40 shows a memory map of the configuration registers. The base address is FFFF F0F0 0000h. All listed
offsets are specified in bytes, relative to this base address.
Table 3–40. Configuration Register Memory Map
NAME
OFFSET
0F00h
0F04h
0F08h
0
1
2
3
4
5
6
7
EEPROM_CNFG
write_protect_control
RSRV
TEST_CNFG
test_en
CCD_PULSE_CNFG
RSRV
RSRV
h2
RSRV
RSRV
RSRV
rst_rg
srg_h1
adclk
CDS_PULSE_CNFG
AUTO_ADJ_CNFG
DAC_OFFSET_CNFG
CCD_OPTICS_CNFG
STATUS_CNFG
0F0Ch
0F10h
0F14h
0F18h
0F1Ch
RSRV
RSRV
RSRV
sv
sr
stable
min_gain
expo_delta_high
expo_delta_low
expo_ref
dac2_en bloom_en
RSRV
dac2_value
blooming_value
offset_level
filter_limit
RSRV
filter
h-center
v-center
stat_input
stat2
RSRV
RSRV
RSRV
RSRV
RSRV
RSRV
stat1
stat0
AFE_SETUP_CNFG
0F20h
0F22h
lines_smpl
pixels_smpl
ccd_sel
v_inv rb_shift
internal_bias
RSRV
afe_sel
ad_inv
VIDEO_OPTIONS_CNFG
h_inv
Hz
RSRV
color_bw pix_shp
3–19
Table 3–40. Configuration Register Memory Map (Continued)
NAME
OFFSET
0
1
2
3
4
5
6
7
MOTOR_POS_CNFG
0F24h
ir_en
RSRV
ir_zoom (msb)
ir_focus (msb)
ir_iris (msb)
ir_zoom (lsb)
ir_focus (lsb)
ir_iris (lsb)
Table 3–41. Field Descriptions for Configuration Registers
REGISTER
EEPROM_CNFG
TEST_CNFG
FIELD CODE
write_protect_
control
BITS
DESCRIPTION
0..31 Write protect control code. Allows write access to EEPROM. Writing 12345678h unlocks,
all other values lock.
test_en
0
Color bar test pattern. Setting this bit high enables color bar test pattern
h2
10..15 H2 pulse position. H2 pulse placement register.
00h : places it at the nominal value for the chosen CCD
3Fh : places it at maximum delay
rst
srg/h1
adclk
sv
18..23 RST pulse position. RST pulse placement register.
00h : places it at the nominal value for the chosen CCD
3Fh : places it at maximum delay
CCD_PULSE_CNFG
26..31 SRG/H1 pulse position. SRG/H1 pulse placement register
00h : places it at the nominal value for the chosen CCD
3Fh : places it at maximum delay
2..7
ADCLK pulse position. ADCLK pulse placement register.
00h : places it at the nominal value for the chosen CCD
3Fh : places it at maximum delay
18..23 SV pulse position. SV pulse placement register.
00h : places it at the nominal value for the chosen CCD
3Fh : places it at maximum delay
CDS_PULSE_CNFG
sr
26..31 SR pulse position. SR pulse placement register.
00h : places it at the nominal value for the chosen CCD
3Fh : places it at maximum delay
stable
0..7
Number of frames before enabling auto exposure. Gives the image time to stabilize at
start-up to prevent oscillation.
min_gain
expo_delta_
high
8..15 Minimum gain to saturate CCD
16..20 Speed control adjustment for auto exposure loop. Applies to frames in which the average
luminanceis very far away from the level specified in expo_ref. As this value is increased,
adjustments are made to gain/exposure more quickly, but setting higher than 11011b can
lead to instability. Recommended value is 10011b.
AUTO_ADJ_CNFG
expo_delta_
medium
21..23 Speed control adjustment for auto exposure loop. Applies to frames in which the average
luminance is deviant from the level specified in expo_ref, but not to the extent as those to
which expo_delta_high applies. As this value is increased, adjustments are made to gain/
exposure more quickly. Recommended value is 010b.
expo_ref
24..31 Autoexposure reference. Target value used in the auto-gain and -exposure feedback
loop. This value is the average luminance of the hot region sampled for the autoexposure
loop.
3–20
Table 3–41. Field Descriptions for Configuration Registers (Continued)
REGISTER
FIELD CODE
BITS
DESCRIPTION
dac2_en
0
DAC-2 enable. Enables output to general purpose DAC in AFE
0 : Disabled
1 : Enabled
bloom_en
1
Blooming DAC enable. Enables output to general purpose DAC in AFE, configured to
supply blooming reference values to the CCD.
0 : Disabled
1 : Enabled
DAC_OFFSET_CNFG
dac2_value
8..15 DAC-2 value. Output value for DAC-2 (see DAC-2 Enable, above)
blooming_value 16..23 Blooming DAC value. Output value for Blooming DAC (see Blooming DAC Enable,
above)
offset_
level
24..31 Black offset reference. Black reference value for digital black clamping. Recommended
value is 40h.
filter_limit
0..7
Filter limit. Specifies the maximum amount of error allowed when the non-linear
interpolation white spot compensation filter is used (see filter field).
filter
8..15 White spot compensation filter select. Selects between two white-spot compensation
filters implemented in the TSB15LV01, or de-activates the filter.
0 : Off
1 : Median Filter
CCD_OPTICS_CNFG
2 : Non-linear Interpolation (requires limit value in filter_limit field, above)
h-center
20..23 Lens horizontal center. Indicates the horizontal position of the CCD image’s upper left
corner, with respect to the left-most active pixels (does not include dummy and black
pixels)
v-center
st_stat
28..31 Lens vertical center. Indicates the vertical position of the CCD image’s upper left corner,
with respect to the top-most pixels (does not include dummy and black pixels)
5..7
Status terminal input/output. Indicates the value being read from or written to the STAT2,
STAT1, and STAT0 terminals, in order from MSB to LSB. If STAT2, STAT1, or STAT0 is
configured as an output, writing to this register changes the output of that terminal.
stat2
stat1
13..15 STAT2 configuration. Indicates which STAT input/output is tied to the STAT2 terminal.
See Table 2-3-1 for corresponding values.
STATUS_CNFG
21..23 STAT1 configuration. Indicates which STAT input/output is tied to the STAT1 terminal.
See Table 2-3-1 for corresponding values.
stat0
29..31 STAT0 configuration. Indicates which STAT input/output is tied to the STAT0 terminal.
See Table 2-3-1 for corresponding values.
lines_smpl
pixels_smpl
0..3
Lines per image. This value is sent to the AFE to tell it the number of lines per image that
should be sampled for black clamping.
4..7
Black clamp sampling. This value is sent to the AFE to tell it the number of pixels per line
that should be sampled for black clamping.
internal_bias
ccd_sel
8..11 AFE bias current. Set to 0110b.
AFE_SETUP_CNFG
12..14 CCD Select. Indicates the CCD being used with this device.
0 : TI TC237 1/3 B&W sensor (if this is selected, color_bw field in
VIDEO_OPTIONS_CNFG must be cleared also.
1 : Sony ICX084AK 1/3 color sensor
2 : Sony ICX098AK ¼ color sensor; Sharp LZ24BP 1/3 color sensor
afe_sel
15
Always set to 1.
3–21
Table 3–41. Field Descriptions for Configuration Registers (Continued)
REGISTER
FIELD CODE
BITS
DESCRIPTION
h_inv
20
Horizontal CCD pulse inversion. Inverts all horizontal drive pulses. Recommended value
is 0.
0 : No inversion
1 : Inversion
v_inv
21
22
Vertical CCD pulse inversion. Inverts all vertical drive pulses. Recommended value is 0.
0 : No inversion
1 : Inversion
rb_shft
Red/Blue pixel shift. Indicates whether one-color pixel shift is implemented.
Recommended value is 1.
0 : No pixel shift
1 : Pixel shift
ad_inv
Hz
23
24
ADCLK Inversion. Inverts pulses from the ADCLK terminal. Recommended value is 0.
0 : No inversion
1 : Inversion
VIDEO_OPTIONS_CNFG
Integration Hz. Reduces the actual frame rate to approximately 83.3% of the one
indicated in the CUR_V_FRM_RATE _CNTL register. For example, 30 fps becomes
25 fps. This can be used to reduce flicker in countries using 50-Hz lighting.
0 : No reduction
1 : Reduction
color_bw
pix_shp
30
31
0
Color/BW. Indicates the type of CCD being used.
0 : Black and white CCD (TC237 only)
1 : Color CCD (all others)
Pixel shape. Indicates the way CCD pixel data are interpreted.
0 : L-Shaped pixels
1 : Square pixels
ir_enable
ir_zoom
ir_focus
ir_iris
IR_Enable. Used internally.
2..11 IR_Zoom. Starting position (IR sensor location) of the zoom stepper motor.
12..21 IR_Focus. Starting position (IR sensor location) of the focus stepper motor.
22..31 IR_Iris. Starting position (IR sensor location) of the iris stepper motor.
MOTOR_POS_CNFG
3–22
4 Electrical Characteristics
4.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (Unless
†
Otherwise Noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
CC
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
I
I
CC
IK
Output clamp current, I (V < 0 or V > V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O
O
CC
Operating free-air temperature range (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
(”I” suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. This applies to external input and bidirectional buffers.
2. This applies to external output and bidirectional buffers.
4.2 Recommended Operating Conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
CC
3
0
0
3.3
3.6
Input voltage, V
V
V
V
I
CC
CC
CC
Output voltage, V (see Note 3)
V
O
High-level input voltage, V
IH
0.7V
V
V
CC
0
Low-level input voltage, V
0.3V
V
IL
Input transition time, t and t (10% to 90%)
CC
25
0
0
ns
f
r
No suffix
25
25
25
70
85
Operating free-air temperature, T
°C
°C
A
”I” suffix
–40
Virtual junction temperature, T (see Note 4)
JC
NOTES: 3. This applies to external output buffers.
0
115
4. The junction temperatures listed reflect simulation conditions. The customer is responsible for verifying the junction temperature.
4–1
4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature (Unless Otherwise Noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
‡
I
I
I
I
= –12 mA
0.8V
OH
OH
OL
OL
CC
V
V
High-level output voltage
V
OH
§
= –8 mA
0.8V
CC
‡
= 24 mA
0.22V
CC
Low-level output voltage
V
OL
§
= 8 mA
0.22V
CC
I
I
Low-level input current
High-level input current
V = V
–1
µA
µA
IL
I
IL
V = V
I
1
IH
IH
High-impedance output
current
I
V
O
= V or GND
CC
±20
µA
OZ
CAMERA_POWER_CNTL
and ISO_EN_CNTL
activated
22
27
All V
and
CC
_CORE terminals
I
Static supply current
mA
CC(Q)
V
CC
CAMERA_POWER_CNTL
and ISO_EN_CNTL
deactivated
†
‡
§
All typical characteristics are measured at V
CC
= 3.3 V and T = 25°C.
A
For ABSP_XSG, IAG_XV3, SAG_XV1, ABD_XSUB, SRG_H1, RST_RG
For all other outputs.
4–2
5 Application Information
A G N D
A G N D
D D A V
D D A V
/ R E S E T
T E R F I 2 L
T E R F I 1 L
V D D P L L
P L L G N D
A G N D
3 2
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
D D A V
D D A V
S M
3 1
3 0
2 9
2 8
S E
T E S T M
2 7
D V D D
2 6
D V D D
2 5
C P S
2 4
P L L G N D
O
/ I S
2 3
P C 2
2 2
X 1
X O
D V D D
D V D D
D G N D
D G N D
P C 1
2 1
P C 0
2 0
C / L K L O N
1 9
D G N D
1 8
D G N D
1 7
D
P A
V C C
G N D
R E S E T
T E S T _ M O D E
6 1
6 2
6 3
6 4
6 5
6 6
6 7
6 8
6 9
7 0
7 1
7 2
7 3
7 4
7 5
7 6
7 7
7 8
7 9
8 0
4 0
R S T _ R G
3 9
S R G _ H 1
3 8
E E P R O M _ S C L K
E E P R O M _ S I
E E P R O M _ C S
H 2
3 7
G N D
3 6
A B D _ X S U B
3 5
S A G _ X V 1
3 4
V C C
P G 2
E E P R O M _ S O
X V 2
3 3
A B S P _ X S G
3 2
V C C _ C O R E
V D D _ C A P
V D D _ C A P
3 1
V C C _ C O R E
3 0
E N Z
G A _ I X V 3
2 9
F O C U S _ M I N U S
F O C U S _ P L U S
I R _ S I G
G N D
P H A S E 2 B
P H A S E 2 A
P H A S E 1 B
P H A S E 1 A
C A M _ P O W E R
2 8
V C C
2 7
P D 0
2 6
P D 0
P D 1
P D 2
P D 3
P D 4
P D 1
2 5
P D 2
2 4
P D 3
2 3
P D 4
2 2
G N D
2 1
5–1
Sheet 2
G A N D 5
R B D
/ O E
S C K P
3 7
3 8
3 9
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
4 8
2 4
2 3
D A C O 2
2 2
R M D
R P D
D V D A 5
V S S
D V D A 1
D A C O 1
2 1
A G N D 3
2 0
D V D A 3
1 9
D I G N D
1 8
A G N D 1
D I V D D
+ 3 .
3 V
P D 9
P D 8
P D 7
P D 6
1 7
1 6
1 5
1 4
1 3
R / S
V / S
M A P / C L
C L R E F
D 9
D 8
D 7
D 6
3
2
V D D
G N D
S U B
C S U B
R G
O U T
G N D
V L
V O 2 B
V O 2 A
V O 3
V O 1
7
6
5
4
3
2
1
0 8
0 9
1 0
1 1
1 2
1 3
1 4
H O 1
H O 2
1
3
5–2
6 Mechanical Information
The TSB15LV01 is packaged in a high-performance 80-pin PFC package. The following shows the mechanical
dimensions of the PFC package.
PFC (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
M
0,50
60
0,08
0,17
41
40
61
80
21
0,13 NOM
1
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
0,25
14,20
SQ
0,05 MIN
0°–ā7°
13,80
0,75
0,45
1,05
0,95
Seating Plane
0,08
1,20 MAX
4073177/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
6–1
6–2
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
TQFP
TQFP
Drawing
TSB15LV01IPFC
TSB15LV01PFC
ACTIVE
ACTIVE
PFC
80
80
96
96
TBD
TBD
Call TI
Level-3-235C-168 HR
PFC
CU NIPDAU Level-3-235C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF009A – OCTOBER 1994 – REVISED DECEMBER 1996
PFC (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
M
0,50
60
0,08
41
40
61
80
21
0,13 NOM
1
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
0,25
14,20
SQ
0,05 MIN
0°–7°
13,80
0,75
0,45
1,05
0,95
Seating Plane
0,08
1,20 MAX
4073177/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
相关型号：
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