TSB43CA42 [TI]
TI iceLynx-Micro⑩ IEEE 1394a-2000 Consumer Electronics Solution; TI iceLynx - Micro⑩器IEEE 1394a -2000消费电子解决方案
| 型号： | TSB43CA42 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TI iceLynx-Micro⑩ IEEE 1394a-2000 Consumer Electronics Solution |
| 文件： | 总97页 (文件大小：1383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TSB43CA43A/TSB43CB43A/TSB43CA42
iceLynx-Micro
IEEE 1394a-2000
Consumer Electronics Solution
ABBREVIATED DATA MANUAL
SLLS546F – September 2004
Texas Instruments Incorporated, Copyright 2004
For more information and/or a complete data manual on this product, contact the
Texas Instruments Product Information Center (PIC). Local PIC contact numbers
are listed on http://www.ti.com/corp/technical_support.htm
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
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Copyright © 2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
2
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
Table of Contents
1
Hardware IC Characteristics..................................................................................................................8
1.1
Feature List................................................................................................................................... 8
1394 Features .........................................................................................................................8
DTLA Encryption Support for MPEG2-DVB, DSS, DV, and Audio (TSB43CA43A and
1.1.1
1.1.2
TSB43CA42 Only)...................................................................................................................8
High Speed Data Interface (HSDI)..........................................................................................9
External CPU Interface............................................................................................................9
Internal ARM7..........................................................................................................................9
Data Buffers.............................................................................................................................9
Hardware Packet Formatting for the Following Standards .....................................................9
Additional Features .................................................................................................................9
Application Diagram.................................................................................................................... 10
Block Diagram............................................................................................................................. 11
TSB43Cx43A Block Diagram ................................................................................................11
TSB43CA42 Block Diagram..................................................................................................12
Pin Out........................................................................................................................................ 13
TSB43CA43A/TSB43CB43A Plastic Quad Flat Pack (PQFP)..............................................13
TSB43CA43A/TSB43CB43A Micro-Star Ball Grid Array (µ*BGA)........................................14
TSB43CA42 Plastic Quad Flat Pack (PQFP)........................................................................15
TSB43CA42 Micro-Star Ball Grid Array (µ*BGA)..................................................................16
Pin Description............................................................................................................................ 17
Memory Map............................................................................................................................... 26
DTCP Encryption – Hardware Implementation (TSB43CA43A and TSB43CA42 Only)............ 27
Program Memory ........................................................................................................................ 27
Overview/Description ............................................................................................................27
External CPU (Parallel Mode) ...............................................................................................27
External CPU Interface............................................................................................................... 27
Overview/Description ............................................................................................................27
Endian Setting (Parallel and Memory Accesses)..................................................................29
Ex-CPU Access.....................................................................................................................30
Ex-CPU Timing......................................................................................................................33
LEB Encryption......................................................................................................................52
Integrated CPU ........................................................................................................................... 53
1.1.3
1.1.4
1.1.5
1.1.6
1.1.7
1.1.8
1.2
1.3
1.3.1
1.3.2
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.5
1.6
1.7
1.8
1.8.1
1.8.2
1.9
1.9.1
1.9.2
1.9.3
1.9.4
1.9.5
1.10
1.10.1 Description/Overview ............................................................................................................53
1.10.2 Interaction With External CPU...............................................................................................53
1.10.3 External Interrupts.................................................................................................................53
1.10.4 Timer .....................................................................................................................................54
1.11
High Speed Data Interface ......................................................................................................... 54
1.11.1 Overview/Description ............................................................................................................54
1.11.2 Frame Sync Detection Circuit................................................................................................56
1.11.3 HSDI Pass-Through Function ...............................................................................................56
1.11.4 HSDI Maximum Clock Rates and Throughput ......................................................................57
1.11.5 HSDI Mode Settings..............................................................................................................57
1.11.6 HSDI Transmit Modes...........................................................................................................59
1.11.7 HSDI Receive Modes............................................................................................................62
1.11.8 Audio Interface on HSDI........................................................................................................66
1.12
UART Interface ........................................................................................................................... 70
1.12.1 UART Registers.....................................................................................................................70
1.12.2 UART Baud Rate...................................................................................................................71
1.13
1.14
JTAG – Boundary Scan and ARM.............................................................................................. 72
Integrated 3-Port PHY ................................................................................................................ 72
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
3
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
1.14.1 3-Port PHY ............................................................................................................................72
1.14.2 PHY Registers.......................................................................................................................72
1.14.3 Port Status Page Register.....................................................................................................75
1.14.4 Vendor Identification Page Register......................................................................................77
1.14.5 PHY Application Information .................................................................................................77
1.14.6 PHY Reference Documents ..................................................................................................79
1.15
Power Management.................................................................................................................... 79
1.15.1 PU to A (Power-Up State to Active State).............................................................................81
1.15.2 A to LP1 (Active State to Low Power 1 State).......................................................................81
1.15.3 LP1 to A (Low Power 1 State to Active State).......................................................................81
1.15.4 A to LP2 (Active State to Low Power 2 State).......................................................................81
1.15.5 LP2 to A (Low Power 2 State to Active State).......................................................................82
1.15.6 A to LP4 (Low Power 3 State to Active State).......................................................................82
1.15.7 LP4 to A (Low Power 3 State to Active State).......................................................................82
1.16
16.5K Byte Memory - FIFO......................................................................................................... 83
1.16.1 Overview/Description ............................................................................................................83
1.16.2 Isochronous FIFOs 0 and 1...................................................................................................83
1.16.3 Asynchronous/Asynchronous Stream FIFOs........................................................................84
1.16.4 Broadcast Receive FIFO.......................................................................................................85
1.16.5 FIFO Priority ..........................................................................................................................85
1.16.6 FIFO Monitoring.....................................................................................................................85
1.17
GPIO Configurations................................................................................................................... 86
1.17.1 GPIO Setup ...........................................................................................................................86
1.18
IEEE 1394a-2000 Requirements................................................................................................ 86
1.18.1 Features ................................................................................................................................86
1.18.2 Cycle Master..........................................................................................................................87
Appendix A: Configuration Registers...................................................................................................88
2
2.1
Configuration Registers .............................................................................................................. 88
Description Notes........................................................................................................................ 88
CFR Address Ranges (Offset from CFR Base Address)............................................................ 88
Register Access.......................................................................................................................... 89
2.2
2.3
2.4
3
4
General Information .............................................................................................................................90
3.1
Package Size.............................................................................................................................. 90
Operating Voltage....................................................................................................................... 90
Operating Temperature .............................................................................................................. 90
3.2
3.3
Absolute Maximum Ratings Over Operating Temperature Ranges†..................................................90
4.1
Recommended Operating Conditions (Analog IEEE 1394 I/F) .................................................. 91
Electrical Characteristics Over Recommended Operating Conditions
4.2
4.3
(Unless Otherwise Noted)........................................................................................................... 92
Electrical Characteristics Over Recommended Ranges of Operating Conditions
(Unless Otherwise Noted)........................................................................................................... 92
Device....................................................................................................................................92
Driver.....................................................................................................................................92
Receiver ................................................................................................................................93
Thermal Characteristics.............................................................................................................. 93
Switching Characteristics for PHY Port Interface ....................................................................... 93
Operating, Timing, and Switching Characteristics of XI ............................................................. 93
4.3.1
4.3.2
4.3.3
4.4
4.5
4.6
5
6
7
Reset Power States .............................................................................................................................94
Configuration Register Map.................................................................................................................94
Mechanical Data ..................................................................................................................................95
7.1
PQFP Package Information........................................................................................................ 95
µ*BGA Package Dimensions...................................................................................................... 96
ZGW Package Dimensions......................................................................................................... 97
7.2
7.3
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
4
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
List Of Figures
Figure 1. TSB43Cx43 Typical Application ..................................................................................................10
Figure 2. TSB43Cx43 System Block Diagram............................................................................................11
Figure 3. TSB43CA42 System Block Diagram ...........................................................................................12
Figure 4. TSB43CA43A Plastic QFP Pin Out .............................................................................................13
Figure 5. TSB43CA43A µ*BGA Pin Out .....................................................................................................14
Figure 6. TSB43CA42 Plastic QFP Pin Out................................................................................................15
Figure 7. TSB43CA42 µ*BGA Pin Out........................................................................................................16
Figure 8. TSB43Cx43 Memory Map ...........................................................................................................26
Figure 9. Ex-CPU Access ...........................................................................................................................30
Figure 10. I/O Type-0 68K + Wait Read .....................................................................................................33
Figure 11. I/O Type-0 68K + Wait Write......................................................................................................35
Figure 12. I/O Type-1 SH3 Read ................................................................................................................37
Figure 13. I/O Type-1 SH3 Write ................................................................................................................39
Figure 14. I/O Type-2 M16C SRAM-Like + Wait Read...............................................................................41
Figure 15. I/O Type-2 M16C SRAM-Like + Wait Write ...............................................................................43
Figure 16. I/O Type-3 MPC850 Read .........................................................................................................45
Figure 17. I/O Type-3 MPC850 Write .........................................................................................................47
Figure 18. Memory Type.............................................................................................................................49
Figure 19. Memory Write.............................................................................................................................51
Figure 20. Watchdog Timer Waveform.......................................................................................................54
Figure 21. Example for Data Pass-Through Function ................................................................................57
Figure 22. MPEG2 Serial Burst I/F (TX Mode 1) ........................................................................................59
Figure 23. MPEG2 Serial Video Burst I/F With Frame Sync Detect Circuit (TX Mode 2)...........................60
Figure 24. MPEG2 Serial Video Burst I/F Clock Active Only When Data Is Valid (TX Mode 3).................60
Figure 25. MPEG2 Serial Video Burst I/F With Data Valid (TX Mode 4)....................................................60
Figure 26. MPEG2 Parallel Burst Video I/F (TX Mode 5) ...........................................................................61
Figure 27. MEPG2 Parallel Video Burst I/F With Frame Sync Detect Circuit (TX Mode 6)........................61
Figure 28. MPEG2 Parallel Video Burst I/F With Data Valid (TX Mode 7) .................................................61
Figure 29. MPEG2 I/F (TX Mode 8)............................................................................................................62
Figure 30. DV I/F (TX Mode 9)....................................................................................................................62
Figure 31. MPEG2 Serial Burst Video I/F (RX Mode 1)..............................................................................63
Figure 32. MPEG2 Parallel Burst Video I/F (RX Mode 2)...........................................................................63
Figure 33. MPEG2 Parallel Burst Video I/F (RX Mode 3)...........................................................................63
Figure 34. DV Parallel Burst Video I/F (RX Mode 4) ..................................................................................64
Figure 35. Transmit HSDI AC Timing .........................................................................................................64
Figure 36. Receive HSDI AC Timing ..........................................................................................................65
Figure 37. Example 1 Sampling Frequency (fs): 192 kHz, Master Clock Frequency: 256fs......................68
Figure 38. Example 2 Sample Frequency (fs): 48 kHz, Master Clock Frequency: 768fs...........................68
Figure 39. AC Timing Characteristic on Receiving.....................................................................................69
Figure 40. AC Timing Characteristic on Transmitting.................................................................................69
Figure 41. TPBP and TPBN Connection.....................................................................................................77
Figure 42. TPAP, TPAN, and TPBIAS Connection.....................................................................................78
Figure 43. R0 and R1 Connection ..............................................................................................................78
Figure 44. FILTER0 and FILTER1 Connection...........................................................................................78
Figure 45. TPB, TPA, and TPBIAS Connection for Terminated Port (Port is not used).............................79
Figure 46. Isochronous FIFOs ....................................................................................................................84
Figure 47. Asynchronous/ Asynchronous Stream FIFOs ...........................................................................84
Figure 48. Broadcast Receive FIFO ...........................................................................................................85
Figure 49. Test Load Diagram ....................................................................................................................93
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
5
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
List Of Tables
Table 1. External CPU MCIF Pin Assignment Modes ................................................................................28
Table 2. Ex-CPU I/F Signals .......................................................................................................................29
Table 3. Ex-CPU Access Limitation............................................................................................................32
Table 4. I/O Type-0 68K + Wait Read MCIF AC-Timing Parameters.........................................................34
Table 5. I/O Type-0 68K + Wait Write MCIF AC Timing Parameters .........................................................36
Table 6. I/O Type-1 SH3 Critical Timing (Read) .........................................................................................38
Table 7. I/O Type-1 SH3 AC Timing (Write) ...............................................................................................40
Table 8. I/O Type-2 M16C SRAM-Like + Wait AC Timing Parameters (Read)..........................................42
Table 9. I/O Type-2 M16C SRAM-Like + Wait AC Timing Parameters (Write) ..........................................44
Table 10. I/O Type-3 MPC850 Read AC Timing Parameters.....................................................................46
Table 11. I/O Type-3 MPC850 Write AC Timing Parameters.....................................................................48
Table 12. Memory Type Read AC Timing Parameters...............................................................................50
Table 13. Memory Type Write AC Timing Parameters...............................................................................52
Table 14. Ex-CPU Encryption First Quadlet ...............................................................................................52
Table 15. Ex-CPU Encryption Reference ...................................................................................................53
Table 16. HSDI Signals...............................................................................................................................55
Table 17. Application Counter Values.........................................................................................................56
Table 18. HSDI Pass-Through Function.....................................................................................................57
Table 19. HSDI Maximum Clock Rates and Throughput............................................................................57
Table 20. General HSDI Mode Settings......................................................................................................58
Table 21. HSDI Video Modes .....................................................................................................................59
Table 22. AC Timing Parameters for Serial I/F (Modes 1 and 4)................................................................64
Table 23. AC Timing Parameters for Serial I/F (Modes 2 and 3)................................................................64
Table 24. AC Timing Parameters for Parallel I/F (Modes 5, 6, and 7)........................................................65
Table 25. AC Timing Parameters for Parallel I/F (Modes 8 and 9).............................................................65
Table 26. AC Timing Parameters for Serial I/F (Mode 1) ...........................................................................65
Table 27. AC Timing Parameters for Parallel I/F (Mode 2).........................................................................65
Table 28. AC Timing Parameters for Parallel I/F (Modes 3 and 4).............................................................66
Table 29. HSDI0 DVD Audio Signals..........................................................................................................66
Table 30. HSDI1 DVD-Audio Signals..........................................................................................................66
Table 31. AC Timing Parameters................................................................................................................68
Table 32. AC Timing Parameters................................................................................................................69
Table 33. AC Timing Parameters................................................................................................................70
Table 34. UART CFR Address Offsets .......................................................................................................70
Table 35. UART Registers ..........................................................................................................................71
Table 36. PHY Access Register..................................................................................................................72
Table 37. Base Register Configuration.......................................................................................................73
Table 38. Base Register Field Descriptions................................................................................................73
Table 39. Page 0 (Port Status) Register Configuration ..............................................................................76
Table 40. Page 0 (Port Status) Register Field Descriptions .......................................................................76
Table 41. Page 1 (Vendor ID) Register Configuration................................................................................77
Table 42. Page 1 (Vendor ID) Register Field Descriptions.........................................................................77
Table 43. Power State Summary................................................................................................................79
Table 44. I/O Pin and CFR Descriptions for Controlling Power Management States.................................82
Table 45. FIFO Monitoring Bits...................................................................................................................85
Table 46. Summary of GPIO Use ...............................................................................................................86
Table 47. CFR Address Ranges.................................................................................................................88
Table 48. Pin State During Power On Reset, Just After Power On Reset and DISABLE_IFn=L...............94
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
6
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
References
The following sources of information were used in the generation of this document:
IEEE Standard for a High Performance Serial Bus, IEEE Standard 1394-1995
IEEE 1394a-2000 Serial Bus Supplement
Digital Interface for consumer audio/video equipment, IEC Document 61883
Home Digital Network Interface Specification, Revision 1.1
5C Digital Transmission Content Protection Specification
Acronyms
The acronyms used in this document are defined below.
5C
Five Company (Intel, Sony, Matsushita, Hitachi, Toshiba)
CFR
DSS
DV
Configuration Register
Direct Satellite System
Digital Video
DVB
Digital Video Broadcasting
DVD
HSDI
IEC
Digital Versatile Disc
High Speed Data Interface
International Electrotechnical Commission
Institute of Electronics and Electrical Engineers
Internet Protocol
IEEE
IP
MPEG
Motion Pictures Experts Group
Device Ordering Information
Ordering Number
TSB43CA43APGF
TSB43CB43APGF
TSB43CA43AGGW
TSB43CB43AIGGW
TSB43CA43AZGW
TSB43CA42PGF
Name
Package
iceM 5C
PQFP 176
iceM non-5C
PQFP 176
µ *BGA 176
µ *BGA 176
µ *BGA 176
PQFP 176
µ *BGA 176
µ *BGA 176
iceM 5C
iceM non-5C, I temperature
iceM 5C
iceM 5C (2 Port)
iceM 5C (2 Port)
iceM 5C (2 Port)
TSB43CA42GGW
TSB43CA42ZGW
The ZGW package is similar to the GGW package with the added benefits of lead-free balls and the use
of environmentally-friendly (green) mold compound.
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
7
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
1
Hardware IC Characteristics
iceLynx-Micro Overview
The iceLynx-Micro (consumer electronics link with integrated microcontroller and physical layer (PHY)) is
a high performance 1394 link-layer device designed as a total solution for digitally interfacing advanced
audio/video consumer electronics applications. The device is offered in both
a
DTCP
encryption/decryption version (TSB43CA43A and TSB43CA42) and a non-DTCP encryption/decryption
version (TSB43CB43).
In addition to supporting transmit and receive of MPEG2 and DSS formatted transport streams with
encryption and decryption, the iceLynx-Micro supports the IEC 61883-6 and audio music protocol
standards for audio format and packetizing and asynchronous and asynchronous stream (as defined by
1394).
The device also features an embedded ARM7TDMI microprocessor core with access to 256K bytes of
internal program memory. The ARM7 is embedded to process 1394 specific transactions, thus
significantly reducing the processing power required by the host CPU and the development time required
by the user. The ARM7 is accessed from the 16/1-bit host CPU interface, from a UART communication
port, or from a JTAG debug port.
The iceLynx-Micro integrated 3-port PHY allows the user enhanced flexibility as two additional devices
can be utilized in a system application. The PHY’s speeds are capable of running at 100 Mbps,
200 Mbps, or 400 Mbps. The PHY follows all requirements as stated in the IEEE 1394-1995 and IEEE
1394a-2000 standards.
The TSB43CA43A and TSB43CA42 version of iceLynx-Micro incorporates two M6 baseline ciphers (one
per HSDI port) per the 5C specification to support transmit and receive of MPEG2 formatted transport
streams with encryption and decryption. The TSB43CB43 version of iceLynx-Micro is identical to the
TSB43CA43A without implementation of the encryption/decryption features. The TSB43CB43 device
allows customers that do not require the encryption/decryption features to incorporate iceLynx-Micro
without becoming DTLA licensees. Both devices support the IEC 61883-6 and audio music protocol
standards for audio format and packetizing.
1.1 Feature List
1.1.1 1394 Features
Integrated 400 Mbps 3-port PHY
Compliant with IEEE 1394-1995 and IEEE 1394a-2000 standards
Supports bus manager functions and automatic 1394 self-ID verification.
Separate Async Ack FIFO decreases the ack-tracking burden on in-CPU and ex-CPU
1.1.2 DTLA Encryption Support for MPEG2-DVB, DSS, DV, and Audio (TSB43CA43A and
TSB43CA42 Only)
Two M6 baseline ciphers (one per HSDI port)
Content key generation from exchange key
•
AKE acceleration features in hardware
•
•
Random Number Generator
Secure Hash Algorithm, Revision 1 (SHA-1)
Other AKE acceleration features
•
•
•
Elliptical curve digital signature algorithm (EC-DCA) both signature and verification
Elliptical curve Diffie-Hellman (EC-DH), first phase value and shared secret calculation
160-bit math functions
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
8
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
1.1.3 High Speed Data Interface (HSDI)
Two configurable high speed data interfaces support the following audio and video modes:
MPEG2-DVB interface
MPEG2-DSS interface
DV codec interface
IEC60958 interface
Audio DAC interface
SACD interface
1.1.4 External CPU Interface
16-bit parallel asynchronous I/O-type
16-bit parallel synchronous I/O-type
16-bit parallel synchronous memory type
1.1.5 Internal ARM7
50-MHz operating frequency
32-bit and thumb (16-bit) mode support
UART included for communication
256K bytes of program memory included on chip
ARM JTAG included for software debug
1.1.6 Data Buffers
Large 16.5K byte total FIFO
Programmable data/space available indicators for buffer flow control
1.1.7 Hardware Packet Formatting for the Following Standards
DVB MPEG2 transport stream (IEC61883-4)
DSS MPEG2 transport stream per standard
DV Stream (IEC 61883-2) SD-DV
Audio over 1394 (IEC 61883-6)
Audio Music Protocol (version 1.0 and enhancements)
Asynchronous and asynchronous stream (as defined by IEEE 1394)
1.1.8 Additional Features
PID filtering for transmit function (up to 16 separate PIDs per HSDI)
Packet insertion – two insertion buffers per HSDI
11 general-purpose inputs/outputs (GPIOs)
Interrupt driven to minimize CPU polling.
Single 3.3-V supply
JTAG interface to support post-assembly scan of device I/O – boundary scan
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
9
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
1.2 Application Diagram
Cable
Broadcast
OR
Digital TV
Digital Set Top Box /
HDTV Receiver /
Satellite Receiver
Decrypt
Encrypt
MPEG2
TSB43Cx43
MPEG2
Demux
TSB43Cx43
Decoder
E
n
c
r
e
n
c
r
Copy Protected 1394 =
d
e
c
r
e
d
e
c
r
n
c
r
y
p
t
y
p
t
y
p
t
TSB43Cx43
TSB43Cx43
TSB43Cx43
y
p
t
y
p
t
AV Receiver
DVD
D-VHS/PVR
Figure 1. TSB43Cx43 Typical Application
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
10
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
1.3 Block Diagram
1.3.1 TSB43Cx43A Block Diagram
8
MPEG2 DVB
ISO
OR
8
HSDI 0
HSDI 0
CFRs
MPEG2 DSS
FIFO
4KB
OR
8
M6
ISO
DIGITAL VIDEO (DV)
CIPHER
PORT
OR
PCM-AUDIO
OR
1394a-2000
1394a-2000
1394
BUS
S400
H / W
AKE
IEC60958 (S/PDIF)
LINK LAYER
CORE
3-PORT
PHY CORE
8
8
8
MPEG2 DVB
M6
OR
ISO
HSDI 1
FIFO
CIPHER
MPEG2 DSS
HSDI 1
PACKETIZER
OR
DIGITAL VIDEO (DV)
OR
ISO
4KB
PORT
SUPER AUDIO CD
OR
BCAST
AUDIO
RX
ASYNC
TX 0 FIFO RX 0 FIFO TX 1 FIFO RX 1 FIFO
2KB 2KB 2KB 2KB
ASYNC
ASYNC
ASYNC
IEC60958 (S/PDIF)
OR
RX
FIFO
512 B
SYT PLL
PCM-AUDIO
CONFIGURATION REGISTERS (CFRs)
L
E
B
256KB RAM
UART
TIMER 0
TIMER 1
MONITOR
16
PROGRAM
MEMORY
DATA
EXT.
MCU
I/F
AND
10
20
ADDRESS
CONTROL
COMM
MEMORY
1KB
1KB
WDOG /
TIMER 2
SHARED RAM
11
ARM7TDMI
RISC
GP I/O
CFRs
JTAG
PORT
ARM
CORE
DEBUGGER
† LEB is an acronym for local encryption block (Note: only included in the TSB43CA43)
Figure 2. TSB43Cx43 System Block Diagram
Note: The M6 Cipher is only included in the TSB43CA43.
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
11
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
1.3.2 TSB43CA42 Block Diagram
8
MPEG2 DVB
ISO
OR
8
HSDI 0
HSDI 0
CFRs
MPEG2 DSS
FIFO
4KB
OR
8
M6
ISO
DIGITAL VIDEO (DV)
CIPHER
PORT
OR
PCM-AUDIO
OR
1394a-2000
S400
1394
BUS
1394a-2000
LINK LAYER
CORE
H / W
AKE
IEC60958 (S/PDIF)
2-PORT
PHY CORE
8
8
8
MPEG2 DVB
M6
OR
ISO
HSDI 1
FIFO
CIPHER
MPEG2 DSS
HSDI 1
PACKETIZER
OR
DIGITAL VIDEO (DV)
OR
ISO
4KB
PORT
SUPER AUDIO CD
OR
BCAST
AUDIO
RX
ASYNC
TX 0 FIFO RX 0 FIFO TX 1 FIFO RX 1 FIFO
2KB 2KB 2KB 2KB
ASYNC
ASYNC
ASYNC
IEC60958 (S/PDIF)
OR
RX
FIFO
512 B
SYT PLL
PCM-AUDIO
CONFIGURATION REGISTERS (CFRs)
L
E
B
256KB RAM
UART
TIMER 0
TIMER 1
MONITOR
16
PROGRAM
MEMORY
DATA
EXT.
MCU
I/F
AND
10
20
ADDRESS
CONTROL
COMM
MEMORY
1KB
1KB
WDOG /
TIMER 2
SHARED RAM
11
ARM7TDMI
RISC
GP I/O
CFRs
JTAG
PORT
ARM
CORE
DEBUGGER
† LEB is an acronym for local encryption block (Note: only included in the TSB43CA42)
Figure 3. TSB43CA42 System Block Diagram
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
12
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
1.4 Pin Out
1.4.1 TSB43CA43A/TSB43CB43A Plastic Quad Flat Pack (PQFP)
3.3v
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
Vss
2
MCIF_ENDIAN
TEST_MODE0
3
Vss
Vdd
TEST_MODE1
4
Vdd
5
MCIF_ADDR10
MCIF_ADDR9
MCIF_ADDR8
MCIF_ADDR7
MCIF_ADDR6
MCIF_ADDR5
MCIF_ADDR4
MCIF_ADDR3
MCIF_ADDR2
MCIF_ADDR1
MCIF_DATA15
MCIF_DATA14
Vss
VCO_CLK
6
REF_SYT
7
DIV_VCO
8
PLL_TEST
9
MLPCM_BCLK
10
MLPCM_LRCLK
11
MLPCM_D0
12
MLPCM_D1
13
MLPCM_D2
14
MLPCM_A
15
GPIO2
16
GPIO3
17
TSB43CA43
GPIO4
18
Vdd
GPIO5
19
REG_OUT1
MCIF_DATA13
MCIF_DATA12
MCIF_DATA11
MCIF_DATA10
MCIF_DATA9
MCIF_DATA8
MCIF_DATA7
MCIF_DATA6
MCIF_DATA5
MCIF_DATA4
MCIF_DATA3
MCIF_DATA2
Vss
MSPCTL
20
Vdd
(iceLynx-Micro)
21
Vss
22
CPS
23
AVdd
24
AGND
25
TPB0_N
26
TPB0_P
27
AGND
INTEGRATED
28
AVdd
29
TPA0_N
30
TPA0_P
31
LLC / PHY
TPBIAS0
32
AVdd
33
Vdd
TPB1_N
34
MCIF_DATA1
MCIF_DATA0
MCIF_BUSCLKz
MCIF_WEz
TPB1_P
Plastic QFP
35
98
AGND
36
97
TPA1_N
37
96
TPA1_P
38
MCIF_OEz
95
TPBIAS1
39
MCIF_ACKz
MCIF_WAITz
MCIF_STRBz
MCIF_R_nWz
MCIF_CS_MEMz
MCIF_CS_IOz
MCIF_INTz
94
TPB2_N
40
93
TPB2_P
41
92
AVdd
42
91
TPA2_N
43
90
TPA2_P
44
89
TPBIAS2
Figure 4. TSB43CA43A Plastic QFP Pin Out
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
13
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
1.4.2 TSB43CA43A/TSB43CB43A Micro-Star Ball Grid Array (µ*BGA)
3.3v
A2
R1
Vss
A3
TPA2_N
P17
P16
P15
P11
P10
P9
HSDI1_60958_OUT
A4
MCIF_WAITz
MCIF_STRBz
MCIF_R_nWz
Vss
HSDI1_AUDIO_ERR
A5
HSDI1_D7
A6
HSDI1_D4
A7
Vdd
A8
GPIO8
HSDI1_DVALIDz
A9
GPIO1
P8
HSDI1_CLKz
A10
HPS
P7
HSDI0_D4
A11
TEST_MODE2
AVdd
P3
HSDI0_D3
A12
P2
HSDI0_D1
A13
TPB2_P
P1
HSDI0_SYNCz
A14
TPB2_N
N17
N16
N15
N3
HSDI0_CLKz
A15
MCIF_WEz
MCIF_OEz
MCIF_ACKz
TPBIAS1
MCIF_MODE2
A16
MCIF_MODE0
B1
Vss
B3
N2
TSB43CA43
Vdd
B4
TPA1_P
N1
HSDI1_AUDIO_MUTE
B5
TPA1_N
M17
M16
M15
M3
M2
M1
L17
L16
L15
L14
L4
HSDI1_AMCLK_IN
B6
MCIF_DATA1
MCIF_DATA0
MCIF_BUSCLKz
AGND
HSDI1_D5
(iceLynx-Micro)
B7
Vss
B8
HSDI1_D0
B9
HSDI1_SYNCz
B10
TPB1_P
HSDI0_D7
B11
TPB1_N
HSDI0_D2
B12
MCIF_DATA3
MCIF_DATA2
Vss
HSDI0_D0
B13
HSDI0_AVz
INTEGRATED
B14
HSDI0_AMCLK_IN
B15
Vdd
MCIF_MODE1
B17
AVdd
L3
MCIF_ENDIAN
TPBIAS0
C1
L2
LLC / PHY
TEST_MODE1
C2
TPA0_P
L1
TEST_MODE0
C4
TPA0_N
K17
K16
K15
K14
K4
HSDI1_60958_IN
C5
MCIF_DATA4
MCIF_DATA7
MCIF_DATA6
MCIF_DATA5
AGND
HSDI1_AMCLK_OUT
µ*BGA
C6
HSDI1_D6
C7
HSDI1_D2
C8
REG_OUT2
C9
K3
HSDI1_AVz
C10
AVdd
K2
HSDI0_D6
TPB0_P
C11
K1
Vss
TPB0_N
C12
J17
J16
J15
J14
HSDI0_DVALIDz
C13
MCIF_DATA8
MCIF_DATA11
MCIF_DATA10
MCIF_DATA9
HSDI0_ENz
C14
HSDI0_60958_IN
C16
Vss
Figure 5. TSB43CA43A µ*BGA Pin Out
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
14
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
1.4.3 TSB43CA42 Plastic Quad Flat Pack (PQFP)
3.3v
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
Vss
2
MCIF_ENDIAN
TEST_MODE0
3
Vss
Vdd
TEST_MODE1
4
Vdd
5
MCIF_ADDR10
MCIF_ADDR9
MCIF_ADDR8
MCIF_ADDR7
MCIF_ADDR6
MCIF_ADDR5
MCIF_ADDR4
MCIF_ADDR3
MCIF_ADDR2
MCIF_ADDR1
MCIF_DATA15
MCIF_DATA14
Vss
VCO_CLK
6
REF_SYT
7
DIV_VCO
8
PLL_TEST
9
MLPCM_BCLK
10
MLPCM_LRCLK
11
MLPCM_D0
12
MLPCM_D1
13
MLPCM_D2
14
MLPCM_A
15
GPIO2
16
GPIO3
17
TSB43CA42
GPIO4
GPIO5
MSPCTL
Vdd
Vdd
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
REG_OUT1
MCIF_DATA13
MCIF_DATA12
MCIF_DATA11
MCIF_DATA10
MCIF_DATA9
MCIF_DATA8
MCIF_DATA7
MCIF_DATA6
MCIF_DATA5
MCIF_DATA4
MCIF_DATA3
MCIF_DATA2
Vss
(iceLynx-Micro)
Vss
CPS
AVdd
AGND
TPB0_N
TPB0_P
AGND
AVdd
INTEGRATED
LLC / PHY
TPA0_N
TPA0_P
TPBIAS0
AVdd
Vdd
TPB1_N
TPB1_P
AGND
TPA1_N
TPA1_P
TPBIAS1
N/C
MCIF_DATA1
MCIF_DATA0
MCIF_BUSCLKz
MCIF_WEz
Plastic QFP
98
97
96
MCIF_OEz
95
MCIF_ACKz
MCIF_WAITz
MCIF_STRBz
MCIF_R_nWz
MCIF_CS_MEMz
MCIF_CS_IOz
MCIF_INTz
94
93
N/C
92
AVdd
91
N/C
90
N/C
89
N/C
Figure 6. TSB43CA42 Plastic QFP Pin Out
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
15
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
1.4.4 TSB43CA42 Micro-Star Ball Grid Array (µ*BGA)
3.3v
A2
R1
Vss
A3
N/C
MCIF_WAITz
MCIF_STRBz
MCIF_R_nWz
Vss
P17
P16
P15
P11
P10
P9
HSDI1_60958_OUT
A4
HSDI1_AUDIO_ERR
A5
HSDI1_D7
A6
HSDI1_D4
A7
Vdd
A8
GPIO8
HSDI1_DVALIDz
A9
GPIO1
P8
HSDI1_CLKz
A10
HPS
P7
HSDI0_D4
A11
TEST_MODE2
AVdd
P3
HSDI0_D3
A12
P2
HSDI0_D1
A13
N/C
P1
HSDI0_SYNCz
A14
N/C
N17
N16
N15
N3
HSDI0_CLKz
A15
MCIF_WEz
MCIF_OEz
MCIF_ACKz
TPBIAS1
MCIF_MODE2
A16
MCIF_MODE0
B1
Vss
B3
N2
TSB43CA42
Vdd
B4
TPA1_P
N1
HSDI1_AUDIO_MUTE
B5
TPA1_N
M17
M16
M15
M3
M2
M1
L17
L16
L15
L14
L4
HSDI1_AMCLK_IN
B6
MCIF_DATA1
MCIF_DATA0
MCIF_BUSCLKz
AGND
HSDI1_D5
(iceLynx-Micro)
B7
Vss
B8
HSDI1_D0
B9
HSDI1_SYNCz
B10
TPB1_P
HSDI0_D7
B11
TPB1_N
HSDI0_D2
B12
MCIF_DATA3
MCIF_DATA2
Vss
HSDI0_D0
B13
HSDI0_AVz
INTEGRATED
B14
HSDI0_AMCLK_IN
B15
Vdd
MCIF_MODE1
B17
AVdd
L3
MCIF_ENDIAN
TPBIAS0
C1
L2
LLC / PHY
TEST_MODE1
C2
TPA0_P
L1
TEST_MODE0
C4
TPA0_N
K17
K16
K15
K14
K4
HSDI1_60958_IN
C5
MCIF_DATA4
MCIF_DATA7
MCIF_DATA6
MCIF_DATA5
AGND
HSDI1_AMCLK_OUT
µ*BGA
C6
HSDI1_D6
C7
HSDI1_D2
C8
REG_OUT2
C9
K3
HSDI1_AVz
C10
AVdd
K2
HSDI0_D6
TPB0_P
C11
K1
Vss
TPB0_N
C12
J17
J16
J15
J14
HSDI0_DVALIDz
C13
MCIF_DATA8
MCIF_DATA11
MCIF_DATA10
MCIF_DATA9
HSDI0_ENz
C14
HSDI0_60958_IN
C16
Vss
Figure 7. TSB43CA42 µ*BGA Pin Out
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Copyright 2004, Texas Instruments Incorporated
Texas Instruments standard warranty. Production processing
TEXAS
does not necessarily include testing of all parameters.
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
16
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
1.5 Pin Description
Terminal
Number
Terminal Name
I/O
Description
BGA
QFP
Miscellanous Pins
Interface disable. When asserted, the interfaces are put into a high-Z
state. Interfaces include: ex-CPU, HSDI, GPIO, and WTCH_DG_TMRn.
Host power status. This indicates the power status of the external system
to iceLynx-Micro. A rising edge indicates the system CPU has been turned
ON. (The internal ARM must wake up.) A falling edge indicates the system
CPU has been turned OFF. (The internal ARM decides if power down is
necessary.)
DISABLE_IFn
T8
64
62
I
I
HPS
P8
Output to system to indicate iceLynx-Micro is ready to go into a low power
LOW_PWR_RDY
WTCH_DG_TMRn
R8
63
88
O
O
state. The ARM and WTCH_DG_TMRn control this pin.
Watch dog timer (for the ARM). iceLynx-Micro hardware asserts this pin
whenever ARM software has not updated the Timer2 register within the
allowed time period.
U16
RESET_ARMn
RESETn
U7
T7
60
59
I
I
ARM reset. This signal resets the internal ARM processor.
Device reset. This signal resets all logic. This includes the PHY, link core,
memory, the ARM, and random logic.
Power and Ground Pins
A2,
1, 21,
55,
B1,
B7,
76,
C11,
C16,
G17,
J1,
102,
117,
131,
146,
162,
176
VSS
Digital ground
L15,
P11,
T6
24,
27,
35,
45,
J2, K4,
M3,
AGND
Analog ground
PLL ground
U2
PLL_GND
R6
54
A7,
4, 20,
56,
B3,
C17,
D3,
75,
101,
116,
130,
145,
161,
175
D11,
H2,
VDD
Digital power supply. Must be set to 3.3-V nominal.
H15,
L14,
R11,
U6
23,
J3, K3, 28,
AVDD
L4,
32,
Analog power supply. Must be set to 3.3-V nominal.
PLL power supply. Must be set to 3.3-V nominal.
P3, R4 41,
48
PLL_VDD
R5
51
Regulator Pins
Internal regulator enable. The iceLynx-Micro core voltage is 1.8 V. Internal
regulators are used to regulate the 3.3-V VDD inputs to 1.8 V. This pin
enables the regulators.
REG_ENn
U11
73
I
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
17
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
Terminal
Number
Terminal Name
I/O
Description
BGA
QFP
1.8-V regulator output. This pin must be connected to ground using a
REG_OUT0
REG_OUT1
REG_OUT2
T11
74
O
O
O
0.1-µF capacitor.
1.8-V regulator output. This pin must be connected to ground using a
0.1-µF capacitor.
1.8-V regulator output. This pin must be connected to ground using a
0.1-µF capacitor.
H14
C8
115
160
External CPU Interface Pins
MCIF acknowledge pin. Default active low. iceLynx-Micro asserts this
signal if it has completed the MCIF request. This signal is driven when
chip select (CS) is asserted. This signal is used for the following modes:
MCIF_ACKz
N15
95
I/O
68000 + wait I/O access
I/O Type-3 MPC850
MCIF address 1 pin. This data pin is the least significant bit of the MCIF
address bus.
MCIF_ADDR1
G14
120
I
MCIF_ADDR0 is internally grounded. Only 16-bit addressing is allowed.
MCIF_ADDR1 must be connected to the Address1 signal of the system
CPU.
MCIF_ADDR2
MCIF_ADDR3
MCIF_ADDR4
MCIF_ADDR5
MCIF_ADDR6
MCIF_ADDR7
MCIF_ADDR8
MCIF_ADDR9
F17
F16
F15
E17
E16
E15
D17
D16
121
122
123
124
125
126
127
128
I
I
I
I
I
I
I
I
MCIF address 2 pin
MCIF address 3 pin
MCIF address 4 pin
MCIF address 5 pin
MCIF address 6 pin
MCIF address 7 pin
MCIF address 8 pin
MCIF address 9 pin
MCIF address 10 pin. This data pin is the most significant bit of the MCIF
MCIF_ADDR10
D15
129
I
address bus.
MCIF bus clock. This pin is only used for the MCIF synchronous mode. I/O
Type-3 MPC850 and the memory access.
MCIF_BUSCLKz
M15
98
I
This signal must be pulled high if not used.
MCIF chip select for all I/O MCIF modes.
MCIF chip select for the memory MCIF mode.
MCIF_CS_IOz
MCIF_CS_MEMz
R16
R17
90
91
I
I
MCIF data 0 pin. This data pin is the least significant bit of the MCIF
MCIF_DATA0
M16
99
I/O
data bus.
MCIF_DATA1
MCIF_DATA2
MCIF_DATA3
MCIF_DATA4
MCIF_DATA5
MCIF_DATA6
MCIF_DATA7
MCIF_DATA8
MCIF_DATA9
MCIF_DATA10
MCIF_DATA11
MCIF_DATA12
MCIF_DATA13
MCIF_DATA14
M17
L16
L17
K17
K14
K15
K16
J17
J14
J15
J16
H17
H16
G16
100
103
104
105
106
107
108
109
110
111
112
113
114
118
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
MCIF data 1 pin
MCIF data 2 pin
MCIF data 3 pin
MCIF data 4 pin
MCIF data 5 pin
MCIF data 6 pin
MCIF data 7 pin
MCIF data 8 pin
MCIF data 9 pin
MCIF data 10 pin
MCIF data 11 pin
MCIF data 12 pin
MCIF data 13 pin
MCIF data 14 pin
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
18
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
Terminal
Number
Terminal Name
I/O
Description
BGA
QFP
MCIF data 15 pin. This data pin is the most significant bit of the MCIF
data bus.
MCIF endian pin. This sets the endianness for accesses between the
external CPU and the internal iceLynx-Micro memory. This pin sets
endianness for all MCIF modes. When set to 0, data is read/written to the
ex-CPU exactly as it is stored in iceLynx-Micro memory. (Big endian)
MCIF_DATA15
MCIF_ENDIAN
MCIF_INTz
G15
119
132
89
I/O
B17
I
When set to 1, data is swapped on half-word and byte boundaries before it
is read/written to the ex-CPU. (Little endian)
MCIF Interrupt. This signal is push-pull (always asserted). It does not
require a pullup resistor.
T17
O
MCIF_MODE0
MCIF_MODE1
MCIF_MODE2
A16
B15
A15
133
134
135
I
I
I
MCIF mode 0. Used to select MCIF mode.
MCIF mode 1. Used to select MCIF mode.
MCIF mode 2. Used to select MCIF mode.
MCIF output enable. Default active low. This input pin indicates if the
system CPU wants to perform a MCIF read access. This signal is used for
the following modes:
SH-3 I/O access
M16C/62 I/O access
Memory access
MCIF_OEz
N16
96
I
This signal must be pulled high if not used.
MCIF read/write pin. Default value for a read is 1. Default value for a write
MCIF_R_nWz
MCIF_STRBz
P15
P16
92
93
I
I
is 0.
MCIF strobe pin. Default active low. This pin is used (along with
MCIF_CS_IOz) to validate the MCIF access. This signal is used for the
following modes:
68000 + wait I/O access
MPC850 I/O access
When not used, this pin must be pulled high.
MCIF wait pin. Default active high. iceLynx-Micro asserts this signal if it is
not ready to service an MCIF request. When not asserted, this signal is in
a high-Z state. This signal is used for the following modes:
MCIF_WAITz
MCIF_WEz
P17
N17
94
97
O
68000 + wait I/O access
SH-3 I/O access
M16C/62 I/O access
MCIF Write Enable. Default active low. This input pin indicates if the
system CPU wants to perform a MCIF write access. This signal is used for
the following modes:
•
•
•
SH-3 I/O access
M16C/62 I/O access
Memory access
I
This signal must be pulled high if not used.
Universal Asynchronous Receiver Transmitter Pins
UART receive port. Data from the system is input to the UART buffer
UART_RxD
UART_TxD
U15
R14
86
85
I
using this pin.
UART transmit port. Data from the UART buffer is output to the system
using this pin.
O
Joint Test Action Group (JTAG) and ARM Pins
JTAG clock pin. Both the boundary scan and ARM JTAG uses this input
for the JTAG clock.
JTAG test data input pin
JTAG_TCK
JTAG_TDI
U13
T12
80
78
I
I
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
19
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
Terminal
Number
Terminal Name
I/O
Description
BGA
R12
QFP
JTAG_TDO
JTAG_TMS
79
77
O
I
JTAG test data output pin
JTAG test mode selector pin
U12
JTAG reset pin. Both the boundary scan and ARM JTAG uses this input
for the JTAG clock.
Note 1: TSB43Cx43A/TSB43CA42 must have JTAG_TRSTn=0 for correct
JTAG_TRSTn
T13
81
I
ARM interrupt operation.
Note 2: JTAG_TRST must be asserted once after power-up for correct
operation of the iceLynx-Micro.
ARM_TDI
ARM_TDO
ARM_TMS
U14
T14
R13
83
84
82
I
O
I
ARM JTAG test data input pin
ARM JTAG test data output pin
ARM JTAG test mode selector pin
General-Purpose Input/Out Pins (GPIO)
GPIO0. Can be programmed as general-purpose input, general-purpose
output, or specific function. Power-up default is input.
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
U9
65
66
15
16
17
18
69
70
71
72
87
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO1. Can be programmed as general-purpose input, general-purpose
P9
output, or specific function. Power-up default is input.
GPIO2. Can be programmed as general-purpose input, general-purpose
output, or specific function. Power-up default is input.
G2
GPIO3. Can be programmed as general-purpose input, general-purpose
G1
output, or specific function. Power-up default is input.
GPIO 4. Can be programmed as general-purpose input, general-purpose
output, or specific function. Power-up default is input.
H1
GPIO 5. Can be programmed as general-purpose input, general-purpose
H4
output, or specific function. Power-up default is input.
GPIO6. Can be programmed as general-purpose input, general-purpose
output, or specific function. Power-up default is input.
U10
T10
P10
R10
T15
GPIO7. Can be programmed as general-purpose input, general-purpose
output, or specific function. Power-up default is input.
GPIO8. Can be programmed as general-purpose input, general-purpose
output, or specific function. Power-up default is input.
GPIO9. Can be programmed as general-purpose input, general-purpose
output, or specific function. Power-up default is input.
GPIO10. Can be programmed as general-purpose input, general-purpose
output, or specific function. Power-up default is input.
GPIO10
Physical Layer Pins
TPA0_N
TPA1_N
TPA2_N
TPA0_P
TPA1_P
TPA2_P
29,
36,
42,
30,
37,
43
L1,
N1,
Twisted pair A differential signal terminals. For an unused port, TPAN and
TPAP signals are left open (i.e., TSB43CA42 for Port 2).
R1,
I/O
L2,
N2, R2
TPB0_N
TPB1_N
TPB2_N
TPB0_P
TPB1_P
TPB2_P
K1,
M1,
P1,
K2,
M2,
P2
25,
33,
39,
26,
34,
40
Twisted pair B differential signal terminals. For an unused port, TPBN and
TPBP signals are left open (i.e., TSB43CA42 for Port 2).
I/O
I/O
Twisted pair bias output. These signals provide the 1.86-V nominal bias
voltage needed for proper operation of the twisted pair driver and
receivers for signaling an active connection to a remote node.
TPBIAS0
TPBIAS1
TPBIAS2
31,
38,
44
L3,
N3, T1
For an unused port, TPBIAS is left unconnected (i.e., TSB43CA42 for
Port 2).
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
20
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
Terminal
Number
Terminal Name
I/O
Description
BGA
QFP
Current setting resistors. These pins are connected to external resistors to
set the internal operating currents and cable driver output currents. A
resistance of 6.34 kΩ ± 1% is required to meet the IEEE 1394-1995 output
voltage limits.
R1
46,
47
T3, U3
-
R0
PLL filter terminals. These terminals are connected to an external
capacitor to form a lag-lead filter required for stable operation of the
internal frequency-multiplier PLL, which is using the crystal oscillator. A
0.1-µF ±10% capacitor is the only external component required to
complete this filter.
FILTER0
FILTER1
49,
50
T4, U4
I/O
Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel
resonant fundamental mode crystal. The optimum values for the external
shunt capacitors are dependent on the crystal used.
Cable power status. This input to iceLynx-Micro detects if cable power is
present. This pin must be connected to the cable power through 390-kΩ
resistor.
XI
52,
53
T5, U5
J4
-
I
X0
CPS
22
Maximum speed of PHY. When this signal is high; S100 and S200
MSPCTL
LINKON
H3
U8
19
61
I
operation. When this signal is low; S100, S200, and S400 operation.
Link-on output. This signal is asserted whenever LPS is low and a link-on
packet is received from the 1394 bus.
O
High Speed Data Interface (HSDI) Port 0 Pins
HSDI0_60958_IN
C14
136
I
I
60958 data input
Audio master clock input. This clock is used to decode the bi-phase
encoding of 60958 data.
HSDI0_AMCLK_IN
B14
137
This pin is also used to input the 1.5 x BCLK for flow control mode.
HSDI port 0 available. Programmable. Default active low.
For receive from 1394, this signal indicates if a 1394 packet is available in
the receive buffer for reading. The HSDI_AV signal for MPEG2 data also
depends on time stamp based release.
HSDI0_AVz
B13
140
O
For transmit to 1394, this signal indicates buffer level in HSDI TX modes 8
and 9 by programming a CFR. If the buffer level is above a programmed
level, HSDI_AV will be asserted.
HSDI port 0 clock. Programmable. Default rising edge sample. This clock
is used to operate the HSDI port 0 logic. In parallel mode the maximum
clock is 27 MHz. in serial mode, the maximum clock is 70 MHz.
This signal is output to HSDI1_CLKz in pass-through mode.
This signal is used as HSDI0_MLPCM_BCLK for DVD-audio transmit.
HSDI0_CLKz
HSDI0_D0
A14
B12
138
143
I
HSDI port 0 data 0 pin. Data 0 is the least significant bit on the HSDI data
bus.
In serial mode, only HSDI0_D0 is used.
I/O
This signal is output to HSDI1_D0 in pass-through mode.
This signal is used as HSDI0_MLPCM_D0 for DVD-audio transmit.
HSDI port 0 Data 1 pin
HSDI0_D1
HSDI0_D2
HSDI0_D3
A12
B11
A11
144
147
148
I/O
I/O
I/O
This signal is output to HSDI1_D1 in pass-through mode.
This signal is used as HSDI0_MLPCM_D1 for DVD-audio transmit.
HSDI port 0 Data 2 pin
This signal is output to HSDI1_D2 in pass-through mode.
This signal is used as HSDI0_MLPCM_D2 for DVD-audio transmit.
HSDI port 0 Data 3 pin
This signal is output to HSDI1_D3 in pass-through mode.
This signal is used as HSDI0_MLPCM_A for DVD-audio transmit.
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
21
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
Terminal
Number
Terminal Name
I/O
Description
BGA
A10
D10
QFP
HSDI port 0 data 4 pin
HSDI0_D4
HSDI0_D5
HSDI0_D6
149
150
151
I/O
I/O
I/O
This signal is output to HSDI1_D4 in pass-through mode.
HSDI port 0 data 5 pin
This signal is output to HSDI1_D5 in pass-through mode.
HSDI port 0 data 6 pin
This signal is output to HSDI1_D6 in pass-through mode.
HSDI port 0 data 7 pin. Data 0 is the most significant bit on the HSDI data
C10
B10
bus.
HSDI0_D7
152
I/O
This signal is output to HSDI1_D7 in pass-through mode.
HSDI port 0 data valid pin. Programmable. Default active high. This pin
indicates if data on the HSDI data bus valid for reading or writing.
For transmit to 1394, this signal is provided by the system with the data.
For receive from 1394, iceLynx-Micro provides this signal with the data.
HSDI0_DVALIDz
C12
142
I/O
For HSDI DV modes, this signal is used as HSDI0_FrameSync indicating
DV frame boundary.
This signal is output to HSDI1_DVALIDz in pass-through mode
If not used in transmit mode, this signal is pulled low.
HSDI port 0 enable. Programmable. Default active low. Input by the
system to enable the HSDI for both transmit to and receive from 1394.
If not used, this signal is pulled enabled (low or high depending on the
polarity set). The application can use HSDI_DVALID or HSDI_SYNC to
validate the HSDI data.
HSDI0_ENz
C13
A13
139
141
I
This signal is used as HSDI0_MLPCM_LRCLK for DVD-audio transmit.
HSDI port 0 sync signal. Programmable. Default active high. This signal
indicates the start of packet.
For transmit to 1394, this signal is provided by the system with the data.
For receive from 1394, iceLynx-Micro provides this signal with the data.
This signal is output to HSDI1_SYNCz in pass-through mode.
HSDI0_SYNCz
I/O
If not used in transmit mode, this signal is pulled low or high depending on
the polarity.
High Speed Data Interface (HSDI) Port 1 Pins
Audio master clock input. This clock is used to decode the bi-phase
encoding of 60958 data.
HSDI1_AMCLK_IN
B5
169
I
This pin also inputs the 1.5 x BCK for flow control mode.
MLPCM interface, HSDI1 audio port, and HSDI1 video port share
IsoPathBuffer 1. Only one interface can access the buffer at a time.
Audio master clock output. This clock is derived from the VCO_CLK input.
60958 data output from iceLynx-Micro is bi-phase encoded using this
clock.
HSDI1_AMCLK_OUT
HSDI1_AUDIO_ERR
C5
A4
170
171
O
O
Audio error signal. iceLynx-Micro asserts this signal whenever an audio
error condition occurs. (Receive from 1394 only.)
Audio mute status. iceLynx-Micro asserts this signal whenever an audio
mute condition has occurred, and hardware has muted the HSDI1 audio
interface. (Receive from 1394 only.)
60958 data input
60958 data output
HSDI1_AUDIO_MUTE
HSDI1_60958_IN
B4
C4
172
173
O
I
HSDI1_60958_OUT
A3
174
O
This signal is also used as FLWCTRL_DVALID in flow control data valid
mode.
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
22
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
Terminal
Number
Terminal Name
I/O
Description
BGA
QFP
HSDI port 1 available. Programmable. Default active low.
For receive from 1394, this signal indicates if a 1394 packet is available in
the receive buffer for reading. The HSDI_AV signal for MPEG2 data also
depends on time stamp based release.
HSDI1_AVz
C9
155
O
For transmit to 1394, this signal indicates the buffer level in HSDI TX
modes 8 and 9 by programming a CFR.
This pin indicates buffer level in transmit mode by programming a CFR. If
the buffer level is above a programmed level, HSDI_AV is asserted.
HSDI port 1 clock. Programmable. Default rising edge sample. This clock
is used to operate the HSDI port 1 logic. In parallel mode, the maximum
clock is 27 MHz. In serial mode, the maximum clock is 70 MHz.
HSDI1_CLKz
HSDI1_D0
A9
153
158
I/O
I/O
This signal is used as HSDI1_SACD_BCLK for SACD transmit and
receive.
MLPCM interface, HSDI1 audio port, and HSDI1 video port share
IsoPathBuffer 1. Only one interface can access the buffer at a time.
HSDI port 1 data 0 pin. Data 0 is the least significant bit on the HSDI data
bus. In serial mode, only HSDI0_D0 is used.
B8
This signal is used as HSDI1_SACD_D0 for SACD transmit and receive.
HSDI port 1 data 1 pin
HSDI1_D1
HSDI1_D2
HSDI1_D3
HSDI1_D4
HSDI1_D5
D8
C7
D7
A6
B6
159
163
164
165
166
I/O
I/O
I/O
I/O
I/O
This signal is used as HSDI1_SACD_D1 for SACD transmit and receive.
HSDI port 1 data 2 pin
This signal is used as HSDI1_SACD_D2 for SACD transmit and receive.
HSDI port 1 data 3 pin
This signal is used as HSDI1_SACD_D3 for SACD transmit and receive.
HSDI port 1 data 4 pin
This signal is used as HSDI1_SACD_D4 for SACD transmit and receive.
HSDI port 1 data 5 pin
This signal is used as HSDI1_SACD_D5 for SACD transmit and receive.
HSDI port 1 data 6 pin
This signal is used as HSDI1_SACD_A for SACD transmit and receive.
HSDI1_D6
HSDI1_D7
C6
A5
167
168
I/O
I/O
HSDI port 1 data 7 pin. Data 0 is the most significant bit on the HSDI
data bus.
HSDI port 1 data valid pin. Programmable. Default active high. This pin
indicates if data on the HSDI data bus valid for reading or writing.
For transmit to 1394, this signal is provided by the system with the data.
For receive from 1394, iceLynx-Micro provides this signal with the data.
HSDI1_DVALIDz
HSDI1_ENz
A8
D9
157
154
I/O
For HSDI DV modes, this signal is used as HSDI0_FrameSync indicating
DV frame boundary.
If not used in transmit mode, this signal is pulled low.
HSDI port 1 enable. Programmable. Default active low. Input by the
system to enable the HSDI for both transmit to and receive from 1394.
I
If not used, this signal is pulled enabled (low or high depending on the
polarity set). The application can use HSDI_DVALID or HSDI_SYNC to
validate the HSDI data.
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
23
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
Terminal
Number
Terminal Name
I/O
Description
BGA
QFP
HSDI port 1 sync signal. Programmable. Default active high. This signal
indicates the start of a packet.
For transmit to 1394, this signal is provided by the system with the data.
For receive from 1394, iceLynx-Micro provides this signal with the data.
HSDI1_SYNCz
B9
156
I/O
If not used in transmit mode, this signal is pulled low or high depending on
the polarity.
This signal is used as HSDI1_SACD_FRAME for SACD transmit and
receive.
DVD-Audio Interface Pins
Audio MLPCM interface ancillary data. Ancillary data is input/output using
this pin. For DVD-Audio, MLPCM_LRCLK determines if ancillary left or
ancillary right data is present.
This signal also functions as FLWCTL_A in flow control mode.
Audio MLPCM interface bit clock. Multiple functions:
MLPCM_A
G3
14
9
I/O
I/O
DVD audio BCK (I)
DVD audio BCK (O)
Flow control BCK (I/O)
MLPCM_BCLK
E1
MLPCM interface, HSDI1 audio port, and HSDI1 video port share
IsoPathBuffer 1. Only one interface can access the buffer at a time.
Audio MLPCM interface D0. Contains channel 1 and channel 2
information. MLPCM_LRCLK determines which channel is present.
This signal also functions as FLWCTL_D0 in flow control mode.
MLPCM_D0
MLPCM_D1
MLPCM_D2
F2
F1
G4
11
12
13
I/O
I/O
I/O
Audio MLPCM interface D1. Contains channel 3 and channel 4
information. MLPCM_LRCLK determines which channel is present.
This signal also functions as FLWCTL_D0 in flow control mode.
Audio MLPCM interface D2. Contains channel 5 and channel 6
information. MLPCM_LRCLK determines which channel is present.
This signal also functions as FLWCTL_D0 in flow control mode
Audio MLPCM interface left-right clock. Multiple functions:
DVD audio LRCLK (I)
DVD audio LRCLK (O)
Flow control LRCLK (I/O)
MLPCM_LRCLK
F3
10
I/O
Audio Phase Lock Loops Pins
Output for external phase detector. This signal is the divided VCO_CLK. It
used by the external phase detector to compare with the REF_SYT signal.
The divide ratios are setup in CFR.
DIV_VCO
PLL_TEST
REF_SYT
E3
E2
D1
7
8
6
O
O
O
PLL test. This signal is used for internal Texas Instruments testing and
must be unconnected for normal operation.
Output for external phase detector. This signal represents the SYT match
for received audio or DV packets. The phase detector uses it as input to
detect differences between the SYT match and the VCO clock.
Input from VCO. This signal generates internal audio and DV clocks for
receive clock recovery.
Audio frequency: 33.868 MHz or 36.864 MHz.
DV frequency: 30.72 MHz, 27 MHz
VCO_CLK
D2
5
I
Test Mode Pins
Test mode. Used for internal Texas Instruments testing. Must be pulled
low for normal operation.
TEST_MODE0
C2
C1
2
3
I/O
I/O
Test mode. Used for internal Texas Instruments testing. Must be pulled
TEST_MODE1
low for normal operation.
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
24
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
Terminal
Number
Terminal Name
I/O
Description
BGA
QFP
Test mode. Used for internal Texas Instruments testing. Must be pulled
low for normal operation.
TEST_MODE2
TEST_MODE3
P7
57
58
I/O
I/O
Test mode. Used for internal Texas Instruments testing. Must be pulled
R7
R9
low for normal operation.
Factory test pin. Must tie to low for normal operation.
Recommend connection to ground through a 1-kΩ resistor.
Factory test pin. Must tie to low for normal operation.
Recommend connection to ground through a 1-kΩ resistor.
TEST4
TEST5
67
68
I/O
I/O
T9
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MARCH 12, 2004
25
TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
1.6 Memory Map
Figure 8 shows the memory map for iceLynx-Micro.
The program memory (256K bytes) includes the communication memory for transactions between the
internal and external CPU. The boundaries of the communication memory are programmable. (Refer
to the register address)
Two 1024-byte RAMs are included for ex-CPU memory access functions.
The configuration registers start at offset 0x 0010 0000.
Note: The program memory is divided into physical blocks. (For example, four blocks of 64K each.) Each
memory block is accessed by the ARM or ex-CPU independently. The ARM could access program
memory in block 1 at the same time as the ex-CPU accesses comm memory in block 4. Because of this,
software must program the comm memory pointers into the highest memory block (the last 64K of
block 4). Noncritical program code can also be loaded into this block.
0000 0000
Exception Vectors
0000 001C
Programmable Write
256 x 1024 Byte
Base Address (Comm
Program Memory
Memory)
Programmable Read
Base Address (Comm
0004 0000
Memory)
2 x 1024 byte RAM
Memory Access
0004 0800
Reserved
0010 0000
Configuration Registers
0010 0800
Reserved
FFFF FFFF
Figure 8. TSB43Cx43 Memory Map
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1.7 DTCP Encryption – Hardware Implementation (TSB43CA43A and TSB43CA42 Only)
The TSB43CA43A and TSB43CA42 version of iceLynx-Micro is fully compliant with the DTCP method of
digital content protection. iceLynx-Micro supports the baseline M6 cipher, content key creation, and key
updates in iceLynx-Micro hardware. iceLynx-Micro has the capability to encrypt or decrypt MPEG2-DVB,
DSS, DV, or audio. The authentication and key exchange (AKE) is also implemented in hardware.
Customers requiring the DTCP version of iceLynx-Micro must have signed an NDA with Texas
Instruments and be a current DTLA licensee. Information on the DTCP implementation within the
TSB43CA43A and TSB43CA42 devices are found in the following document provided by Texas
Instruments:
Note: Recipients must have signed Texas Instruments NDA and be a current DTLA licensee to receive
this document.
1.8 Program Memory
1.8.1 Overview/Description
The iceLynx-Micro provides 256K bytes of internal program RAM. The program memory is loaded by the
external CPU interface. The external CPU cannot read the program memory.
Anytime the RESET_ARMn pin is asserted (transitions from high to low), the cipher and AKE registers are
cleared.
1.8.2 External CPU (Parallel Mode)
Steps for loading program memory:
1) ARM is placed in reset (using RESET_ARMn pin) and ex-CPU initiates write to the program
memory CFR (Sys.IntMemLoad at 0x5C).If the ARM is only put into reset, there is no change in
the program memory.
2) The program must contain a 2-quadlet header. The 2-quadlet header specifies if the program is
LEB encrypted. See Section 1.9.5 for more information on LEB.
3) The program is loaded into program memory through the Sys.IntMemLoad CFR. The program is
placed in memory starting at address 0x 0000 0000. The ex-CPU indicates the end of program
load by deasserting the RESET_ARMn signal. When the RESET_ARMn signal is deasserted, the
iceLynx-Micro hardware pads the rest of program memory with zeros.
4) The ARM is executing code as soon as RESET_ARMn signal is deasserted and all 256K bytes of
program memory are loaded.
1.9 External CPU Interface
1.9.1 Overview/Description
The ex-CPU accesses iceLynx-Micro configuration registers and FIFOs using 32-bit addressing. The
quadlet-aligned address is provided for the first 16-bit access. The iceLynx-Micro internally increments the
address for the second 16-bit access. All 32 bits of a register or FIFO must be read using back-to-back
transactions. An access to address N must be followed by address N+2.
A 16-bit processor can be used with iceLynx-Micro. However, the processor must access the entire
quadlet address (all 32 bits) in order. For example, for a register address N, the ex-CPU must first access
register address N and then address N+2. It cannot access address N+2 first. If the ex-CPU accesses the
32-bit address incorrectly, the ExCPUInt.ExCPUErr interrupt occurs.
The Ex-CPU can access to iceLynx-Micro by I/O- or memory-type methods. The iceLynx-Micro supports
four memory types of processor interfaces: Type-1, Type-2, I/O Type-1 SH3, and I/O Type-2 M16C. The
ex-CPU I/Fs and access types are categorized as follows:
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1. Asynchronous I/O-type
Bus clock is not provided.
I/O Type-0 68K + wait
I/O Type-1 SH3 SRAM-like + wait
I/O Type-2 M16C SRAM-like + wait
2. Synchronous I/O-type
Bus clock is provided.
I/O Type-3 MPC850
3. Memory-type
Access to single port RAM. Timing matches for I/O type except bus clock are provided and a special
memory chip select signal is used.
Type-1 memory access
Type-2 memory access
SH3-type memory access
M16C/62 memory access
Users can select the ex-CPU by setting the external pin MCIF_MODE[2:0]. Table 1 shows the pin
assignments.
Table 1. External CPU MCIF Pin Assignment Modes
†
External MCU Interface Method
MCIF_MODE[2:0]
I/O Type
Memory Type
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
I/O Type-0: 68K+ wait
I/O Type-1: SH3 + wait
I/O Type-2: M16C + wait
I/O Type-3: MPC850
Memory access available
I/O types reserved
Memory access invalid
† External MCU access type (I/O or memory) is dependent on the chip select signal used, MCIF_CS_IOz
or MCIF_CS_MEMz, respectively.
With regard to the above four types of processors, Table 2 shows the relation between the signals of the
iceLynx-Micro and those of the ex-CPU.
‡Note: ARM must be in reset to load program memory.
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Table 2. Ex-CPU I/F Signals
External Interface Method
Signal Name
Port Type
Type-0 (68K)
Type-1 (SH3)
Type-2 (M16C) Type-3 (MPC850)
I/O Type
MCIF_CS_IOz
MCIF_RW
MCIF_STRBz
MCIF_ACKz
MCIF_WAITz
MCIF_OEz
I
I
I
CSn
R_nW
STRBz
NA
WAITz
----
CSn
----
----
CSn
----
----
CSn
R_nW
TSn
TAn
----
----
----
BUSCLKz
O (3S)
O (3S)
----
----
WAITz
RDn
WRn
----
WAITz
RDn
WRn
----
I
I
I
MCIF_WEz
----
----
MCIF_BUSCLKz
Memory Type
MCIF_CS_MEMz
MCIF_OEz
MCIF_WEz
MCIF_BUSCLKz
I
I
I
I
CSn
RDn
WRn
BUSCLKz
1.9.2 Endian Setting (Parallel and Memory Accesses)
The iceLynx-Micro registers in the CFR map are structured as (byte 0, byte 1, byte 2, and byte 3). The
iceLynx-Micro has an endian pin (MCIF_ENDIAN) that controls the byte order between the ex-CPU
interface and internal iceLynx-Micro memory (including CFRs, FIFOs, and RAM for memory access). The
status of the MCIF_ENDIAN pin is shown at ExCPUCfg.Endian CFR.
Note: In I/O mode, the MCIF_ENDIAN pin is asserted or deasserted for individual 32-bit accesses.
MCIF_A[1] = 0, Data = ABCD
MCIF_A[1] = 1, Data = EF01
If MCIF_ENDIAN is set to 0, the data written to the FIFO is ABCD EF01.
If MCIF_ENDIAN is set to 1, the data written to the FIFO is EF01 ABCD.
1.9.2.1 Parallel Mode and Memory Access
In I/O mode, the ex-CPU has access to program memory, comm memory, and CFRs through
registers. The ex-CPU only has write access to the program memory. It can only perform writes
while the ARM is in reset.
In memory mode, the ex-CPU directly accesses the two 1024-byte single port RAMs. The two
RAMs are used individually (1024 bytes each) and are randomly accessed by the ARM (32-bit)
and ex-CPU (16-bit). The MCIF_ADDR signals indicate where the ex-CPU is accessing. The
MCIF_ADDR range to address the single port RAMs is 0x000 through 0x7FF. The ex-CPU has
priority access to the RAM. The software must assure there are no collisions. (Use GPInts)
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1.9.3 Ex-CPU Access
Async Tx 0,1
ASYNC TX FIFO
2048 byte
CFR
CFR
Program Memory
256K bytes
Async Rx 0,1
ASYNC RX FIFO
2048 byte
Comm
Write
Base
Addr
Ex-CPU Write Area
Comm
Read
ARM
Base
Addr
Ex-CPU Read Area
1024 byte RAM
1024 byte RAM
CFR
I/O Type
Access
Ex-CPU
Memory Access
Figure 9. Ex-CPU Access
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The communication area is part of the 256K-byte memory. This area is used for data communication
between Ex-CPU and ARM. CFR CommWrBase and CommRdBase define the top address of the area.
The communication area consists of an ex-CPU write area and ex-CPU read area.
Write
Ex-CPU Write Area
Read
Host
ARM
Read
Ex-CPU Read Area
Write
Upon the chip reset, CommWrBase and CommRdBase are 0x 0000 FFFF. When set to this default value,
the ex-CPU is not allowed to access the communication memory.
The ARM manages the communication area between the ex-CPU and ARM. General interrupts share the
access time for the areas. The ARM has full random access of the communication memory area. The
parallel ex-CPU can access the communication memory through the CommData CFR.
The ARM can know how much data was read or written into the communication area by reading the
Sys.CommStat.RdCnt and Sys.CommStat.WrCnt bits in CFR. The ARM can also reset the internal
address counters using Sys.CommStat.RdCnt and Sys.CommStat.WrCnt bits in CFR.
Note: Only the ARM can set the Comm (read/write) base addresses.
1.9.3.1
Ex-CPU and ARM Communication Sequence in Parallel Ex-CPU I/F Mode
The Ex-CPU and ARM use GPInts (general-purpose interrupts) for communication. Any reference to
interrupt in the following sections refers to the GPInts. GPInts are available in the Sys.InCPUCommInt
and Sys.ExCPUCommInt CFRs.
1.9.3.1.1 Ex-CPU Read
ARM sends an interrupt to ex-CPU as READ ENABLE.
Ex-CPU sends an interrupt to ARM as READ REQUEST. ARM invokes a timer to watch access
timeout and can't access read communication area memory ex-CPU access end.
Ex-CPU reads data from communication area.
Ex-CPU sends an interrupt to ARM as READ ACCESS END. ARM stops the timer. ARM sends
an interrupt to Ex-CPU as READ DISABLE" Sys.*
CPUInt.GPInt bits and the associated Sys.*CPUCommInt CFRs are used for this communication.
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1.9.3.1.2 Ex-CPU Write
ARM sends an interrupt to ex-CPU as WRITE ENABLE.
Ex-CPU sends an interrupt to ARM as WRITE REQUEST. ARM invokes a timer to watch access
timeout and can't access write communication memory until ex-CPU access end.
Ex-CPU writes data into communication area.
Ex-CPU sends an interrupt to ARM as WRITE ACCESS END. ARM stops the timer.
ARM sends an interrupt toeEx-CPU as WRITE DISABLE.
Sys.*CPUInt.GPInt bits and the associated Sys.*CPUCommInt CFRs are used for this
communication.
1.9.3.1.3 Ex-CPU Access Limitation
Table 3. Ex-CPU Access Limitation
Addr
018h
018h
018h
048h
04Ch
05Ch
Bit
16
8
N/A
15:0
15:0
31:0
Bit Name
InCPUCfg.DbgRegUnlock
InCPUCfg.DebugEn
RSVD
CommWrBase.Addr
CommRdBase.Addr
IntMemLoad.IntMemLoad
Read Access
Write Access
Condition
Yes
Yes
N/A
No
No
Yes
No
N/A
No
No
Conditional
Conditional
Write access only while ARM_RESET =
LOW in normal operation mode:
IntMemDiag.ProtectDis = 0.
Read and write access in diagnostic mode:
IntMemDiag.ProtectDis = 1
060h
060h
03Ch
25
24
31:0
31:0
31:0
N/A
IntMemDiag.EncryptDis
IntMemDiag.ProtectDis
InCPUComIntEn.*
InCPUInt.*
Yes
Yes
Yes
Yes
Yes
N/A
No
No
No
No
No
N/A
024h
028h, 02Ch
InCPUIntEn.*
1FAh -1FCh,
RSVD
324h – 32Ch
200h - 204h,
330h – 334h
N/A
N/A
N/A
RSVD
RSVD
RSVD
N/A
N/A
N/A
N/A
N/A
N/A
208h - 20Ch,
338h – 33Ch
630h – 774h
Note: The BOLD coded CFRs are reserved (RSVD).
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1.9.4 Ex-CPU Timing
1.9.4.1 I/O Type-0 68K + Wait
0x0 †
MCIF_MODE
MCIF_ENDIAN
MCIF_CS_MEMz
MCIF_CS_IOz
I
I
I
I
Tsu4
Th4
‡
Tsu3
Th3
Tw1
Th5
Tw2
§
Th5
MCIF_STRBz
MCIF_R_nWz
I
I
I
Tsu2
Th2
Tsu2
Th2
¶
Tsu1
Th1
Tsu1
ADDR N or N+2
Th1
#
#
MCIF_ADDR[10:1]
ADDR N or N+2
Tv2
Tdis2
Tdis2
Tv2
Tv1
DATA n+2
Ten2
Tv1
DATA n
Ten2
Td2||
MCIF_DATA[15:0]
MCIF_ACKz
IO
O
Td1||
Ten1
Tdis1
Td3
Ten1
Td3
Tdis1
MCIF_WAITz
O
NOTES: A. The timing diagram assumes MCIF signals used their default polarities. The MCIF_WAITz defaults
to the active high polarity in the MCIF I/O Type-0 68K mode.
B. MCIF_OEz, MCIF_WEz and MCIF_BUSCLKz are "Don't Care" for the MCIF I/O Type-0 68K mode.
C. Single 16-bit read accesses will not result in an error or an interrupt.
D. For a read access to occur both MCIF_CS_IOz and MCIF_STRBz must be asserted.
†
MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE
should not change during a quadlet access cycle.
‡ MCIF_ENDIAN may change during device operation. It should not change during a quadlet access
or data corruption may result.
§ The MCIF_STRBz is not required to deassert between accesses.
¶ MCIF_R_nWz may change between accesses.
#
CFR accesses must be quadlet aligned. The MCIF_ADDR[1] bit is immaterial and the MCIF_ADDR
may be of value "N" or "N+2" when considered as a byte address ( ADDR[10:0] ). MCIF_ADDR[0] is
internally grounded. MCIF_ADDR[1] is used in the Memory MCIF mode.
|| The MCIF_ACKz / MCIF_WAITz assert delays Td1 and Td2 are measured from the MCIF_CS_IOz or
MCIF_STRBz assert, whichever occurs last in the access.
Figure 10. I/O Type-0 68K + Wait Read
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Table 4. I/O Type-0 68K + Wait Read MCIF AC-Timing Parameters
Description
Min
0
0
0
0
Max
Units
ns
ns
ns
ns
Tsu1
Tsu2
Tsu3
Tsu4
Th1
Setup time, MCIF_ADDR valid before MCIF_CS_IOz asserted
Setup time, MCIF_R_nWz before MCIF_CS_IOz asserted
Setup time, MCIF_CS_MEMz deasserted before MCIF_CS_IOz asserted
Setup time, MCIF_ENDIAN before MCIF_CS_IOz asserted
Hold time, MCIF_ADDR valid after MCIF_ACKz asserted
Hold time, MCIF_R_nWz after MCIF_ACKz asserted
0
0
ns
ns
Th2
Th3
Th4
Hold time, MCIF_CS_MEMz deasserted after MCIF_CS_IOz deasserted
Hold time, MCIF_ENDIAN after MCIF_CS_IOz deasserted
0
0
ns
ns
Th5
Hold time, MCIF_CS_IOz or MCIF_STRBz after MCIF_ACKz asserted /
0
ns
MCIF_WAITz deasserted
Td1
Td2
Delay time, read access, MCIF_ACKz asserted / MCIF_WAITz deasserted
after MCIF_STRBz asserted
260
260
15
ns
ns
Delay time, read access, MCIF_ACKz asserted / MCIF_WAITz deasserted
after MCIF_CS_IOz asserted
Td3
Tv1
Delay time, MCIF_WAITz asserted after MCIF_CS_IOz asserted
ns
ns
Valid time, MCIF_DATA before MCIF_ACKz asserted / MCIF_WAITz
0
0
deasserted
Tv2
Valid time, MCIF_DATA after MCIF_CS_IOz or MCIF_STRBz deasserted
Enable time, MCIF_CS_IOz asserted to MCIF_ACKz / MCIF_WAITz driven
Enable time, MCIF_CS_IOz and MCIF_STRBz asserted to MCIF_DATA driven
ns
ns
ns
ns
Ten1
Ten2
Tdis1
15
15
15
Disable time, MCIF_ACKz / MCIF_WAITz high impedance from MCIF_CS_IOz
deasserted
Tdis2
Disable time, MCIF_DATA high impedance from MCIF_CS_IOz or
MCIF_STRBz deasserted
15
ns
Tw1
Tw2
Access width, MCIF_CS_IOz deasserted to MCIF_CS_IOz asserted
Access width, MCIF_STRBz deasserted to MCIF_STRBz asserted
25
0
ns
ns
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0x0 †
MCIF_MODE
MCIF_ENDIAN
MCIF_CS_MEMz
MCIF_CS_IOz
I
I
I
I
Tsu5
Th5
‡
Tsu4
Th4
Tw1
Th6
Tw2
§
Th6
I
MCIF_STRBz
MCIF_R_nWz
Tsu2
Th2
Tsu2
Th2
I
¶
Tsu1
Th1
Tsu1
Th1
#
#
I
MCIF_ADDR[10:1]
MCIF_DATA[15:0]
MCIF_ACKz
ADDR N or N+2
Tsu3
ADDR N or N+2
Tsu3
Th3
Th3
IO
O
DATA n
DATA n+2
Ten1
Td1 ||
Tdis1
Tdis1
Td2 ||
Tdis1
Tdis1
Td3
Ten1
Td3
O
MCIF_WAITz
NOTES: A. The timing diagram assumes MCIF signals used their default polarities. The MCIF_WAITz defaults
to the active high polarity in the MCIF I/O Type-0 68K mode.
B. MCIF_OEz, MCIF_WEz and MCIF_BUSCLK are "Don't Care" for the MCIF I/O Type-0 68K mode.
C. Single 16-bit write accesses are not allowed, resulting in the ExCPUErr interrupt bit being set.
D. For a write access to occur both MCIF_CS_IOz and MCIF_STRBz must be asserted.
†
MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE
should not change during a quadlet write cycle.
‡ MCIF_ENDIAN may change during device operation. It should not change during a quadlet access
or data corruption may result.
§ MCIF_STRBz is not required to deassert between accesses.
¶ MCIF_R_nWz may change between accesses.
#
CFR accesses must be quadlet aligned. The MCIF_ADDR[1] bit is immaterial and the MCIF_ADDR
may be of value "N" or "N+2" when considered as a byte address ( ADDR[10:0] ). MCIF_ADDR[0] is
internally grounded. MCIF_ADDR[1] is used in the Memory MCIF mode.
|| The MCIF_ACKz / MCIF_WAITz assert delays Td1 and Td2 are measured from the MCIF_CS_IOz or
MCIF_STRBz assert, whichever occurs last in the access.
Figure 11. I/O Type-0 68K + Wait Write
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Table 5. I/O Type-0 68K + Wait Write MCIF AC Timing Parameters
Description
Min
0
0
-40
0
0
Max
Units
ns
ns
ns
ns
ns
ns
ns
Tsu1
Tsu2
Tsu3
Tsu4
Tsu5
Th1
Setup time, MCIF_ADDR valid before MCIF_CS_IOz asserted
Setup time, MCIF_R_nWz before MCIF_CS_IOz asserted
Setup time, MCIF_DATA valid before MCIF_CS_IOz asserted
Setup time, MCIF_CS_MEMz deasserted before MCIF_CS_IOz asserted
Setup time, MCIF_ENDIAN before MCIF_CS_IOz asserted
Hold time, MCIF_ADDR valid after MCIF_CS_IOz asserted
Hold time, MCIF_R_nWz after MCIF_CS_IOz asserted
0
0
Th2
Th3
Hold time, MCIF_DATA valid after MCIF_ACKz asserted / MCIF_WAITz
0
ns
deasserted
Th4
Th5
Th6
Hold time, MCIF_CS_MEMz deasserted after MCIF_CS_IOz deasserted
Hold time, MCIF_ENDIAN after MCIF_CS_IOz deasserted
0
0
0
ns
ns
ns
Hold time, MCIF_CS_IOz or MCIF_STRBz after MCIF_ACKz asserted /
MCIF_WAITz deasserted
Td1
Td2
Delay time, first write access, MCIF_ACKz asserted / MCIF_WAITz deasserted
after MCIF_CS_IOz / MCIF_STRBz asserted
140
100
ns
ns
Delay time, second write access, MCIF_ACKz asserted / MCIF_WAITz
deasserted after MCIF_CS_IOz / MCIF_STRBz asserted
Td3
Ten1
Tdis1
Delay time, MCIF_WAITz asserted after MCIF_CS_IOz asserted
Enable time, MCIF_CS_IOz asserted to MCIF_ACKz / MCIF_WAITz driven
15
15
15
ns
ns
ns
Disable time, MCIF_ACKz / MCIF_WAITz high impedance from MCIF_CS_IOz
deasserted
Tw1
Tw2
Tsu1
Access width, MCIF_CS_IOz deasserted to MCIF_CS_IOz asserted
Access width, MCIF_STRBz deasserted to MCIF_STRBz asserted
Setup time, MCIF_ADDR valid before MCIF_CS_IOz asserted
25
0
0
ns
ns
ns
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1.9.4.2 I/O Type-1 SH3 SRAM-Like + Wait
This I/O interface type supports SH3(HD6417709A) bus state controller specification.
0x1 †
‡
I
I
I
I
MCIF_MODE
MCIF_ENDIAN
MCIF_CS_MEMz
MCIF_CS_IOz
Tsu5
Th5
Tsu4
Th4
Tw1
Th2
Tw2
§
Tsu2
Th2
Tsu2
I
I
I
RDn (MCIF_OEz)
WRn (MCIF_WEz)
MCIF_ADDR[10:1]
Tsu3
Th3
Tsu1
Th1
Tsu1
ADDR N or N+2
Th1
¶
¶
ADDR N or N+2
Ten2
Tv2 #
Tdis2
Tdis2
Tv1
Ten2
Tv2 #
Tdis1
IO MCIF_DATA[15:0]
DATA n
DATA n+2
Td1
Td1
Ten1
Ten1
Tdis1
O
(RDY) MCIF_WAITz
NOTES: A. The timing diagram assumes MCIF signals used their default polarities. The RDY (MCIF_WAITz)
defaults to the active low polarity in the MCIF I/O Type-1 SH3 mode.
B. The MCIF_STRBz, MCIF_R_nWz and MCIF_BUSCLKz inputs are "Don't Care" and the MCIF_ACKz
output is not used in the MCIF I/O Type-1 SH3 mode.
C. Single 16-bit read accesses will not result in an error or an interrupt.
†
MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE
should not change during a quadlet access cycle.
‡ MCIF_ENDIAN may change during device operation. It should not change during a quadlet access
or data corruption may result.
§
For a read access to occur, both MCIF_CS_IOz and RDn (MCIF_OEz) must be asserted. The
RDn (MCIF_OEz) is not required to deassert between accesses.
¶ CFR accesses must be quadlet aligned. The MCIF_ADDR[1] bit is immaterial and the MCIF_ADDR
may be of value "N" or "N+2" when considered as a byte address ( ADDR[10:0] ). MCIF_ADDR[0] is
internally grounded. MCIF_ADDR[1] is used in the Memory MCIF mode.
#
Valid time Tv2 is from RDn (MCIF_OEz) or MCIF_CS_IOz, whichever deasserts first in the access.
Figure 12. I/O Type-1 SH3 Read
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Table 6. I/O Type-1 SH3 Critical Timing (Read)
Description
Min
0
-40
0
0
0
Max
Units
ns
ns
ns
ns
Tsu1
Tsu2
Tsu3
Tsu4
Tsu5
Th1
Setup time, MCIF_ADDR valid before MCIF_CS_IOz asserted
Setup time, RDn (MCIF_OEz) asserted before MCIF_CS_IOz asserted
Setup time, WRn (MCIF_WEz) deasserted before MCIF_CS_IOz asserted
Setup time, MCIF_CS_MEMz deasserted before MCIF_CS_IOz asserted
Setup time, MCIF_ENDIAN before MCIF_CS_IOz asserted
ns
Hold time, MCIF_ADDR valid after RDY (MCIF_WAITz) asserted
0
ns
Th2
Hold time, RDn (MCIF_OEz) or MCIF_CS_IOz asserted after RDY
0
ns
(MCIF_WAITz) asserted
Th3
Th4
Th5
Td1
Hold time, WRn (MCIF_WEz) deasserted after MCIF_CS_IOz deasserted
Hold time, MCIF_CS_MEMz deasserted after MCIF_CS_IOz deasserted
Hold time, MCIF_ENDIAN after MCIF_CS_IOz deasserted
0
0
0
ns
ns
ns
ns
Delay time, read access, RDY (MCIF_WAITz) asserted after MCIF_CS_IOz
260
asserted
Tv1
Tv2
Ten1
Ten2
Valid time, MCIF_DATA before RDY (MCIF_WAITz) asserted
Valid time, MCIF_DATA after MCIF_CS_IOz or RDn (MCIF_OEz) deasserted
Enable time, MCIF_CS_IOz asserted to RDY (MCIF_WAITz) driven
0
0
ns
ns
ns
ns
15
15
Enable time, MCIF_CS_IOz and RDn (MCIF_OEz) asserted to MCIF_DATA
driven
Tdis1
Tdis2
Disable time, RDY (MCIF_WAITz) high impedance after MCIF_CS_IOz
deasserted
15
15
ns
ns
Disable time, MCIF_DATA high impedance after MCIF_CS_IOz or RDn
(MCIF_OEz) deasserted
Tw1
Tw2
Access width, MCIF_CS_IOz deasserted to MCIF_CS_IOz asserted
Access width, RDn (MCIF_OEz) deasserted to RDn (MCIF_OEz) asserted
25
0
ns
ns
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0x1 †
MCIF_MODE
MCIF_ENDIAN
MCIF_CS_MEMz
MCIF_CS_IOz
I
I
I
I
I
Tsu6
Th6
‡
Tsu5
Th5
Tw1
Th2
Tsu4
Th4
RDn (MCIF_OEz)
Th2
Tsu2
Tsu2
Tw2
§
I
I
WRn (MCIF_WEz)
MCIF_ADDR[10:1]
MCIF_DATA[15:0]
Tsu1
Th1
Tsu1
ADDR N or N+2
Th1
¶
¶
ADDR N or N+2
Tsu3
Th3
Tsu3
Th3
IO
DATA n
DATA n+2
Td1
Td2
Ten1
Ten1
Tdis1
Tdis1
O
RDY (MCIF_WAITz)
NOTES: A. The timing diagram assumes MCIF signals used their default polarities. The RDY (MCIF_WAITz)
defaults to the active low polarity in the MCIF I/O Type-1 SH3 mode.
B. The MCIF_STRBz, MCIF_R_nWz and MCIF_BUSCLKz inputs are "Don't Care" and the MCIF_ACKz
output is not used in the MCIF I/O Type-1 SH3 mode.
C. Single 16-bit write accesses are not allowed, resulting in the ExCPUErr interrupt bit being set.
†
MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE
should not change during a quadlet access cycle.
‡ MCIF_ENDIAN may change during device operation. It should not change during a quadlet access
or data corruption may result.
§
For a write access to occur, both MCIF_CS_IOz and MCIF_WEz must be asserted. The WRn
(MCIF_WEz) is not required to deassert between accesses.
¶
CFR accesses must be quadlet aligned. The MCIF_ADDR[1] bit is immaterial and the MCIF_ADDR
may be of value "N" or "N+2" when considered as a byte address ( ADDR[10:0] ). MCIF_ADDR[0] is
internally grounded. MCIF_ADDR[1] is used in the Memory MCIF mode.
Figure 13. I/O Type-1 SH3 Write
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Table 7. I/O Type-1 SH3 AC Timing (Write)
Description
Min
0
-40
-40
0
Max
Units
ns
ns
ns
ns
Tsu1
Tsu2
Tsu3
Tsu4
Tsu5
Tsu6
Th1
Setup time, MCIF_ADDR valid before MCIF_CS_IOz asserted
Setup time, WRn (MCIF_WEz) asserted before MCIF_CS_IOz asserted
Setup time, MCIF_DATA valid before MCIF_CS_IOz asserted
Setup time, RDn (MCIF_OEz) deasserted before MCIF_CS_IOz asserted
Setup time, MCIF_CS_MEMz deasserted before MCIF_CS_IOz asserted
Setup time, MCIF_ENDIAN before MCIF_CS_IOz asserted
0
0
ns
ns
Hold time, MCIF_ADDR valid after RDY (MCIF_WAITz) asserted
0
ns
Th2
Hold time, WRn (MCIF_WEz) or MCIF_CS_IOz asserted after RDY
0
ns
(MCIF_WAITz) asserted
Th3
Th4
Th5
Th6
Td1
Hold time, MCIF_DATA valid after RDY (MCIF_WAITz) asserted
Hold time, RDn (MCIF_OEz) deasserted after MCIF_CS_IOz deasserted
Hold time, MCIF_CS_MEMz deasserted after MCIF_CS_IOz deasserted
Hold time, MCIF_ENDIAN after MCIF_CS_IOz deasserted
0
0
0
0
ns
ns
ns
ns
ns
Delay time, first write access, RDY (MCIF_WAITz) asserted after
120
120
MCIF_CS_IOz asserted
Td2
Delay time, second write access, RDY (MCIF_WAITz) asserted after
MCIF_CS_IOz asserted
ns
Ten1
Tdis1
Enable time, MCIF_CS_IOz asserted to RDY (MCIF_WAITz) driven
15
15
ns
ns
Disable time, RDY (MCIF_WAITz) high impedance after MCIF_CS_IOz
deasserted
Tw1
Tw2
Access width, MCIF_CS_IOz deasserted to MCIF_CS_IOz asserted
Access width, WRn (MCIF_WEz) deasserted to WRn (MCIF_WEz) asserted
25
0
ns
ns
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1.9.4.3 I/O Type-2 M16C SRAM-Like + Wait
This type supports the M16C/62-compatible interface timing.
I
I
I
I
MCIF_MODE
MCIF_ENDIAN
MCIF_CS_MEMz
MCIF_CS_IOz
0x2 †
Tsu5
Th5
‡
Tsu4
Th4
Tw1
Th2
Tw2
Tsu2
Th2
Tsu2
I
I
I
RDn (MCIF_OEz)
WRn (MCIF_WEz)
MCIF_ADDR[10:1]
§
Tsu3
Th3
Tsu1
Th1
Tsu1
Th1
¶
¶
ADDR N or N+2
Ten2
ADDR N or N+2
Ten2
Tdis2
Tv2 #
Tdis2
Tv1
DATA n
Tv1
DATA n+2
Tv2 #
Tdis1
IO MCIF_DATA[15:0]
Td1
Td1
Tdis1
Ten1
Ten1
(RDY) MCIF_WAITz
O
NOTES: A. The timing diagram assumes MCIF signals used their default polarities. The RDY (MCIF_WAITz)
defaults to the active low polarity in the MCIF I/O Type-2 M16C mode.
B. The MCIF_STRBz, MCIF_R_nWz and MCIF_BUSCLKz inputs are "Don't Care" and the MCIF_ACKz
output is not used in the MCIF I/O Type-2 M16C mode.
C. Single 16-bit read accesses will not result in an error or an interrupt.
†
MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE
should not change during a quadlet access cycle.
‡ MCIF_ENDIAN may change during device operation. It should not change during a quadlet access
or data corruption may result.
§
For a read access to occur, both MCIF_CS_IOz and RDz (MCIF_OEz) must be asserted. The
RDn (MCIF_OEz) is not required to deassert between accesses.
¶
CFR accesses must be quadlet aligned. The MCIF_ADDR[1] bit is immaterial and the MCIF_ADDR
may be of value "N" or "N+2" when considered as a byte address ( ADDR[10:0] ). MCIF_ADDR[0] is
internally grounded. MCIF_ADDR[1] is used in the Memory MCIF mode.
#
Valid time Tv2 is from RDn (MCIF_OEz) or MCIF_CS_IOz, whichever deasserts first in the access.
Figure 14. I/O Type-2 M16C SRAM-Like + Wait Read
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Table 8. I/O Type-2 M16C SRAM-Like + Wait AC Timing Parameters (Read)
Description
Min
0
-40
0
0
0
Max
Units
ns
ns
ns
ns
Tsu1
Tsu2
Tsu3
Tsu4
Tsu5
Th1
Setup time, MCIF_ADDR valid before MCIF_CS_IOz asserted
Setup time, RDn (MCIF_OEz) asserted before MCIF_CS_IOz asserted
Setup time, WRn (MCIF_WEz) deasserted before MCIF_CS_IOz asserted
Setup time, MCIF_CS_MEMz deasserted before MCIF_CS_IOz asserted
Setup time, MCIF_ENDIAN before MCIF_CS_IOz asserted
Hold time, MCIF_ADDR valid after RDY (MCIF_WAITz) asserted
ns
ns
0
Th2
Hold time, RDn (MCIF_OEz) or MCIF_CS_IOz asserted after RDY
0
ns
(MCIF_WAITz) asserted
Th3
Th4
Th5
Td1
Hold time, WRn (MCIF_WEz) deasserted after MCIF_CS_IOz deasserted
Hold time, MCIF_CS_MEMz deasserted after MCIF_CS_IOz deasserted
Hold time, MCIF_ENDIAN after MCIF_CS_IOz deasserted
0
0
0
ns
ns
ns
ns
Delay time, read access, RDY (MCIF_WAITz) asserted after MCIF_CS_IOz
210
340
asserted
Tv1
Tv2
Ten1
Ten2
Valid time, MCIF_DATA before RDY (MCIF_WAITz) asserted
Valid time, MCIF_DATA after MCIF_CS_IOz or RDn (MCIF_OEz) deasserted
Enable time, MCIF_CS_IOz asserted to RDY (MCIF_WAITz) driven
30
0
ns
ns
ns
ns
15
15
Enable time, MCIF_CS_IOz and RDn (MCIF_OEz) asserted to MCIF_DATA
driven
Tdis1
Tdis2
Disable time, RDY (MCIF_WAITz) high impedance after MCIF_CS_IOz
deasserted
15
15
ns
ns
Disable time, MCIF_DATA high impedance after MCIF_CS_IOz or RDn
(MCIF_OEz) deasserted
Tw1
Tw2
Access width, MCIF_CS_IOz deasserted to MCIF_CS_IOz asserted
Access width, RDn (MCIF_OEz) deasserted to RDn (MCIF_OEz) asserted
25
0
ns
ns
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0x2 †
MCIF_MODE
MCIF_ENDIAN
MCIF_CS_MEMz
MCIF_CS_IOz
I
I
I
I
I
Tsu6
Th6
‡
Tsu5
Th5
Tw1
Th2
Tsu4
Th4
RDn (MCIF_OEz)
Th2
Tsu2
Tw2
§
Tsu2
WRn (MCIF_WEz)
MCIF_ADDR[10:1]
MCIF_DATA[15:0]
I
I
Tsu1
Th1
Tsu1
Th1
¶
¶
ADDR N or N+2
ADDR N or N+2
Tsu3
Tsu3
Th3
Th3
IO
DATA n
DATA n+2
Td1
Ten1
Tdis1
Td2
Ten1
Tdis1
RDY (MCIF_WAITz)
O
NOTES: A. The timing diagram assumes MCIF signals used their default polarities. The RDY (MCIF_WAITz)
defaults to the active low polarity in the MCIF I/O Type-2 M16C mode.
B. The MCIF_STRBz, MCIF_R_nWz and MCIF_BUSCLK inputs are "Don't Care" and the MCIF_ACKz
output is not used in the MCIF I/O Type-2 M16C mode.
C. Single 16-bit write accesses are not allowed, resulting in the ExCPUErr interrupt bit being set.
†
MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE
should not change during a quadlet access cycle.
‡ MCIF_ENDIAN may change during device operation. It should not change during a quadlet access
or data corruption may result.
§
For a write access to occur, both MCIF_CS_IOz and WRn (MCIF_WEz) must be asserted. The
WRn (MCIF_WEz) is not required to deassert between accesses.
¶
CFR accesses must be quadlet aligned. The MCIF_ADDR[1] bit is immaterial and the MCIF_ADDR
may be of value "N" or "N+2" when considered as a byte address ( ADDR[10:0] ). MCIF_ADDR[0] is
internally grounded. MCIF_ADDR[1] is used in the Memory MCIF mode.
Figure 15. I/O Type-2 M16C SRAM-Like + Wait Write
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Table 9. I/O Type-2 M16C SRAM-Like + Wait AC Timing Parameters (Write)
Description
Min
0
-40
-40
0
0
0
0
Max
Units
ns
ns
ns
ns
ns
ns
ns
Tsu1
Tsu2
Tsu3
Tsu4
Tsu5
Tsu6
Th1
Setup time, MCIF_ADDR valid before MCIF_CS_IOz asserted
Setup time, WRn (MCIF_WEz) asserted before MCIF_CS_IOz asserted
Setup time, MCIF_DATA valid before MCIF_CS_IOz asserted
Setup time, RDn (MCIF_OEz) deasserted before MCIF_CS_IOz asserted
Setup time, MCIF_CS_MEMz deasserted before MCIF_CS_IOz asserted
Setup time, MCIF_ENDIAN before MCIF_CS_IOz asserted
Hold time, MCIF_ADDR valid after RDY (MCIF_WAITz) asserted
Th2
Hold time, WRn (MCIF_WEz) or MCIF_CS_IOz asserted after RDY
0
ns
(MCIF_WAITz) asserted
Th3
Th4
Th5
Th6
Td1
Hold time, MCIF_DATA valid after RDY (MCIF_WAITz) asserted
Hold time, RDn (MCIF_OEz) deasserted after MCIF_CS_IOz deasserted
Hold time, MCIF_CS_MEMz deasserted after MCIF_CS_IOz deasserted
Hold time, MCIF_ENDIAN after MCIF_CS_IOz deasserted
0
0
0
0
80
ns
ns
ns
ns
ns
Delay time, first write access, RDY (MCIF_WAITz) asserted after
340
340
MCIF_CS_IOz asserted
Td2
Delay time, second write access, RDY (MCIF_WAITz) asserted after
MCIF_CS_IOz asserted
80
ns
Ten1
Tdis1
Enable time, MCIF_CS_IOz asserted to RDY (MCIF_WAITz) driven
15
15
ns
ns
Disable time, RDY (MCIF_WAITz) high impedance after MCIF_CS_IOz
deasserted
Tw1
Tw2
Access width, MCIF_CS_IOz deasserted to MCIF_CS_IOz asserted
Access width, WRn (MCIF_WEz) deasserted to WRn (MCIF_WEz) asserted
25
0
ns
ns
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1.9.4.4 I/O Type-3 MPC850
Supports Motorola MPC850 external bus.
Td1
Td1
R_nW = Read
Read Data n
Read Data n+2
TAn Assert N+2
TSn Detect N
TAn N Asserted
CSn Detect
TSn Detect N+2
Tc
CSn_Detect
Tc
Tc
Tc
Tc
Tc
Tc
Tc
I
I
MCIF_BUSCLK
MCIF_MODE
0x3 †
Tsu6
Th6
MCIF_ENDIAN
‡
I
I
Tsu5
Th5
MCIF_CS_MEMz
Th4
§
Tsu4
Tsu4
I
I
I
I
MCIF_CS_IOz
MCIF_ADDR[10:1]
MCIF_R_nWz
Th1
Th1
Tsu1
Tsu1
¶
¶
ADDR N or N+2
ADDR N or N+2
Th2
Th2
Tsu2
Tsu2
#
¶
Th3
Th3
Tsu3
Tsu3
TSn (MCIF_STRBz)
#
¶
Tv2
Tv1
Tv1
Ten2
Tv2
Tdis2
IO MCIF_DATA[15:0]
DATA n
DATA n+2
Tdis1
Tv4
Tv3
Tv4
Tv3
Ten1
O
TAn (MCIF_ACKz)
NOTES: A. The timing diagram assumes MCIF signals used their default polarities.
B. MCIF_OEz, MCIF_WEz and MCIF_WAITz are "Don't Care" for the MCIF I/O Type-3 MPC850 mode.
C. Single 16-bit read accesses will not result in an error or an interrupt.
†
MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE
should not change during a quadlet access cycle.
‡ MCIF_ENDIAN may change during device operation. It should not change during a quadlet access
or data corruption may result.
§ MCIF_CS_IOz may deassert after TAn (MCIF_ACKz) is detected as long as Th5 is met. In
synchronous designs it may be better to allow at least one clock period delay between TAn
(MCIF_ACKz) detect and the next MCIF_CS_IOz access cycle.
¶ CFR accesses must be quadlet aligned. The MCIF_ADDR[1] bit is immaterial and the MCIF_ADDR
may be of value "N" or "N+2" when considered as a byte address ( ADDR[10:0] ). MCIF_ADDR[0] is
internally grounded. MCIF_ADDR[1] is used in the Memory MCIF mode.
# MCIF_R_nWz and TSn (MCIF_STRBz) may remain valid / asserted or become invalid /deasserted
during the access.
Figure 16. I/O Type-3 MPC850 Read
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Table 10. I/O Type-3 MPC850 Read AC Timing Parameters
Description
Min
24
2
Max
Units
ns
ns
Tc
Tsu1
Cycle time, MCIF_BUSCLKz
Setup time, MCIF_ADDR valid before MCIF_BUSCLKz rising edge [TSn
(MCIF_STRBz) assert cycle]
Tsu2
Setup time, MCIF_R_nWz before MCIF_BUSCLKz rising edge [TSn
(MCIF_STRBz) assert cycle]
16
ns
Tsu3
Tsu4
Tsu5
Setup time, TSn (MCIF_STRBz) asserted before MCIF_BUSCLKz rising edge
Setup time, MCIF_CS_IOz asserted before MCIF_BUSCLKz rising edge
15
4
4
ns
ns
ns
Setup time, MCIF_CS_MEMz deasserted before MCIF_BUSCLKz rising edge
(MCIF_CS_IOz assert cycle)
Tsu6
Th1
Th2
Setup time, MCIF_ENDIAN before MCIF_BUSCLKz rising edge (MCIF_CS_IOz
assert cycle)
4
14
2
ns
ns
ns
Hold time, MCIF_ADDR valid after MCIF_BUSCLKz rising edge [TSn
(MCIF_ACKz) assert cycle]
Hold time, MCIF_R_nWz after MCIF_BUSCLKz rising edge [TSn (MCIF_ACKz)
assert cycle]
Th3
Th4
Hold time, TSn (MCIF_STRBz) asserted after MCIF_BUSCLKz rising edge
2
14
ns
ns
Hold time, MCIF_CS_IOz asserted after MCIF_BUSCLKz rising edge [TAn
(MCIF_ACKz) assert cycle]
Th5
Th6
Td1
Tv1
Tv2
Hold time, MCIF_CS_MEMz deasserted after MCIF_BUSCLKz rising edge
[MCIF_CS_IOz deassert cycle]
0
0
ns
ns
ns
ns
ns
Hold time, MCIF_ENDIAN after MCIF_BUSCLKz rising edge [MCIF_CS_IOz
deassert cycle]
Delay time, read access, TSn (MCIF_STRBz) assert cycle to TAn (MCIF_ACKz)
assert cycle
150
Valid time, MCIF_DATA before MCIF_BUSCLKz rising edge [TAn (MCIF_ACKz)
10
2
asserted cycle]
Valid time, MCIF_DATA after MCIF_BUSCLKz rising edge [TAn (MCIF_ACKz)
asserted cycle]
Tv3
Tv4
Ten1
Ten2
Valid time, TAn (MCIF_ACKz) asserted before MCIF_BUSCLKz rising edge
Valid time, TAn (MCIF_ACKz) asserted after MCIF_BUSCLKz rising edge
Enable time, MCIF_CS_IOz asserted to TAn (MCIF_ACKz) driven
11
0
ns
ns
ns
ns
15
15
Enable time, MCIF_BUSCLKz rising edge to MCIF_DATA driven [TSn
(MCIF_ACKz) assert cycle]
Tdis1 Disable time, TAn (MCIF_ACKz) high impedance after MCIF_CS_IOz
deasserted
Tdis2 Disable time, MCIF_DATA high impedance after MCIF_CS_IOz deasserted
15
15
ns
ns
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Td1
Td1
R_nW_=_Write
R_nW = Write
Write Data n
TSn Detect N
Write Data n + 2
TSn Detect N+2
TAn Assert N+2
CSn Detect
Tc
TAn Assert N
Tc
CSn_Detect
Tc
Tc
Tc
Tc
Tc
Tc
I
I
MCIF_BUSCLK
MCIF_MODE
0x3 †
Tsu7
Th7
MCIF_ENDIAN
‡
I
I
Tsu6
Tsu4
Th6
MCIF_CS_MEMz
Th4
§
Tsu4
I
I
I
I
MCIF_CS_IOz
MCIF_ADDR[10:1]
MCIF_R_nWz
Th1
Th1
Tsu1
Tsu1
¶
¶
ADDR N or N+2
ADDR N or N+2
Th2
Th2
Tsu2
Tsu2
#
¶
¶
Th3
Th3
Tsu3
Tsu3
TSn (MCIF_STRBz)
#
Th5
Th5
Tsu5
Tsu5
IO MCIF_DATA[15:0]
DATA n
DATA n+2
Tdis1
Tv2
Tv1
Tv2
Tv1
Ten1
O
TAn (MCIF_ACKz)
NOTES: A. The timing diagram assumes MCIF signals used their default polarities.
B. MCIF_OEz, MCIF_WEz and MCIF_WAITz are "Don't Care" for the MCIF I/O Type-3 MPC850 mode.
C. Single 16-bit write accesses are not allowed, resulting in the ExCPUErr interrupt bit being set.
†
MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE
should not change during a quadlet access cycle.
‡ MCIF_ENDIAN may change during device operation. It should not change during a quadlet access
or data corruption may result.
§ MCIF_CS_IOz may deassert after TAn (MCIF_ACKz) is detected as long as Th5 is met. In
synchronous designs it may be better to allow at least one clock period delay between TAn
(MCIF_ACKz) detect and the next MCIF_CS_IOz access cycle.
¶ CFR accesses must be quadlet aligned. The MCIF_ADDR[1] bit is immaterial and the MCIF_ADDR
may be of value "N" or "N+2" when considered as a byte address ( ADDR[10:0] ). MCIF_ADDR[0] is
internally grounded. MCIF_ADDR[1] is used in the Memory MCIF mode.
#
MCIF_R_nWz and TSn (MCIF_STRBz) may remain valid / asserted or become invalid /deasserted
during the access.
Figure 17. I/O Type-3 MPC850 Write
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Table 11. I/O Type-3 MPC850 Write AC Timing Parameters
Description
Min
Max
Units
Tsu1
Tsu2
Setup time, MCIF_ADDR valid before MCIF_BUSCLKz rising edge [TSn
2
ns
(MCIF_STRBz) assert cycle]
Setup time, MCIF_R_nWz before MCIF_BUSCLKz rising edge [TSn
(MCIF_STRBz) assert cycle]
16
ns
Tsu3
Tsu4
Tsu5
Setup time, TSn (MCIF_STRBz) asserted before MCIF_BUSCLKz rising edge
Setup time, MCIF_CS_IOz asserted before MCIF_BUSCLKz rising edge
15
4
16
ns
ns
ns
Setup time, MCIF_DATA valid before MCIF_BUSCLKz rising edge [TSn
(MCIF_ACKz) assert cycle]
Tsu6
Tsu7
Th1
Setup time, MCIF_CS_MEMz deasserted before MCIF_BUSCLKz rising edge
(MCIF_CS_IOz assert cycle)
4
4
ns
ns
ns
Setup time, MCIF_ENDIAN before MCIF_BUSCLKz rising edge (MCIF_CS_IOz
assert cycle)
Hold time, MCIF_ADDR valid after MCIF_BUSCLKz rising edge [TSn
(MCIF_ACKz) assert cycle]
14
Th2
Th3
Th4
Hold time, TSn (MCIF_STRBz) asserted after MCIF_BUSCLKz rising edge
Hold time, TAn (MCIF_ACKz) asserted after MCIF_BUSCLKz rising edge
2
0
14
ns
ns
ns
Hold time, MCIF_CS_IOz asserted after MCIF_BUSCLKz rising edge [TAn
(MCIF_ACKz) assert cycle]
Th5
Th6
Th7
Td1
Hold time, MCIF_DATA valid after MCIF_BUSCLKz rising edge [TSn
(MCIF_ACKz) assert cycle]
2
0
0
ns
ns
ns
ns
Hold time, MCIF_CS_MEMz deasserted after MCIF_BUSCLKz rising edge
[MCIF_CS_IOz deassert cycle]
Delay time, read access, TSn (MCIF_STRBz) assert cycle to TAn (MCIF_ACKz)
assert cycle
Delay time, read access, TSn (MCIF_STRBz) assert cycle to TAn (MCIF_ACKz)
130
assert cycle
Tv1
Tv2
Ten1
Valid time, TAn (MCIF_ACKz) asserted before MCIF_BUSCLKz rising edge
Valid time, TAn (MCIF_ACKz) asserted after MCIF_BUSCLKz rising edge
11
2
ns
ns
ns
Enable time, MCIF_BUSCLKz rising edge to TAn (MCIF_ACKz) driven
15
15
(MCIF_CS_IOz assert cycle)
Tdis1
Disable time, TAn (MCIF_ACKz) high impedance after MCIF_BUSCLKz rising
edge (MCIF_CS_IOz deassert cycle)
ns
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1.9.4.5 Memory Type
All ex-CPU modes (Type-0 (68K) and Type-2 (M16C/62)) use the same timing for memory access. The
ex-CPU provides the bus clock (MCIF_BUSCLKz) in all modes.
MCIF_MODE
MCIF_BUSCLK
MCIF_ENDIAN
MCIF_CS_IOz
I
I
I
I
0x0 - 0x3 †
Tc
Tc
Tc
Tc
Tc
Tsu6
Tsu5
Th6
‡
Th5
Tw1
§
Tsu3
Th3
Tsu3
Th3
MCIF_CS_MEMz
I
Tw2
Tsu2
Th2
Tsu2
Th2
RDn (MCIF_OEz)
WRn (MCIF_WEz)
I
I
§
Tsu4
Th4
Th1
Tsu1
ADDR N
Th1
Tsu1
ADDR M+1
¶
¶
¶
MCIF_ADDR[10:1]
MCIF_DATA[15:0]
I
ADDR M
Ten1
Tv1
Tv3
Tdis1
Tv1
DATA n
Tdis1
Tv3
Tv1
DATA m+1
Ten1
Tv2 #
Tv2
IO
DATA m
NOTES: A. The timing diagram assumes MCIF signals used their default polarities.
B. The MCIF_STRBz and MCIF_R_nWz inputs are "Don't Care". The MCIF_ACKz and
MCIF_WAITz outputs are not used in the MCIF Memory Access mode.
C. Single 16-bit read accesses will not result in an error or an interrupt.
D. MCIF Memory Mode read access latency is two clock cycles.
†
MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE
should not change during an MCIF Memory Access cycle. Memory accesses may only occur if
MCIF_MODE is valid (0x0 through 0x3).
‡ MCIF_ENDIAN may change during device operation. It should not change during an access or data
corruption may result.
§
For a read access to occur, both MCIF_CS_MEMz and RDn (MCIF_OEz) must be asserted. The
MCIF_CS_MEMz and RDn (MCIF_OEz) are not required to deassert between accesses.
¶ Memory accesses are not required to be quadlet aligned. The MCIF_ADDR[1] bit is used along with
the MCIF_ENDIAN to determine which 16-bit word is read. Addressing should be considered as byte
addressing ( ADDR[10:0] ) with MCIF_ADDR[0] internally grounded.
#
Valid time Tv2 is from MCIF_CS_MEMz or RDn (MCIF_OEz), whichever deasserts first in the access.
Figure 18. Memory Type
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Table 12. Memory Type Read AC Timing Parameters
Description
Min
8.33
8
Max
142.86
Units
ns
ns
Tc
Tsu1
Cycle time, MCIF_BUSCLKz [Assume 20-pF loading]
Setup time, MCIF_ADDR valid before MCIF_BUSCLKz rising edge
(MCIF_CS_MEMz assert cycle)
Tsu2
Setup time, RDn (MCIF_OEz) asserted before MCIF_BUSCLKz rising edge
(MCIF_CS_MEMz assert cycle)
8
ns
Tsu3
Tsu4
Setup time, MCIF_CS_MEMz asserted before MCIF_BUSCLKz rising edge
8
8
ns
ns
Setup time, WRn (MCIF_WEz) deasserted before MCIF_BUSCLKz rising edge
(MCIF_CS_MEMz assert cycle)
Tsu5
Tsu6
Th1
Th2
Th3
Th4
Th5
Setup time, MCIF_CS_IOz deasserted before MCIF_BUSCLKz rising edge
(MCIF_CS_MEMz assert cycle)
8
8
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
Setup time, MCIF_ENDIAN before MCIF_BUSCLKz rising edge
(MCIF_CS_MEMz assert cycle)
Hold time, MCIF_ADDR valid after MCIF_BUSCLKz rising edge
(MCIF_CS_MEMz assert cycle)
Hold time, RDn (MCIF_OEz) asserted after MCIF_BUSCLKz rising edge (data
read cycle)
Hold time, MCIF_CS_MEMz asserted after MCIF_BUSCLKz rising edge (data
read cycle)
Hold time, WRn (MCIF_WEz) deasserted after MCIF_BUSCLKz rising edge
(data read cycle)
Hold time, MCIF_CS_IOz deasserted after MCIF_BUSCLKz rising edge (data
read cycle)
Th6
Tv1
Tv2
Tv3
Ten1
Hold time, MCIF_ENDIAN after MCIF_BUSCLKz rising edge (data read cycle)
Valid time, MCIF_DATA before MCIF_BUSCLKz rising edge (data read cycle)
Valid time, MCIF_DATA after MCIF_CS_MEMz or RDn (MCIF_OEz) deasserted
Valid time, MCIF_DATA after MCIF_BUSCLKz rising edge (data read cycle)
0
8
8
2
ns
ns
ns
ns
ns
Enable time, MCIF_CS_MEMz and RDn (MCIF_OEz) asserted to MCIF_DATA
15
15
driven
Tdis1
Tw1
Tw2
Disable time, MCIF_DATA high impedance after MCIF_CS_MEMz deasserted
Access width, MCIF_CS_MEMz deasserted to MCIF_CS_MEMz asserted
Access width, RDn (MCIF_OEz) deasserted to RDn (MCIF_OEz) asserted
ns
ns
ns
0
0
Note: Measurements are based on a 20-pF loading.
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I
I
I
I
MCIF_MODE
MCIF_BUSCLK
MCIF_ENDIAN
MCIF_CS_IOz
0x0 - 0x3 †
Tc
Tc
Tc
Tsu7
Th7
‡
Tsu6
Th6
Tw1
§
Tsu5
Th5
Tsu5
Th5
I
I
MCIF_CS_MEMz
RDn (MCIF_OEz)
Tsu4
Th4
Tsu2
Tsu2
Th1
Th2
Tw2
§
Th2
WRn (MCIF_WEz)
MCIF_ADDR[10:1]
I
I
Th1
Th1
Tsu1
ADDR M+1
Tsu1
ADDR N
Tsu1
ADDR M
¶
¶
¶
¶
ADDR P
DATA p
Th3
Th3
Th3
Tsu3
DATA m+1
Tsu3
DATA n
Tsu3
IO MCIF_DATA[15:0]
DATA m
NOTES: A. The timing diagram assumes MCIF signals used their default polarities.
B. The MCIF_STRBz and MCIF_R_nWz inputs are "Don't Care". The MCIF_ACKz and
MCIF_WAITz outputs are not used in the MCIF Memory Access mode.
C. Single 16-bit write accesses are allowed and will not result in an error or an interrupt.
D. MCIF Memory Mode write access latency is zero clock cycles.
†
MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE
should not change during an MCIF Memory Access cycle. Memory accesses may only occur if
MCIF_MODE is valid (0x0 through 0x3).
‡ MCIF_ENDIAN may change during device operation. It should not change during an access or data
corruption may result.
§
For a write access to occur, both MCIF_CS_MEMz and WRn (MCIF_WEz) must be asserted. The
MCIF_CS_MEMz and WRn (MCIF_WEz) are not required to deassert between accesses.
¶ Memory accesses are not required to be quadlet aligned. The MCIF_ADDR[1] bit is used along with
the MCIF_ENDIAN to determine which 16-bit word is written. Addressing should be considered as byte
addressing ( ADDR[10:0] ) with MCIF_ADDR[0] internally grounded.
Figure 19. Memory Write
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Table 13. Memory Type Write AC Timing Parameters
Description
Min
8
8
Max
Units
ns
ns
Tsu1
Tsu2
Tsu3
Tsu4
Setup time, MCIF_ADDR valid before MCIF_BUSCLKz rising edge
Setup time, WRn (MCIF_WEz) asserted before MCIF_BUSCLKz rising edge
Setup time, MCIF_DATA valid before MCIF_BUSCLKz rising edge
8
ns
Setup time, RDn (MCIF_OEz) deasserted before MCIF_BUSCLKz rising edge
8
ns
(data write cycle)
Tsu5
Tsu6
Setup time, MCIF_CS_MEMz asserted before MCIF_BUSCLKz rising edge
8
8
ns
ns
Setup time, MCIF_CS_IOz deasserted before MCIF_BUSCLKz rising edge
(data write cycle)
Tsu7
Setup time, MCIF_ENDIAN before MCIF_BUSCLKz rising edge (data write
cycle)
8
ns
Th1
Th2
Th3
Th4
Hold time, MCIF_ADDR valid after MCIF_BUSCLKz rising edge
Hold time, WRn (MCIF_WEz) asserted after MCIF_BUSCLKz rising edge
Hold time, MCIF_DATA valid after MCIF_BUSCLKz rising edge
0
0
0
0
ns
ns
ns
ns
Hold time, RDn (MCIF_OEz) deasserted after MCIF_BUSCLKz rising edge
(data write cycle)
Th5
Th6
Hold time, MCIF_CS_MEMz asserted after MCIF_BUSCLKz rising edge (data
write cycle)
0
0
ns
ns
Hold time, MCIF_CS_IOz deasserted after MCIF_BUSCLKz rising edge (data
write cycle)
Th7
Tw1
Tw2
Hold time, MCIF_ENDIAN after MCIF_BUSCLKz rising edge (data write cycle)
Access width, MCIF_CS_MEMz deasserted to MCIF_CS_MEMz asserted
Access width, WRn (MCIF_WEz) deasserted to WRn (MCIF_WEz) asserted
0
0
0
ns
ns
ns
Note: Measurements are based on a 20-pF loading.
1.9.5 LEB Encryption
The external CPU interface contains an option for encryption. The encryption protects DTLA key transfer
over the external CPU interface. The parallel external CPU mode uses this method.
1) The external CPU starts the program load to the iceLynx-Micro. The code is loaded starting at
address 0h. The first two quadlets have encryption information. The other quadlets are the encrypted
download program (up to 256K bytes). The program code must always contain these two header
quadlets, even if the data is not encrypted. The C bits indicate if data must be decrypted.
The first two quadlets have the following format:
Table 14. Ex-CPU Encryption First Quadlet
31 29
C
28 24
Key No
23
0
Key Seed
Key Seed
2) The iceLynx-Micro uses the values in the first quadlet to determine how to decrypt the data.
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Table 15. Ex-CPU Encryption Reference
Field
Description
Purpose
Indicates encryption mode. Values from 000 to 111 are valid.
If value is 111, the hardware stops LEB decryption. The program is
C
Three bit encryption indicator
Key Number (see Note 1)
loaded to program memory without being decrypted.
If value is any other than 111, the hardware performs LEB decryption
on the data loaded into program memory.
Used to indicate which 56-bit key the iceLynx-Micro uses for LEB
decryption. The keys are available in a Device Key ROM table. There
are 32 separate 56-bit entries.
Each key corresponds to a specific Key No.
Key No
Single LEB
Key No
0
1
2
31
AAAA AAAA AAAA AA
BBBB BBBB BBBB BB
CCCC CCCC CCCC CC
6666 6666 6666 66
Key
Seed value provided by
ex-CPU
This 56-bit number is used as an input to the Single LEB decryption
Seed
hardware.
Note 1: Contact Texas Instruments for actual key numbers and key data.
3) LEB decryption hardware
An XOR operation is performed on the Key Seed provided by the ex-CPU and the Device Key (selected
from the Device Key ROM table by Key No). If the C values are any value except 111, the hardware
decrypts the program code.
The maximum throughput for the program load using LEB is 20 Mbytes per second.
1.10 Integrated CPU
1.10.1 Description/Overview
The iceLynx-Micro has an integrated ARM7TDMI processor. The operating frequency is 50 MHz. The
processor is intended to handle all 1394 transactions as well as DTCP related software. It operates in
16-bit mode in addition to 32-bit mode.
Access to CFRs requires three clock cycles for reads and writes. All other internal memory locations are
accessed in a single cycle.
1.10.2 Interaction With External CPU
Only one CPU (internal or external) can access memory locations at one time. This includes configuration
registers and FIFOs. The integrated CPU has access to program memory and communication memory in
byte mode, 16-bit mode, or 32-bit mode. The external CPU has priority over the internal CPU. While the
ex-CPU performs a memory access (2x1024-byte RAMs), the ARM can use the internal bus freely.
1.10.3 External Interrupts
The GPIO pins are configured as IRQ and/or FIQ interrupts used to signal interrupts for the ARM. GPIO
pins can also be configured as other types of interrupts as specified in GPIOIntCfg CFR. General-purpose
interrupts can also be used for communication between the internal and external processors. These
interrupts are available in InCPUComInt and ExCPUComInt CFRs.
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1.10.4 Timer
The iceLynx-Micro has three general timers. One of these timers, Timer2, is configured as the watchdog
timer. The WTCH_DG_TMRn (watchdog timer output) port detects any internal ARM software failure. If
the watchdog timer expires, hardware sets WTCH_DG_TMRn = low, Low_Pwr_Rdy = low.
The value for CFR and output are as follows:
Low_Pwr_Rdy = low (hardware sets)
WTCH_DG_TMRn = low (hardware sets)
HPS = high (external application sets)
LPS = high
RESET_ARMn = low (external application sets)
PHYNoticeEn = high or low
The following describes the WTCH_DG_TMRn behavior whenever PinCfg.WtchDgTmrN is set to 0.
The WTCH_DG_TMRn pin reflects the value of Timer2.Enable.
(b)
(c)
(d)
WTCH_DG_TMRZ
(a)
Figure 20. Watchdog Timer Waveform
At phase (a), the iceLynx-Micro is in the power-up stage. The ARM has not been programmed and is not
operating. Sys.Timer2.Enable bit is 0, and the WTCH_DG_TMRn pin is asserted (low).
At phase (b), the iceLynx-Micro is in the active stage. The ARM is executing code and has set
Sys.Timer2.Enable = 1. The ARM clears the Timer2 counter by periodically writing a 1 to
Sys.Timer2.Enable bit to keep Sys.Timer2.Counter from equaling Sys.Timer2.Period. The
WTCH_DG_TMRn pin reflects the status of Sys.Timer2.Enable and is deasserted (high).
At phase (c), the iceLynx-Micro is still in the active stage. However, the ARM has failed to clear the
Timer2 counter in time. Sys.Timer2.Counter = Sys.Timer2.Period. At this point, iceLynx-Micro hardware
clears Sys.Timer2.Enable. The WTCH_DG_TMRn pin is asserted (low). If Sys.Timer2.RstInCPU == 1,
the ARM gets a reset. The Sys.*CPUInt.Timer2 interrupt indicates what happened to the ARM after it
comes out of reset.
The system decides to perform a device reset and reload program code according to system conditions.
At phase (d), the ARM (or Ex-CPU) has set Sys.Timer2.Enable == 1. The WTCH_DG_TMRn signal is
deasserted (goes high).
Note: WTCH_DG_TMRn function is independent of Sys.InCPUCfg.Reset function. If the ARM is placed
in reset by setting Sys.InCPUCfg.Reset = 1, WTCH_DG_TMRn is still active as long as
Sys.Timer2.Enable = 1.
1.11 High Speed Data Interface
1.11.1 Overview/Description
The high speed data interface (HSDI) is used for transmitting and receiving high-speed video data. The
HSDI is connected to the isochronous buffers. HSDI0 is connected to ISO FIFO 0 and HSDI1 is
connected to ISO FIFO 1. The HSDI ports can be configured as transmit or receive. A single port cannot
transmit and receive at the same time. The buffer direction, HSDI mode, and stream type are all set by
CFR. See Table 16 for a description of the HSDI signals.
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Table 16. HSDI Signals
Signal
Polarity
Tx
Rx
Description
Direction Direction
HSDI*_CLK
Programmable
Defaults to
Input
Input
All activity on HSDI uses this clock.
The clock must be always provided by an external
codec in read and write mode except for TX
mode 3. In TX mode 3, the clock is only available
during data transmit.
rising edge
HSDI*_EN
Programmable
Defaults to
active low
Input
Input
Input
Enables the HSDI interface. This signal must be
enabled all the time by tying it low or high for
modes that do not provide an enable signal.
HSDI*_SYNC
(See Note1)
Programmable
Output
HSDI*_SYNC indicates the start of the packet.
The rising edge (or falling edge, depending on
polarity setting) of this signal indicates first byte of
data. An internal packet counternote2 keeps track
of the packet end. For TX operations of all data
types, the packet counter must be programmed by
software in HSDI*Cfg.TxDatBlkSz. On TX
operation, the width of the HSDI*_SYNC pulse
can vary. On RX operation, HSDI*_SYNC is an
output from iceLynx-Micro. It is the width of one
HSDI*_CLK cycle.
Defaults to
active high
For DVB TX, if the application chooses to use the
modes that do not provide the HSDI*_Sync signal,
the frame sync detection circuitry must be enabled
by setting HSDI*Cfg.FrmSyncDetEn = 1.
HSDI*_AV
Programmable
Defaults to
active low
Output
for HSDI
TX
Output
Indicates data is available in FIFO for reading. For
MPEG2 RX, data is available once SPH=cycle
timer (timestamp). For DV, data is available once
the entire 480-byte cell has been received into the
FIFO.
For HSDI TX modes 8 and 9, it indicates the
number of quadlets in the TX ISO buffer is over
the programmed limit. The limit is programmed at
CFR.
modes 8
and 9
(DV)
HSDI*_Data
Input
Input
Output
Output
Byte wide data bus. HSDI*_D7 is MSB.
For serial mode, only HSDI*_D0 is used.
For transmit, this signal is input and indicates data
is valid and is written to TX ISO buffer. For
receive, this signal is output and indicates data is
valid on HSDI.
HSDI*_DVALID Programmable
HSDI*_FrameS
ync
Defaults to
active high
On RX operation, this signal is not deasserted for
back to back packets.
In DV I/F mode (HSDI TX mode 9, RX mode 4),
HSDI*_DVALID is used as HSDI*_FrameSync.
Notes:
1) HSDI*SYNC
Data on HSDI is ignored until the HSDI*_SYNC signal is detected. In frame sync detection mode,
data is ignored until the SyncLock event occurs.
The SyncLock event is signaled by an interrupt in CFR-Iso*CPUInt.SyncLock when the
HSDI*_Sync signal is activated as programmed in CFR–or in frame sync detection mode when
the MPEG2-DVB synchronization byte 0x47 are detected 188 bytes apart.
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The Iso*TxCfg.SyncLock status bit is also asserted. The Iso*TxCfg.SyncLock status bit stays
asserted until a Sync violation event occurs. If a sync violation occurs (such as a synchronization
byte occurs too soon or too late), the Iso*InCPUInt.SyncUnlock interrupt occurs and the current
packet is flushed.
2) Packet Counter
Once the HSDI*_SYNC edge or SyncLock event is detected, the counter starts. The packet is
written into the FIFO once the counter value is reached. Data on the HSDI is ignored until the
next HSDI*_SYNC or SyncLock event when the frame sync detection circuitry is enabled. If
another HSDI*_SYNC occurs before the end of the counter, the packet is aborted. More details
on the frame sync detection circuit provided in Section 1.12.2. Table 17 shows the counter values
to be programmed for the applications shown below:
Table 17. Application Counter Values
Application
MPEG2-DVB
MPEG2-DSS-130
MPEG2-DSS-140
DV-SD
Counter Value
188 bytes
130 bytes
140 bytes
480 bytes
1.11.2 Frame Sync Detection Circuit
The iceLynx-Micro supports the frame sync detection feature for MPEG2-DVB applications that do not
provide a sync signal (=byte start) to the HSDI. It is enabled in CFR using HSDI*Cfg.FrmSyncDetEn. The
frame detection circuit looks for the MPEG2-DVB transport stream synchronization byte, (0x47). The
iceLynx-Micro detects synchronization bytes that are 188 bytes apart and signal a SyncLock event. The
number of sync bytes detected for a lock condition is programmable in HSDICfg.SyncLockDetNum (the
range is 2-7).
For example, if HSDICfg.SyncLockDetNum is set to 2, the iceLynx-Micro searches for two
synchronization bytes 188 bytes apart. The second synchronization byte must be marked as start of
packet and assert the Iso*CPUInt.SyncLock Interrupt. The first packet is confirmed into the TX FIFO when
the second synchronization byte is detected. Otherwise, the first packet is flushed from the FIFO. After
the last byte is input to HSDI (188th byte), the iceLynx-Micro does not capture any packet data until the
next MPEG2 transport stream synchronization byte.
Note: The frame sync detection circuit can only be used for MPEG2-DVB (188-byte) data.
1.11.3 HSDI Pass-Through Function
This function is enable/disabled by a CFR setting (HSDI*Cfg.PassThru). Both the HSDI0 and HSDI1 ports
support the data pass-through function in accordance with the following conditions:
The MPEG2-TS data for HSDI TX modes 1-7.
The pass through direction is input to HSDI0 and output HSDI1.
1.In this case, HSDI*Cfg.PassThru and Iso*Cfg.Enable must both be set. The DVD MPEG2-TS
data is transmitted to 1394 as well as passed through to HSDI1. The audio interface, which uses
ISO PATH1 (data buffer 1), can also be used at the same time.
2. The direction is only HSDI0->HSDI1 available.
3. When the data pass through function is enabled, the signals shown in Table 18 are handled.
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Table 18. HSDI Pass-Through Function
HSDI0 -> HSDI1
Signal Name of HSDI0
Data CLK
SYNC
Data valid
I/O
Direction
Signal Name of HSDI1
Data CLK
SYNC
I/O
O
O
I
I
I
->
->
->
Data Valid
O
IEEE 1394 Serial Bus
Internal Circuit
MUX
CFR
HSDI_0
HSDI_1
TransPort
FrontEnd
LSI
BackEnd
LSI
Decrypt
Demux
Data
I
->
Data
O
Figure 21. Example for Data Pass-Through Function
1.11.4 HSDI Maximum Clock Rates and Throughput
See Table 19 for the maximum clock rates and throughput on the HSDI interface.
Table 19. HSDI Maximum Clock Rates and Throughput
HSDI Format
Serial
Maximum Clock Rate
70 MHz
Maximum Throughput
8.75 Mbytes/sec
Parallel
27 MHz
27 Mbytes/sec
1.11.5 HSDI Mode Settings
The HSDI modes, for both transmit and receive, are set by CFR bits (HSDI*Cfg.Mode) as shown below.
See Table 20 for general mode settings.
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Table 20. General HSDI Mode Settings
Mode Setting At
HSDI*Cfg.Mode
Description
Video Modes
0000b
Serial video burst I/F (MPEG2, DSS)
0001b
Serial video burst I/F (MPEG2, DSS) clock active only when data is valid
0010b
0011b
Parallel fideo burst I/F (MPEG2, DSS)
MPEG2 I/F mode
0100b
DV I/F mode
Audio Modes
0101b
60958 interface
For HSDI0, uses HSDI0_AMCLK_IN and HSDI0_60958_IN signals. For transmit only.
For HSDI1, uses HSDI1_AMCLK_IN and HSDI1_60958_IN for transmit. Uses
HSDI1_AMCLK_OUT and HSDI1_60958_OUT for receive.
0110b
0111b
60958 data with MLPCM Interface
For HSDI0, uses DVD-Audio-In pins muxed on HSDI0 interface (D0 only). For transmit
only.
For HSDI1, uses DVD-Audio I/F for receive only, defined as:
MLPCM_BCLK
MLPCM_LRCLK
MLPCM_D0
MLPCM I/F
For HSDI0, uses DVD-Audio-In pins muxed on HSDI0 interface. For transmit only.
For HSDI1, uses DVD-Audio I/F for transmit and receive defined as:
MLPCM_BCLK
MLPCM_LRCLK
MLPCM_D0-D2
MLPCM_A
1000b
SACD I/F
For HSDI0, there is no SACD I/F.
For HSDI1, uses SACD-IN and SACD-OUT signal multiplexed on HSDI1 signals.
For flow control mode, uses DVD-Audio I/F signals.
Other bits also determine the HSDI operations. Table 21 summarizes all HSDI video modes available in
the iceLynx-micro.
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Table 21. HSDI Video Modes
Corresponding
Transmit Modes
(see Timing
Corresponding
Receive Modes
(see Timing
HSDI*Cf
HSDI*.FrmSyn
g.Mode
HSDI*.Valid
En Setting
Description
cDetEn Setting
Setting
Diagrams in
Diagrams in
Section 1.12.6)
Section 1.12.7)
0000
0000
0
1
0
0
TX mode 1
None
Serial video burst I/F
(MPEG2, DSS)
Serial video burst I/F
(MPEG2, DSS) with frame
sync detect circuit
TX mode 2
None
0000
0001
0
1
1
0
TX mode 4
TX mode 3
RX mode 1
--none**--
Serial video burst I/F
(MPEG2, DSS) with data
valid signal
Serial video burst I/F
(MPEG2-DVB) clock active
only when data is valid
0010
0010
0
1
0
1
TX mode 5
TX mode 6
None
None
Parallel video burst I/F
(MPEG2, DSS)
Parallel video burst I/F
(MPEG2-DVB) with frame
sync detect circuit
0010
0
1
0
TX mode 7
RX mode 2
Parallel video burst I/F
(MPEG2, DSS) with data
valid signal
MPEG2 I/F mode
DV I/F mode
0011
0100
0
0
TX mode 8
TX mode 9
RX mode 3
RX mode 4
NA
(see Note 1)
Note 1: DV I/F mode (TX mode 9, RX mode 4).
1.11.6 HSDI Transmit Modes
The following MPEG2-TS and DV write function timing diagrams are with the polarity of data CLK, sync,
data valid, HSDI*_FrameSync, enable, and available signals at their default setting.
1.11.6.1 TX Mode 1: Serial Burst I/F (MPEG2)
HSDI*_CLK(i)
HSDI*_SYNC(i)
HSDI*_D0(i)
Packet N
Packet N+1
Notes:
1. HSDI*_EN must be pulled low for this mode (HSDI*_EN defaults to active low).
2. HSDI*_DVALID is a don’t care for this mode. It is pulled low.
Figure 22. MPEG2 Serial Burst I/F (TX Mode 1)
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1.11.6.2 TX Mode 2: Serial Video Burst I/F (MPEG2) With Frame Sync Detect Circuit
HSDI*_CLK(i)
HSDI*_D0(i)
Packet N
Packet N+1
Packet N+2
Notes:
1. HSDI*_EN must be pulled low for this mode (HSDI*_EN defaults to active low).
2. HSDI*_DVALID is a don’t care for this mode. It is pulled low.
Figure 23. MPEG2 Serial Video Burst I/F With Frame Sync Detect Circuit (TX Mode 2)
1.11.6.3 TX Mode 3: Serial Video Burst I/F (MPEG2) Clock Active Only When Data Is Valid
HSDI*_CLK(i)
Min 240ns between pkts
HSDI*_D0(i)
Packet N
Packet N+1
Notes:
1. HSDI*_EN must be pulled low for this mode (HSDI*_EN defaults to active low) and stay active
at all times. HSDI*_EN must not be toggled.
2. HSDI*_DVAILD is a don’t care for this mode. It is pulled low.
3. Frame sync detect circuit is used.
Figure 24. MPEG2 Serial Video Burst I/F Clock Active Only When Data Is Valid (TX Mode 3)
1.11.6.4 TX Mode 4: Serial Video Burst I/F (MPEG2) With Data Valid
HSDI*_CLK(i)
HSDI*_SYNC(i)
HSDI*_DVALID(i)
HSDI*_D0(i)
Pkt N
Pkt N
Pkt N+1
Note: HSDI*_EN must be pulled low for this mode (HSDI*_EN defaults to active low).
Figure 25. MPEG2 Serial Video Burst I/F With Data Valid (TX Mode 4)
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1.11.6.5 TX Mode 5: Parallel Burst Video I/F (MPEG2)
HSDI*_CLK(i)
HSDI*_SYNC(i)
HSDI*_D[7:0](i)
Packet N
Packet N+1
Notes:
1. HSDI*_EN must be pulled low for this mode (HSDI*_EN defaults to active low).
2. HSDI*_DVALID is a don’t care for this mode. It is pulled low.
Figure 26. MPEG2 Parallel Burst Video I/F (TX Mode 5)
1.11.6.6 TX Mode 6: Parallel Video Burst I/F (MPEG2) With Frame Sync Detect Circuit
HSDI*_CLK(i)
HSDI*_DVALID(i)
HSDI*_D[7:0](i)
Pkt N
Pkt N
Pkt N+1
Note: HSDI*_EN must be pulled low for this mode (HSDI*_EN defaults to active low).
Figure 27. MEPG2 Parallel Video Burst I/F With Frame Sync Detect Circuit (TX Mode 6)
1.11.6.7 TX Mode 7: Parallel Video Burst I/F (MPEG2) With Data Valid
HSDI*_CLK(i)
HSDI*_SYNC(i)
HSDI*_DVALID(i)
HSDI*_D[7:0](i)
Pkt N
Pkt N
Pkt N+1
Note: HSDI*_EN must be pulled low for this mode (HSDI*_EN defaults to active low).
Figure 28. MPEG2 Parallel Video Burst I/F With Data Valid (TX Mode 7)
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1.11.6.8 TX Mode 8: MPEG2 I/F Mode
HSDI*_CLK(i)
HSDI*_EN(i)
HSDI*_SYNC(i)
HSDI*_D[7:0](i)
Pkt N
Hold
Pkt N
Pkt N+1
HSDI*_AV(o)
Note:
1. HSDI*_DVALID is a don’t care for this mode. It is pulled low.
2. HSDI*_AV is an output in this mode. It indicates if the number of quadlets in the ISO transmit
buffer is over a programmed limit. The watermark control must be programmed for the
watermark high. If Iso*WtrMrk.HSDIAvailEn is set to 1, the limit is programmed in
Iso*WtrMrk.Level0. The watermark must be programmed less than BUFFER SIZE – (packet
length + packet header).
Figure 29. MPEG2 I/F (TX Mode 8)
1.11.6.9 TX Mode 9: DV I/F Mode
HSDI*_CLK(i)
HSDI*_EN(i)
HSDI*_SYNC(i)
HSDI*_D[7:0](i)
HSDI*_AV(o)
Pkt N
Hold
Pkt N
Pkt N+1
HSDI*_FrameSync(i)
Notes:
1. The HSDI*_FrameSync signal and SYT circuit are independent of the HSDI*Data [7:0].
2. HSDI*_FrameSync is multiplexed with HSDI*_DVALID. HSDI*_AV is an output in this mode. It
indicates if the number of quadlets in the transmit buffer is over a programmed limit. The
watermark control must be programmed for the watermark high. If Iso*WtrMrk.HSDIAvailEn is
set to 1, the limit is programmed in Iso*WtrMrk.Level0. The watermark must be programmed
less than BUFFER SIZE – (packet length + packet header).
Figure 30. DV I/F (TX Mode 9)
1.11.7 HSDI Receive Modes
The following MPEG2-TS and DV read function timing diagrams are with the polarity of data CLK, sync,
data valid, HSDI*_FrameSync, enable, and available signals are default setting.
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1.11.7.1 RX Mode 1: Serial Burst Video I/F (MPEG2)
HSDI*_CLK(i)
HSDI*_SYNC(o)
HSDI*_DVALID(o)
HSDI*_D0(o)
Packet N
Packet N+1
Note: HSDI*_EN must be pulled low for this mode (HSDI*_EN defaults to active low).
Figure 31. MPEG2 Serial Burst Video I/F (RX Mode 1)
1.11.7.2 RX Mode 2: Parallel Burst Video I/F (MPEG2)
HSDI*_CLK(i)
HSDI*_SYNC(o)
HSDI*_DVALID(o)
HSDI*_D[7:0](o)
Packet N
Packet N+1
Note: HSDI*_EN must be pulled low for this mode (HSDI*_EN defaults to active low).
Figure 32. MPEG2 Parallel Burst Video I/F (RX Mode 2)
1.11.7.3 RX Mode 3: Parallel Burst Video I/F (MPEG2) Mode
HSDI*_CLK(i)
HSDI*_EN(i)
HSDI*_AV(o)
HSDI*_SYNC(o)
HSDI*_D[7:0](o)
Hold
Pkt N
Pkt N+1
Hold
Pkt N+1
Figure 33. MPEG2 Parallel Burst Video I/F (RX Mode 3)
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1.11.7.4 RX Mode 4: Parallel Burst Video I/F (DV) Mode
HSDI*_CLK(i)
HSDI*_EN(i)
HSDI*_AV(o)
HSDI*_SYNC(o)
HSDI*_D[7:0](o)
Hold
Pkt N
Pkt N+1
Hold
Pkt N+
HSDI*_FrameSync(o)
Notes:
1. The HSDI*_FrameSync signal and the SYT circuit are independent of the HSDI*_D [7:0].
2. HSDI*_FrameSync is multiplexed with HSDI*_DVALID.
Figure 34. DV Parallel Burst Video I/F (RX Mode 4)
1.11.7.5 HSDI A/C Timing
1.11.7.5.1 Transmit HSDI AC Timing
T1
HSDI*_CLK
T3
T2
Input Signals*
T4
HSDI*_AV
Figure 35. Transmit HSDI AC Timing
Input signals include the following: HSDI*_SYNC, HSDI*_DVALID, HSDI*_D [7:0], HSDI*_EN, and
HSDI*_FrameSync.
Table 22. AC Timing Parameters for Serial I/F (Modes 1 and 4)
Description
Data CLK period
Signals setup to rising edge of data CLK
Signals hold to rising edge of data CLK
Min
14.3
2.2
0
Max Units
T1
T2
T3
ns
ns
ns
Table 23. AC Timing Parameters for Serial I/F (Modes 2 and 3)
Description
Data CLK period
Signals setup to rising edge of data CLK
Signals hold to rising edge of data CLK
Min
12.5
2.2
0
Max Units
T1
T2
T3
ns
ns
ns
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Table 24. AC Timing Parameters for Parallel I/F (Modes 5, 6, and 7)
Description
T1 Data CLK period
T2 Signals setup to rising edge of data CLK
T3 Signals hold to rising edge of data CLK
Min
37
11
0
Max Units
ns
ns
ns
Table 25. AC Timing Parameters for Parallel I/F (Modes 8 and 9)
Description
Data CLK period
Signals setup to rising edge of data CLK
Signals hold to rising edge of data CLK
Signals delay from rising edge of data CLK
Min
37
15
0
Max Units
T1
T2
T3
T4
ns
ns
ns
7
ns
Note: Measurements based on a 20-pF loading.
1.11.7.5.2 Receive HSDI AC Timing
T3
T2
T1
HSDI*_CLK
Output Signals*
HSDI*_EN
T6
T4
T5
Figure 36. Receive HSDI AC Timing
Output signals include the following: HSDI*_SYNC, HSDI*_DVALID, HSDI*_D[7:0], HSDI*_AV, and
HSDI*_FrameSync.
Table 26. AC Timing Parameters for Serial I/F (Mode 1)
Description
Data CLK period
CLK low width
Min
14.3
4
4
2.2
0
Max Units
T1
T2
T3
T4
T5
T6
ns
ns
ns
ns
ns
CLK high width
Signals setup to rising edge of data CLK
Signals hold to rising edge of data CLK
Signals delay from rising edge of data CLK
7
ns
Table 27. AC Timing Parameters for Parallel I/F (Mode 2)
Description
Data CLK period
CLK low width
Min
37
14
14
2.4
0
Max Units
T1
T2
T3
T4
T5
T6
ns
ns
ns
ns
ns
CLK high width
Signals setup to rising edge of data CLK
Signals hold to rising edge of data CLK
Signals delay from rising edge of data CLK
7
ns
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Table 28. AC Timing Parameters for Parallel I/F (Modes 3 and 4)
Description
Data CLK period
CLK low width
Min
37
15
0
2.4
0
Max Units
T1
T2
T3
T4
T5
T6
ns
ns
ns
ns
ns
CLK high width
Signals setup to rising edge of data CLK
Signals hold to rising edge of data CLK
Signals delay from rising edge of data CLK
2.4
25
ns
Note: Measurements are based on a 20-pF loading.
1.11.8 Audio Interface on HSDI
1.11.8.1 HSDI0
On HSDI0, only DVD-Audio (MBLA) transmit and 60958 transmit are supported. DVD-Audio (MBLA) and
60958 data cannot be transmitted at the same time. Both interfaces share the same data buffer. The
hardware selects the interface based on Iso*Cfg.DataType. For DVD-Audio transmit, the DVD-Audio
signals are muxed onto the HSDI pins as follows:
Table 29. HSDI0 DVD Audio Signals
DVD-Audio Signal
Muxed HSDI Pin
HSDI0_CLKz
HSDI0_ENz
HSDI0_D0
BCLK
LRCLK
D0
D1
HSDI0_D1
D2
HSDI0_D2
Ancillary
HSDI0_D3
For 60958 data, the HSDI0_AMCLK_IN and HSDI0_60958_IN pins are used.
1.11.8.2 HSDI1
On HSDI1, 60958, SACD, and DVD-Audio (MBLA) are all supported for transmit or receive. The DVD-
Audio (MBLA) has dedicated pins, which are not muxed with HSDI pins. However, the DVD-Audio
(MBLA) pins and HSDI pins cannot be used at the same time. They access the same data buffer. The
hardware selects the interface based on Iso*Cfg.DataType. DVD-Audio (MBLA) dedicated pins are also
used for DVD-Audio (MBLA) flow control mode. HSDI1 signal descriptions are given in Table 30.
Table 30. HSDI1 DVD-Audio Signals
Audio Signal
SACD
MCLK
FRAME
D0
Direction
Hardware Pin
Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
HSDI1_CLKz
HSDI1_SYNCz
HSDI1_D0
HSDI1_D1
HSDI1_D2
HSDI1_D3
HSDI1_D4
D1
D2
D3
D4
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Audio Signal
Direction
Tx/Rx
Hardware Pin
HSDI1_D5
D5
D6
Tx/Rx
HSDI1_D6
60958
CLK
DATA
CLK
DATA
Tx
Tx
Rx
Rx
HSDI1_AMCLK_IN
HSDI1_60958_IN
HSDI1_AMCLK_OUT
HSDI1_60958_OUT
DVD-AUDIO (MBLA)
BCLK
LRCLK
D0
D1
D2
Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
MLPCM_BCLK
MLPCM_LRCLK
MLPCM_D0
MLPCM_D1
MLPCM_D2
MLPCM_A
Ancillary
1.11.8.3 IEC60958 I/F AC Timing Characteristic
1.11.8.3.1 AC Timing Characteristic on Receiving
The CeLynx_Micro must follow sections 5.3.4.2 and 5.3.4.3 of EIAJ (Electronic Industries Association of
Japan) CP-1201 Digital Audio Interface standard.
Extracts from EIAJ CP-1201
[5.3.4.2 rise and fall time rates]
Rise and fall time rates are specified by the following equations.
100×T r
( )
rise _ time _ rate =
fall _ time _ rate =
(%)
(%)
T
(
l
)
+ T
100×T
+ T
(
h
)
)
f
T
(
l
)
h
( )
Rise and fall time rates must be less than the following ranges.
When the data bit is 1: 0% ~ 20%.
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When the data bit is 0 continuously for two times: 0% ~ 10%
T(h)
T(l)
90%
50%
10%
T(r)
T(f)
[5.3.4.3 duty cycle rate]
Duty cycle rate are specified by following equation.
100×T h
( )
( ) ( )
T l + T h
duty _ cycle _ rate =
(%)
Duty cycle rate must be less than following ranges.
When the data bit is logically 1: 40% ~ 60%
When the data bit is logically 0 continuously for 2 times: 45% ~ 55%
1.11.8.3.2 AC Timing Characteristic on Transmitting
T1
HSDI*_AMCLK_IN
T2
T3
HSDI*_60958_IN
Figure 37. Example 1 Sampling Frequency (fs): 192 kHz, Master Clock Frequency: 256fs
T1
HSDI*_AMCLK_IN
T2
T3
HSDI*_60958_IN
Figure 38. Example 2 Sample Frequency (fs): 48 kHz, Master Clock Frequency: 768fs
Table 31. AC Timing Parameters
Symbol
T1
Description
Data CLK period
Signals setup to rising edge of data CLK
Signals hold to rising edge of data CLK
Min
27
5
Max Units
ns
ns
ns
T2
T3
5
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1.11.8.3.3 MLPCM I/F AC Timing Characteristic
T2
T3
T1
BCLK*
T4
Data**
T5
LRCLK***
Notes:
*
BCLK includes the following: MLPCM_BCLK and FLWCTL_BCLK.
** Data includes the following: MLPCM_D[2:0], MLPCM_A, FLWCTL_D[2:0], and FLWCTL_A.
*** LRCLK includes the following: MLPCM_LRCLK and FLWCTL_LRCLK.
Figure 39. AC Timing Characteristic on Receiving
Table 32. AC Timing Parameters
Description
Data CLK period
CLK low width
CLK high width
Signals delay to data CLK
Signals delay to data CLK
Min
50
20
Max Units
T1
T2
T3
T4
T5
ns
ns
ns
20
10
10
ns
ns
T2
T1
T3
T5
BCLK*
Data**
T4
T6
t7
LRCLK***
Notes:
*
BCLK includes the following: HSDI0_MLPCM_BCLK and MLPCM_BCLK.
** Data includes the following: HSDI0_MLPCM_D[2:0], HSDI0_MLPCM_A, MLPCM_D[2:0], and
MLPCM_A.
*** LRCLK includes the following: HSDI0_MLPCM_LRCLK and MLPCM_LRCLK.
Figure 40. AC Timing Characteristic on Transmitting
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Table 33. AC Timing Parameters
Description
Data CLK period
CLK low width
Min
75
35
35
8
Max Units
T1
T2
T3
T4
T5
T6r
T7
ns
ns
ns
ns
ns
ns
ns
CLK high width
Signals setup to data CLK
Signals hold to data CLK
Signals setup to data CLK
Signals hold to data CLK
8
8
8
1.12 UART Interface
The iceLynx-Micro includes one UART port that is memory mapped and fully accessible from the internal
CPU. The output of the UART requires level shifting for RS-232 compliance. This UART
transmits/receives one start bit, 7 or 8 data bits, optional parity, and 1 or 2 stop bits.
The UART errors are indicated in the iceLynx-Micro interrupts shown in Table 34.
1.12.1 UART Registers
Software uses the iceLynx-Micro UART CFR (0x070) to access UART registers. The UART CFR contains
address offset, data, and read/write control bits. The UART address offsets are described in Table 34.
Table 34. UART CFR Address Offsets
DLAB
0
A2
0
A1
0
A0
0
Name
Register
RBR/THR Receiver buffer register (read) or transmitter holding register (write)
0
0
0
0
0
1
1
1
1
0
1
1
1
0
0
1
1
1
0
0
1
0
1
0
1
IER
IIR
Interrupt enable register
Interrupt ID register (read only)
FIFO control register (write)
Link control register
Modem control register
Link status register
Modem status register
Scratch register
Divisor latch (LSB)
X
X
X
X
X
X
X
1
FCR
LCR
MCR
LSR
MSR
SCR
DLL
DLH
0
0
0
0
0
1
1
Divisor latch (MSB)
Note: Only A2-A0 address bits are implemented in the UART register. The DLAB bit is set in the LCR register. If
DLAB is set to 0, reads/writes to addresses 000b and 001b access the RBR/THR and IER registers. If DLAB is set
to 1, reads/writes to addresses 000b and 001b access the DLL and DLH registers.
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Table 35. UART Registers
Register
Address
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
RBR
000
Data bit 0
Data bit 1
Data bit 2
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
(RX only)
DLAB=0
THR
000
Data bit 0
Data bit 1
Data bit 2
Data bit 3
Data bit 4
0
Data bit 5
0
Data bit 6
0
Data bit 7
0
(TX only)
DLAB=0
IER
001
Enable
receiver
data
Enable
Enable
receiver
line status
Int
Enable
DLAB=0
transmitter
holding
Modem
status Int
available
int
register
empty Int
IIR
010
010
0 if int
Int ID bit 1
Int ID bit 2
Int ID bit 3
0
0
FIFOs
FIFOs
(read only)
pending
enabled
enabled
FCR
(write
only)
FIFO
RX FIFO
reset
TX FIFO
reset
DMA
RSVD
RSVD
Receiver
trigger
(LSB)
Receiver
enable
mode
select
trigger
(MSB)
LCR
011
Word
Word length Number of
Parity
Even
parity
select
Stick
Break
Divisor
length
select bit 1
stop bits
enable
parity
control
latch
select bit 0
access bit
(DLAB)
MCR
LSR
100
101
110
111
Data
Request to
send
OUT1
OUT2
Loop
Autoflow
control
enable
RSVD
RSVD
terminal
ready
Data
Overrun
error
Parity
error
Framing
error
Break int
Transmitte Transmitte Error in
ready
r holding
r empty
RCVR
register
FIFO
MSR
Data clear
to send
Delta set
ready
Trailing
Delta
Clear to
send
Data set
ready
Ring
Carrier
detect
edge ring
indicator
carrier
detect
indicator
SCR
DLL
Bit 0
Bit 0
Bit 1
Bit 1
Bit 2
Bit 2
Bit 3
Bit 3
Bit 4
Bit 4
Bit 5
Bit 5
Bit 6
Bit 6
Bit 7
Bit 7
000
DLAB=1
DLH
001
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
DLAB=1
1.12.2 UART Baud Rate
Example: To set the UART baud speed, Equation 1 must be used to determine the divisor value. The
divisor value is written into the UART registers to set the baud rate.
Baud rate = 50 MHz/ (16 x divisor value)
Equation 1
Write 0x0000 43X1 to UART0 register. This tells the iceLynx-Micro to write a value of X1 to the UART
address offset 3 (LCR register). The value X1 sets the DLAB bit to 1.
Write 0x0000 40XX to UART0 register. This tells the iceLynx-Micro to write a value of XX to the UART
DLL register. This is the divisor latch LSB.
Write 0x0000 41XX to UART0 register. This tells the iceLynx-Micro to write a value of XX to the UART
DLH register. This is the divisor latch MSB.
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1.13 JTAG – Boundary Scan and ARM
The iceLynx-Micro implements IEEE 1149.1 JTAG for boundary scan (iceLynx-Micro and ARM core) and
ARM debug. Control signals include:
JTAG_TMS – Test mode select for JTAG boundary scan
JTAG_TDI – Test data input for JTAG boundary scan
JTAG_TDO - Test data output for JTAG boundary scan
ARM_JTAG_TMS – Test mode select for ARM
ARM_JTAG_TDI – Test data input for ARM
ARM_JTAG_TDO – Test data output for ARM
JTAG_TCK – Test clock - Common pin for boundary scan and ARM
JTAG_TRSTn – Test reset (active low) common pin for boundary scan and ARM.
A JTAG boundary scan is always available.
To disable JTAG, the JTAG_TRSTn signal must be held high.
The JTAG_TCK can operate up to 10.358 MHz; the frequency used by the TI-ARM JTAG emulation tools.
The ARM JTAG can only be enabled by the ARM. A small program must be loaded into program memory
that enables the ARM JTAG (InCPUCfg.DebugEn).
1.14 Integrated 3-Port PHY
1.14.1 3-Port PHY
The iceLynx-Micro contains an integrated 3-port PHY. The PHY operates at 100 Mbps, 200 Mbps, or
400 Mbps and meets the requirements as stated in the IEEE 1394-1995 and IEEE 1394a-2000
standards. For applications that only need two PHY ports, the TPB± signals are terminated to ground on
the board, or the PHY port is disabled through a CFR. When this occurs, the PHY still reports itself as a
3-port node in self-ID packets.
The PHY core contains a CFR bit that controls the BIAS function. This bias function can either operate
using the IEEE 1394-1995 method of bias or the IEEE 1394a-2000 method of bias. The IEEE 1394-1995
method always asserts a continuous bias. The IEEE 1394a-2000 method asserts bias for 980 ms.
The PHY can be set to operate at S100 and S200 nodes only. If the MSPCTL hardware pin is asserted to
a high state, the maximum transaction speed is S200. Also PHY maximum node speed is recognized as
S200. If MSPCTL is zero (i.e., pulled to ground), the PHY supports S100, S200, and S400.
The PHY registers are accessed through the PhyAccess configuration register as described in Table 36.
Table 36. PHY Access Register
31
30
29 28
27 24
23 16
15 12
11
8
7
0
RdReg WrReg
RSVD
PhyRegAddr
PhyRegWrData RSVD PhyRegAddrRcvd
PhyRegDatRcvd
1.14.2 PHY Registers
In the iceLynx-Micro are 16 accessible internal PHY registers. They are accessed using the PHY access
register. The address offset specifies the location. The configuration of the registers at addresses 0
through 7 (the base registers) is fixed, while the configuration of the registers at addresses 8 through Fh
(the paged registers) is dependent upon which one of eight pages, numbered 0 through 7, is currently
selected. The selected page is set in base register 7.
The configuration of the base registers is shown in Table 37 and the corresponding field descriptions are
given in Table 38. The base register field definitions are unaffected by the selected page number.
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A reserved register or register field (marked as Reserved or Rsvd in the register configuration tables
below) is read as 0, but is subject to future usage. All registers in pages 2 through 6 are reserved.
Table 37. Base Register Configuration
Bit Position
Address
0
1
2
3
4
5
6
7
0000
0001
0010
0011
0100
0101
0110
0111
Physical ID
R
CPS
RHB
IBR
Extended (‘b111)
PHY_Speed (‘b010)
C
Gap_Count
Rsvd
Rsvd
Num_Ports (‘b0011)
Delay (‘b0000)
Pwr_Class
LCtrl
WDIE
Jitter (‘b000)
CPSI
ISBR
CTOI
STOI
PEI
EAA
EMC
Reserved
Rsvd
Page_Select
Port_Select
Table 38. Base Register Field Descriptions
FIELD
SIZE
TYPE
DESCRIPTION
Physical ID
6
Rd
This field contains the physical address ID of this node determined during self-ID. The
physical-ID is invalid after a bus-reset until self-ID has completed as indicated by an
unsolicited register-0 status transfer.
R
1
1
Rd
Rd
Root. This bit indicates that this node is the root node. The R bit is reset to 0 by bus-
reset, and is set to 1 during tree-ID if this node becomes root.
CPS
Cable-power-status. This bit indicates the state of the CPS input pin. The CPS pin is
normally pulled to serial bus cable power through a 400-kΩ resistor. A 0 in this bit
indicates that the cable power voltage has dropped below its threshold for guaranteed
reliable operation.
RHB
IBR
1
1
Rd/Wr
Rd/Wr
Root-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus-
reset. The RHB bit is reset to 0 by hardware reset and is unaffected by bus-reset.
Initiate bus-reset. This bit instructs the PHY to initiate a long (166 µs) bus reset at the
next opportunity. Any receive or transmit operation in progress when this bit is set
completes before the bus reset is initiated. The IBR bit is reset to 0 by hardware reset or
bus reset.
Gap_Count
6
Rd/Wr
Arbitration gap count. This value sets the subaction (fair) gap, arb-reset gap, and arb-
delay times. The gap count is set either by a write to this register or by reception or
transmission of a PHY_CONFIG packet. The gap count is set to 3Fh by hardware reset
or after two consecutive bus-resets without an intervening write to the gap count register
(either by a write to the PHY register or by a PHY_CONFIG packet).
Extended
Num_Ports
PHY_Speed
Delay
3
4
3
4
Rd
Rd
Rd
Rd
Extended register definition. For iceLynx-Micro this field is ‘b111, indicating that the
extended register set is implemented.
Number of ports. This field indicates the number of ports implemented in the PHY. For
iceLynx-Micro this field is three.
PHY speed capability. For iceLynx-Micro PHY this field is ‘b010, indicating S400 speed
capability. The setting of this field also depends on the MSPCTL setting.
PHY repeater data delay. This field indicates the worst-case repeater data delay of the
PHY, expressed as 144+(delay*20) ns. This field is 0 (default.)
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FIELD
LCtrl
SIZE
1
TYPE
Rd/Wr
DESCRIPTION
Link-active status control. This bit controls the active status of the LLC as indicated
during self-ID. The logical AND of this bit and the LPS active status is replicated in the L
field (bit 9) of the self-ID packet. The LLC is considered active only if both the LPS input
is active and the LCtrl bit is set.
The LCtrl bit provides software controllable means to indicate the LLC active status in
lieu of using the LPS input.
The LCtrl bit is set to 1 by hardware reset and is unaffected by bus reset.
Note: The state of the PHY-LLC interface is controlled solely by the LPS input,
regardless of the state of the LCtrl bit. If the PHY-LLC interface is operational as
determined by the LPS input being active, then received packets and status information
continues to be presented on the interface, and any requests indicated on the LREQ
input is processed, even if the LCtrl bit is cleared to 0.
C
1
Rd/Wr
Contender status. This bit indicates that this node is a contender for the bus or
isochronous resource manager. This bit is replicated in the c field (bit 20) of the self-ID
packet. This bit is set to the state specified by the C/LKON input pin upon hardware reset
and is unaffected by bus reset.
Jitter
3
3
Rd
PHY repeater jitter. This field indicates the worst-case difference between the fastest and
slowest repeater data delay, expressed as (JITTER+1)*20 ns. For iceLynx-Micro this field
is 0.
Pwr_Class
Rd/Wr
Node power class. This field indicates this node’s power consumption and source
characteristics, and is replicated in the pwr field (bits 21–23) of the self-ID packet. This
field is set to 000 default value at hardware reset and is unaffected by bus-reset.
Software can program this field to change the power class. Software must perform a bus
reset after setting this field.
WDIE
ISBR
1
1
Rd/Wr
Rd/Wr
Watchdog interrupt enable. This bit, if set to 1, enables the port event interrupt (PEI) bit to
be set whenever resume operations begin on any port. This bit also enables the C/LKON
output signal to be activated whenever the LLC is inactive and any of the CTOI, CPSI, or
STOI interrupt bits is set. This bit is reset to 0 by hardware reset and is unaffected by bus
reset.
Initiate short arbitrated bus-reset. This bit, if set to 1, instructs the PHY to initiate a short
(1.30 µs) arbitrated bus-reset at the next opportunity. This bit is reset to 0 by bus reset.
Note: Legacy IEEE Std 1394-1995 compliant PHYs may not be capable of performing
short bus-resets. Therefore, initiation of a short bus-reset in a network that contains such
a legacy device results in a long bus reset being performed.
CTOI
1
Rd/Wr
Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times
out during tree-ID start, and indicates that the bus is configured in a loop. This bit is reset
to 0 by hardware reset or by writing a 1 to this register bit.
If the CTOI and RPIE bits are both set and the LLC is or becomes inactive, the PHY
activates the C/LKON output to notify the LLC to service the interrupt.
Note: If the network is configured in a loop, only those nodes that are part of the loop
generate a configuration time-out interrupt. All other nodes instead, time-out waiting for
the tree-ID and/or self-ID process to complete and then generate a state time-out
interrupt and bus reset.
CPSI
STOI
1
1
Rd/Wr
Rd/Wr
Cable power status interrupt. This bit is set to 1 whenever the CPS input transitions from
high to low indicating that cable power is too low for reliable operation. This bit is reset to
1 by a hardware reset. It is cleared by writing a 1 to this register bit.
If the CPSI and RPIE bits are both set and the LLC is or becomes inactive, the PHY
activates the C/LKON output to notify the LLC to service the interrupt.
State time-out interrupt. This bit indicates that a state time-out has occurred (which also
causes a bus reset to occur). This bit is reset to 0 by hardware reset or by writing a 1 to
this register bit.
If the STOI and RPIE bits are both set and the LLC is or becomes inactive, the PHY
activates the C/LKON output to notify the LLC to service the interrupt.
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FIELD
SIZE
TYPE
DESCRIPTION
PEI
1
Rd/Wr
Port event interrupt. This bit is set to 1 upon a change in the bias (unless disabled),
connected, disabled, or fault bits for any port for which the port interrupt enable (PIE) bit
is set. Additionally, if the resuming port interrupt enable (RPIE) bit is set, the PEI bit is set
to 1 at the start of resume operations on any port. This bit is reset to 0 by hardware reset,
or by writing a 1 to this register bit.
If the PEI bit is set (regardless of the state of the RPEI bit) and the LLC is or becomes
inactive, the PHY activates the C/LKON output to notify the LLC to service the interrupt.
EAA
1
1
Rd/Wr
Rd/Wr
Enable accelerated arbitration. This bit enables the PHY to perform the various
arbitration acceleration enhancements defined in 1394a-2000 (ACK-accelerated
arbitration, asynchronous fly-by concatenation, and isochronous fly-by concatenation).
This bit is reset to 0 by hardware reset and is unaffected by bus reset.
Note: The EAA bit must be set only if the attached LLC is IEEE 1394a-2000 compliant. If
the LLC is not IEEE 1394a-2000 compliant, use of the arbitration acceleration
enhancements interferes with isochronous traffic by excessively delaying the
transmission of cycle-start packets.
Enable multi-speed concatenated packets. This bit enables the PHY to transmit
concatenated packets of differing speeds in accordance with the protocols defined in
IEEE 1394a-2000. This bit is reset to 0 by a hardware reset and is unaffected by bus-
reset.
EMC
Note: The use of multi-speed concatenation is completely compatible with networks
containing legacy IEEE Std 1394-1995 PHYs. However, use of multi-speed
concatenation requires that the attached LLC be 1394a-2000 compliant.
Page_Select
Port_Select
3
4
Rd/Wr
Rd/Wr
Page-select. This field selects the register page to use when accessing register
addresses 8 through 15. This field is reset to 0 by a hardware reset and is unaffected by
bus-reset.
Port-select. This field selects the port when accessing per-port status or control (e.g.,
when one of the port status/control registers is accessed in page 0). Ports are numbered
starting at 0. This field is reset to 0 by a hardware reset and is unaffected by bus-reset.
1.14.3 Port Status Page Register
The port status page provides access to configuration and status information for each of the ports. The
port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field
in base register 7. The configuration of the port status page registers is shown in Table 39 and
corresponding field descriptions given in Table 40. If the selected port is unimplemented, all registers in
the Port Status page are read as 0.
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Table 39. Page 0 (Port Status) Register Configuration
Bit Position
Address
0
1
2
3
4
5
6
7
1000
1001
1010
1011
1100
1101
1110
1111
Astat
Peer_Speed
Bstat
Ch
Fault
Con
Bias
Reserved
Dis
PIE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 40. Page 0 (Port Status) Register Field Descriptions
FIELD
AStat
SIZE
2
TYPE
Rd
DESCRIPTION
TPA line state. This field indicates the TPA line state of the selected port, encoded as follows:
Code
Line State
11
Z
01
1
0
10
00
invalid
Bstat
Ch
2
1
Rd
Rd
TPB line state. This field indicates the TPB line state of the selected port. This field has the
same encoding as the ASTAT field.
Child/parent status. A 1 indicates that the selected port is a child port. A 0 indicates that the
selected port is the parent port. A disconnected, disabled, or suspended port is reported as a
child port. The Ch bit is invalid after a bus reset until tree-ID has completed.
Con
1
Rd
Debounced port connection status. This bit indicates that the selected port is connected. The
connection must be stable for the debounce time of approximately 341 ms for the Con bit to
be set to 1. The Con bit is reset to 0 by hardware reset and is unaffected by bus reset.
Note: The Con bit indicates that the port is physically connected to a peer PHY, but the port is
not necessarily active.
Bias
Dis
1
1
3
Rd
Rd/Wr
Rd
Debounced incoming cable bias status. A 1 indicates that the selected port is detecting
incoming cable bias. The incoming cable bias must be stable for the debounce time of 52 µs
for the Bias bit to be set to 1.
Port disabled control. If 1, the selected port is disabled. The Dis bit is reset to 0 by hardware
reset (all ports are enabled for normal operation following hardware reset). The Dis bit is not
affected by bus reset.
Peer_S
peed
Port peer speed. This field indicates the highest speed capability of the peer PHY connected
to the selected port, encoded as follows:
Code
000
Peer Speed
S100
001
S200
010
S400
011–111
invalid
The Peer_Speed field is invalid after a bus-reset until self-ID has completed.
Note: Peer speed codes higher than ‘b010 (S400) are defined in 1394a-2000. However,
iceLynx-Micro is only capable of detecting peer speeds up to S400.
PIE
1
1
Rd/Wr
Rd/Wr
Port event interrupt enable. When set to 1, a port event on the selected port sets the port
event interrupt (PEI) bit and notify the link. This bit is reset to 0 by hardware reset and is
unaffected by bus reset.
Fault. This bit indicates that a resume-fault or suspend-fault has occurred on the selected port
and that the port is in the suspended state. A resume-fault occurs when a resuming port fails
to detect incoming cable bias from its attached peer. A suspend-fault occurs when a
suspending port continues to detect incoming cable bias from its attached peer. Writing 1 to
this bit clears the Fault bit to 0. This bit is reset to 0 by hardware reset and is unaffected by
bus reset.
Fault
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1.14.4 Vendor Identification Page Register
The vendor identification page identifies the vendor/manufacturer and compliance level. The page is
selected by writing 1 to the Page_Select field in base register 7. The configuration of the vendor
identification page is shown in Table 41 and the corresponding field descriptions given in Table 42.
Table 41. Page 1 (Vendor ID) Register Configuration
Bit Position
Address
1000
1001
0
1
2
3
4
5
6
7
Compliance
Reserved
1010
1011
Vendor_ID[0]
Vendor_ID[1]
1100
1101
1110
1111
Vendor_ID[2]
Product_ID[0]
Product_ID[1]
Product_ID[2]
Table 42. Page 1 (Vendor ID) Register Field Descriptions
FIELD
Compliance
Vendor_ID
SIZE
8
24
TYPE
Rd
Rd
DESCRIPTION
Compliance level. For iceLynx-Micro, this field is controlled by a link register bit.
Manufacturer’s organizationally unique identifier (OUI). For iceLynx-Micro, this field is
08_00_28h (Texas Instruments) (the MSB is at register address ‘b1010).
Product_ID
24
Rd
Product identifier. For iceLynx-Micro, this field is 41_44_99h (the MSB is at register address
‘b1101).
1.14.5 PHY Application Information
The PHY pins must be connected as shown in the following figures. XI and XO pins must be connected to
a crystal as described by Texas Instruments application note SLLA051.
TPBP
1394 Connector
TPBN
56 Ω
56 Ω
5 kΩ
220 pF
Figure 41. TPBP and TPBN Connection
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1 uF
TPBIAS
56 Ω
56 Ω
TPAP
TPAN
1394 Connector
Figure 42. TPAP, TPAN, and TPBIAS Connection
R0
.3k
FILTER0
FILTER1
0.1 uF
+/- 10%
Figure 43. R0 and R1 Connection
Figure 44. FILTER0 and FILTER1 Connection
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Figure 45. TPB, TPA, and TPBIAS Connection for Terminated Port (Port is not used)
1.14.6 PHY Reference Documents
Visit the Texas Instruments website to obtain the following reference documents:
Literature Number
SLLA117
Title
IEEE 1394 EMI Board Design and Layout Guidelines
SLLA051
Selection and Specification of Crystals for Texas Instruments IEEE 1394 Physical Layers
1.15 Power Management
The iceLynx-Micro operates from a single 3.3-V power supply. When REG_ENn is asserted, three internal
regulators operate the 1.8-V core. When the internal regulator is not supplied, the application must
externally supply the core voltage. The PHY also automatically conforms to IEEE1394a-2000 power
states according to bus activity. Table 43 summarizes all the power modes that the iceLynx-Mirco
supports.
Table 43. Power State Summary
Max Power
Max Power
w/External
Power State
InCPUCfg.Reset
PhyCfg.LPS
PHY Ports
Active
w/Internal Regulator
Enabled (mW)
Regulator
Enabled (mW)
531
Active - Full
0
1
0
1
0
695
473
125
31
power Link,
ARM, and PHY
are active
Low power 1 -
ARM Active
0
1
1
Disabled or
suspended by
software
223
102
4
Link and PHY
are low power
Low power 2 -
Link and PHY
only ARM in low
power
Active
Low power 3 -
PHY only – PHY
low power Link
and ARM are
low power
Disabled or
suspended by
software
Note: All other configurations are not valid for normal operation.
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Low Power(LP)
Power-Up(PU)
Active(A)
States
State
State
A to LP1
LP1 to A
Low Power1
ARM active
PHY in low power
Link off
A to LP2
LP2 to A
Low Power2
Link, PHY active
ARM off
Power-Up
Active
PU to A
PHY in Repeater Mode.
All register values at
default
PHY Active
ARM Active
Link Active
A to LP3
LP3 to A
Low Power3
PHY in low power
ARM, Link off
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1.15.1 PU to A (Power-Up State to Active State)
At the power-up state, all registers are at the default value. Following are the power-up status of registers
and signals related to power control.
Register/Pin Name
InCPUCfg.Reset
Power-up Status
0 (ARM is held in reset using RESET_ARMn pin)
InCPUCfg.ClkEn
InCPUCfg.PhyNoticeEn
PhyCfg.LPS
1
0
0 (PHY is in repeater mode)
WTCH_DG_TMRn
HPS
Low
High
1. The external system holds the ARM in reset using RESET_ARMn pin.
2. The external CPU loads the ARM program code. Once it has completed loading the code, it
deasserts RESET_ARMn.
3. The ARM sets PhyCfg.LPS to 1. Now the PHY, link, and ARM are fully functional.
1.15.2 A to LP1 (Active State to Low Power 1 State)
In the active state, the link, ARM, and PHY are fully operational. In the low power state 1, the link is off.
The PHY ports are suspended or disabled. The ARM may choose to put the iceLynx-Micro into a low
power state based on the HPS pin. A falling edge of the HPS pin indicates the external system is ready
for the iceLynx-Micro to go into low power mode.
The ARM sets the following bits to move to LP1 state.
1. Suspend or disable PHY ports. S/W can disable a PHY port by setting the Dis bit in PHY register
b1000. S/W can suspend a PHY port by sending an IEEE 1394a-2000 remote command packet to its
own node.
2. PhyCfg.LPS = 0 (PHY can go into low power mode according to IEEE 1394a-2000)
1.15.3 LP1 to A (Low Power 1 State to Active State)
1. On the detection of the following events, ARM must enable the link and PHY to the active state.
• Rising edge of HPS input pin.
• InCPUCfg.PhyNoticeEn = 1 and LinkOn or PHY_INT occurs.
2. ARM must set PhyCfg.LPS = 1. If any of the ports were disabled, software must reenable the PHY
ports by setting the Dis bit in PHY register b1000 to make the PHY active. The software must issue a
bus reset once PhyCfg.LPS is set to 1.
1.15.4 A to LP2 (Active State to Low Power 2 State)
In the active state, the Link, ARM, and PHY are fully operational. In the low power state 2, the ARM is off
and the link and PHY are fully operational. The system may choose to put the iceLynx-Micro into the low
power state 2 when the internal ARM is not used.
The ex-CPU sets the following bits to move to LP2 state:
1. Set InCPUCfg.Reset = 1 and InCPUCfg.ClkEn = 0 at the same time.
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1.15.5 LP2 to A (Low Power 2 State to Active State)
1. The iceLynx-Micro hardware sets InCPUCfg.Reset = 0 and InCPUClkEn = 1 for either of the following
conditions:
• Rising edge of HPS input pin.
• InCPUCfg.PhyNoticeEn=1 and LinkOn or PHY_INT occurs.
1.15.6 A to LP4 (Low Power 3 State to Active State)
In the active state, the link, ARM, and PHY are fully operational. In the low power state 4, the ARM and
link are off. The PHY ports are suspended or disabled. The ARM may choose to put iceLynx-Micro into a
low power state based on the HPS pin. A falling edge indicates the external system is ready for iceLynx-
Micro to go into low power mode.
The ARM sets the following bits to move to LP4 state:
1. Suspend or disable PHY ports. S/W can disable a PHY port by setting the Dis bit in PHY register
0b1000. S/W can suspend a PHY port by sending an IEEE 1394a-2000 remote command packet to
its own node.
2. PhyCfg.LPS = 0 {PHY can go into low power mode according to IEEE 1394a-2000}
3. Set InCPUCfg.Reset = 1 and InCPUClkEn = 0 at the same time.
1.15.7 LP4 to A (Low Power 3 State to Active State)
1. The iceLynx-Micro hardware sets InCPUCfg.Reset = 0 and InCPUClkEn = 1 for either of the following
conditions:
• Rising edge of HPS input pin
• InCPUCfg.PhyNoticeEn=1 and LinkOn or PHY_INT occurs
Once the ARM and link are active, the ARM must set PhyCfg.LPS = 1. If any of the ports were disabled,
software must reenable the PHY ports by setting the Dis bit in PHY register b1000 to make the PHY
active. The software must issue a bus reset once PhyCfg.LPS is set to 1.
The input/output pins and CFRs that control each power management state are defined in Table 44.
Table 44. I/O Pin and CFR Descriptions for Controlling Power Management States
Signal Name
Location
Direction
Description
LOW_PWR_RDY
Pin and CFR
Output
This signal is output to the system to indicate iceLynx-Micro can
go into a low power state. The ARM controls this output signal
using CFR. The signal also depends on the watchdog timer output
signal. If the watchdog timer is asserted, this signal is asserted.
InCPUCfg.LowPwrRdy
WTCH_DG_TMRn
Pin
Output
Input
Indicates watchdog timer status. Hardware asserts this when the
ARM software is not functioning correctly.
HPS
Pin and CFR
Host power status (ex-CPU power status). This signal indicates
the ex-CPU’s power status. A rising edge indicates the ex-CPU
has been turned ON. The internal ARM must wake up. The
internal ARM decides if it must wake up the rest of iceLynx-Micro.
ExCPUCfg.HPS
InCPUInt.HPSHi
InCPUInt.HPSLo
A falling edge indicates the ex-CPU has shut down. ARM can
decide how to react.
Interrupts are available for both the rising and falling edge of this
signal.
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Signal Name
PhyCfgLPS
Location
CFR
Direction
Description
This bit is set in CFR to indicate low power status to the PHY. The
ARM must set this when it wants to put the link into lower power
mode. The ARM must clear this bit to bring the link out of low
power mode.
Note: Software must wait at least 2 ms before setting PhyCtrl.LPS
after iceLynx-Micro power up. This ensures the internal clocks are
stable.
InCPUCfg.PhyNoticeEn
CFR
This bit enables PHY events. These PHY events signal a wake up
event to the ARM while the ARM is powered down. The PHY
events include LinkOn and PHY_INT.
RESET_ARMn
Pin and CFR
Input
This pin and CFR bit put ARM into reset.
InCPUCfg.Reset
ARM cannot be put into reset by setting InCPUCfg.Reset = 1 if
InCPUCfg.ResetDis is set to 1. See the description for
InCPUCfg.ResetDis. InCPUCfg.ResetDis bit must be cleared
before the ARM is put into reset. The RESET_ARMn pin does not
have these qualifying conditions. When RESET_ARMn = low, the
ARM is put into reset regardless of InCPUCfg.ResetDis bit status.
LINKON PhyCfg.LinkOn
DISABLE_IFn
Pin and CFR
Pin
Output
Input
This signal is asserted whenever LPS is low and a LinkOn packet
is received.
It is cleared whenever LPS is detected or the PHY register LCtrl bit
is set to zero. PhyCfg.LinkOn gives the current status of the
LINKON signal.
Interface disable. When this pin is asserted by the system, all
interfaces on iceLynx-Micro are in high-Z state. This includes Ex-
CPU I/F, HSDI I/F, GPIO, and WTCH_DG_TMRn. This function
does not include LOW_PWR_RDY.
This function is active low. The interface is disabled if
DISABLE_IFn=0.
InCPUCfg.ResetDis
CFR
This bit is set by hardware any time one of the following bits
transitions from 0 to 1.
PhyCfg.LinkOn
LinkInt.PhyInt
InCPUInt.HPSHi
Note: The WTCH_DG_TMRn is configured for output on the Timer2 interrupt.
1.16 16.5K Byte Memory - FIFO
1.16.1 Overview/Description
The iceLynx-Micro has 16.5K byte FIFO. The FIFO sizes are set and not programmable.
1.16.2 Isochronous FIFOs 0 and 1
These FIFOs are connected to the HSDI0 and HSDI1 ports, respectively. They are both 4K bytes in size.
These FIFOs are designed to handle MPEG2, DSS, DV, or audio data. These data types cannot be
interleaved. The buffer must be dedicated to one data type and a single direction. It can be
reprogrammed to handle different data types. Both of these buffers can be configured for either transmit
or receive. The buffer is only accessible using the HSDI. See Figure 46 for a block diagram of the
isochronous FIFO architecture.
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ISO FIFO 0
HSDI0
Packetizer
4K
ISO FIFO 1
Packetizer
HSDI1
4K
Figure 46. Isochronous FIFOs
1.16.3 Asynchronous/Asynchronous Stream FIFOs
These FIFOs are connected to the external and internal CPU interfaces. The transmit FIFOs are 2048
bytes each and the receive FIFOs are 2048 bytes each. Either FIFO can be configured for asynchronous
stream or asynchronous packets. See Figure 47 for a block diagram of the asynchronous FIFO
architecture.
Asynchronous or
Asynchrnous Stream
Transmit FIFO 0
2K
External
or Internal
Host
Packetizer/ Transmitter
Packetizer/ Transmitter
Asynchronous or
Asynchronous Stream
Transmit FIFO 1
2K
External
or Internal
Host
Asynchronous or
Asynchrnous Stream
Receive FIFO 0
2K
External
or Internal
Host
Packetizer/ Receiver
Packetizer/ Receiver
Asynchronous or
Asynchronous Stream
Receive FIFO 1
2K
External
or Internal
Host
Figure 47. Asynchronous/ Asynchronous Stream FIFOs
Note: The iceLynx-Micro has the ability to insert headers for asynchronous stream transmit. This feature must be
used for asynchronous stream TX only. For any type of packet other than asynchronous stream, do not enable this
feature.
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1.16.4 Broadcast Receive FIFO
This FIFO is designed to receive all broadcast packets, such as self-IDs, broadcast asynchronous
packets, and PHY packets. The broadcast receive FIFO is 512 bytes in size to accommodate self-Ids for
a 63-node network. This FIFO is accessed separately for software convenience. It is only accessible by
the external or internal CPU. This FIFO is only for receive operations. All transmit operations must take
place using an asynchronous transmit FIFO. See Figure 48 for a block diagram of the broadcast FIFO
architecture.
Broadcast Receive
FIFO
512 bytes
External
or Internal
Host
Packetizer/ Receiver
Figure 48. Broadcast Receive FIFO
1.16.5 FIFO Priority
For two FIFOs that are the same data type, the lower number FIFO always has priority. For example, if
the iceLynx-Micro were configured for two asynchronous transmit FIFOs, FIFO 0 and 1, FIFO 0 would
have priority over FIFO 1.
1.16.6 FIFO Monitoring
The FIFO size is monitored by several interrupts and status bits. An example of these monitoring bits is
included in Table 45.
Table 45. FIFO Monitoring Bits
Name
Description
Watermark High
The watermark control (Iso*WtrMrk.Control*) needs to be set to 1. The watermark level is
(Iso*CPUInt.WtrMrk*,
Iso*BufStat.WtrMrk*)
programmed at Iso*WtrMrk.Level*.
When the level in the FIFO is above the programmed value at Iso*WtrMrk.Level*, the Watermark
High is activated.
Watermark Low
The watermark control (Iso*WtrMrk.Control*) needs to be set to 0. The watermark level is
(Iso*CPUInt.WtrMrk*,
Iso*BufStat.WtrMrk*)
programmed at Iso*WtrMrk.Level*.
When the level in the FIFO is below the programmed value at Iso*WtrMrk.Level*, the watermark
low is activated.
Cell Available
A full 1394 packet (or individual cell: 188 bytes for DVB, 480 bytes for DV, 130 or 140 bytes for
(Iso*CPUInt.CellAvail,
Iso*BufStat.CellAvail)
DSS) is available in the FIFO. This is valid for transmit or receive.
Quadlets Available
This value reflects the number of quadlets currently in FIFO. This is valid for transmit or receive.
(Iso*BufStat.QuadAvail)
Notes: The FIFO watermark levels are only checked on packet boundaries. If the buffer is not a multiple of (packet
_length+ header length) and the watermark level is programmed between BUFFER SIZE and (BUFFER SIZE – 1
Packet Length – Header Length), watermark level indicators (Iso*CPUInt.WtrMrk*, Iso*BufStat.WtrMrk*) are not
activated.
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1.17 GPIO Configurations
GPIOs can be configured to achieve the following:
DSS TX – DSS SCC (system clock count) input and DSS error flag
Watermark level indicator in FIFOs
Flow control
GPIO interrupts. There are four possible GPIO interrupts. These are configured as ARM FIQ or
IRQs.
Note: GPIO interrupts are synchronously detected. The interrupt must be held at the level for at least one
50-MHz clock cycle (for both level sensitive and edge sensitive interrupts).
Example:
The FIQ and IRQ GPIOs are programmed in CFR.
For example, the FIQ interrupt is input using GPIO9.
1. The GPIOCfg.GPIO9Sel is set to “general purpose input.”
2. The GPIOIntCfg.GPIOInt*Sel bits (or GPIOIntCfg.GPIOIntYSel bits) are set to reference
GPIO 9.
3. The edge detection is set in GPIOIntCfg.GPIOInt*Det bit.
4. After this setup is complete, the InCPUInt.GPIO* (or InCPUInt.GPIOY) bit indicates when the
programmed edge occurs on FIQ GPIO. This must be enabled in IntCPUHiIntEn.GPIO*. The
GPIOData.GPIO9 indicates the GPIO9 status.
Table 46. Summary of GPIO Use
GPIO Function
DSS SCC input
Programmable GPIOs
GPIO 2, GPIO 3 for HSDI 0
DSS error flag
GPIO 6, GPIO 7 for HSDI 1
Wather Marks for Iso FIFOs
GPIO 0, GPIO 1 for Iso data path 0
GPIO 4, GPIO 5 for Iso data path 1
Note: All GPIOs (i.e., GPIO 0 through GPIO 10) can be configured as general-purpose input/output.
1.17.1 GPIO Setup
The flow control writes to GPIOs through the software functions. The GPIO is set up as a general-purpose
input or output. The values are read/written using the GPIOStat CFR for the appropriate GPIO.
The watermark GPIOs are linked to the watermark status bits.
1.18 IEEE 1394a-2000 Requirements
1.18.1 Features
The iceLynx-Micro is compliant to the IEEE 1394a-2000 standard. This requires the following features:
Arbitrated (short) bus reset
Ack-accelerated arbitration
Fly-by concatenation
Multi-speed packet concatenation
PHY ping packets
Priority arbitration
Port disable, suspend, and resume
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1.18.2 Cycle Master
The hardware automatically makes the node cycle master. This depends on the root status of the node. If
LinkCfg.CycMasAuto = 1 and the node is root, the node becomes the cycle master after the next bus
reset. The software must set LinkCfg.CycMasAuto = 1 at initialization phase immediately after device
reset or power-up.
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2
Appendix A: Configuration Registers
2.1 Configuration Registers
The configuration registers are maintained in a separate document.
2.2 Description Notes
R – Bit location is read by software
R0- Bit location is read by software and always returns 0 when read
R1 - Bit location is read by software and always returns 1 when read
R0W – Bit location is read by software and always returns 0 when read. Bit location can also be
written by software.
RCS – Bit location is read. Writing a 1 to the bit clears the field. The bit is synchronously
updated.
RS – Bit location is read by software and is synchronously updated
RW – Bit location is read and written by software
RWS - Bit location is read and written by software. Bit is synchronously updated.
RM – Read, write to 1 modify. The result of the write depends on which CPU (internal or
external) performed the write. This function is used for CPU communication interrupts. For the
external CPU interrupts, a write from the internal CPU sets the bit. A write from the external
CPU clears the bit. For the internal CPU interrupts, a write from the internal CPU clears the bit.
A write from the external CPU sets the bit.
2.3 CFR Address Ranges (Offset from CFR Base Address)
The CFR Base Address is offset 10 0000 hex.
Table 47. CFR Address Ranges
Name
SYS
LLC
IsoDP0
IsoDP1
Aud0
Starting Address Offset (hex)
Ending Address Offset (hex)
000
0A0
100
230
360
3E0
460
4B0
500
550
5A0
5E0
09F
0FF
22F
35F
3DF
45F
4AF
4FF
54F
59F
5DF
62F
Aud1
AsyTx0
AsyTx1
AsyRx0
AsyRx1
BrdCstRx
PLL
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2.4 Register Access
The IntCPUCfg.CFRLock bit is included to lock the ex-CPU from all DTCP related registers. When this bit
is set to 1, the ex-CPU cannot access these registers.
All register accesses by the external CPU are 32 bits. During reads, a snap shot value is used for both the
lower and upper 16-bit accesses. This snap shot value is created during the first access to the register. It
expires after a short amount of time.
For the internal ARM, some registers have restricted accesses.
32-bit access only. These registers can only be accessed 32 bits at a time.
CycTmr
AsyTx*AckBuffer
Anc*Data
32-bit write access while the associated function is being used. 32-/16-/8-bit access during read
accesses and when the associated function is not being used.
Iso*TmStmp
Iso*CIP1
Iso*FltrCIP1
Iso*MskCIP1
PLL*Cfg2
PLL*Cfg3
PLL*Cfg4
PLL*Cfg5
Aud*NoData
16-bit write access while the associated function is being used. 32-/16-/8-bit access during all read
accesses and while the associated function is not being used
Timer0
Timer1
Timer2
BusRstDat (read only register)
Iso0BufStat
HSDI0Cfg
Iso*WtrMrk
Iso*Hdr
Iso*FltrIsoHdr
Iso*MskIsoHdr
Iso*DVTmgCtl
Iso*DVTmgCfg
Anc*Data
Anc*Def
Anc*Data1
Anc*Data2
Anc*NoData
AsyRx*WtrMrk
AsyTx*WtrMrk
AsyTx*StrmHdr
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3
General Information
3.1 Package Size
The iceLynx-Micro includes two package pinout options: 176-pin MicroStar BGA and 176-pin QFP.
3.2 Operating Voltage
Min Voltage
Nominal Voltage
Max Voltage
3 V
3.3 V
3.6 V
Note: I/Os are not 5-V tolerant.
3.3 Operating Temperature
MIN
-20
-40
NOM
MAX
Unit
°C
°C
Commercial
Industrial
70
85
Operating ambient temperature
4
Absolute Maximum Ratings Over Operating Temperature Ranges†
Supply voltage range: ........... AVDD
VDD
- 0.3 V to 4 V
- 0.3 V to 4 V
PLL_VDD
- 0.3 V to 4 V
Input clamp current, IIK (VI < 0 or VI > VDD) (see Note 1)
Output clamp current, IOK (VO < 0 or VO > VDD) (see Note 2)
Electrostatic discharge (see Note 3)
Continuous total power dissipation
Operating free-air temperature, TA (Commercial)
(Industrial)
± 20 mA
± 20 mA
HBM: 2 kV
See Dissipation Rating Table
-20°C to 70°C
-40°C to 85°C
-65°C to 150°C
260°C
Storage temperature range, Tstg
Lead temperature 1,6 mm (1/16 inch) from cage for 10 seconds
†
Stresses beyond those listed under the absolute maximum ratings causes’ permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended
operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods affects device reliability.
NOTES: 1. Applies to external input and bidirectional buffers.
2. Applies to external output and bidirectional buffers.
3. HBM is human body model, MM is machine model.
DISSIPATION RATING TABLE
DERATING FACTOR
ABOVE TA = 25°C
13.8 mW/ OC
TA = 25°C
POWER RATING
1.1 W
TA = 70°C
POWER RATING
0.5 W
TA = 85°C
PACKAGE
POWER RATING
0.3 W
µ*BGA 176 #
µ*BGA 176 *
TQFP 176 #
TQFP 176 *
0.8 W
10.4 mW/OC
0.4 W
-
-
-
1.8 W
1.3 W
22.6 mW/ OC
0.8 W
0.6 W
16.5 mW/ OC
Notes: 1) *: Standard JEDEC Low-K board
2) #: Standard JEDEC High-K board
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4.1 Recommended Operating Conditions (Analog IEEE 1394 I/F)
TEST
PARAMETER
CONDITION
MIN NOM
MAX UNIT
Analog voltage, AVdd
Supply voltage, Vdd
PLL supply voltage, PLL_Vdd
Output voltage, VO
3
3
2.7
0
3.3
3.3
3
3.6
3.6
3.6
VDD
VDD
V
V
V
V
V
LVCMOS terminals
LVCMOS terminals
†
High-level input voltage, VIH
2
†
LVCMOS terminals
Low-level input voltage, VIL
0
0.8
V
Output current, IO
TPBIAS outputs
Cable inputs, during data
reception
-5.6
118
1.3
260
mA
Differential input voltage, VID
mV
Cable inputs, during arbitration
168
265
TPB cable inputs, source power
0.9706
2.515
node
Common-mode input
voltage, VIC
V
TPB cable inputs, nonsource
power node
0.4706
2.015
176-PQFP high-K JEDEC board
RθJA =44.3°C /W, TA = 70°C, PD
= 0.6 W
176-PQFP low-K JEDEC board
RθJA = 60.8°C /W, TA = 70°C, PD
= 0.6 W
176-u*BGA high-K JEDEC board
RθJA = 72.5°C /W, TA = 70°C, PD
= 0.6 W
176-u*BGA low-K JEDEC board
RθJA = 96.7°C /W, TA = 70°C, PD
= 0.6 W
96.6
107
113
128
128
Maximum junction
temperature, TJ
°C
176-u*BGA high-K JEDEC board
RθJA =72.5°C /W, TA = 85°C, PD
= 0.6 W
Power-up reset time, tpu
Power-up reset time, tpu
RESETn input
RESET_ARMn input
2
ms
ms
ns
TPA, TPB cable inputs, S100
±1.08
±0.5
operation
TPA, TPB cable inputs, S200
operation
ns
ns
ns
ns
ns
Receive input jitter
Receive input skew
TPA, TPB cable inputs, S400
±0.315
±0.8
operation
Between TPA and TPB cable
inputs, S100 operation
Between TPA and TPB cable
±0.55
±0.5
inputs, S200 operation
Between TPA and TPB cable
inputs, S400 operation
†
§
¶
Applies to external inputs and bidirectional buffers without hysteresis.
Applies to external output buffers.
For a node that does not source power; see Section 4.2.2.2 in IEEE Std 1394a–2000.
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4.2 Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise
Noted)
TEST
PARAMETER
High-level output voltage
OPERATION
MIN
MAX UNIT
CONDITIONS
VOH
VOL
IOZ
IOH = -2 mA
2.4
V
Low-level output voltage
3-state output high impedance
IOL = 6 mA
VO = VDD or GND
VI = GND
VI = GND
VI = Vdd
0.5
±20
±20
V
µA
Output pins
Input pins
I/O pins†
3.6 V
3.6 V
3.6 V
3.6 V
IIL
Low-level input current
High-level input current
µA
µA
±20
±20
IIH
†
For I/O terminals, input leakage (IIL and IIH) includes IOZ of the disabled output.
4.3 Electrical Characteristics Over Recommended Ranges of Operating Conditions (Unless
Otherwise Noted)
4.3.1 Device
PARAMETER
TEST CONDITIONS
See Note 4
MIN
TYP
MAX UNIT
Idd
Supply current (internal voltage regulator
180
mA
enabled, REG_ENn = L)
400-kΩ resistor†
At rated IO current
VI = 1.5 V
4.7
1.665
-90
7.5
V
VTH
VO
Power status threshold, CPS input†
TPBIAS output voltage
2.015
V
-20
-20
IIRST
Pullup current (RESETn input)
µA
-90
VI = 0 V
†
Measured at cable power side of resistor.
NOTES: 4. Conditions:
VDD = 3.3 V
HSDI0: MPEG TS Tx (mode-7)
HSDI1: Audio Rx (IEC60958, 44.1 kHz)
Three Ports Connected
Cipher not enabled
ARM: Application PGM running
4.3.2 Driver
PARAMETER
Differential output voltage
Driver difference current, TPA+, TPA-, TPB+,
and TPB-
TEST CONDITIONS
MIN
172
MAX UNIT
VOD
IDIFF
265
mV
mA
56 Ω, see Figure 49
Drivers enabled, speed signaling off
-1.05‡
1.05‡
ISP200 Common-mode speed signaling current,
TPB+, TPB-
S200 speed signaling enabled
S400 speed signaling enabled
Drivers disabled, see Figure 49
-4.84§
-12.4§
-2.53§
-8.10§
20
mA
mA
mV
ISP400 Common-mode speed signaling current,
TPB+, TPB-
VOFF
Off-state differential voltage
‡
Limits defined as algebraic sum of TPA+ and TPA- driver currents. Limits also apply to TPB+ and TPB - algebraic sum of driver
currents.
§
Limits defined as absolute limit of each of TPB+ and TPB - driver currents.
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TPAx+
TPBx+
56
Ω
TPAx-
TPBx-
Figure 49. Test Load Diagram
4.3.3 Receiver
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ZID
ZIC
Differential impedance
Drivers disabled
4
7
10
4
kΩ
pF
Common-mode impedance
Drivers disabled
Drivers disabled
20
kΩ
pF
24
30
VTH–R
Receiver input threshold voltage
-30
0.6
89
-168
49
mV
V
VTH–CB
Cable bias detect threshold, TPBx cable inputs
Positive arbitration comparator threshold voltage
Negative arbitration comparator threshold voltage
Drivers disabled
1
VTH
VTH
+
-
Drivers disabled
168
-89
131
mV
mV
mV
Drivers disabled
VTH-SP200 Speed signal threshold
TPBIAS-TPA common-mode
voltage, drivers disabled
TPBIAS-TPA common-mode
voltage, drivers disabled
VTH-SP400 Speed signal threshold
314
396
mV
4.4 Thermal Characteristics
PARAMETER
176-µBGA RθJA, high-K board
176-µBGA RθJA, low-K board
TEST CONDITIONS
MIN
TYP
TYP
MAX UNIT
63.93
Board mounted, no air flow, JEDEC test board
Board mounted, no air flow, JEDEC test board
Board mounted, no air flow, JEDEC test board
Board mounted, no air flow, JEDEC test board
°C/W
82.1
°C/W
44.3
176-PQFP
176-PQFP
RθJA, high-K board
RθJA, low-K board
°C/W
60.8
°C/W
4.5 Switching Characteristics for PHY Port Interface
PARAMETER
Jitter, transmit
Skew, transmit
TEST CONDITIONS
Between TPA and TPB
Between TPA and TPB
10% to 90%, at 1394 connector
90% to 10%, at 1394 connector
MIN
MAX UNIT
±0.15
±0.1
1.2
ns
ns
ns
ns
0.5
0.5
tr
tf
TP differential rise time, transmit
TP differential fall time, transmit
1.2
4.6 Operating, Timing, and Switching Characteristics of XI
PARAMETER
MIN
TYP
MAX
UNIT
V
V
V
MHz
ppm
V/ns
3
3.3
3.6
VDD
VIH
VIL
PLL_VDD
0.63 VDD
High-level input voltage
Low-level input voltage
Input clock frequency
Input clock frequency tolerance
Input slew rate
0.33 VDD
24.576
<100
4
0.2
40%
60%
Input clock duty cycle
Note: When using an external clock, the input is supplied to XI, the XO terminal must be left unconnected, and the XI clock must be
stable before the 2-ms device reset begins.
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Reset Power States
Table 48. Pin State During Power On Reset, Just After Power On Reset and DISABLE_IFn=L
RESETn=H and
DISABLE_IFn=H
Just After Power On
RESETn=H and
DISABLE_IFn=L
DISABLE_IFn=L
High Z
0
RESETn=L and
DISABLE_IFn=L During
Power On
Pin Name
WTCH_DG_TMRn
LOW_PWR_RDY
MCIF_INTz
High Z
0
0
0
1
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
MCIF_CS_IOz=
MCIF_CS_MEMz
MCIF_ACKz
MCIF_WAITz
MCIF_DATA[15:0]
HSDI*_D[0]
HSDI*_D[7:1]
HSDI*_EN
HSDI*_SYNC
HSDI*_DVALID
HSDI*_AV
HSDI*_AMCLK_OUT
HSDI1_AUDIO_ERR
HSDI1_AUDIO_MUTE
MLPCM_LRCLK
MLPCM_BCLK
MLPCM_D{2:0]
MLPCM_A
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
0
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
HSDI*_60958_OUT
Note: All CFR values are the default value.
6
Configuration Register Map
See Appendix A for the configuration register map and descriptions.
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Mechanical Data
7.1 PQFP Package Information
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7.2 µ*BGA Package Dimensions
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7.3 ZGW Package Dimensions
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