TUSB1210 [TI]
高速 480Mbps USB 2.0 OTG 收发器;
| 型号： | TUSB1210 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 高速 480Mbps USB 2.0 OTG 收发器 电信 电信电路 网络接口 |
| 文件： | 总64页 (文件大小：1093K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TUSB1210
Standalone USB Transceiver Chip Silicon
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLLSE09F
November 2009–Revised August 2012
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
Contents
1
2
Features ............................................................................................................................. 6
Description ......................................................................................................................... 7
2.1
Terminal Description ........................................................................................................ 7
TUSB1210 Block Diagram ................................................................................................. 9
2.2
3
4
Electrical Characteristics .................................................................................................... 10
3.1
3.2
3.3
Absolute Maximum Ratings .............................................................................................. 10
Recommended Operating Conditions .................................................................................. 10
ESD Electrical Parameters ............................................................................................... 10
Clock System .................................................................................................................... 11
4.1
4.2
4.3
4.4
4.5
USB PLL Reference Clock ............................................................................................... 11
ULPI Input Clock Configuration .......................................................................................... 11
ULPI Output Clock Configuration ........................................................................................ 11
Clock 32 kHz ............................................................................................................... 12
Reset ........................................................................................................................ 12
5
Power Module ................................................................................................................... 13
5.1
Power Providers ........................................................................................................... 13
5.1.1
5.1.2
5.1.3
VDD33 Regulator ................................................................................................. 13
VDD18 Supply ..................................................................................................... 13
VDD15 Regulator ................................................................................................. 13
5.2
5.3
5.3.1
6
USB Connectivity .............................................................................................................. 17
6.1
6.2
6.3
Timing Parameter Definitions ............................................................................................ 17
Interface Target Frequencies ............................................................................................ 17
USB Transceiver ........................................................................................................... 17
6.3.1
6.3.2
6.3.3
TUSB1210 Modes vs ULPI Pin Status ...................................................................... 18
ULPI Interface Timing .......................................................................................... 19
PHY Electrical Characteristics ................................................................................ 19
6.3.3.1 LS/FS Single-Ended Receivers .................................................................. 20
6.3.3.2 LS/FS Differential Receiver ....................................................................... 20
6.3.3.3 LS/FS Transmitter .................................................................................. 20
6.3.3.4 HS Differential Receiver ........................................................................... 22
6.3.3.5 HS Differential Transmitter ........................................................................ 22
6.3.3.6 UART Transceiver ................................................................................. 23
OTG Electrical Characteristics ................................................................................ 24
6.3.4
7
I/O Electrical Characteristics ............................................................................................... 26
7.1
7.2
7.3
Analog I/O Electrical Characteristics .................................................................................... 26
Digital I/O Electrical Characteristics ..................................................................................... 26
Electrical Characteristics: Digital IO Pins (Non-ULPI) ................................................................ 26
8
9
External Components ........................................................................................................ 27
Register Map ..................................................................................................................... 28
9.1
TUSB1210 Product ........................................................................................................ 28
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
VENDOR_ID_LO ............................................................................................... 29
VENDOR_ID_HI ................................................................................................ 29
PRODUCT_ID_LO ............................................................................................. 29
PRODUCT_ID_HI .............................................................................................. 30
FUNC_CTRL .................................................................................................... 30
FUNC_CTRL_SET ............................................................................................. 31
2
Contents
Copyright © 2009–2012, Texas Instruments Incorporated
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
9.1.7
9.1.8
9.1.9
FUNC_CTRL_CLR ............................................................................................. 31
IFC_CTRL ....................................................................................................... 32
IFC_CTRL_SET ................................................................................................ 33
9.1.10 IFC_CTRL_CLR ................................................................................................ 34
9.1.11 OTG_CTRL ...................................................................................................... 34
9.1.12 OTG_CTRL_SET ............................................................................................... 36
9.1.13 OTG_CTRL_CLR ............................................................................................... 36
9.1.14 USB_INT_EN_RISE ............................................................................................ 37
9.1.15 USB_INT_EN_RISE_SET ..................................................................................... 38
9.1.16 USB_INT_EN_RISE_CLR ..................................................................................... 38
9.1.17 USB_INT_EN_FALL ........................................................................................... 39
9.1.18 USB_INT_EN_FALL_SET ..................................................................................... 40
9.1.19 USB_INT_EN_FALL_CLR ..................................................................................... 40
9.1.20 USB_INT_STS .................................................................................................. 41
9.1.21 USB_INT_LATCH .............................................................................................. 42
9.1.22 DEBUG .......................................................................................................... 43
9.1.23 SCRATCH_REG ................................................................................................ 43
9.1.24 SCRATCH_REG_SET ......................................................................................... 44
9.1.25 SCRATCH_REG_CLR ......................................................................................... 44
9.1.26 VENDOR_SPECIFIC1 ......................................................................................... 45
9.1.27 VENDOR_SPECIFIC1_SET .................................................................................. 45
9.1.28 VENDOR_SPECIFIC1_CLR .................................................................................. 46
9.1.29 VENDOR_SPECIFIC2 ......................................................................................... 47
9.1.30 VENDOR_SPECIFIC2_SET .................................................................................. 48
9.1.31 VENDOR_SPECIFIC2_CLR .................................................................................. 48
9.1.32 VENDOR_SPECIFIC1_STS .................................................................................. 49
9.1.33 VENDOR_SPECIFIC1_LATCH ............................................................................... 49
9.1.34 VENDOR_SPECIFIC3 ......................................................................................... 50
9.1.35 VENDOR_SPECIFIC3_SET .................................................................................. 51
9.1.36 VENDOR_SPECIFIC3_CLR .................................................................................. 51
10
Application Information ...................................................................................................... 53
10.1 Host or OTG, ULPI Input Clock Mode Application .................................................................... 53
10.2 Device, ULPI Output Clock Mode Application ......................................................................... 53
Glossary ........................................................................................................................... 55
TUSB1210 Package ............................................................................................................ 57
12.1 TUSB1210 Standard Package Symbolization ......................................................................... 57
12.2 Package Thermal Resistance Characteristics ......................................................................... 57
11
12
Copyright © 2009–2012, Texas Instruments Incorporated
Contents
3
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
List of Figures
5-1
TUSB1210 Power-Up Timing (ULPI Clock Input Mode) .................................................................... 15
6-1
USB UART Data Flow ........................................................................................................... 23
Host or OTG, ULPI Input Clock Mode Application Diagram................................................................ 53
Device, ULPI Output Clock Mode Application Diagram ..................................................................... 54
Printed Device Reference ....................................................................................................... 57
10-1
10-2
12-1
4
List of Figures
Copyright © 2009–2012, Texas Instruments Incorporated
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
List of Tables
2-1
4-1
4-2
4-3
5-1
5-2
5-3
5-4
6-1
6-2
6-3
Terminal Functions ................................................................................................................
8
Electrical Characteristics: Clock Input ........................................................................................ 11
Electrical Characteristics: REFCLK ........................................................................................... 11
Performances ..................................................................................................................... 12
Summary of TUSB1210 Power Providers..................................................................................... 13
VDD33 Internal LDO Regulator Characteristics ................................................................................ 13
VDD15 Internal LDO Regulator Characteristics ................................................................................ 14
Power Consumption ............................................................................................................. 14
Timing Parameter Definitions................................................................................................... 17
TUSB1210 Interface Target Frequencies ..................................................................................... 17
TUSB1210 Modes vs ULPI Pin Status:ULPI Synchronous Mode Power-Up
...................................................................................................................................... 18
6-4
TUSB1210 Modes vs ULPI Pin Status: USB Suspend Mode ............................................................. 18
TUSB1210 Modes vs ULPI Pin Status: ULPI 6-Pin Serial Mode and UART Mode ..................................... 19
ULPI Interface Timing............................................................................................................ 19
LS/FS Single-Ended Receivers ................................................................................................ 20
LS/FS Differential Receiver ..................................................................................................... 20
LS Transmitter .................................................................................................................... 20
FS Transmitter.................................................................................................................... 22
HS Differential Receiver......................................................................................................... 22
HS Transmitter.................................................................................................................... 23
USB UART Interface Timing Parameters ..................................................................................... 23
CEA-2011/UART Transceiver .................................................................................................. 23
Pullup/Pulldown Resistors....................................................................................................... 24
OTG VBUS Electrical.............................................................................................................. 24
OTG ID Electrical................................................................................................................. 25
Electrical Characteristics: Analog Output Pins .............................................................................. 26
TUSB1210 External Components.............................................................................................. 27
TUSB1210 VBUS Capacitors..................................................................................................... 27
USB Register Summary ......................................................................................................... 28
TUSB1210 Nomenclature Description......................................................................................... 57
TUSB1210 Thermal Resistance Characteristics ............................................................................. 57
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
7-1
8-1
8-2
9-1
12-1
12-2
Copyright © 2009–2012, Texas Instruments Incorporated
List of Tables
5
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
Standalone USB Transceiver Chip Silicon
Check for Samples: TUSB1210
1
Features
Controller Core.
• Complete HS-USB Physical Front-End:
• USB2.0 PHY Transceiver Chip, Designed to
Interface With a USB Controller via a ULPI
Interface, Fully Compliant With:
– Supports High Speed (480 Mbit/s), Full
Speed (12 Mbit/s) and Low Speed (1.5 Mbit/s)
– Universal Serial Bus Specification Rev. 2.0
– On-The-Go Supplement to the USB 2.0
Specification Rev. 1.3
– UTMI+ Low Pin Interface (ULPI) Specification
– Integrated Phase-Locked Loop (PLL)
Supporting 2 Clock Frequencies 19.2 MHz/26
MHz
Rev. 1.1
– ULPI 12-pin SDR Interface
– Integrated 45 Ω ±10% High-Speed
Termination Resistors, 1.5 kΩ Full-Speed
Device Pull-up Resistor, 15 kΩ Host
Termination Resistors
– Integrated Transmit and Receive Paths for
Parallel-to-Serial and Serial-to-Parallel Data
Conversion
– USB Data Recovery to Allow Recovery of
USB Data up to ±500 ppm Frequency Drift
– Bit-Stuffing Insertion During Transmit and
Removal During Receive
• DP/DM Line External Component
Compensation (TI Patent Pending)
• Interfaces to Host, Peripheral and OTG Device
Cores; Optimized for Portable Devices or
System ASICs with Built-in USB OTG Device
Core
• Complete USB OTG Physical Front-End that
Supports Host Negotiation Protocol (HNP) and
Session Request Protocol (SRP)
– Non-Return-to-Zero Inverted (NRZI)
Encoding and Decoding
• VBUS Overvoltage Protection Circuitry Protects
VBUS Pin in Range –2 V to 20 V
– Supports Bus Reset, Suspend, Resume and
High-Speed Detection Handshake (Chirp)
• Internal 5 V Short-Circuit Protection of DP, DM,
and ID Pins for Cable Shorting to VBUS Pin
– HS USB DP/DM Impedance Programmability
for External Component Compensation
• OTG Ver1.3 :
• ULPI Interface:
– I/O Interface (1.8V) Optimized for Non-
Terminated 50 Ω Line Impedance
– Control of External VBUS Switch or Charge
Pump
– ULPI CLOCK Pin (60 MHz) Supports Both
Input and Output Clock Configurations
– Both Session Request Protocol (SRP)
Methods Supported: Data Pulsing and VBUS
Pulsing
– Integrated VBUS Detectors and Cable
Detection (ID)
– Fully Programmable ULPI-Compliant
Register Set
• Full Industrial Grade Operating Temperature
Range from –40°C to 85°C
• Available in a 32-Pin Quad Flat No Lead [QFN
(RHB)] Package
• Internal Power-On Reset (POR) Circuit
• Flexible System Integration and Very Low
Current Consumption, Optimized for Portable
Devices
• Can Be Interfaced to Peripheral, Host or OTG
Controller Devices via ULPI. Suited to Portable
Devices or System ASICs with Built-In
6
Features
Copyright © 2009–2012, Texas Instruments Incorporated
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
2
Description
The TUSB1210 is a USB2.0 transceiver chip, designed to interface with a USB controller via a ULPI
interface. It supports all USB2.0 data rates (High-Speed 480Mbps, Full-Speed 12 Mbps and Low-Speed
1.5Mbps), and is compliant to both Host and Peripheral modes. It additionally supports a UART mode and
legacy ULPI serial modes.
TUSB1210 also supports the OTG (Ver1.3) optional addendum to the USB 2.0 Specification, including
Host Negotiation Protocol (HNP) and Session Request Protocol (SRP).
TUSB1210 is optimized to be interfaced through a 12-pin SDR UTMI Low Pin Interface (ULPI), supporting
both input clock and output clock modes, with 1.8 V interface supply voltage.
TUSB1210 integrates a 3.3 V LDO, which makes it flexible to work with either battery operated systems or
pure 3.3 V supplied systems. Both the main supply and the 3.3 V power domain can be supplied through
an external switched-mode converter for optimized power efficiency.
TUSB1210 includes a POR circuit to detect supply presence on VBAT and VDDIO pins. TUSB1210 can be
disabled or configured in low power mode for energy saving.
TUSB1210 is protected against accidental shorts to 5 V or ground on its exposed interface (DP/DM/ID). It
is also protected against up to 20 V surges on VBUS
.
TUSB1210 integrates a high-performance low-jitter 480 MHz PLL and supports two clock configurations.
Depending on the required link configuration, TUSB1210 supports both ULPI input and output clock
mode : input clock mode, in which case a square-wave 60 MHz clock is provided to TUSB1210 at the
ULPI interface CLOCK pin; and output clock mode in which case TUSB1210 can accept a square-wave
reference clock at REFCLK of either 19.2 MHz, 26 MHz. Frequency is indicated to TUSB1210 via the
configuration pin CFG. This can be useful if a reference clock is already available in the system.
1
2.1 Terminal Description
RHB PACKAGE
(TOP VIEW)
24
23
22
21
20
19
18
REFCLK
1
2
3
4
5
6
7
N/C
NXT
DATA0
DATA1
DATA2
DATA3
DATA4
ID
V
TUSB1210
32-pin QFN
BUS
V
V
BAT
DD33
DM
DP
GND
17
N/C
8
CPEN
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2009–2012, Texas Instruments Incorporated
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
Table 2-1. Terminal Functions
TERMINAL
A/D
TYPE
LEVEL
DESCRIPTION
NO.
NAME
VDD33 Reference clock input (square-wave only). Tie to GND when pin 26
(CLOCK) is required to be Input mode. Connect to square-wave reference
clock of amplitude in the range of 3 V to 3.6 V when Pin 26 (CLOCK) is
required to be Output mode. See pin 14 (CFG) description for REFCLK
input frequency settings.
1
REFCLK
A
I
3.3 V
2
3
NXT
D
D
D
D
D
D
–
O
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
ULPI NXT output signal
DATA0
DATA1
DATA2
DATA3
DATA4
N/C
I/O
I/O
I/O
I/O
I/O
–
ULPI DATA input/output signal 0 synchronized to CLOCK
ULPI DATA input/output signal 1 synchronized to CLOCK
ULPI DATA input/output signal 2 synchronized to CLOCK
ULPI DATA input/output signal 3 synchronized to CLOCK
ULPI DATA input/output signal 4 synchronized to CLOCK
No connect
4
5
6
7
8
9
DATA5
DATA6
D
D
I/O
I/O
ULPI DATA input/output signal 5 synchronized to CLOCK
ULPI DATA input/output signal 6 synchronized to CLOCK
10
Active-high chip select pin. When low the IC is in power down and ULPI
bus is tri-stated. When high normal operation. Tie to VDDIO if unused.
11
CS
D
I
VDDIO
12
13
VDD15
DATA7
A
D
power
I/O
1.5-V internal LDO output. Connect to external filtering capacitor.
ULPI DATA input/output signal 7 synchronized to CLOCK
VDDIO
VDDIO
REFCLK clock frequency configuration pin. Two frequencies are
supported: 19.2 MHz when 0, or 26 MHz when 1.
14
CFG
D
I
15
16
17
18
19
20
21
22
23
24
25
N/C
N/C
–
–
–
–
–
No connect
–
No connect
CPEN
DP
D
A
A
A
A
A
A
–
O
VDD33
VDD33
VDD33
VDD33
VBAT
VBUS
VDD33
–
CMOS active-high digital output control of external 5V VBUS supply
DP pin of the USB connector
I/O
DM
I/O
DM pin of the USB connector
VDD33
VBAT
VBUS
ID
power
power
power
I/O
3.3-V internal LDO output. Connect to external filtering capacitor.
Input supply voltage or battery source
VBUS pin of the USB connector
Identification (ID) pin of the USB connector
No connect
N/C
–
N/C
–
–
–
No connect
ULPI 60 MHz clock on which ULPI data is synchronized.
Two modes are possible:
26
CLOCK
D
O
I
VDDIO
Input Mode: CLOCK defaults as an input.
Output Mode: When an input clock is detected on REFCLK pin (after 4
rising edges) then CLOCK will change to an output.
When low, all digital logic (except 32 kHz logic required for power up
sequencing) including registers are reset to their default values, and ULPI
bus is tri-stated. When high, normal USB operation.
27
RESETB
D
VDDIO
28
29
30
31
VDD18
STP
A
D
A
D
power
VDD18
VDDIO
VDD18
VDDIO
External 1.8-V supply input. Connect to external filtering capacitor.
ULPI STP input signal
I
VDD18
DIR
power
O
External 1.8-V supply input. Connect to external filtering capacitor.
ULPI DIR output signal
External 1.8V supply input for digital I/Os. Connect to external filtering
capacitor.
32
VDDIO
A
I
VDDIO
8
Description
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
2.2 TUSB1210 Block Diagram
POR
VDDIO (32)
VIO
CTRL
POR
VBAT
VBAT (21)
( 1) REFCLK
(11) CS
(14) CFG
POR
DIG
BGAP
& REF
1V5
32K
RST_DIG
(27) RESETB
VDD15 (12)
(
)
)
)
)
8
N/C
N/C
N/C
N/C
N/C
DIG
(
(
(
15
16
25
USB-IP
VDD18 (30)
1V8
VDD18 (28)
PWR_ FSM
PHY
PLL
DIG
+
(24)
VDD33 (20)
3V3
OTG
PHY
ANA
ULPI
+
REGS
DP (18)
DM (19)
ID (23)
OTG
(17) CPEN
TEST
(22)
VBUS
PKG Substrate
(Ground )
Copyright © 2009–2012, Texas Instruments Incorporated
Description
9
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
3
Electrical Characteristics
3.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
CONDITIONS
MIN
MAX UNIT
VCC
Main battery supply voltage (2)
0
5
V
Where supply represents the voltage applied
to the power supply pin associated with the
input
Voltage on any input(3)
–0.3 1 × VCC +0.3
V
VBUS input
–2
20
5.25
1.98
125
85
V
V
ID, DP, DM inputs
Stress condition guaranteed 24h
Continuous
–0.3
VDDIO
Tstg
TA
IO supply voltage
V
Storage temperature range
Ambient temperature range
–55
–40
–40
–40
°C
°C
Absolute maximum rating
150
125
TJ
Ambient temperature range
°C
°C
For parametric compliance
Ambient temperature for parametric
compliance
With max 125°C as junction temperature
–40
85
DP, DM or ID pins short circuited to VBUS
supply, in any mode of TUSB1210 operation,
continuously for 24 hours
DP, DM, ID high voltage short circuit
DP, DM, ID low voltage short circuit
5.25
V
V
DP, DM or ID pins short circuited to GND in
any mode of TUSB1210 operation,
continuously for 24 hours
0
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The product will have negligible reliability impact if voltage spikes of 5.5 V occur for a total (cumulative over lifetime) duration of 5
milliseconds.
(3) Except VBAT input, VBUS, ID, DP, and DM pads
3.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN NOM
MAX UNIT
VBAT
Battery supply voltage
2.7
3.15
3.05
1.71
–40
3.6
4.8
V
V
VBAT
CERT
When VDD33 is supplied internally
Battery supply voltage for USB 2.0 compliancy
(USB 2.0 certification)
When VDD33 is shorted to VBAT externally
VDDIO
TA
Digital IO pin supply
1.98
85
V
Ambient temperature range
°C
3.3 ESD Electrical Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CDM
HBM
Charged-Device Model stress voltage
Human-Body Model stress voltage
All pads
All pads
500
V
V
2000
10
Electrical Characteristics
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
4
Clock System
4.1 USB PLL Reference Clock
The USB PLL block generates the clocks used to synchronize :
•
•
the ULPI interface (60 MHz clock)
the USB interface (depending on the USB data rate, 480 Mbps, 12 Mbps or 1.5 Mbps)
TUSB1210 requires an external reference clock which is used as an input to the 480 MHz USB PLL block.
Depending on the clock configuration, this reference clock can be provided either at REFCLK pin or at
CLOCK pin. By default CLK pin is configured as an input.
Two clock configurations are possible:
•
•
Input clock configuration (see Section 4.2)
Output clock configuration (see Section 4.3)
4.2 ULPI Input Clock Configuration
In this mode REFCLK must be externally tied to GND. CLOCK remains configured as an input.
When the ULPI interface is used in “input clock configuration”, i.e., the 60 MHz ULPI clock is provided to
TUSB1210 on Clock pin, then this is used as the reference clock for the 480 MHz USB PLL block.
Table 4-1. Electrical Characteristics: Clock Input
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
%
Clock input duty cycle
40
60
fCLK
Clock nominal frequency
Clock input rise/fall time
Clock input frequency accuracy
Clock input integrated jitter
60
MHz
%
In % of clock period tCLK ( = 1/fCLK
)
10
250
600
ppm
ps rms
4.3 ULPI Output Clock Configuration
In this mode a reference clock must be externally provided on REFCLK pin When an input clock is
detected on REFCLK pin then CLK will automatically change to an output, i.e., 60 MHz ULPI clock is
output by TUSB1210 on CLK pin.
Two reference clock input frequencies are supported. REFCLK input frequency is communicated to
TUSB1210 via a configuration pin, CFG, see fREFCLK in Table 8-1 for frequency correspondence.
TUSB1210 supports square-wave reference clock input only. Reference clock input must be square-wave
of amplitude in the range 3.0 V to 3.6 V.
Table 4-2. Electrical Characteristics: REFCLK
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFCLK input duty cycle
40
60
%
When CFG pin is tied to GND
When CFG pin is tied to VDDIO
In % of clock period tREFCLK ( =
19.2
26
fREFCLK
REFCLK nominal frequency
REFCLK input rise/fall time
MHz
%
20
1/fREFCLK
)
REFCLK input frequency accuracy
REFCLK input integrated jitter
250
600
ppm
ps rms
Copyright © 2009–2012, Texas Instruments Incorporated
Clock System
11
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
4.4 Clock 32 kHz
An internal clock generator running at 32 kHz has been implemented to provide a low-speed, low-power
clock to the system
Table 4-3. Performances
PARAMETER
Output duty cycle
TEST CONDITIONS
Input duty cycle 40–60%
MIN
48
TYP
50
MAX
UNIT
%
52
38
Output frequency
23
32
kHz
4.5 Reset
All logic is reset if CS = 0 or VBAT are not present.
All logic (except 32 kHz logic) is reset if VDDIO is not present.
PHY logic is reset when any supplies are not present (VDDIO, VDD15, VDD18, VDD33) or if RESETB pin is low.
TUSB1210 may be reset manually by toggling the RESETB pin to GND for at lease 200 ns.
If manual reset via RESETB is not required then RESETB pin may be tied to VDDIO permanently.
12
Clock System
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
5
Power Module
This chapter describes the electrical characteristics of the voltage regulators and timing characteristics of
the supplies digitally controlled within the TUSB1210.
5.1 Power Providers
Table 5-1. Summary of TUSB1210 Power Providers(1)
TYPICAL
VOLTAGE (V)
MAXIMUM
CURRENT (mA)
NAME
USAGE
TYPE
VDD15
VDD18
VDD33
Internal
External
Internal
LDO
LDO
LDO
1.5
1.8
3.1
50
30
15
(1) VDD33 may be supplied externally, or by shorting the VDD33 pin to VBAT pin provided VBAT min is in
range [3.2 V : 3.6 V]. Note that the VDD33 LDO will always power-on when the chip is enabled,
irrespective of whether VDD33 is supplied externally or not. In the case the VDD33 pin is not supplied
externally in the application, the electrical specs for this LDO are provided below.
5.1.1 VDD33 Regulator
The VDD33 internal LDO regulator powers the USB PHY, charger detection, and OTG functions of the USB
subchip inside TUSB1210. Table 5-2 describes the regulator characteristics.
VDD33 regulator takes its power from VBAT
.
Since the USB2.0 standard requires data lines to be biased with pullups biased from a supply greater than
3 V, and since VDD33 regulator has an inherent voltage drop from its input, VBAT, to its regulated output,
TUSB1210 will not meet USB 2.0 Standard if operated from a battery whose voltage is lower than 3.3 V.
Table 5-2. VDD33 Internal LDO Regulator Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
3.6
2.5
2.75
3.0
3.1
3.2
3.3
3.4
3.5
MAX UNIT
VINVDD33
Input voltage
VBAT USB
ON mode,
VVDD33 typ + 0.2
4.5
2.6
2.85
3.1
3.2
3.3
3.4
3.5
3.6
15
V
VUSB3V3_VSEL = ‘000
VUSB3V3_VSEL = ‘001
VUSB3V3_VSEL = ‘010
VUSB3V3_VSEL = ‘011 (default)
VUSB3V3_VSEL = ‘100
VUSB3V3_VSEL = ‘101
VUSB3V3_VSEL = ‘110
VUSB3V3_VSEL = ‘111
Active mode
2.4
2.65
2.9
3.0
3.1
3.2
3.3
3.4
VVDD33
Output voltage
V
IVDD33
Rated output current
VBAT USB
mA
Suspend/reset mode
1
5.1.2 VDD18 Supply
The VDD18 supply is powered externally at the VDD18 pin. See Table 8-1 for external components.
5.1.3 VDD15 Regulator
The VDD15 internal LDO regulator powers the USB subchip inside TUSB1210. Table 5-3 describes the
regulator characteristics.
Copyright © 2009–2012, Texas Instruments Incorporated
Power Module
13
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
MAX UNIT
Table 5-3. VDD15 Internal LDO Regulator Characteristics
PARAMETER
Input voltage
TEST CONDITIONS
On mode, VIN VDD15 = VBAT
VINVDD15 min – VINVDD15 max
On mode
MIN
2.7
TYP
3.6
VIN VDD15
VVDD15
IVDD15
4.5
1.65
30
V
V
Output voltage
Rated output current
1.45
1.56
mA
5.2 Power Consumption
Table 5-4 describes the power consumption depending on the use cases.
NOTE
The typical power consumption is obtained in the nominal operating conditions and with the
TUSB1210 standalone.
Table 5-4. Power Consumption
TYPICAL
CONSUMPTION
MODE
CONDITIONS
SUPPLY
UNIT
IVBAT
IVDDIO
IVDD18
ITOTAL
IVBAT
8
3
VBAT = 3.6 V, VDDIO = 1.8 V, VDD18
= 1.8 V, CS = 0 V
OFF Mode
µA
µA
5
16
204
3
IVDDIO
IVDD18
ITOTAL
IVBAT
VBUS = 5 V, VBAT = 3.6 V, VDDIO
1.8 V, No clock
=
Suspend Mode
3
210
24.6
1.89
21.5
48
IVDDIO
IVDD18
ITOTAL
IVBAT
HS USB Operation
(Synchronous Mode)
VBAT = 3.6 V, VDDIO = 1.8 V, VDD18
= 1.8 V, active USB transfer
mA
mA
µA
25.8
1.81
4.06
31.7
237
3
IVDDIO
IVDD18
ITOTAL
IVBAT
FS USB Operation
(Synchronous Mode)
VBAT = 3.6 V, VDDIO = 1.8 V, active
USB transfer
IVDDIO
IVDD18
ITOTAL
RESETB = 0 V, VBUS = 5 V, VBAT
= 3.6 V, VDDIO = 1.8 V, No clock
Reset Mode
3
243
14
Power Module
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
5.3 Power Management
5.3.1 Power On Sequence
5.3.1.1 Timing Diagram
VBAT , VDD33
VDDIO, VDD18
IORST
CS
TVBBDET (10us)
TBGAP (2ms)
ICACT
BGOK
TPWONVDD15 (100us)
VDD15
DIGPOR
CK32K
TCK32K_PWON (125us)
TDELRSTPWR (61us)
CK32KOK
RESETN_PWR
MNTR_(VDD18,VIO)_OK
MNTR_VDD33_OK
(input 60M) CLOCK
RESETB
TDELMNTRVIOEN (91.5us)
TMNTR (183.1us)
TDELVDD33EN (91.5us)
TMNTR (183.1us)
TDELRESETB (244.1us)
TPLL (300us)
PLL 480M LOCKED
DIR
TDEL_RST_DIR (0.54ms)
TDEL_CS_SUPPLYOK (2.84ms)
Figure 5-1. TUSB1210 Power-Up Timing (ULPI Clock Input Mode)
Copyright © 2009–2012, Texas Instruments Incorporated
Power Module
15
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
5.3.2 Timers and Debounce
PARAMETER
COMMENTS
MIN
TYP
2.84
0.54
MAX
4.10
UNIT
ms
TDEL_CS_SUPPLYOK
TDEL_RST_DIR
Chip-select-to-supplies OK delay
RESETB to PHY PLL locked and DIR
falling-edge delay
0.647
ms
TVBBDET
VBAT detection delay
10
2
us
ms
us
us
us
us
us
us
us
us
TBGAP
Bandgap power-on delay
VDD15 power-on delay
32-KHz RC-OSC power-on delay
Power control reset delay
Monitor enable delay
TPWONVDD15
TPWONCK32K
TDELRSTPWR
TDELMNTRVIOEN
TMNTR
100
125
61
91.5
183.1
93.75
244.1
300
Supply monitoring debounce
VDD33 LDO enable delay
RESETB internal delay
PLL lock time
TDELVDD33EN
TDELRESETB
TPLL
16
Power Module
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
6
USB Connectivity
6.1 Timing Parameter Definitions
The timing parameter symbols used in the timing requirement and switching characteristic tables are
created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other
related terminologies have been abbreviated as shown in Table 6-1.
Table 6-1. Timing Parameter Definitions
LOWERCASE SUBSCRIPTS
SYMBOL
PARAMETER
Cycle time (period)
Delay time
C
D
Dis
En
H
Disable time
Enable time
Hold time
Su
START
T
Setup time
Start bit
Transition time
Valid time
V
W
Pulse duration (width)
Unknown, changing, or don't care level
High
X
H
L
Low
V
Valid
IV
Invalid
AE
FE
LE
Z
Active edge
First edge
Last edge
High impedance
6.2 Interface Target Frequencies
Table Table 6-2 assumes testing over the recommended operating conditions.
Table 6-2. TUSB1210 Interface Target Frequencies
IO
INTERFACE DESIGNATION
TARGET
FREQUENCY
1.5 V
INTERFACE
USB
Universal
serial bus
High speed
Full speed
Low speed
480 Mbits/s
12 Mbits/s
1.5 Mbits/s
6.3 USB Transceiver
The TUSB1210 device includes a universal serial bus (USB) on-the-go (OTG) transceiver that supports
USB 480 Mb/s high-speed (HS), 12 Mb/s full-speed (FS), and USB 1.5 Mb/s low-speed (LS) through a 12-
pin UTMI+ low pin interface (ULPI).
Copyright © 2009–2012, Texas Instruments Incorporated
USB Connectivity
17
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
NOTE
LS device mode is not allowed by a USB2.0 HS capable PHY, therefore it is not supported
by TUSB1210. This is clearly stated in USB2.0 standard Chapter 7, page 119, second
paragraph: “A high-speed capable upstream facing transceiver must not support low-speed
signaling mode..” There is also some related commentary in Chapter 7.1.2.3.
6.3.1 TUSB1210 Modes vs ULPI Pin Status
Table 6-3, Table 6-4, and Table 6-5 show the status of each of the 12 ULPI pins including input/output
direction and whether output pins are driven to ‘0’ or to ‘1’, or pulled up/pulled down via internal
pullup/pulldown resistors.
Note that pullup/pulldown resistors are automatically replaced by driven ‘1’/’0’ levels respectively once
internal IORST is released, with the exception of the pullup on STP which is maintained in all modes.
Pin assignment changes in ULPI 3-pin serial mode, ULPI 6-pin serial mode, and UART mode. Unused
pins are tied low in these modes as shown below.
Table 6-3. TUSB1210 Modes vs ULPI Pin Status:ULPI Synchronous Mode Power-Up
ULPI SYNCHRONOUS MODE POWER-UP
UNTIL IORST RELEASE
PLL OFF
PLL ON + STP HIGH
PLL ON + STP LOW
PIN
NO.
PIN NAME
DIR
PU/PD
DIR
PU/PD
DIR
PU/PD
DIR
PU/PD
26
31
2
CLOCK
DIR
Hiz
Hiz
Hiz
Hiz
Hiz
Hiz
Hiz
Hiz
Hiz
Hiz
Hiz
Hiz
PD
PU
PD
PU
PD
PD
PD
PD
PD
PD
PD
PD
I
PD
IO
-
IO
O
-
O, (‘1’)
O, (‘0’)
I
-
O, (‘0’)
-
-
NXT
-
O, (‘0’)
-
O
-
29
3
STP
PU
I
I
I
I
I
I
I
I
I
PU
PD
PD
PD
PD
PD
PD
PD
PD
I
PU
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
O, (‘0’)
O, (‘0’)
O, (‘0’)
O, (‘0’)
O, (‘0’)
O, (‘0’)
O, (‘0’)
O, (‘0’)
-
-
-
-
-
-
-
-
IO
IO
IO
IO
IO
IO
IO
IO
-
-
-
-
-
-
-
-
4
5
6
7
9
10
13
Table 6-4. TUSB1210 Modes vs ULPI Pin Status: USB Suspend Mode
LINK / EXTERNAL RECOMMENDED
SETTING DURING SUSPEND MODE
SUSPEND MODE
PIN NO.
PIN NAME
CLOCK
DIR
DIR
PU/PD
DIR
PU/PD
26
31
2
I
-
O
-
-
-
-
-
O, (‘1’)
O, (‘0’)
I
-
I
NXT
-
PU(1)
-
I
29
3
STP
O, (‘0’)
I
DATA0
O,
(LINESTATE0)
4
DATA1
O,
-
I
-
(LINESTATE1)
5
6
DATA2
DATA3
O, (‘0’)
-
-
I
I
-
-
O, (INT)
(1) Can be disabled by software before entering Suspend Mode to reduce current consumption
USB Connectivity
18
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
Table 6-4. TUSB1210 Modes vs ULPI Pin Status: USB Suspend Mode
(continued)
LINK / EXTERNAL RECOMMENDED
SETTING DURING SUSPEND MODE
SUSPEND MODE
PIN NO.
PIN NAME
DATA4
DIR
PU/PD
DIR
PU/PD
7
9
O, (‘0’)
O, (‘0’)
O, (‘0’)
O, (‘0’)
-
-
-
-
I
I
I
I
-
-
-
-
DATA5
10
13
DATA6
DATA7
Table 6-5. TUSB1210 Modes vs ULPI Pin Status: ULPI 6-Pin Serial Mode and UART Mode
ULPI 6-PIN SERIAL MODE
ULPI 3-PIN SERIAL MODE
UART MODE
PIN NO.
PIN NAME
DIR
IO
O
O
I
PU/PD
PIN NAME
DIR
IO
O
O
I
PU/PD
PIN NAME
CLOCK (1)
DIR
DIR
IO
O
O
I
PU/PD
26
31
2
CLOCK (1)
DIR
-
CLOCK (1)
DIR
-
-
-
-
-
NXT
-
NXT
-
NXT
-
29
3
STP
PU
STP
PU
STP
PU
TX_ENABLE
TX_DAT
TX_SE0
INT
I
-
-
-
-
-
-
-
-
TX_ENABLE
DAT
I
-
-
-
-
-
-
-
-
TXD
I
-
-
-
-
-
-
-
4
I
IO
IO
O
O
O
O
O
RXD
IO
O
O
O
O
O
O
5
I
SE0
tie low
INT
6
O
O
O
O
O
INT
7
RX_DP
RX_DM
RX_RCV
tie low
tie low
tie low
tie low
tie low
tie low
tie low
tie low
tie low
9
10
13
-
6.3.2 ULPI Interface Timing
Table 6-6. ULPI Interface Timing
INPUT CLOCK
OUTPUT CLOCK
MIN
PARAMETER
UNIT
MIN
MAX
MAX
TSC,TSD
TSC,THD
TDC,TDD
Set-up time (control in, 8-bit data in)
Hold time (control in, 8-bit data in)
Output delay (control out, 8-bit data out)
3
6
ns
ns
ns
1.5
0
6
9
6.3.3 PHY Electrical Characteristics
The PHY is the physical signaling layer of the USB 2.0. It essentially contains all the drivers and receivers
required for physical data and protocol signaling on the DP and DM lines.
The PHY interfaces to the USB controller through a standard 12-pin digital interface called UTMI+ low pin
interface (ULPI).
The transmitters and receivers inside the PHY are classified into two main classes.
•
•
The full-speed (FS) and low-speed (LS) transceivers. These are the legacy USB1.x transceivers.
The HS (HS) transceivers
In order to bias the transistors and run the logic, the PHY also contains reference generation circuitry
which consists of:
•
A DPLL which does a frequency multiplication to achieve the 480-MHz low-jitter lock necessary for
USB and also the clock required for the switched capacitor resistance block.
•
A switched capacitor resistance block which is used to replicate an external resistor on chip.
Copyright © 2009–2012, Texas Instruments Incorporated
USB Connectivity
19
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
Built-in pullup and pulldown resistors are used as part of the protocol signaling.
Apart from this, the PHY also contains circuitry which protects it from accidental 5-V short on the DP and
DM lines.
6.3.3.1 LS/FS Single-Ended Receivers
In addition to the differential receiver, there is a single-ended receiver (SE–, SE+) for each of the two data
lines D+/–. The main purpose of the single-ended receivers is to qualify the D+ and D– signals in the full-
speed/low-speed modes of operation.
Table 6-7. LS/FS Single-Ended Receivers
PARAMETER
USB single-ended receivers
Skew between VP and VM
Single-ended hysteresis
High (driven)
COMMENTS
MIN
TYP
MAX
UNIT
SKWVP_VM
VSE_HYS
VIH
Driver outputs unloaded
–2
50
2
0
2
ns
mV
V
VIL
Low
0.8
2
V
VTH
Switching threshold
0.8
V
6.3.3.2 LS/FS Differential Receiver
A differential input receiver (Rx) retrieves the LS/FS differential data signaling. The differential voltage on
the line is converted into digital data by a differential comparator on DP/DM. This data is then sent to a
clock and data recovery circuit which recovers the clock from the data. An additional serial mode exists in
which the differential data is directly output on the RXRCV pin.
Table 6-8. LS/FS Differential Receiver
PARAMETER
COMMENTS
MIN
200
0.8
TYP
MAX
UNIT
mV
V
VDI
Differential input sensitivity
Ref. USB2.0
Ref. USB2.0
VCM Differential Common mode range
2.5
6.3.3.3 LS/FS Transmitter
The USB transceiver (Tx) uses a differential output driver to drive the USB data signal D+/– onto the USB
cable. The driver's outputs support 3-state operation to achieve bidirectional half-duplex transactions.
Table 6-9. LS Transmitter
PARAMETER
COMMENTS
Ref. USB2.0
Ref. USB2.0
MIN
0
TYP
MAX UNIT
VOL
Low
300
3.6
2
mV
V
VOH
VCRS
High (driven)
2.8
1.3
Output signal crossover voltage
Ref. USB2.0, covered by
eye diagram
V
TFR
Rise time
Ref. USB2.0, covered by
eye diagram
75
300
ns
TFF
Fall time
75
80
300
125
ns
%
TFRFM
TFDRATE
Differential rise and fall time matching
Low-speed data rate
Ref. USB2.0, covered by
eye diagram
1.4775
1.5225 Mb/s
TDJ1
Source jitter total (including
frequency tolerance)
To next transition
For paired transitions
Ref. USB2.0, covered by
eye diagram
-25
-10
25
10
ns
us
TDJ2
TFEOPT
Source SE0 interval of EOP
Ref. USB2.0, covered by
eye diagram
1.25
1.5
20
USB Connectivity
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
Table 6-9. LS Transmitter (continued)
PARAMETER
Downstream eye diagram
COMMENTS
MIN
TYP
MAX UNIT
Ref. USB2.0, covered by
eye diagram
VCM
Differential common mode range
Ref. USB2.0
0.8
2.5
V
Copyright © 2009–2012, Texas Instruments Incorporated
USB Connectivity
21
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
MAX UNIT
Table 6-10. FS Transmitter
PARAMETER
COMMENTS
Ref. USB2.0
Ref. USB2.0
MIN
0
TYP
VOL
VOH
Low
300
3.6
2
mV
V
High (driven)
2.8
1.3
Ref. USB2.0, covered by eye
diagram
V
VCRS
Output signal crossover voltage
tFR
Rise time
Ref. USB2.0
Ref. USB2.0
4
4
20
20
ns
ns
%
tFF
Fall time
tFRFM
Differential rise and fall time matching
Ref. USB2.0, covered by eye
diagram
90
111.1
1
ZDRV
Driver output resistance
Ref. USB2.0
28
44
Ω
TFDRATE Full-speed data rate
Ref. USB2.0, covered by eye
diagram
11.97
12.03 Mb/s
TDJ1
To next transition
Ref. USB2.0, covered by eye
diagram
-2
-1
2
1
ns
ns
Source jitter total (including
frequency tolerance)
TDJ2
For paired transitions
TFEOPT
Source SE0 interval of EOP
Downstream eye diagram
Upstream eye diagram
Ref. USB2.0, covered by eye
diagram
160
175
Ref. USB2.0, covered by eye
diagram
6.3.3.4 HS Differential Receiver
The HS receiver consists of the following blocks:
A differential input comparator to receive the serial data
•
•
A squelch detector to qualify the received data
An oversampler-based clock data recovery scheme followed by a NRZI decoder, bit unstuffing, and
serial-to-parallel converter to generate the ULPI DATAOUT
Table 6-11. HS Differential Receiver
PARAMETER
COMMENTS
MIN
TYP
MAX UNIT
VHSSQ
High-speed squelch detection threshold
(differential signal amplitude)
Ref. USB2.0
100
150
mV
mV
mV
mV
ps
VHSDSC High-speed disconnect detection threshold
(differential signal amplitude)
Ref. USB2.0
525
-50
625
High-speed differential input signaling levels
Ref. USB2.0, specified by eye pattern
templates
VHSCM
High-speed data signaling common mode
voltage range (guidelines for receiver)
Ref. USB2.0
500
150
Receiver jitter tolerance
Ref. USB2.0, specified by eye pattern
templates
6.3.3.5 HS Differential Transmitter
The HS transmitter is always operated via the ULPI parallel interface. The parallel data on the interface is
serialized, bit stuffed, NRZI encoded, and transmitted as a dc output current on DP or DM depending on
the data. Each line has an effective 22.5-Ω load to ground, which generates the voltage levels for
signaling.
A disconnect detector is also part of the HS transmitter. A disconnect on the far end of the cable causes
the impedance seen by the transmitter to double thereby doubling the differential amplitude seen on the
DP/DM lines.
22
USB Connectivity
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
Table 6-12. HS Transmitter
PARAMETER
High-speed idle level
COMMENTS
MIN TYP MAX UNIT
VHSOI
VHSOH
VHSOL
Ref. USB2.0
Ref. USB2.0
Ref. USB2.0
Ref. USB2.0
Ref. USB2.0
-10
360
-10
10
440
mV
mV
mV
mV
mV
ps
High-speed data signaling high
High-speed data signaling low
10
VCHIRPJ Chirp J level (differential voltage)
VCHIRPK Chirp K level (differential voltage)
700
-900
500
500
40.5
1100
-500
THSR
Rise Time (10% - 90%)
Fall time (10% - 90%)
Ref. USB2.0, covered by eye diagram
THSR
Ref. USB2.0, covered by eye diagram
Ref. USB2.0
ps
ZHSDRV
Driver output resistance (which also serves as
high-speed termination)
49.5
Ω
THSDRAT High-speed data range
Ref. USB2.0, covered by eye diagram
479.76
480. Mb/s
24
Data source jitter
Ref. USB2.0, covered by eye diagram
Ref. USB2.0, covered by eye diagram
Ref. USB2.0, covered by eye diagram
Downstream eye diagram
Upstream eye diagram
6.3.3.6 UART Transceiver
In this mode, the ULPI data bus is redefined as a 2-pin UART interface, which exchanges data through a
direct access to the FS/LS analog transmitter and receiver.
Table 6-13. USB UART Interface Timing Parameters
PARAMETER
Phone D+ connect time
MIN
100
150
MAX
UNIT
ms
tPH_DP_CON
tPH_DISC_DET
fUART_DFLT
Phone D+ disconnect time
ms
Default UART signaling rate (typical rate)
9600
bps
Figure 6-1. USB UART Data Flow
Table 6-14. CEA-2011/UART Transceiver
PARAMETER
COMMENTS
MIN
TYP
MAX
UNIT
UART Transmitter CEA-2011
Phone UART edge rates
Serial interface output high
Serial interface output low
UART Receiver CEA-2011
Serial interface input high
Serial interface input low
Switching threshold
tPH_UART_EDGE
VOH_SER
DP_PULLDOWN asserted
ISOURCE = 4 mA
ISINK = –4 mA
1
3.6
0.4
Μs
V
2.4
0
3.3
0.1
VOL_SER
V
VIH_SER
VIL_SER
VTH
DP_PULLDOWN asserted
DP_PULLDOWN asserted
2
V
V
V
0.8
2
0.8
Copyright © 2009–2012, Texas Instruments Incorporated
USB Connectivity
23
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
Table 6-15. Pullup/Pulldown Resistors
PARAMETER
COMMENTS
MIN
TYP
MAX UNIT
Bus pullup resistor on upstream port
(idle bus)
Bus idle
0.9
1.1
1.575
3.09
3.6
kΩ
RPUI
Bus pullup resistor on upstream port
(receiving)
Bus driven/driver's outputs unloaded
1.425
2.7
3
2.2
RPUA
High (floating)
Pullups/pulldowns on both DP and
DM lines
V
V
VIHZ
VPH_DP_UP
Phone D+ pullup voltage
Pulldown resistors
Driver's outputs unloaded
3.3
18
3.6
RPH_DP_DWN
RPH_DM_DWN
Phone D+/– pulldown
Driver's outputs unloaded
14.25
2.7
24.8
3.6
kΩ
High (floating)
Pullups/pulldowns on both DP and
DM lines
V
VIHZ
D+/– Data line
CINUB
Upstream facing port
[1.0]
22
75
pF
V
VOTG_DATA_LK On-the-go device leakage
G
[2]
0.342
Input impedance exclusive of
pullup/pulldown
Driver's outputs unloaded
300
kΩ
ZINP
6.3.4 OTG Electrical Characteristics
The on-the-go (OTG) block integrates three main functions:
•
•
•
The USB plug detection function on VBUS and ID
The ID resistor detection
The VBUS level detection
Table 6-16. OTG VBUS Electrical
PARAMETER
COMMENTS
MIN
TYP
MAX UNIT
VBUS Comparators
VA_SESS_VLD
VA_VBUS_VLD
VB_SESS_END
VB_SESS_VLD
VBUS Line
A-device session valid
A-device VBUS valid
B-device session end
B-device session valid
0.8
4.4
0.2
2.1
1.4
2.0
V
V
V
V
4.5 4.625
0.5
2.4
0.8
2.7
RA_BUS_IN
A-device VBUS input impedance to
ground
SRP (VBUS pulsing) capable A-device not
driving VBUS
40
70
100
kΩ
RB_SRP_DWN
RB_SRP_UP
B-device VBUS SRP pulldown
B-device VBUS SRP pullup
5.25 V / 8 mA, Pullup voltage = 3 V
0.656
0.281
10
1
kΩ
kΩ
(5.25 V – 3 V) / 8 mA, Pullup voltage = 3 V
2
tRISE_SRP_UP_MAX B-device VBUS SRP rise time
maximum for OTG-A communication
0 to 2.1 V with < 13 μF load
0.8 to 2.0 V with > 97 μF load
TBD
ms
tRISE_SRP_UP_MIN
B-device VBUS SRP rise time
minimum for standard host
connection
TBD
ms
24
USB Connectivity
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
Table 6-17. OTG ID Electrical
PARAMETER
ID Comparators — ID External Resistors Specifications
COMMENTS
MIN
TYP
MAX
UNIT
RID_GND
ID ground comparator
ID Float comparator
ID Line
ID_GND interrupt
12
20
28
kΩ
kΩ
RID_FLOAT
ID_FLOAT interrupt
200
500
RPH_ID_UP
VPH_ID_UP
Phone ID pullup to VPH_ID_UP
Phone ID pullup voltage
ID line maximum voltage
ID unloaded (VRUSB
)
70
90
286
3.2
kΩ
V
Connected to VRUSB
2.5
5.25
V
Copyright © 2009–2012, Texas Instruments Incorporated
USB Connectivity
25
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
7
I/O Electrical Characteristics
7.1 Analog I/O Electrical Characteristics
Table 7-1. Electrical Characteristics: Analog Output Pins
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
CPEN Output Pin
VOLCPEN CPEN low-level output voltage
VOHCPEN CPEN high-level output voltage
IOL = 3 mA
IOH = -3 mA
0.3
V
V
VDD33-0.3
7.2 Digital I/O Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
VOL (V)
VOH (V)
VIL (V)
VIH (V)
MIN
MAX
LOAD
(pF)
OUTPUT
MODE
MAX
FREQ
(MHz)
MAX
RISE TIME
(ns)
MAX
FALL TIME
(ns)
PIN
NAME
MIN MAX
MIN
MAX
MIN
MAX
MAX
CLOCK
STP
0.45
0.45
0.45
0.45
0.45
0.45
0.45
0.45
0.45
0.45
0.45
0.45
VDDIO-0.45
0.35´VDDIO
0.35´VDDIO
0.35´VDDIO
0.35´VDDIO
0.35´VDDIO
0.35´VDDIO
0.35´VDDIO
0.35´VDDIO
0.35´VDDIO
0.35´VDDIO
0.35´VDDIO
0.35´VDDIO
0.65´VDDIO
60
30
30
30
30
30
30
30
30
30
30
30
10
10
10
10
10
10
10
10
10
10
10
10
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VDDIO-0.45
VDDIO-0.45
VDDIO-0.45
VDDIO-0.45
VDDIO-0.45
VDDIO-0.45
VDDIO-0.45
VDDIO-0.45
VDDIO-0.45
VDDIO-0.45
VDDIO-0.45
0.65´VDDIO
0.65´VDDIO
0.65´VDDIO
0.65´VDDIO
0.65´VDDIO
0.65´VDDIO
0.65´VDDIO
0.65´VDDIO
0.65´VDDIO
0.65´VDDIO
0.65´VDDIO
DIR
NXT
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
7.3 Electrical Characteristics: Digital IO Pins (Non-ULPI)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
CS, CFG, RESETB Input Pins
VIL
CONDITIONS
MIN
TYP
MAX
UNIT
0.35 *
VDDIO
Maximum low-level input voltage
V
V
VIH
Minimum high-level input voltage
0.65*VDDIO
RESETB Input Pin Timing Spec
tw(POR)
Internal power-on reset pulse
width
0.2
8
μs
tw(RESET)
Applied to external RESETB pin when
CLOCK is toggling.
CLOCK
cycles
External RESETB pulse width
26
I/O Electrical Characteristics
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
8
External Components
Table 8-1. TUSB1210 External Components
FUNCTION
COMPONENT
REFERENCE
VALUE
NOTE
LINK
VDDIO
Capacitor
CVDDIO
100 nF
Suggested value, application
dependent
Figure 10-1
VDD33
VDD15
VDD18
Capacitor
Capacitor
Capacitor
CVDD33
CVDD15
2.2 μF
2.2 μF
100 nF
Range: [0.45 μF : 6.5 μF] ,
ESR = [0 : 600 mΩ] for f> 10 kHz
Figure 10-1
Figure 10-1
Figure 10-1
Range: [0.45 μF : 6.5 μF] ,
ESR = [0 : 600 mΩ] for f> 10 kHz
Ext 1.8V supply
CVDD18
Suggested value, application
dependent
VBAT
VBUS
Capacitor
Capacitor
CBYP
100 nF(1)
Range: [0.45 μF : 6.5 μF] ,
ESR = [0 : 600 mΩ] for f> 10 kHz
Figure 10-1
Figure 10-1
CVBUS
See table 1.2
Place close to USB connector
(1) Recommended value but 2.2 uF may be sufficient in some applications
Table 8-2. TUSB1210 VBUS Capacitors
FUNCTION
VBUS - HOST
VBUS – DEVICE
VBUS - OTG
COMPONENT
Capacitor
REFERENCE
CVBUS
VALUE
>120 μF
4.7 μF
NOTE
LINK
Figure 10-1
Figure 10-1
Figure 10-1
Capacitor
CVBUS
Range: 1.0 μF to 10.0 μF
Range: 1.0 μF to 6.5 μF
Capacitor
CVBUS
4.7 μF
Copyright © 2009–2012, Texas Instruments Incorporated
External Components
27
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
9
Register Map
9.1 TUSB1210 Product
Table 9-1. USB Register Summary
REGISTER WIDTH
PHYSICAL
ADDRESS
REGISTER NAME
TYPE
(BITS)
VENDOR_ID_LO
VENDOR_ID_HI
R
8
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19 0x2E
0x2F
0x30 0x3C
0x3D
0x3E
0x3F
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
R
8
PRODUCT_ID_LO
R
8
PRODUCT_ID_HI
R
8
FUNC_CTRL
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
8
FUNC_CTRL_SET
FUNC_CTRL_CLR
IFC_CTRL
8
8
8
IFC_CTRL_SET
8
IFC_CTRL_CLR
8
OTG_CTRL
8
OTG_CTRL_SET
8
OTG_CTRL_CLR
8
USB_INT_EN_RISE
USB_INT_EN_RISE_SET
USB_INT_EN_RISE_CLR
USB_INT_EN_FALL
USB_INT_EN_FALL_SET
USB_INT_EN_FALL_CLR
USB_INT_STS
8
8
8
8
8
8
8
USB_INT_LATCH
R
8
DEBUG
R
8
SCRATCH_REG
RW
RW
RW
R
8
SCRATCH_REG_SET
SCRATCH_REG_CLR
Reserved
8
8
8
ACCESS_EXT_REG_SET
Reserved
RW
R
8
8
VENDOR_SPECIFIC1
VENDOR_SPECIFIC1_SET
VENDOR_SPECIFIC1_CLR
VENDOR_SPECIFIC2
VENDOR_SPECIFIC2_SET
VENDOR_SPECIFIC2_CLR
VENDOR_SPECIFIC1_STS
VENDOR_SPECIFIC1_LATCH
VENDOR_SPECIFIC3
VENDOR_SPECIFIC3_SET
VENDOR_SPECIFIC3_CLR
RW
RW
RW
RW
RW
RW
R
8
8
8
8
8
8
8
R
8
RW
RW
RW
8
8
8
28
Register Map
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
9.1.1 VENDOR_ID_LO
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x00
0x00
INSTANCE
USB_SCUSB
Lower byte of vendor ID supplied by USB-IF (TI Vendor ID = 0x0451)
R
WRITE LATENCY
7
6
5
4
3
2
1
0
VENDOR_ID
DESCRIPTION
BITS
FIELD NAME
VENDOR_ID
TYPE
RESET
7:00
R
0x51
9.1.2 VENDOR_ID_HI
ADDRESS OFFSET
PHYSICAL ADDRESS
0x01
0x01
INSTANCE
USB_SCUSB
DESCRIPTION
TYPE
Upper byte of vendor ID supplied by USB-IF (TI Vendor ID = 0x0451)
R
WRITE LATENCY
7
6
5
4
3
2
1
0
VENDOR_ID
DESCRIPTION
BITS
FIELD NAME
TYPE
RESET
7:00
VEN DOR_ID
R
0x04
9.1.3 PRODUCT_ID_LO
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x02
0x02
INSTANCE
USB_SCUSB
Lower byte of Product ID supplied by Vendor (TUSB1210 Product ID is
0x1507).
TYPE
R
WRITE LATENCY
7
6
5
4
3
2
1
0
PRODUCT_ID
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:00
PRODUCT_ID
R
0x07
Copyright © 2009–2012, Texas Instruments Incorporated
Register Map
29
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
9.1.4 PRODUCT_ID_HI
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x03
0x03
INSTANCE
USB_SCUSB
Upper byte of Product ID supplied by Vendor (TUSB1210 Product ID is
0x1507).
TYPE
R
WRITE LATENCY
7
6
5
4
3
2
1
0
PRODUCT_ID
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
0x15
7:00
PRODUCT_ID
R
9.1.5 FUNC_CTRL
ADDRESS OFFSET
PHYSICAL ADDRESS
0x04
0x04
INSTAN USB_SCUSB
CE
DESCRIPTION
TYPE
Controls UTMI function settings of the PHY.
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
R
RESET
7
6
0
1
SUSPENDM
Active low PHY suspend. Put PHY into Low Power Mode. In Low Power
Mode the PHY power down all blocks except the full speed receiver, OTG
comparators, and the ULPI interface pins. The PHY automatically set this bit
to '1' when Low Power Mode is exited.
RW
5
4:03
2
RESET
Active high transceiver reset. Does not reset the ULPI interface or ULPI
register set.
RW
RW
RW
0
0x0
0
Once set, the PHY asserts the DIR signal and reset the UTMI core. When the
reset is completed, the PHY de-asserts DIR and clears this bit. After de-
asserting DIR, the PHY re-assert DIR and send an RX command update.
Note: This bit is auto-cleared, this explain why it can't be read at '1'.
Select the required bit encoding style during transmit
0x0: Normal operation
OPMODE
0x1: Non-driving
0x2: Disable bit-stuff and NRZI encoding
0x3: Reserved (No SYNC and EOP generation feature not supported)
TERMSELECT
Controls the internal 1.5Kohms pull-up resistor and 45ohms HS terminations.
Control over bus resistors changes depending on XcvrSelect, OpMode,
DpPulldown and DmPulldown.
30
Register Map
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
BITS
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
FIELD NAME
XCVRSELECT
DESCRIPTION
Select the required transceiver speed.
TYPE
RESET
1:00
RW
0x1
0x0: Enable HS transceiver
0x1: Enable FS transceiver
0x2: Enable LS transceiver
0x3: Enable FS transceiver for LS packets
(FS preamble is automatically pre-pended)
9.1.6 FUNC_CTRL_SET
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x05
0x05
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the func_ctrl register with read/set-only property (write '1' to
set a particular bit, a write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
BITS
7
FIELD NAME
DESCRIPTION
TYPE
R
RESET
Reserved
SUSPENDM
RESET
0
1
6
RW
RW
RW
RW
RW
5
0
4:03
2
OPMODE
0x0
0
TERMSELECT
XCVRSELECT
1:00
0x1
9.1.7 FUNC_CTRL_CLR
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x06
0x06
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the func_ctrl register with read/clear-only property (write '1' to
clear a particular bit, a write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
Copyright © 2009–2012, Texas Instruments Incorporated
Register Map
31
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
BITS
7
FIELD NAME
Reserved
DESCRIPTION
TYPE
R
RESET
0
1
6
SUSPENDM
RESET
RW
RW
RW
RW
RW
5
0
4:03
2
OPMODE
0x0
0
TERMSELECT
XCVRSELECT
1:00
0x1
9.1.8 IFC_CTRL
ADDRESS OFFSET
PHYSICAL ADDRESS
0x07
0x07
INSTANCE
USB_SCUSB
DESCRIPTION
TYPE
Enables alternative interfaces and PHY features.
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
6
INTERFACE_PROTECT Controls circuitry built into the PHY for protecting the ULPI interface when the
RW
0
_DISABLE
link tri-states stp and data.
0b: Enables the interface protect circuit
1b: Disables the interface protect circuit
INDICATORPASSTHRU Controls whether the complement output is qualified with the internal
vbusvalid comparator before being used in the VBUS State in the RXCMD.
RW
0
0b: Complement output signal is qualified with the internal VBUSVALID
comparator.
1b: Complement output signal is not qualified with the internal VBUSVALID
comparator.
5
4
INDICATORCOMPLEM Tells the PHY to invert EXTERNALVBUSINDICATOR input signal, generating
RW
RW
0
1
ENT
the complement output.
0b: PHY will not invert signal EXTERNALVBUSINDICATOR (default)
1b: PHY will invert signal EXTERNALVBUSINDICATOR
Enables the PHY to automatically transmit resume signaling.
Refer to USB specification 7.1.7.7 and 7.9 for more details.
0 = AutoResume disabled
AUTORESUME
1 = AutoResume enabled (default)
3
CLOCKSUSPENDM
Active low clock suspend. Valid only in Serial Modes. Powers down the
internal clock circuitry only. Valid only when SuspendM = 1b. The PHY must
ignore ClockSuspend when SuspendM = 0b. By default, the clock will not be
powered in Serial and Carkit Modes.
RW
0
0b : Clock will not be powered in Serial and UART Modes.
1b : Clock will be powered in Serial and UART Modes.
32
Register Map
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
BITS
FIELD NAME
CARKITMODE
DESCRIPTION
TYPE
RESET
2
Changes the ULPI interface to UART interface. The PHY automatically clear
this field when UART mode is exited.
RW
0
0b: UART disabled.
1b: Enable serial UART mode.
1
0
FSLSSERIALMODE_3PI Changes the ULPI interface to 3-pin Serial.
N
RW
RW
0
0
The PHY must automatically clear this field when serial mode is exited.
0b: FS/LS packets are sent using parallel interface
1b: FS/LS packets are sent using 4-pin serial interface
FSLSSERIALMODE_6PI Changes the ULPI interface to 6-pin Serial.
N
The PHY must automatically clear this field when serial mode is exited.
0b: FS/LS packets are sent using parallel interface
1b: FS/LS packets are sent using 6-pin serial interface
9.1.9 IFC_CTRL_SET
ADDRESS OFFSET
0x08
0x08
PHYSICAL ADDRESS
DESCRIPTION
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the ifc_ctrl register with read/set-only property (write '1' to set
a particular bit, a write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
BITS
FIELD NAME
DESCRIPTION
TYPE
RW
RW
RW
RW
RW
RW
RW
R
RESET
7
6
5
4
3
2
1
0
INTERFACE_PROTECT_DISABLE
INDICATORPASSTHRU
INDICATORCOMPLEMENT
AUTORESUME
0
0
0
1
0
0
0
0
CLOCKSUSPENDM
CARKITMODE
FSLSSERIALMODE_3PIN
FSLSSERIALMODE_6PIN
Copyright © 2009–2012, Texas Instruments Incorporated
Register Map
33
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
9.1.10 IFC_CTRL_CLR
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x09
0x09
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the ifc_ctrl register with read/clear-only property (write '1' to
clear a particular bit, a write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
BITS
FIELD NAME
DESCRIPTION
TYPE
RW
RW
RW
RW
RW
RW
RW
R
RESET
7
6
5
4
3
2
1
0
INTERFACE_PROTECT_DISABLE
INDICATORPASSTHRU
INDICATORCOMPLEMENT
AUTORESUME
0
0
0
1
0
0
0
0
CLOCKSUSPENDM
CARKITMODE
FSLSSERIALMODE_3PIN
FSLSSERIALMODE_6PIN
9.1.11 OTG_CTRL
ADDRESS OFFSET
0x0A
0x0A
PHYSICAL ADDRESS
DESCRIPTION
TYPE
INSTANCE
USB_SCUSB
Controls UTMI+ OTG functions of the PHY.
RW
WRITE LATENCY
34
Register Map
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
7
6
5
4
3
2
1
0
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
USEEXTERNALVBUSINDICA Tells the PHY to use an external VBUS over-current indicator.
TOR
RW
0
0b: Use the internal OTG comparator (VA_VBUS_VLD) or internal
VBUS valid indicator (default)
1b: Use external VBUS valid indicator signal.
6
DRVVBUSEXTERNAL
Selects between the internal and the external 5 V VBUS supply.
RW
RW
0
0
0b: Pin17 (CPEN) is disabled (output GND level). TUSB1210 does
not support internal VBUS supply.
1b: Pin17 (CPEN) is set to ‘1’ (output VDD33 voltage level) if
DRVVBUS bit is ‘1’, else Pin17 (CPEN) is disabled (output GND
level) if DRVVBUS bit is ‘0’
5
DRVVBUS
VBUS output control bit
0b : do not drive VBUS
1b : drive 5V on VBUS
Note: Both DRVVBUS and DRVVBUSEXTERNAL bits must be set
to 1 in order to to set Pin17 (CPEN). CPEN pin can be used to
enable an external VBUS supply
4
3
CHRGVBUS
Charge VBUS through a resistor. Used for VBUS pulsing SRP. The
Link must first check that VBUS has been discharged (see
DischrgVbus register bit), and that both D+ and D- data lines have
been low (SE0) for 2ms.
RW
RW
0
0
0b : do not charge VBUS
1b : charge VBUS
DISCHRGVBUS
Discharge VBUS through a resistor. If the Link sets this bit to 1, it
waits for an RX CMD indicating SessEnd has transitioned from 0 to
1, and then resets this bit to 0 to stop the discharge.
0b : do not discharge VBUS
1b : discharge VBUS
2
1
0
DMPULLDOWN
DPPULLDOWN
IDPULLUP
Enables the 15k Ohm pull-down resistor on D-.
0b : Pull-down resistor not connected to D-.
1b : Pull-down resistor connected to D-.
Enables the 15k Ohm pull-down resistor on D+.
0b : Pull-down resistor not connected to D+.
1b : Pull-down resistor connected to D+.
RW
RW
RW
1
1
0
Connects a pull-up to the ID line and enables sampling of the signal
level.
0b : Disable sampling of ID line.
1b : Enable sampling of ID line.
Copyright © 2009–2012, Texas Instruments Incorporated
Register Map
35
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
9.1.12 OTG_CTRL_SET
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x0B
0x0B
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the otg_ctrl register with read/set-only property (write '1' to set
a particular bit, a write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
BITS
FIELD NAME
DESCRIPTION
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RESET
7
6
5
4
3
2
1
0
USEEXTERNALVBUSINDICATOR
DRVVBUSEXTERNAL
DRVVBUS
0
0
0
0
0
1
1
0
CHRGVBUS
DISCHRGVBUS
DMPULLDOWN
DPPULLDOWN
IDPULLUP
9.1.13 OTG_CTRL_CLR
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x0C
0x0C
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the otg_ctrl register with read/Clear-only property (write '1' to
clear a particular bit, a write '0' has no-action).
TYPE
RW
WRITE LATENCY
36
Register Map
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
7
6
5
4
3
2
1
0
BITS
FIELD NAME
DESCRIPTION
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RESET
7
6
5
4
3
2
1
0
USEEXTERNALVBUSINDICATOR
DRVVBUSEXTERNAL
DRVVBUS
0
0
0
0
0
1
1
0
CHRGVBUS
DISCHRGVBUS
DMPULLDOWN
DPPULLDOWN
IDPULLUP
9.1.14 USB_INT_EN_RISE
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x0D
0x0D
INSTANCE
USB_SCUSB
If set, the bits in this register cause an interrupt event notification to be
generated when the corresponding PHY signal changes from low to high. By
default, all transitions are enabled.
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
R
RESET
7
6
5
4
0
0
0
1
Reserved
R
Reserved
R
IDGND_RISE
Generate an interrupt event notification when IdGnd changes from
low to high.
RW
Event is automatically masked if IdPullup bit is clear to 0 and for
50ms after IdPullup is set to 1.
3
SESSEND_RISE
Generate an interrupt event notification when SessEnd changes
from low to high.
RW
1
Copyright © 2009–2012, Texas Instruments Incorporated
Register Map
37
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
2
SESSVALID_RISE
Generate an interrupt event notification when SessValid changes
from low to high. SessValid is the same as UTMI+ AValid.
RW
1
1
0
VBUSVALID_RISE
Generate an interrupt event notification when VbusValid changes
from low to high.
RW
RW
1
1
HOSTDISCONNECT_RISE
Generate an interrupt event notification when Hostdisconnect
changes from low to high. Applicable only in host mode
(DpPulldown and DmPulldown both set to 1b).
9.1.15 USB_INT_EN_RISE_SET
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x0E
0x0E
This register doesn't physically exist.
INSTANCE
USB_SCUSB
It is the same as the usb_int_en_rise register with read/set-only property (write
'1' to set a particular bit, a write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
BITS
FIELD NAME
DESCRIPTION
TYPE
R
RESET
7
6
5
4
3
2
1
0
Reserved
Reserved
0
0
0
1
1
1
1
1
R
Reserved
R
IDGND_RISE
SESSEND_RISE
SESSVALID_RISE
VBUSVALID_RISE
RW
RW
RW
RW
RW
HOSTDISCONNECT_RIS
E
9.1.16 USB_INT_EN_RISE_CLR
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x0F
0x0F
This register doesn't physically exist.
INSTANCE
USB_SCUSB
It is the same as the usb_int_en_rise register with read/clear-only property
(write '1' to clear a particular bit, a write '0' has no-action).
TYPE
RW
WRITE LATENCY
38
Register Map
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
7
6
5
4
3
2
1
0
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
R
RESET
7
6
5
4
3
2
1
0
0
0
0
1
1
1
1
1
Reserved
R
Reserved
R
IDGND_RISE
RW
RW
RW
RW
RW
SESSEND_RISE
SESSVALID_RISE
VBUSVALID_RISE
HOSTDISCONNECT_RISE
9.1.17 USB_INT_EN_FALL
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x10
0x10
INSTANCE
USB_SCUSB
If set, the bits in this register cause an interrupt event notification to be
generated when the corresponding PHY signal changes from low to high. By
default, all transitions are enabled.
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
R
RESET
7
6
5
4
0
0
0
1
Reserved
R
Reserved
R
IDGND_FALL
Generate an interrupt event notification when IdGnd changes
from high to low.
RW
Event is automatically masked if IdPullup bit is clear to 0 and for
50ms after IdPullup is set to 1.
3
2
1
SESSEND_FALL
SESSVALID_FALL
VBUSVALID_FALL
Generate an interrupt event notification when SessEnd changes
from high to low.
RW
RW
RW
1
1
1
Generate an interrupt event notification when SessValid changes
from high to low. SessValid is the same as UTMI+ AValid.
Generate an interrupt event notification when VbusValid changes
from high to low.
Copyright © 2009–2012, Texas Instruments Incorporated
Register Map
39
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
0
HOSTDISCONNECT_FALL
Generate an interrupt event notification when Hostdisconnect
changes from high to low. Applicable only in host mode
(DpPulldown and DmPulldown both set to 1b).
RW
1
9.1.18 USB_INT_EN_FALL_SET
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x11
0x11
This register doesn't physically exist.
INSTANCE
USB_SCUSB
It is the same as the usb_int_en_fall register with read/set-only property (write
'1' to set a particular bit, a write '0' has no-action)
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
R
RESET
7
6
5
4
3
2
1
0
0
0
0
1
1
1
1
1
Reserved
R
Reserved
R
IDGND_FALL
RW
RW
RW
RW
RW
SESSEND_FALL
SESSVALID_FALL
VBUSVALID_FALL
HOSTDISCONNECT_FALL
9.1.19 USB_INT_EN_FALL_CLR
ADDRESS OFFSET
0x12
0x12
PHYSICAL ADDRESS
INSTANC USB_SCUSB
E
DESCRIPTION
This register doesn't physically exist.
It is the same as the usb_int_en_fall register with read/clear-only property
(write '1' to clear a particular bit, a write '0' has no-action).
TYPE
RW
WRITE LATENCY
40
Register Map
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
7
6
5
4
3
2
1
0
BITS
FIELD NAME
DESCRIPTION
TYPE
R
RESET
7
6
5
4
3
2
1
0
Reserved
0
0
0
1
1
1
1
1
Reserved
R
Reserved
R
IDGND_FALL
RW
RW
RW
RW
RW
SESSEN D_FALL
SESSVALID_FALL
VBUSVALID_FALL
HOSTDISCONNECT_FALL
9.1.20 USB_INT_STS
ADDRESS OFFSET
0x13
0x13
PHYSICAL ADDRESS
DESCRIPTION
TYPE
INSTANCE
USB_SCUSB
Indicates the current value of the interrupt source signal.
R
WRITE LATENCY
7
6
5
4
3
2
1
0
Copyright © 2009–2012, Texas Instruments Incorporated
Register Map
41
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
RESET
7
6
5
4
R
R
R
R
0
0
0
0
Reserved
Reserved
IDGND
Current value of UTMI+ IdGnd output.
This bit is not updated if IdPullup bit is reset to 0 and for 50 ms after IdPullup is set to
1.
3
2
1
0
SESSEND
Current value of UTMI+ SessEnd output.
R
R
R
R
0
0
0
0
SESSVALID
VBUSVALID
Current value of UTMI+ SessValid output. SessValid is the same as UTMI+ AValid.
Current value of UTMI+ VbusValid output.
HOSTDISCONNECT Current value of UTMI+ Hostdisconnect output.
Applicable only in host mode.
Automatically reset to 0 when Low Power Mode is entered.
NOTE: Reset value is '0' when host is connected.
Reset value is '1' when host is disconnected.
9.1.21 USB_INT_LATCH
ADDRESS OFFSET
0x14
0x14
PHYSICAL ADDRESS
INSTANC USB_SCUSB
E
DESCRIPTION
These bits are set by the PHY when an unmasked change occurs on the
corresponding internal signal. The PHY will automatically clear all bits when
the Link reads this register, or when Low Power Mode is entered. The PHY
also clears this register when Serial Mode or Carkit Mode is entered regardless
of the value of ClockSuspendM.
The PHY follows the rules defined in Table 26 of the ULPI spec for setting any
latch register bit. It is important to note that if register read data is returned to
the Link in the same cycle that a USB Interrupt Latch bit is to be set, the
interrupt condition is given immediately in the register read data and the Latch
bit is not set.
Note that it is optional for the Link to read the USB Interrupt Latch register in
Synchronous Mode because the RX CMD byte already indicates the interrupt
source directly
TYPE
R
WRITE LATENCY
7
6
5
4
3
2
1
0
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
RESET
7
6
5
4
R
R
R
R
0
0
0
0
Reserved
Reserved
IDGND_LATCH
Set to 1 by the PHY when an unmasked event occurs on IdGnd. Cleared
when this register is read.
42
Register Map
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
BITS
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
FIELD NAME
DESCRIPTION
TYPE
RESET
3
SESSEND_LATCH
Set to 1 by the PHY when an unmasked event occurs on SessEnd.
Cleared when this register is read.
R
0
2
SESSVALID_LATCH
Set to 1 by the PHY when an unmasked event occurs on SessValid.
Cleared when this register is read. SessValid is the same as UTMI+
AValid.
R
0
1
0
VBUSVALID_LATCH
Set to 1 by the PHY when an unmasked event occurs on VbusValid.
Cleared when this register is read.
R
R
0
0
HOSTDISCONNECT_LAT Set to 1 by the PHY when an unmasked event occurs on
CH
Hostdisconnect. Cleared when this register is read. Applicable only in
host mode.
NOTE: As this IT is enabled by default, the reset value depends on the
host status
Reset value is '0' when host is connected.
Reset value is '1' when host is disconnected.
9.1.22 DEBUG
ADDRESS OFFSET
0x15
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x15
INSTANCE USB_SCUSB
Indicates the current value of various signals useful for debugging.
R
WRITE LATENCY
7
6
5
4
3
2
1
0
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
6
Reserved
R
R
R
R
R
R
R
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
LINESTATE
5
0
4
0
3
0
2
0
1:00
These signals reflect the current state of the single ended receivers. They directly
reflect the current state of the DP (LineState[0]) and DM (LineState[1]) signals.
0x0
Read 0x0: SE0 (LS/FS), Squelch (HS/Chirp)
Read 0x1: LS: 'K' State,
FS: 'J' State,
HS: !Squelch,
Chirp: !Squelch & HS_Differential_Receiver_Output
Read 0x2: LS: 'J' State,
FS: 'K' State,
HS: Invalid,
Chirp: !Squelch & !HS_Differential_Receiver_Output
Read 0x3: SE1 (LS/FS), Invalid (HS/Chirp)
9.1.23 SCRATCH_REG
Copyright © 2009–2012, Texas Instruments Incorporated
Register Map
43
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x16
0x16
INSTANCE
USB_SCUSB
Empty register byte for testing purposes. Software can read, write, set, and
clear this register and the PHY functionality will not be affected.
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
SCRATCH
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:00
SCRATCH
Scratch data.
RW
0x00
9.1.24 SCRATCH_REG_SET
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x17
0x17
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the scratch_reg register with read/set-only property (write '1'
to set a particular bit, a write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
SCRATCH
DESCRIPTION
BITS
FIELD NAME
SCRATCH
TYPE
RESET
7:00
RW
0x00
9.1.25 SCRATCH_REG_CLR
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x18
0x18
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the scratch_reg with read/clear-only property (write '1' to clear
a particular bit, a write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
SCRATCH
DESCRIPTION
BITS
FIELD NAME
SCRATCH
TYPE
RESET
7:00
RW
0x00
44
Register Map
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
9.1.26 VENDOR_SPECIFIC1
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x3D
0x3D
INSTANCE
USB_SCUSB
Power Control register .
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
BITS
FIELD NAME
SPARE
DESCRIPTION
Reserved. The link must never write a 1b to this bit.
TYPE
RW
RESET
7
6
0
0
MNTR_VUSBIN_OK_EN When set to 1, it enables RX CMDs for high to low or low to high
transitions on MNTR_VUSBIN_OK. This bit is provided for debugging
purposes.
RW
5
4
ID_FLOAT_EN
When set to 1, it enables RX CMDs for high to low or low to high
transitions on ID_FLOAT. This bit is provided for debugging purposes.
RW
RW
0
0
ID_RES_EN
When set to 1, it enables RX CMDs for high to low or low to high
transitions on ID_RESA, ID_RESB and ID_RESC. This bit is provided for
debugging purposes.
3
2
BVALID_FALL
BVALID_RISE
SPARE
Enables RX CMDs for high to low transitions on BVALID. When BVALID
changes from high to low, the USB TRANS will send an RX CMD to the
link with the alt_int bit set to 1b.
RW
RW
0
0
This bit is optional and is not necessary for OTG devices. This bit is
provided for debugging purposes. Disabled by default.
Enables RX CMDs for low to high transitions on BVALID. When BVALID
changes from low to high, the USB Trans will send an RX CMD to the link
with the alt_int bit set to 1b.
This bit is optional and is not necessary for OTG devices. This bit is
provided for debugging purposes. Disabled by default.
1
0
Reserved. The link must never write a 1b to this bit.
RW
RW
0
0
ABNORMALSTRESS_E When set to 1, it enables RX CMDs for low to high and high to low
N
transitions on ABNORMALSTRESS. This bit is provided for debugging
purposes.
9.1.27 VENDOR_SPECIFIC1_SET
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x3E
0x3E
INSTANCE USB_SCUSB
This register doesn't physically exist.
It is the same as the func_ctrl register with read/set-only property (write '1' to
set a particular bit, a write '0' has no-action).
TYPE
RW
WRITE LATEN CY
Copyright © 2009–2012, Texas Instruments Incorporated
Register Map
45
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
7
6
5
4
3
2
1
0
BITS
FIELD NAME
DESCRIPTION
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RESET
7
6
5
4
3
2
1
0
SPARE
0
0
0
0
0
0
0
0
MNTR_VUSBIN_OK_EN
ID_FLOAT_EN
ID_RES_EN
BVALID_FALL
BVALID_RISE
SPARE
ABNORMALSTRESS_EN
9.1.28 VENDOR_SPECIFIC1_CLR
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x3F
0x3F
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the func_ctrl register with read/clear-only property (write '1' to
clear a particular bit, a write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
BITS
FIELD NAME
DESCRIPTION
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RESET
7
6
5
4
3
2
1
0
SPARE
0
0
0
0
0
0
0
0
MNTR_VUSBIN_OK_EN
ID_FLOAT_EN
ID_RES_EN
BVALID_FALL
BVALID_RISE
SPARE
ABNORMALSTRESS_EN
46
Register Map
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
9.1.29 VENDOR_SPECIFIC2
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x80
0x80
INSTANCE
USB_SCUSB
Eye diagram programmability and DP/DM swap control .
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
IHSTX
BITS
7
FIELD NAME
SPARE
DESCRIPTION
TYPE
RW
RESET
0
1
6
DATAPOLARITY
ZHSDRV
Control data polarity on dp/dm
RW
5:04
High speed output impedance configuration for eye diagram tuning :
RW
0x0
00 45.455 Ω
01 43.779 Ω
10 42.793 Ω
11 42.411 Ω
3:00
IHSTX
High speed output drive strength configuration for eye diagram tuning :
0000 17.928 mA
RW
0x1
0001 18.117 mA
0010 18.306 mA
0011 18.495 mA
0100 18.683 mA
0101 18.872 mA
0110 19.061 mA
0111 19.249 mA
1000 19.438 mA
1001 19.627 mA
1010 19.816 mA
1011 20.004 mA
1100 20.193 mA
1101 20.382 mA
1110 20.570 mA
1111 20.759 mA
IHSTX[0] is also the AC BOOST enable
IHSTX[0] = 0 à AC BOOST is disabled
IHSTX[0] = 1 à AC BOOST is enabled
Copyright © 2009–2012, Texas Instruments Incorporated
Register Map
47
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
9.1.30 VENDOR_SPECIFIC2_SET
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x81
0x81
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the VENDOR_SPECIFIC1 register with read/set-only property
(write '1' to set a particular bit, a write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
IHSTX
BITS
7
FIELD NAME
SPARE
DESCRIPTION
TYPE
RW
RESET
0
6
DATAPOLARITY
ZHSDRV
RW
1
5:04
3:00
RW
0x0
0x1
IHSTX
RW
9.1.31 VENDOR_SPECIFIC2_CLR
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x82
0x82
INSTANCE
USB_SCUSB
This register doesn't physically exist.
It is the same as the VENDOR_SPECIFIC1 register with read/clear-only
property (write '1' to clear a particular bit, a write '0' has no-action).
TYPE
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
IHSTX
BITS
7
FIELD NAME
SPARE
DESCRIPTION
TYPE
RW
RESET
0
6
DATAPOLARITY
ZHSDRV
RW
1
5:04
3:00
RW
0x0
0x1
IHSTX
RW
48
Register Map
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
9.1.32 VENDOR_SPECIFIC1_STS
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x83
0x83
INSTANCE
USB_SCUSB
Indicates the current value of the interrupt source signal.
R
WRITE LATEN CY
7
6
5
4
3
2
1
0
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
R
RESET
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
MNTR_VUSBIN_OK_STS
ABNORMALSTRESS_STS
ID_FLOAT_STS
ID_RESC_STS
Current value of MNTR_VUSBIN_OK output
Current value of ABNORMALSTRESS output
Current value of ID_FLOAT output
Current value of ID_RESC output
R
R
R
R
ID_RESB_STS
Current value of ID_RESB output
R
ID_RESA_STS
Current value of ID_RESA output
R
BVALID_STS
Current value of VB_SESS_VLD output
R
9.1.33 VENDOR_SPECIFIC1_LATCH
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
0x84
0x84
INSTANCE
USB_SCUSB
These bits are set by the PHY when an unmasked change occurs on the
corresponding internal signal. The PHY will automatically clear all bits when
the Link reads this register, or when Low Power Mode is entered. The PHY
also clears this register when Serial mode is entered regardless of the value of
ClockSuspendM.
The PHY follows the rules defined in Table 26 of the ULPI spec for setting any
latch register bit.
TYPE
R
WRITE LATENCY
7
6
5
4
3
2
1
0
Copyright © 2009–2012, Texas Instruments Incorporated
Register Map
49
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE RESET
7
6
R
R
0
0
MNTR_VUSBIN_OK_LATCH
Set to 1 when an unmasked event occurs on MNTR_VUSBIN_OK_LATCH.
Clear on read register.
5
4
3
2
1
0
ABNORMALSTRESS_LATCH Set to 1 when an unmasked event occurs on ABNORMALSTRESS. Clear on
read register.
R
R
R
R
R
R
0
0
0
0
0
0
ID_FLOAT_LATCH
ID_RESC_LATCH
ID_RESB_LATCH
ID_RESA_LATCH
BVALID_LATCH
Set to 1 when an unmasked event occurs on ID_FLOAT. Clear on read
register.
Set to 1 when an unmasked event occurs on ID_RESC. Clear on read
register.
Set to 1 when an unmasked event occurs on ID_RESB. Clear on read
register.
Set to 1 when an unmasked event occurs on ID_RESA. Clear on read
register.
Set to 1 when an unmasked event occurs on VB_SESS_VLD. Clear on read
register.
9.1.34 VENDOR_SPECIFIC3
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x85
0x85
INSTANCE
USB_SCUSB
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
RW
RESET
7
6
0
0
SOF_EN
0: HS USB SOF detector disabled.
RW
1: Enable HS USB SOF detection when PHY is set in device mode.
SOF are output on CPEN pin. HS USB SOF (start-of-frame) output
clock is available on CPEN pin when this bit is set. HS USB SOF
packet rate is 8 kHz.
This bit is provided for debugging purpose only. It must never been
write to ‘1’ in functional mode
5
CPEN_OD
This bit has no effect when CPEN_ODOS = ‘0’, else :
0: CPEN pad is in OS (Open Source) mode.
RW
0
In this case CPEN pin has an internal NMOS driver, and will be active
LOW.
Externally there should be a pullup resistor on CPEN (min 1kohm) to a
supply voltage (max 3.6V).
1: CPEN pad is in OD (Open Drain) mode
In this case CPEN pin has an internal PMOS driver, and will be active
HIGH.
Externally there should be a pull-down resistor on CPEN (min 1 kΩ to
GND.
50
Register Map
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
4
CPEN_ODOS
Mode selection bit for CPEN pin.
0 : CPEN pad is in CMOS mode
RW
0
1: CPEN pad is in OD (Open Drain) or OS (Open Source) mode
(controlled by CPEN_OD bit)
3
IDGND_DRV
Drives ID pin to ground
RW
RW
0x0
0x3
2:00
VUSB3V3_VSEL
000 VRUSB3P1V = 2.5 V
001 VRUSB3P1V = 2.75 V
010 VRUSB3P1V = 3.0 V
011 VRUSB3P1V = 3.10 V (default)
100 VRUSB3P1V = 3.20 V
101 VRUSB3P1V = 3.30 V
110 VRUSB3P1V = 3.40 V
111 VRUSB3P1V = 3.50 V
9.1.35 VENDOR_SPECIFIC3_SET
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x86
0x86
INSTANCE
USB_SCUSB
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
RW
RW
RW
RW
RW
RW
RESET
7
6
0
0
SOF_EN
5
CPEN_OD
0
4
CPEN _ODOS
IDGND_DRV
VUSB3V3_VSEL
0
3
0x0
0x3
2:00
9.1.36 VENDOR_SPECIFIC3_CLR
ADDRESS OFFSET
PHYSICAL ADDRESS
DESCRIPTION
TYPE
0x87
0x87
INSTANCE
USB_SCUSB
RW
WRITE LATENCY
7
6
5
4
3
2
1
0
Copyright © 2009–2012, Texas Instruments Incorporated
Register Map
51
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
RW
RW
RW
RW
RW
RW
RESET
7
6
0
0
SOF_EN
5
CPEN_OD
0
4
CPEN_ODOS
IDGND_DRV
VUSB3V3_VSEL
0
3
0x0
0x3
2:00
52
Register Map
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
10 Application Information
10.1 Host or OTG, ULPI Input Clock Mode Application
Figure 10-1 shows a suggested application diagram for TUSB1210 in the case of ULPI input-clock mode
(60 MHz ULPI clock is provided by link processor), in Host or OTG application. Note this is just one
example, it is of course possible to operate as HOST or OTG while also in ULPI output-clock mode.
Link Controller
TUSB1210
V
Supply
DDIO
CS_OUT
(See Note D)
14
11
27
13
10
9
CFG
CS
RESETB
RESETB
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
STP
(See Note A)
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
STP
17
12
CPEN
7
V
6
DD15
VBUS Switch
EN
5
C
VDD15
22
4
3
29
2
V
5 V
IN OUT
BUS
NXT
NXT
3.1–5.5 V
Supply
31
1
DIR
DIR
(See Note B)
REFCLK
21
CLOCK
V
BAT
C
(See Note C)
20
BYP
26
32
V
Supply
C
CLOCK
DDIO
USB Receptacle
ESD
V
DD33
C
V
VDD33
DDIO
C
VBUS
1.8-V Supply
C
V
BUS
ID
28, 30
VDDIO
V
23
19
18
DD18
ID
25
24
16
15
8
VDD18
DM
DP
DM
DP
N/C
N/C
N/C
N/C
N/C
SHIELD
GND
(See Note E)
GND
A. Pin 11 (CS) : can be tied high to VIO if CS_OUT pin unavailable; Pin 14 (CFG) : tie-high is Don’t Care since ULPI
clock is used in input mode
B. Pin 1 (REFCLK) : must be tied low
C. Ext 3 V supply supported
D. Pin 27 (RESETB) can be tied to VDDIO if unused.
E. Pins labeled N/C (no-connect) are truly no-connect, and can be tied or left floating.
Figure 10-1. Host or OTG, ULPI Input Clock Mode Application Diagram
10.2 Device, ULPI Output Clock Mode Application
Figure 10-2 shows a suggested application diagram for TUSB1210 in the case of ULPI output clock mode
(60 MHz ULPI clock is provided by TUSB1210, while link processor or another external circuit provides
REFCLK), in Device mode application. Note this is just one example, it is of course possible to operate as
Device while also in ULPI input-clock mode. Refer also to Figure 10-1.
Copyright © 2009–2012, Texas Instruments Incorporated
Application Information
53
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
Link Controller
TUSB1210
V
Supply
DDIO
CS_OUT
RESETB
(See Note D)
27
13
10
9
RESETB
14
11
CFG
CS
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
STP
(See Note A)
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
STP
7
17
12
CPEN
6
V
DD15
5
C
4
VDD15
22
3
29
2
V
NXT
BUS
NXT
31
1
DIR
DIR
3.1–5.5 V
Supply
REFCLK
CLKIN
REFCLK
21
V
BAT
(See Note B)
26
C
(See Note C)
20
BYP
CLOCK
V
Supply
C
DDIO
USB Receptacle
ESD
V
32
DD33
V
DDIO
C
1.8-V Supply
C
VDD33
C
VBUS
28, 30
VDDIO
V
V
DD18
BUS
23
19
18
ID
VDD18
25
24
16
15
8
N/C
N/C
N/C
N/C
N/C
DM
DP
DM
DP
SHIELD
GND
(See Note E)
GND
A. Pin 11 (CS) : can be tied high to VIO if CS_OUT pin unavailable; Pin 14 (CFG) : Tied to VDDIO for 26MHz REFCLK
mode here, tie to GND for 19.2MHz mode.
B. Pin 1 (REFCLK) : connect to external 3.3V square-wave reference clock
C. Ext 3 V supply supported
D. Pin 27 (RESETB) can be tied to VDDIO if unused.
E. Pins labeled N/C (no-connect) are truly no-connect, and can be tied or left floating.
Figure 10-2. Device, ULPI Output Clock Mode Application Diagram
54
Application Information
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
11 Glossary
CMOS
DM
Complimentary Metal Oxide Semiconductor
Data manual
DSP
ESD
ESR
hiZ
Digital signal processor
Electrostatic discharge
Equivalent series resistance
High-impedance
High speed
HS
HW
Hardware
IC
Integrated circuit
Identification
ID
IDDQ
IF
Direct drain quiescent current
Interface
IO or I/O
JTAG
LDO
LS
Input/output
Joint test action group, ieee 1149.1 standard
Low dropout regulator
Low speed
NA
Not applicable
OTG
PBGA
PCB
PD
On the go
Plastic ball grid array
Printed circuit board
Pulldown
PLL
Phase locked loop
Polarity
POL
PSRR
PU
Power supply rejection ratio
Pullup
RX
Receive
SW
Software
Copyright © 2009–2012, Texas Instruments Incorporated
Glossary
55
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
SYNC/SYNCHRO Synchronization
SYS
TBD
TRM
TX
System
To be defined
Technical reference manual
Transmit
UART
ULPI
USB
UTMI
Universal asynchronous receiver transmitter
UTMI+ low pin interface
Universal serial bus
USB transceiver macrocell interface
56
Glossary
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TUSB1210
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
12 TUSB1210 Package
12.1 TUSB1210 Standard Package Symbolization
TUSB1210BRHB
Pin 1 Indicator
YMLLLLS
$
Figure 12-1. Printed Device Reference
Table 12-1. TUSB1210 Nomenclature Description
FIELDS
MEANING
P
Marking used to note prototype (X), preproduction (P), or
qualified/production device (Blank)(1)
A
Mask set version descriptor (initial silicon = BLANK, first
silicon revision = A, second silicon revision = B,...)(2)
YM
LLLLS
$
Year month
Lot code
Fab Planning Code
12.2 Package Thermal Resistance Characteristics
Table 12-2 provides the thermal resistance characteristics for the recommended package type RHB (S-
PQFP-N32) used for the TUSB1210 device. Refer to the application report IC Package Thermal Metrics,
TI literature number SPRA953, further details concerning parameter definitions and usage.
Table 12-2. TUSB1210 Thermal Resistance Characteristics
PARAMETER
VALUE
34.72
37.3
UNIT
°C/W
°C/W
°C/W
MEASUREMENT METHOD
EIA/JESD 51-1
No current JEDEC specification(2)
No current JEDEC specification(2)
θJA
Junction-to-ambient thermal resistance
Junction-to-case top thermal resistance(1)
Junction-to-case bottom thermal resistance(3)
θJC top
θJC
bottom
3.6
θJB
Junction-to-board thermal resistance or junction-
to-pin thermal resistance
10.3
0.5
°C/W
°C/W
°C/W
EIA/ JESD 51-8.
EIA/JESD 51-2
EIA/JESD 51-6
ΨJT
Junction-to-top of package (not a true thermal
resistance)
ΨJB
Junction-to-board (not a true thermal resistance)
10.5
(1) Top is surface of the package facing away from the PCB.
(2) Refer to measurement method in Chapter 2 of IC Package Thermal Metrics, TI literature number SPRA953.
(3) Bottom surface is the surface of the package facing towards the PCB.
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
TUSB1210 Package
57
Product Folder Links: TUSB1210
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jul-2013
PACKAGING INFORMATION
Orderable Device
TUSB1210BRHBR
TUSB1210BRHBT
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
VQFN
VQFN
RHB
32
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
T1210B
T1210B
ACTIVE
RHB
250
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TUSB1210BRHBR
TUSB1210BRHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.5
1.5
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jul-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TUSB1210BRHBR
TUSB1210BRHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
Video and Imaging
www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明