TUSB2E22 [TI]
USB 2.0-eUSB2 双路中继器;
| 型号： | TUSB2E22 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | USB 2.0-eUSB2 双路中继器 中继器 |
| 文件： | 总26页 (文件大小：649K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TUSB2E22
SNLS648A –FEBRUARY 2019–REVISED DECEMBER 2019
TUSB2E22 eUSB2-USB 2.0 Dual Repeater
1 Features
3 Description
TUSB2E22 enables implementation of USB 2.0
compliance port on newer processors using lower
voltage processes.
1
•
•
Compliance to USB 2.0 and eUSB2 (rev 1.1)
Support for Low-speed (LS), Full-speed (FS),
High-speed (HS)
TUSB2E22 is a USB-Compliant eUSB2-USB 2.0
repeater supporting both device and host modes.
•
•
•
Dual repeater with 2:2 crossbar Mux
Host and device mode (DRD) support
TUSB2E22 supports USB Low-speed (LS) and Full-
speed (FS) signals and High-speed (HS) signals.
4 eUSB2 compensation settings to meet different
system requirements
TUSB2E22 is designed to interface with eUSB2
eDSPr or eUSPr operating at 1.2 V single-ended
signaling.
•
eUSB2 LS/FS signaling meets 1.2 V option of the
eUSB2 interface
TUSB2E22 has 4 levels of compensation settings via
EQ0 and EQ1 pins. These settings could be used to
optimize compensation for different eUSB2 channel
loss profiles.
2 Applications
•
•
•
•
•
Notebooks and desktops
Cell phones
Tablets
(1)
Device Information
Wearables
PART NUMBER PACKAGE
BODY SIZE (NOM)
Portable electronics
TUSB2E22 DSBGA (25) 2.0 mm x 2.0 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
CROSS
Repeater
Connector
EQ0
EQ1
Port
Protection
(Optional)
2x2
CrossPoint
Mux
RESETB
eUSB0
eUSB2 t USB 2.0
Repeater 0
AP
USBA
USBB
USBA
USBB
eUSB2 t USB 2.0
Repeater 1
eUSB1
VDD3V3
VDD1V8
VSS
TUSB2E22
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB2E22
SNLS648A –FEBRUARY 2019–REVISED DECEMBER 2019
www.ti.com
Table of Contents
10.1 Application Information.......................................... 13
10.2 Typical Dual Port System Implementation............ 13
10.3 Design Requirements............................................ 13
10.4 Detailed Design Procedure ................................... 14
10.5 Application Curve.................................................. 14
11 Power Supply Recommendations ..................... 14
11.1 Power Up Reset.................................................... 14
12 Layout................................................................... 15
12.1 Layout Guidelines ................................................. 15
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Simplified Schematic............................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 6
7.6 Switching Characteristics.......................................... 9
7.7 Timing Requirements.............................................. 10
Parametric Measurement Information ............... 10
Detailed Description ............................................ 11
9.1 Overview ................................................................. 11
9.2 Functional Block Diagram ....................................... 11
9.3 Feature Description................................................. 12
9.4 Device Functional Modes........................................ 12
12.2 Example Layout For Application With No Cross
MUX Function. ......................................................... 16
13 Device and Documentation Support ................. 17
13.1 Related Links ........................................................ 17
13.2 Receiving Notification of Documentation Updates 17
13.3 Support Resources ............................................... 17
13.4 Trademarks........................................................... 17
13.5 Electrostatic Discharge Caution............................ 17
13.6 Glossary................................................................ 17
8
9
14 Mechanical, Packaging, and Orderable
Information ........................................................... 17
14.1 Package Option Addendum .................................. 18
10 Applications and Implementation...................... 13
5 Revision History
DATE
REVISION
NOTE
December 2019
*
Initial public release
2
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TUSB2E22
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SNLS648A –FEBRUARY 2019–REVISED DECEMBER 2019
6 Pin Configuration and Functions
25-YCG (2.0 mm x 2.0 mm)
Top View
1
2
3
4
5
eDP0
RSVD1
RSVD2
RSVD3
VDD1V8
VSS
DPA
A
B
C
D
E
eDN0
VDD3V3
CROSS
VDD3V3
EQ0
VSS
DNA
VSS
VDD1V8
VSS
eDN1
VSS
VDD1V8
DNB
eDP1
EQ1
RESETB
DPB
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SNLS648A –FEBRUARY 2019–REVISED DECEMBER 2019
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Pin Functions
PIN
ASSOCIAT
ED ESD
SUPPLY
RESET
I/O
DESCRIPTION
STATE
NAME
NO.
VDD3V3
VDD1V8
VSS
B2, D2
PWR
PWR
GND
N/A
N/A
N/A
N/A
N/A
N/A
3.3V Supply Voltage
1.8V Analog Supply Voltage
GND
C3, B4, D4
C1, C4, B3, D3, C5
Active Low Reset. Upon de-assertion of RESETB both repeaters will be enabled
and be in eUSB2 default mode awaiting configuration from eDSPr or eUSPr.
RESETB
E4
Digital Input N/A
VDD1V8
Indicates mux orientation. Used to specify orientation of internal Crossbar switch
CROSS = Low: eUSB0 «–» USBA and eUSB1 «–» USBB
CROSS = High: eUSB0 «–» USBB and eUSB1«–» USBA
Sampled at de-assertion of RESETB
CROSS
C2
Digital Input N/A
VDD3V3
RSVD1
RSVD2
A2
A3
Digital I/O Hi-Z
Digital I/O Hi-Z
VDD3V3
VDD3V3
Reserved pins connect 1 kΩ pull up to 1.8V
Reserved pins connect 1 kΩ pull up to 1.8V
Digital
Hi-Z
RSVD3
EQ0
A4
E2
VDD3V3
Reserved pin leave it unconnected
Output
Digital I/O Hi-Z (input) VDD3V3
Compensation Level 0: EQ1=low EQ0= low
Compensation Level 1: EQ1=low EQ0=high
Compensation Level 2: EQ1=high EQ0=low
Compensation Level 3: EQ1=high EQ0=high
Pins are sampled at RESETB de-assertion
EQ1
E3
Digital I/O Hi-Z (input) VDD3V3
eDP0
eDN0
eDN1
eDP1
DPA
A1
B1
D1
E1
A5
B5
D5
E5
Analog I/O Hi-Z
Analog I/O Hi-Z
Analog I/O Hi-Z
Analog I/O Hi-Z
Analog I/O Hi-Z
Analog I/O Hi-Z
Analog I/O Hi-Z
Analog I/O Hi-Z
VDD1V8
VDD1V8
VDD1V8
VDD1V8
VDD3V3
VDD3V3
VDD3V3
VDD3V3
eUSB2 port 0 D+ pin
eUSB2 port 0 D- pin
eUSB2 port 1 D- pin
eUSB2 port 1 D+ pin
USB port A D+ pin
USB port A D- pin
USB port B D- pin
USB port B D+ pin
DNA
DNB
DPB
4
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SNLS648A –FEBRUARY 2019–REVISED DECEMBER 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply voltage
VDD3V3
–0.3
4.32
V
range
Analog Supply
VDD1V8
–0.3
–0.3
2.1
6
V
V
voltage range
DPA, DNA, DPB, DNB, 1000 total number of short events and
Voltage range
cummulative duration of 1000 hrs.
Voltage range
Voltage range
eDP0, eDN0, eDP1, eDN1
–0.3
–0.3
1.6
2.1
V
V
CROSS, RESETB, RSVD1, RSVD2, RSVD3, EQ1, EQ0
Junction
temperature
TJ(max)
Tstg
125
150
°C
°C
Storage
temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±1500
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.0
NOM
3.3
MAX
3.6
UNIT
V
VDD3V3
VDD1V8
TA
Supply voltage (VDD3V3)
Analog Supply voltage (VDD1V8)
Operating free-air temperature
Junction temperature
1.62
-20
-20
-20
-20
1.8
1.98
85
V
°C
°C
°C
°C
TJ
105
105
92
TCASE
TPCB
Case temperature
PCB temperature (1mm away from the device)
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SNLS648A –FEBRUARY 2019–REVISED DECEMBER 2019
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7.4 Thermal Information
TUSB2E22
YCG (DSBGA)
25 PINS
73.5
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
0.4
18.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.2
ΨJB
18.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DIGITAL INPUTS
VIH
VIL
VIL
VIH
High level input voltage
Low-level input voltage
Low-level input voltage
High level input voltage
CROSS, EQ1, EQ0
1.053
V
CROSS, EQ1, EQ0
RESETB
0.693
0.35
V
V
V
RESETB
0.75
VIH = 1.98V, VDD3V3=3.0V or 0V,
VDD1V8=1.62V or 0V
CROSS, RESETB, EQ1, EQ0
IIH
High level input current
Low level input current
2
2
µA
µA
VIL = 0V, VDD3V3=3.0V or 0V,
VDD1V8=1.62V or 0V
IIL
CROSS, RESETB, EQ1, EQ0
USBA (DPA, DNA), USBB (DPB, DNB)
Zinp_Dx Impedance to GND, no pull up/down
RPUI
RPUR
RPD
Vin=3.6V, VDD3V3=3.0V USB 2.0 Spec
Section 7.1.6
390
0.92
kΩ
kΩ
kΩ
kΩ
Bus Pull-up Resistor on Upstream Facing
Port (idle)
USB 2.0 Spec Section 7.1.5
USB 2.0 Spec Section 7.1.5
USB 2.0 Spec Section 7.1.5
1.1
2.2
19
1.475
2.99
24.6
Bus Pull-up Resistor on Upstream Facing
Port (receiving)
1.525
14.35
Bus Pull-down Resistor on Downstream
Facing Port
USB 2.0 Spec Section 7.1.6.2, The
output voltage in the high-speed idle
state
VHSTERM
Termination voltage in highspeed
–10
10
mV
USB TERMINATION
Driver Output Resistance (which also
serves as high speed termination)
USBA, USBB INPUT LEVELS LS/FS
(VOH= 0 to 600mV) USB 2.0 Spec
Section 7.1.1.1,
ZHSTERM
40.5
45
49.5
Ω
USB 2.0 Spec Section 7.1.4 (measured
at connector)
VIH
High (driven)
2
V
USB 2.0 Spec Section 7.1.4 (HOST
downstream port pull down resistor
enabled and external device pull up 1.5K
+/-5% to 3.0-3.6V).
VIHZ
High (floating)
Low
2.7
3.6
0.8
V
V
VIL
USB 2.0 Spec Section 7.1.4
USBA, USBB OUTPUT LEVELS LS/FS
USB 2.0 Spec Section 7.1.1, (measured
at connector with RL of 1.425 kΩ to 3.6
V. )
VOL
Low
0
0.3
V
6
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
USB 2.0 Spec Section 7.1.1 (measured
at connector with RL of 14.25 kΩ to
GND. )
VOH
High (Driven)
2.8
3.6
44
2
V
Ω
V
USB 2.0 Spec Section 7.1.1, Measured it
during VOL or VOH
ZFSTERM
Driver Series Output Resistance
Output Signal Crossover Voltage
28
Measured as in USB 2.0 Spec Section
7.1.1 Figure 7-8; Excluding the first
transition from the Idle state
VCRS
1.3
USBA, USBB OUTPUT LEVELS HS
USB 2.0 Spec Section 7.1.7.2, measured
single ended peak voltage per USB 2.0
test measurement spec, Test load is an
ideal 45ohm to GND on DP and DN
VHSOH
High-speed data signaling high
360
440
mV
High-speed data signaling low, driver is
off termination is on (measured single
ended)
USB 2.0 Spec Section 7.1.7.2,Test load
is an ideal 45ohm to GND on DP and
DN.
VHSOL
–10
700
10
mV
mV
USB 2.0 Spec Section 7.1.7.2 , Test load
is an ideal 45ohm to GND on DP and
DN.
VCHIRPJ
Chirp J level (differential voltage)
900
1100
USB 2.0 Spec Section 7.1.7.2 , Test load
is an ideal 45ohm to GND on DP and
DN.
VCHIRPK
Chirp K level (differential voltage)
High-speed TX DC Common Mode
-900
-50
-700
200
-500
500
mV
mV
U2_TXCM
eUSB2 TERMINATION
High speed transmit source termination
impedance
RSRC_HS
ΔRSRC_HS
RRCV_DIF
eUSB2 Spec Section 7.1.1
33
40
47
4
Ω
Ω
Ω
High speed source impedance mismatch eUSB2 Spec Section 7.1.1
High speed differential receiver
eUSB2 Spec Section 7.1.2
termination (repeater)
74
6
80
8
86
eUSB2 Spec Section 7.3, active during
LS, FS and HS
RPD
Pull-down resistors on eDP/eDN
10
59
kΩ
eUSB2 Spec Section 7.2.1, Table 7-13
TX output impedance to match spec
version 1.10
RSRC_LSFS
Transmit output impedance
28
44
Ω
eUSB0, eUSB1 FS/LS INPUT LEVELS
VIL
Single-ended input low
Single-ended input high
eUSB2 Spec Section 7.2.1, Table 7-13
eUSB2 Spec Section 7.2.1, Table 7-13
–0.1
0.819
43.2
0.399
1.386
V
V
VIH
VHYS
Receive single-ended hysteresis voltage eUSB2 Spec Section 7.2.1, Table 7-13
mV
eUSB0, eUSB1 FS/LS OUTPUT LEVELS
VOL
VOH
Single-ended output low
Single-ended output high
eUSB2 Spec Section 7.2.1, Table 7-13
eUSB2 Spec Section 7.2.1, Table 7-13
0.198
1.32
V
V
0.918
280
eUSB0, eUSB1 HS INPUT LEVELS
VRX_CM Receive DC common mode range (low)
VRX_CM
eUSB2 Spec Section 7.1.2 (normative),
low DC common mode RX must tolerate
120
mV
mV
eUSB2 Spec Section 7.1.2 (normative),
high DC common mode RX must tolerate
Receive DC common mode range (high)
eUSB2 Spec Section 7.1.2 (informative),
across the DC common mode range of
120mV to 280mV. (RX capability tested
with intentional TX Rise/Fall Time
Receiver AC common mode (50MHz-
480MHz)
VCM_RX_AC
–60
15
60
50
mV
pF
mismatch and prop delay mismatch)
CRX_CM
Receive center-tapped capacitance
eUSB2 Spec Section 7.1.2 (informative)
VRX_DIF_SEN Receive differential sensitivity, RX should eUSB2 Spec Section 7.1.2, VCM
=
120 mVp-p
be able to receive less than this value.
120mV to 450mV
S
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
eUSB0, eUSB1 HS OUTPUT LEVELS
eUSB2 Spec Section 7.1.1, An ideal 80Ω
Rx differential termination and center tap
cap of 15pF, with maximum DC common
mode range
VETX_CM_AC Transmit CM AC (50MHz-480MHz)
–30
30
mV
Measured p2p, RL = 80 Ω, ideal 80Ω Rx
differential termination load
VEHSOD
Transmit differential (terminated)
Transmit DC common mode
400
mV
mV
VE_TX_CM
eUSB2 Spec Section 7.1.1
170
230
8
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7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DPA, DNA, DPB, DNB, FS Driver Switching Characteristics
TFR
TFF
Rise Time (10% - 90%)
Fall Time (10% - 90%)
USB 2.0 Spec Figure 7-8; Figure 7-9
USB 2.0 Spec Figure 7-8; Figure 7-9
4
4
20
20
ns
ns
USB 2.0 Spec 7.1.2, Excluding the first
transition from the Idle state
TFRFM
(TFR/TFM
)
90
111.1
%
DPA, DNA, DPB , DNB, LS Driver Switching Characteristics
TLR
TLF
Rise Time (10% - 90%)
Fall Time (10% - 90%)
USB 2.0 Spec Figure 7-8
USB 2.0 Spec Figure 7-8
75
75
300
300
ns
ns
eDP0, eDN0, eDP1, eDN1, HS Driver Switching Characteristics
eUSB2 Spec Section 7.2.1,
TEHSRF_
MM
Rise/fall mismatch = absolute delta of
(rise – fall time) / (average of rise and fall
time).
Transmit rise/fall mismatch
25
%
eDP0, eDN0, eDP1, eDN1, LS/FS Driver Switching Characteristics
TERF
Rise/Fall Time (10% - 90%)
eUSB2 Spec Section 7.2.1
eUSB2 Spec Section 7.2.1
2
6
ns
%
TERF_MM Transmit rise/fall mismatch
25
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UNIT
7.7 Timing Requirements
MIN
NOM
MAX
RESET TIMING
t_VDD1V8_R
AMP
Ramp time for VDD1V8 to reach minimum 1.62V
2
2
ms
ms
t_VDD3V3_R
AMP
Ramp time for VDD3V3 to reach minimum 3.0V
t_su_CROSS Setup time for CROSS sampled at the de-assertion of RESETB
0
3
ms
ms
us
t_hd_CROSS Hold time for CROSS sampled at the de-assertion of RESETB
t_aRESETB
duration for RESETB to be asserted low to complete reset while powered
Time for eUSB2 interface to be ready after RESETB is de-asserted or
10
t_RH_READY (VDD1V8 and VDD3V3) reach minimum recommended voltages, whichever
is later
3
ms
8 Parametric Measurement Information
eUSB2
USB 2.0
22.1 ꢀ
15.8 ꢀ
15.8 ꢀ
86100
Scope
or
81130A
Pattern Generator
or
Repeater
Test Channel
BERT
Test Channel
BERT
22.1 ꢀ
50Ω
50Ω
40Ω
45Ω
USB 2.0 High speed test packets
Vin * 0.76
Vin scaled for impedance conversion
Impedance
conversion
Impedance
conversion
eUSB2 TX Vpp * 0.56
Vout scaled for impedance conversion
Figure 1. USB 2.0 TX Output (Egress) Jitter, Eye Mask Test Setup
eUSB2 USB 2.0
22.1 ꢀ
22.1 ꢀ
15.8 ꢀ
15.8 ꢀ
81130A
Pattern Generator
or
86100
Scope
or
Repeater
Test Channel
Test Channel
BERT
BERT
50Ω
50Ω
40Ω
45Ω
USB 2.0 High speed test packets
Impedance
conversion
Impedance
conversion
Vin * 0.693
Vin scaled for impedance conversion
USB 2.0 TX Vpp * 0.68
Vout scaled for impedance conversion
Figure 2. eUSB2 TX Output (Ingress) Jitter, Eye Mask Test Setup
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9 Detailed Description
9.1 Overview
The TUSB2E22 is a dual eUSB2 to USB 2.0 repeater that resides between SoC with one or two eUSB2 port and
an external connector that supports USB 2.0. Each repeater is independently configurable as either a host or
device repeater (DRD repeater).
The USB 2.0 ports A and B can be swapped by an internal crossbar switch by configuring CROSS pin at reset.
CROSS pin is ignored after power up reset.
9.2 Functional Block Diagram
VDD3V3 VDD1V8
Common Module
Power System
LDOs
Clock & Reset
Reference System
Bandgap IREF
Power System
LDOs
Internal
Oscillator
PoR
eUSB2
Phy
USB2.0
Phy
USB/eUSB2 Translator &
State Machine
2x2
CrossPoint
Mux
eDP0
eDN0
DPA
DNA
eUSB0
USBA
CROSS
eUSB2
Phy
USB2.0
Phy
eDN1
eDP1
DNB
DPB
eUSB1
USBB
USB/eUSB2 Translator &
State Machine
RESETB
EQ1
EQ0
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9.3 Feature Description
9.3.1 USB 2.0
TUSB2E22 supports two USB 2.0 ports. Each port supports Low Speed, Full Speed and High Speed operations.
9.3.2 eUSB2
TUSB2E22 supports ttwo eUSB2 ports with 1.2V single ended signaling. Each port support Low Speed, Full
Speed and High Speed operations.
9.3.3 Cross MUX
TUSB2E22 supports a cross mux functionality that can map either of the two eUSB2 ports to the two USB 2.0
ports providing design flexibility.
9.4 Device Functional Modes
9.4.1 Repeater Mode
Upon de-assertion of RESETB and after t_RH_READY , TUSB2E22 will enable and enter default state and be ready
to accept eUSB2 packets.
Table 1. Number of Hubs Supported with Host and/or Peripheral Repeater
Number of eUSB2
Repeaters
Number of Hubs
Operating at HS
Number of Hubs
Operating at FS
1
2
0
4
3
5
2
1
5
Number of hubs operating at FS is reduced due to
Te_to_U_DJ1 and TRJR1
Number of hubs operating at HS is reduced due to
SOP truncation and EOP dribble
.
non-eUSB2 system for reference
9.4.2 Power Down Mode
RESETB could be used as a power down pin when asserted low. Power down mode will put TUSB2E22 in
lowest power mode.
9.4.3 CROSS
CROSS pin will control the orientation of the integrated cross bar mux.
Upon de-assertion of RESETB followed by internally generated reset signal and 1ms delay, CROSS pin is
sampled and latched.
The system needs to make sure that CROSS meets t_su_CROSS and t_hd_CROSS with respect to power supply ramp
and RESETB de-assertion per Power Supply Recommendations.
Changes to the state of the CROSS input while RESETB is high will be ignored
Table 2. eUSB2 to USB Mapping
CROSS = 0
CROSS = 1
eUSB0 (eDP0, eDN0)
eUSB1 (eDP1, eDN1)
USBA (DPA, DNA)
USBB (DPB, DNB)
USBB (DPB, DNB)
USBA (DPA, DNA)
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10 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
TUSB2E22 can be used in either HOST or Peripheral implementation. The mode is configured by the eUSB2
SoC.
10.2 Typical Dual Port System Implementation
VDD18
VDD12
0.1uF+
0.1uF+
VDD18
VDD33
1k
1k
0.1uF+
0.1uF+
+ Decoupling capacitorsof
0.1uF should be placed
less than 2mm from the
power supply balls.
APU
RSVD2
RSVD1
VDD1V8 VDD1V8
RSVD1
VDD3V3 VDD3V3
RSVD2
RSVD3
Connector 1
DP
DN
eDP0
eDN0
DPA
DNA
Repeater
VBUS
VBUS
DN
DP
eDN1
eDP1
DNB
DPB
VSS
EQ0
EQ1
RESETB
CROSS
Connector 2
10k* 10k*
GND
*Pull Up and Pull Down
Resistor Options
CROSS
10k*
10k*
RESETB
Figure 3. Typical Dual Port System Implementation
10.3 Design Requirements
TUSB2E22 supports the 1.2V option of the eUSB2 specification. eUSB2 SoC must be compliant to the 1.2V
option of the eUSB2 specification.
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10.4 Detailed Design Procedure
TUSB2E22 has four loss compensation settings for high speed operation and proper setting should be selected
to match the system loss profile to optimize jitter performance. USB 2.0 high speed eye diagram measurements
could be used as a guide to confirm the loss compensation is optimum for a given system.
10.5 Application Curve
Figure 4. Typical USB 2.0 High Speed Eye Diagram
11 Power Supply Recommendations
11.1 Power Up Reset
RESETB pin is active low reset pin and can also be used as a power down pin.
TUSB2E22 does not have power supply sequence requirements between VDD3V3 and VDD1V8.
Maximum VDD3V3 and VDD1V8 ramp time to reach minimum supply voltages should be 2ms.
Internal power on reset circuit along with the external RESETB input pin ensures proper initialization when
RESETB is de-asserted high prior to the power rails being valid. If RESETB de-assert high before the power
supplies are stable, internal power on reset circuit will hold off internal reset until the supplies are stable.
Upon de-assertion of RESETB followed by internally generated reset signal and 1ms delay, CROSS pin is
sampled and latched.
Upon de-assertion of RESETB and after t_RH_READY, TUSB2E22 will enable and enter default state and be ready
to accept eUSB2 packets. Each repeater will either be in host repeater mode or device repeater mode depending
on the receipt of either host mode enable or peripheral mode enable.
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12 Layout
12.1 Layout Guidelines
1. Place supply bypass capacitors as close to VDD1V8 and VDD3V3 pins as possible and avoid placing the
bypass caps near the eDP/eDN and DP/DN traces.
2. Route the high-speed USB signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points on twisted
pair lines; through-hole pins are not recommended.
3. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
4. Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices or ICs that use or duplicate clock signals.
5. Avoid stubs on the high-speed USB signals due to signal reflections. If a stub is unavoidable, then the stub
must be less than 200 mil
6. Route all high-speed USB signal traces over continuous GND planes, with no interruptions.
7. Avoid crossing over anti-etch, commonly found with plane splits.
8. Due to high frequencies associated with the USB, a printed circuit board with at least four layers is
recommended; two signal layers separated by a ground and power layer as shown in . Figure 5
Signal 1
GND Plane
Power Plane
Signal 2
Figure 5. Four-Layer Board Stack-Up
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12.2 Example Layout For Application With No Cross MUX Function.
VDD18
VDD18
1k
1k
Via to
VDD33
Plane
Via to
VDD18
Plane
Via to
GND
Plane
VDD33
VDD18
GND
eDP0
RSVD1
RSVD2
GND
RSVD3
DPA
eDP0
DPA
DNA
SoC
USB 2.0
eUSB2
Port 0
connector A
eDN0
VDD33
VDD18
DNA
eDN0
0.1uF
0.1uF
VDD18
GND
GND
CROSS
VSS
GND
GND
GND
GND
GND
GND
0.1uF
0.1uF
VDD18
VDD33
GND
eDN1
DNB
eDN1
eDP1
DNB
DPB
SoC
eUSB2
Port 1
USB 2.0
connector B
eDP1
EQ0
EQ1
RESETB
DPB
*Pull Up and Pull Down
Resistor Options
VDD18
VDD18
10k*
10k*
10k*
10k*
Reset
control
from
SoC
GND
GND
Figure 6. Example Layout of Application With No Cross MUX Function
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13 Device and Documentation Support
13.1 Related Links
For related documentation see the following:
•
•
•
USB 2.0 Board Design and Layout Guidelines
High-Speed Layout Guidelines Application Report
High-Speed Interface Layout Guidelines
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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14.1 Package Option Addendum
14.1.1 Packaging Information
Package
Type
Package
Drawing
Package
Qty
Lead/Ball
Finish(3)
(1)
(2)
(4)
Orderable Device
Status
Pins
Eco Plan
MSL Peak Temp
Op Temp (°C)
Device Marking(5)(6)
2E
TUSB2E22YCGR
PREVIEW
DSBGA
YCG
25
3000
Green
SAC396
MSL1, 250°C
-20°C - 85°C
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
(3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
(4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
(5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
(6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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14.1.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
TUSB2E22
DSBGA
YCG
25
3000
180
8.4
2.17
2.17
0.6
4
8
Q1
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
Package Drawing Pins
YCG 25
SPQ
Length (mm) Width (mm)
182 182
Height (mm)
TUSB2E22
DSBGA
3000
20
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PACKAGE OUTLINE
YCG0025
DSBGA - 0.5 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
D: Max = 2.02 mm, Min = 1.98 mm
E: Max = 2.02 mm, Min = 1.98 mm
C
0.5 MAX
SEATING PLANE
0.05 C
BALL TYP
0.16
0.10
1.4 TYP
SYMM
E
D
C
1.4
SYMM
TYP
B
A
0.35
TYP
1
2
4
3
5
0.225
0.185
25X
0.015
0.35 TYP
C A B
4224054/A 11/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YCG0025
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
3
25X ( 0.2)
1
4
5
2
A
(0.35) TYP
B
C
SYMM
D
E
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 40X
0.0325 MIN
0.0325 MAX
METAL UNDER
SOLDER MASK
( 0.2)
METAL
EXPOSED
METAL
(
0.2)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON-SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4224054/A 11/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
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EXAMPLE STENCIL DESIGN
YCG0025
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
(R0.05) TYP
25X ( 0.21)
1
4
5
2
3
A
(0.35) TYP
B
C
SYMM
METAL
TYP
D
E
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 40X
4224054/A 11/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TUSB2E22YCGR
TUSB2E22YCGT
ACTIVE
ACTIVE
DSBGA
DSBGA
YCG
YCG
25
25
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-20 to 85
-20 to 85
T2E2
T2E2
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2021
Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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