TUSB3410_10_技术文档

TUSB3410, TUSB3410I

USB to Serial Port Controller

Data Manual

January 2010

Connectivity Interface Solutions

SLLS519H

Contents

Page

Contents

Section

1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

2

1.1

1.2

1.3

Controller Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3

2

Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5

2.1

2.2

2.3

2.4

USB Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Enhanced UART Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Terminal Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5

6

3

Detailed Controller Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9

3.1

3.2

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

USB Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9

3.2.1

3.2.2

External Memory Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Host Download Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9

3.3

3.4

3.5

USB Data Movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Port Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Port Data Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9

3.5.1

3.5.2

3.5.3

RS-232 Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RS-485 Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IrDA Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10

13

14

15

18

4

MCU Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1

Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.1

4.1.2

4.1.3

ROMS: ROM Shadow Configuration Register (Addr:FF90h) . . . . . . . . . . . . . . . . . . .

Boot Operation (MCU Firmware Loading) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

WDCSR: Watchdog Timer, Control, and Status Register (Addr:FF93h) . . . . . . . . .

4.2

4.3

Buffers + I/O RAM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Endpoint Descriptor Block (EDB−1 to EDB−3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.1

OEPCNF_n: Output Endpoint Configuration (n = 1 to 3)

(Base Addr: FF08h, FF10h, FF18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

19

20

21

4.3.2

4.3.3

4.3.4

4.3.5

4.3.6

4.3.7

OEPBBAX_n: Output Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1) . . . .

OEPBCTX_n: Output Endpoint X Byte Count (n = 1 to 3) (Offset 2) . . . . . . . . . . . .

OEPBBAY_n: Output Endpoint Y-Buffer Base Address (n = 1 to 3) (Offset 5) . . . .

OEPBCTY_n: Output Endpoint Y-Byte Count (n = 1 to 3) (Offset 6) . . . . . . . . . . . .

OEPSIZXY_n: Output Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7) . . . . . . . . .

IEPCNF_n: Input Endpoint Configuration (n = 1 to 3)

(Base Addr: FF48h, FF50h, FF58h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21

22

23

24

4.3.8

4.3.9

4.3.10

4.3.11

4.3.12

IEPBBAX_n: Input Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1) . . . . . .

IEPBCTX_n: Input Endpoint X-Byte Count (n = 1 to 3) (Offset 2) . . . . . . . . . . . . . .

IEPBBAY_n: Input Endpoint Y-Buffer Base Address (n = 1 to 3) (Offset 5) . . . . . .

IEPBCTY_n: Input Endpoint Y-Byte Count (n = 1 to 3) (Offset 6) . . . . . . . . . . . . . . .

IEPSIZXY_n: Input Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7) . . . . . . . . . . . .

4.4

Endpoint-0 Descriptor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.1

4.4.2

4.4.3

4.4.4

IEPCNFG_0: Input Endpoint-0 Configuration Register (Addr:FF80h) . . . . . . . . . . .

IEPBCNT_0: Input Endpoint-0 Byte Count Register (Addr:FF81h) . . . . . . . . . . . . .

OEPCNFG_0: Output Endpoint-0 Configuration Register (Addr:FF82h) . . . . . . . . .

OEPBCNT_0: Output Endpoint-0 Byte Count Register (Addr:FF83h) . . . . . . . . . . .

iii

May 2008

SLLS519G

Contents

Section

Page

5

USB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25

26

27

28

29

30

31

33

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

FUNADR: Function Address Register (Addr:FFFFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

USBSTA: USB Status Register (Addr:FFFEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

USBMSK: USB Interrupt Mask Register (Addr:FFFDh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

USBCTL: USB Control Register (Addr:FFFCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MODECNFG: Mode Configuration Register (Addr:FFFBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Vendor ID/Product ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SERNUM7: Device Serial Number Register (Byte 7) (Addr:FFEFh) . . . . . . . . . . . . . . . . . . . . . .

SERNUM6: Device Serial Number Register (Byte 6) (Addr:FFEEh) . . . . . . . . . . . . . . . . . . . . . .

SERNUM5: Device Serial Number Register (Byte 5) (Addr:FFEDh) . . . . . . . . . . . . . . . . . . . . . .

SERNUM4: Device Serial Number Register (Byte 4) (Addr:FFECh) . . . . . . . . . . . . . . . . . . . . . .

SERNUM3: Device Serial Number Register (Byte 3) (Addr:FFEBh) . . . . . . . . . . . . . . . . . . . . . .

SERNUM2: Device Serial Number Register (Byte 2) (Addr:FFEAh) . . . . . . . . . . . . . . . . . . . . . .

SERNUM1: Device Serial Number Register (Byte 1) (Addr:FFE9h) . . . . . . . . . . . . . . . . . . . . . .

SERNUM0: Device Serial Number Register (Byte 0) (Addr:FFE8h) . . . . . . . . . . . . . . . . . . . . . .

Function Reset And Power-Up Reset Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pullup Resistor Connect/Disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9

5.10

5.11

5.12

5.13

5.14

5.15

5.16

6

DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 DMA Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.1

6.1.2

6.1.3

6.1.4

DMACDR1: DMA Channel Definition Register (UART Transmit Channel)

(Addr:FFE0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

34

35

DMACSR1: DMA Control And Status Register (UART Transmit Channel)

(Addr:FFE1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DMACDR3: DMA Channel Definition Register (UART Receive Channel)

(Addr:FFE4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DMACSR3: DMA Control And Status Register (UART Receive Channel)

(Addr:FFE5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

36

37

38

39

40

41

42

43

44

46

47

48

6.2

Bulk Data I/O Using the EDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.1

6.2.2

IN Transaction (TUSB3410 to Host) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OUT Transaction (Host to TUSB3410) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

7.1.6

7.1.7

7.1.8

7.1.9

7.1.10

7.1.11

7.1.12

7.1.13

7.1.14

RDR: Receiver Data Register (Addr:FFA0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TDR: Transmitter Data Register (Addr:FFA1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LCR: Line Control Register (Addr:FFA2h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FCRL: UART Flow Control Register (Addr:FFA3h) . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmitter Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MCR: Modem-Control Register (Addr:FFA4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LSR: Line-Status Register (Addr:FFA5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MSR: Modem-Status Register (Addr:FFA6h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DLL: Divisor Register Low Byte (Addr:FFA7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DLH: Divisor Register High Byte (Addr:FFA8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Baud-Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

XON: Xon Register (Addr:FFA9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

XOFF: Xoff Register (Addr:FFAAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MASK: UART Interrupt-Mask Register (Addr:FFABh) . . . . . . . . . . . . . . . . . . . . . . . .

iv

SLLS519G

May 2008

Contents

Page

Section

7.2

UART Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

48

49

50

51

53

54

55

57

58

59

60

61

63

64

65

66

68

69

71

72

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.2.6

Receiver Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Hardware Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Auto RTS (Receiver Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Auto CTS (Transmitter Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Xon/Xoff Receiver Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Xon/Xoff Transmit Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8

9

Expanded GPIO Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1 Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1.1 PUR_3: GPIO Pullup Register For Port 3 (Addr:FF9Eh) . . . . . . . . . . . . . . . . . . . . . .

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1 8052 Interrupt and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1.1

9.1.2

9.1.3

9.1.4

8052 Standard Interrupt Enable (SIE) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Additional Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VECINT: Vector Interrupt Register (Addr:FF92h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Logical Interrupt Connection Diagram (Internal/External) . . . . . . . . . . . . . . . . . . . . . .

10 I2C Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

10.1

I C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

10.1.1

10.1.2

10.1.3

10.1.4

I2CSTA: I C Status and Control Register (Addr:FFF0h) . . . . . . . . . . . . . . . . . . . . . .

2

I2CADR: I C Address Register (Addr:FFF3h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

I2CDAI: I C Data-Input Register (Addr:FFF2h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

I2CDAO: I C Data-Output Register (Addr:FFF1h) . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.2

10.3

10.4

10.5

10.6

Random-Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current-Address Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Sequential-Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Byte-Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page-Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11 TUSB3410 Bootcode Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.1

11.2

11.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bootcode Programming Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Default Bootcode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.1

11.3.2

11.3.3

11.3.4

11.3.5

Device Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Configuration Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interface Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Endpoint Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

String Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

11.4

External I C Device Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.4.1

11.4.2

Product Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Descriptor Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.5

11.6

Checksum in Descriptor Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Header Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.6.1

11.6.2

11.6.3

TUSB3410 Bootcode Supported Descriptor Block . . . . . . . . . . . . . . . . . . . . . . . . . . .

USB Descriptor Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Autoexec Binary Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.7

USB Host Driver Downloading Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

May 2008

SLLS519G

Contents

Section

Page

11.8

Built-In Vendor Specific USB Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

72

73

74

77

78

79

81

82

11.8.1

11.8.2

11.8.3

11.8.4

11.8.5

11.8.6

11.8.7

Reboot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Force Execute Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

I C Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

I C Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Internal ROM Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.9

Bootcode Programming Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.9.1

11.9.2

USB Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Hardware Reset Introduced by the Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.10 File Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1

12.2

12.3

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Commercial Operating Condition (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1

13.2

13.3

13.4

Crystal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Circuit Required for Reliable Bus Powered Suspend Operation . . . . . . . . . . . . . . . . . .

Wakeup Timing (WAKEUP or RI/CP Transitions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

SLLS519G

May 2008

List of Illustrations

Figure

1−1

1−2

3−1

3−2

3−3

4−1

5−1

5−2

7−1

7−2

7−3

9−1

Title

Page

Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

USB-to-Serial (Single Channel) Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RS-232 and IR Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

USB-to-Serial Implementation (RS-232) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RS-485 Bus Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MCU Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reset Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pullup Resistor Connect/Disconnect Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MSR and MCR Registers in Loop-Back Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receiver/Transmitter Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Auto Flow Control Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Internal Vector Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

2

11

12

13

31

45

49

55

75

76

81

82

11−1 Control Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−2 Control Write Transfer Without Data Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−1 Crystal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−2 External Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−3 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vii

May 2008

SLLS519G

List of Tables

Table

Title

Page

2−1

4−1

4−2

4−3

4−4

4−5

4−6

4−7

6−1

6−2

7−1

7−2

7−3

7−4

9−1

9−2

11−1

11−2

11−3

11−4

11−5

11−6

11−7

11−8

11−9

Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ROM/RAM Size Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

XDATA Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Memory-Mapped Registers Summary (XDATA Range = FF80h ” FFFFh) . . . . . . . . . . . . . . . . . . . .

EDB Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Endpoint Registers and Offsets in RAM (n = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Endpoint Registers Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input/Output EDB-0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DMA Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DMA IN-Termination Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

UART Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmitter Flow-Control Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receiver Flow-Control Possibilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DLL/DLH Values and Resulted Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8052 Interrupt Location Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Vector Interrupt Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Device Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Configuration Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interface Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Endpoint1 Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

String Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

USB Descriptors Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Autoexec Binary Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Host Driver Downloading Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bootcode Response to Control Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7

14

15

16

17

19

23

33

36

39

42

47

53

54

65

66

67

70

72

75

76

77

11−10 Bootcode Response to Control Write Without Data Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−11 Vector Interrupt Values and Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

SLLS519G

May 2008

Introduction

1

Introduction

1.1 Controller Description

The TUSB3410 provides bridging between a USB port and an enhanced UART serial port. The TUSB3410

contains all the necessary logic to communicate with the host computer using the USB bus. It contains an 8052

microcontroller unit (MCU) with 16K bytes of RAM that can be loaded from the host or from the external

2

on-board memory via an I C bus. It also contains 10K bytes of ROM that allow the MCU to configure the USB

2

port at boot time. The ROM code also contains an I C boot loader. All device functions, such as the USB

command decoding, UART setup, and error reporting, are managed by the internal MCU firmware under the

auspices of the PC host.

The TUSB3410 can be used to build an interface between a legacy serial peripheral device and a PC with USB

ports, such as a legacy-free PC. Once configured, data flows from the host to the TUSB3410 via USB OUT

commands and then out from the TUSB3410 on the SOUT line. Conversely, data flows into the TUSB3410

on the SIN line and then into the host via USB IN commands.

Out

SOUT

Legacy

Serial

Peripheral

Host

(PC or On-The-Go

Dual-Role Device)

USB

In

TUSB3410

SIN

Figure 1−1. Data Flow

1

SLLS519H—January 2010

TUSB3410, TUSB3410I

Introduction

12 MHz

Clock

Oscillator

8052

Core

PLL

and

24 MHz

Dividers

8

2 × 16-Bit

Timers

10K × 8

ROM

USB

TxR

DP, DM

16K × 8

RAM

4

P3.4

P3.3

P3.1

P3.0

Port 3

2K × 8

SRAM

8

2

I C

2

I C Bus

Controller

DMA-1

DMA-3

8

CPU-I/F

Suspend/

Resume

USB

Serial

Interface

Engine

8

RTS

CTS

DTR

DSR

8

UART−1

UBM

USB Buffer

Manager

SIN

SOUT

TDM

Control

Logic

IR

M

U

X

Encoder

SOUT/IR_SOUT

IR

SIN/IR_SIN

M

U

X

Decoder

Figure 1−2. USB-to-Serial (Single Channel) Controller Block Diagram

2

TUSB3410, TUSB3410I

SLLS519H—January 2010

Introduction

1.2 Ordering Information

PACKAGED DEVICES

T

COMMENT

A

32-TERMINAL LQFP PACKAGE

32-TERMINAL QFN PACKAGE

Industrial temperature range

Shipped in trays

TUSB3410 I VF

TUSB3410 VF

TUSB3410 I RHB

−40°C to 85°C

0°C to 70°C

Industrial temperature range

Tape and Reel Option

Shipped in trays

TUSB3410 I RHBR

TUSB3410 RHB

TUSB3410 RHBR

Tape and Reel Option

1.3 Revision History

Version

Date

Changes

Mar−2002

Apr−2002

Initial Release

A

1. General grammatical corrections

2. Added Design−in warning on cover sheet

3. Removed references to Optional preprogrammed VID/PID Registers from Section 5.1.6 through 5.1.11. Re-

number the remainder of Section 5.1 accordingly – option no longer supported.

4. Clarified GPIO pin availability

B

Jun−2002

1. Removed Design−in warning from cover sheet

2. Added Note 8 to Terminal Functions Table for GPIO Pins.

3. Removed Section 3.2.3 – Production Programming Mode – Mode no longer supported.

4. Added Clock Output Control description to section 5.1.5.

5. Removed Section 11.6.4 USB Descriptor with Binary Firmware

6. Added Icc Spec to Table 12.3

C

D

Nov−2003

July 2005

1. Added Industrial Temperature Option and Information

2. Added USB Logo to Cover

1. General grammatical corrections

2. Numerous technical corrections

F

July 2007

May 2008

Jan 2010

1. Added ordering information for TUSB3410IRHBR and TUSB3410RHBR

1. Added terminal assignments for RHB package

G

H

1. Removed reference to 48-MHz in 13.4

3

SLLS519H—January 2010

TUSB3410, TUSB3410I

Introduction

4

TUSB3410, TUSB3410I

SLLS519H—January 2010

Main Features

2

Main Features

2.1 USB Features

•

Fully compliant with USB 2.0 full speed specifications: TID #40340262

Supports 12-Mbps USB data rate (full speed)

Supports USB suspend, resume, and remote wakeup operations

Supports two power source modes:

−

Bus-powered mode

Self-powered mode

•

Can support a total of three input and three output (interrupt, bulk) endpoints

2.2 General Features

•

Integrated 8052 microcontroller with

−

256 × 8 RAM for internal data

2

10K × 8 ROM (with USB and I C boot loader)

2

16K × 8 RAM for code space loadable from host or I C port

2K × 8 shared RAM used for data buffers and endpoint descriptor blocks (EDB)

Four GPIO terminals from 8052 port 3

2

Master I C controller for EEPROM device access

MCU operates at 24 MHz providing 2 MIPS operation

128-ms watchdog timer

•

Built-in two-channel DMA controller for USB/UART bulk I/O

Operates from a 12-MHz crystal

Supports USB suspend and resume

Supports remote wake-up

Available in 32-terminal LQFP

3.3-V operation with 1.8-V core operating voltage provided by on-chip 1.8-V voltage regulator

2.3 Enhanced UART Features

•

Software/hardware flow control:

−

Programmable Xon/Xoff characters

Programmable Auto-RTS/DTR and Auto-CTS/DSR

•

Automatic RS-485 bus transceiver control, with and without echo

Selectable IrDA mode for up to 115.2 kbps transfer

Software selectable baud rate from 50 to 921.6 k baud

Programmable serial-interface characteristics

−

5-, 6-, 7-, or 8-bit characters

Even, odd, or no parity-bit generation and detection

1-, 1.5-, or 2-stop bit generation

5

SLLS519H—January 2010

TUSB3410, TUSB3410I

Main Features

•

Line break generation and detection

Internal test and loop-back capabilities

Modem-control functions (CTS, RTS, DSR, DTR, RI, and DCD)

Internal diagnostics capability

−

Loopback control for communications link-fault isolation

Break, parity, overrun, framing-error simulation

2.4 Terminal Assignment

VF PACKAGE

(TOP VIEW)

24 23 22 21 20 19 18 17

25

26

27

28

29

30

31

32

VCC

X2

X1/CLKI

GND

P3.4

16 RI/CP

15

14

13

12

11

10

9

DCD

DSR

CTS

WAKEUP

SCL

P3.3

P3.1

P3.0

SDA

RESET

1

2

3

4

5

6

7

8

RHB PACKAGE

(BOTTOM VIEW)

1

2

3

4

6

7

8

9

32

P3.0

P3.1

P3.3

RESET

SDA

SCL

WAKEUP

CTS

DSR

10

11

12

13

14

15

16

31

30

29

28

27

26

25

P3.4

GND

X1/CLKI

X2

DCD

RI/CP

VCC

24 23 22 21 20 19 18 17

6

TUSB3410, TUSB3410I

SLLS519H—January 2010

Main Features

Table 2−1. Terminal Functions

TERMINAL

NAME

CLKOUT

I/O

DESCRIPTION

NO.

22

O

Clock output (controlled by bits 2 (CLKOUTEN) and 3(CLKSLCT) in the MODECNFG register (see

Section 5.5 and Note 1)

CTS

DCD

DM

13

15

7

I

UART: Clear to send (see Note 4)

UART: Data carrier detect (see Note 4)

Upstream USB port differential data minus

Upstream USB port differential data plus

UART: Data set ready (see Note 4)

UART: Data terminal ready (see Note 1)

I/O

I

DP

6

DSR

DTR

GND

P3.0

P3.1

P3.3

P3.4

PUR

RESET

RI/CP

RTS

SCL

SDA

14

21

O

8, 18, 28 GND Digital ground

32

31

30

29

5

I/O

O

General-purpose I/O 0 (port 3, terminal 0) (see Notes 3, 5, and 8)

General-purpose I/O 1 (port 3, terminal 1) (see Notes 3, 5, and 8)

General-purpose I/O 3 (port 3, terminal 3) (see Notes 3, 5, and 8)

General-purpose I/O 4 (port 3, terminal 4) (see Notes 3, 5, and 8)

Pull-up resistor connection (see Note 2)

9

I

Device master reset input (see Note 4)

16

20

11

10

17

19

2

I

UART: Ring indicator (see Note 4)

O

UART: Request to send (see Note 1)

2

O

Master I C controller: clock signal (see Note 1)

2

I/O

I

Master I C controller: data signal (see Notes 1 and 5)

SIN/IR_SIN

UART: Serial input data / IR Serial data input (see Note 6)

UART: Serial output data / IR Serial data output (see Note 7)

SOUT/IR_SOUT

SUSPEND

O

Suspend indicator terminal (see Note 3). When this terminal is asserted high, the device is in

suspend mode.

TEST0

TEST1

23

24

I

Test input (for factory test only) (see Note 5). This terminal must be tied to VCC through a 10-kΩ

resistor.

Test input (for factory test only) (see Note 5). This terminal must be tied to VCC through a 10-kΩ

resistor.

VCC

3, 25

4

PWR 3.3 V

VDD18

PWR 1.8-V supply. An internal voltage regulator generates this supply voltage when terminal VREGEN is

low. When VREGEN is high, 1.8 V must be supplied externally.

VREGEN

WAKEUP

X1/CLKI

X2

1

I

This active-low terminal is used to enable the 3.3-V to 1.8-V voltage regulator.

Remote wake-up request terminal. When low, wakes up system (see Note 5)

12-MHz crystal input or clock input

12

27

26

I

O

12-MHz crystal output

NOTES: 1. 3-state CMOS output ( 4-mA drive/sink)

2. 3-state CMOS output ( 8-mA drive/sink)

3. 3-state CMOS output ( 12-mA drive/sink)

4. TTL-compatible, hysteresis input

5. TTL-compatible, hysteresis input, with internal 100-μA active pullup resistor

6. TTL-compatible input without hysteresis, with internal 100-μA active pullup resistor

7. Normal or IR mode: 3-state CMOS output ( 4-mA drive/sink)

8. The MCU treats the outputs as open drain types in that the output can be driven low continuously, but a high output is driven for two

clock cycles and then the output is high impedance.

7

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TUSB3410, TUSB3410I

Main Features

8

TUSB3410, TUSB3410I

SLLS519H—January 2010

Detailed Controller Description

3

Detailed Controller Description

3.1 Operating Modes

The TUSB3410 controls its USB interface in response to USB commands, and this action is independent of

the serial port mode selected. On the other hand, the serial port can be configured in three different modes.

As with any interface device, data movement is the main function of the TUSB3410, but typically the initial

configuration and error handling consume most of the support code. The following sections describe the

various modes the device can be used in and the means of configuring the device.

3.2 USB Interface Configuration

The TUSB3410 contains onboard ROM microcode, which enables the MCU to enumerate the device as a USB

peripheral. The ROM microcode can also load application code into internal RAM from either external memory

2

via the I C bus or from the host via the USB.

3.2.1 External Memory Case

After reset, the TUSB3410 is disconnected from the USB. Bit 7 (CONT) in the USBCTL register (see

2

Section 5.4) is cleared. The TUSB3410 checks the I C port for the existence of valid code; if it finds valid code,

then it uploads the code from the external memory device into the RAM program space. Once loaded, the

TUSB3410 connects to the USB by setting the CONT bit and enumeration and configuration are performed.

This is the most likely use of the device.

3.2.2 Host Download Case

2

If the valid code is not found at the I C port, then the TUSB3410 connects to the USB by setting bit 7 (CONT)

in the USBCTL register (see Section 5.4), and then an enumeration and default configuration are performed.

The host can download additional microcode into RAM to tailor the application. Then, the MCU causes a

disconnect and reconnect by clearing and setting the CONT bit, which causes the TUSB3410 to be

re-enumerated with a new configuration.

3.3 USB Data Movement

From the USB perspective, the TUSB3410 looks like a USB peripheral device. It uses endpoint 0 as its control

endpoint, as do all USB peripherals. It also configures up to three input and three output endpoints, although

most applications use one bulk input endpoint for data in, one bulk output endpoint for data out, and one

interrupt endpoint for status updates. The USB configuration likely remains the same regardless of the serial

port configuration.

Most data is moved from the USB side to the UART side and from the UART side to the USB side using on-chip

DMA transfers. Some special cases may use programmed I/O under control of the MCU.

3.4 Serial Port Setup

The serial port requires a few control registers to be written to configure its operation. This configuration likely

remains the same regardless of the data mode used. These registers include the line control register that

controls the serial word format and the divisor registers that control the baud rate.

These registers are usually controlled by the host application.

3.5 Serial Port Data Modes

The serial port can be configured in three different, although similar, data modes: the RS-232 data mode, the

RS-485 data mode, and the IrDA data mode. Similar to the USB mode, once configured for a specific

application, it is unlikely that the mode would be changed. The different modes affect the timing of the serial

input and output or the use of the control signals. However, the basic serial-to-parallel conversion of the

receiver and parallel-to-serial conversion of the transmitter remain the same in all modes. Some features are

available in all modes, but are only applicable in certain modes. For instance, software flow control via Xoff/Xon

characters can be used in all modes, but would usually only be used in RS-232 or IrDA mode because the

RS-485 mode is half-duplex communication. Similarly, hardware flow control via RTS/CTS (or DTR/DSR)

handshaking is available in RS-232 or IrDA mode. However, this would probably be used only in RS-232 mode,

since in IrDA mode only the SIN and SOUT paths are optically coupled.

9

SLLS519H—January 2010

TUSB3410, TUSB3410I

Detailed Controller Description

3.5.1 RS-232 Data Mode

The default mode is called the RS-232 mode and is typically used for full duplex communication on SOUT and

SIN. In this mode, the modem control outputs (RTS and DTR) communicate to a modem or are general

outputs. The modem control inputs (CTS, DSR, DCD, and RI/CP) communicate to a modem or are general

inputs. Alternatively, RTS and CTS (or DTR and DSR) can throttle the data flow on SOUT and SIN to prevent

receive FIFO overruns. Finally, software flow control via Xoff/Xon characters can be used for the same

purpose.

This mode represents the most general-purpose applications, and the other modes are subsets of this mode.

3.5.2 RS-485 Data Mode

The RS-485 mode is very similar to the RS-232 mode in that the SOUT and SIN formats remain the same.

Since RS-485 is a bus architecture, it is inherently a single duplex communication system. The TUSB3410

in RS-485 mode controls the RTS and DTR signals such that either can enable an RS-485 driver or RS-485

receiver. When in RS-485 mode, the enable signals for transmitting are automatically asserted whenever the

DMA is set up for outbound data. The receiver can be left enabled while the driver is enabled to allow an echo

if desired, but when receive data is expected, the driver must be disabled. Note that this precludes use of

hardware flow control, since this is a half-duplex operation, it would not be effective. Software flow control is

supported, but may be of limited value.

The RS-485 mode is enabled by setting bit 7 (485E) in the FCRL register (see Section 7.1.4), and bit 1 (RCVE)

in the MCR register (see Section 7.1.6) allows the receiver to eavesdrop while in the RS-485 mode.

3.5.3 IrDA Data Mode

The IrDA mode encodes SOUT and decodes SIN in the manner prescribed by the IrDA standard, up to

115.2 kbps. Connection to an external IrDA transceiver is required. Communications is usually full duplex.

Generally, in an IrDA system, only the SOUT and SIN paths are connected so hardware flow control is usually

not an option. Software flow control is supported.

The IrDA mode is enabled by setting bit 6 (IREN) in the USBCTL register (see Section 5.4).

The IR encoder and decoder circuitry work with the UART to change the serial bit stream into a series of pulses

and back again. For every zero bit in the outbound serial stream, the encoder sends a low-to-high-to-low pulse

with the duration of 3/16 of a bit frame at the middle of the bit time. For every one bit in the serial stream, the

output remains low for the entire bit time.

The decoding process consists of receiving the signal from the IrDA receiver and converting it into a series

of zeroes and ones. As the converse to the encoder, the decoder converts a pulse to a zero bit and the lack

of a pulse to a one bit.

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TUSB3410, TUSB3410I

SLLS519H—January 2010

Detailed Controller Description

SOUT

IR_TX

0

M

U

X

SOUT/IR_SOUT

Terminal

SOUT

IR

From

UART

1

Encoder

IREN (in

USBCTL

Register)

0

UART

BaudOut

Clock

M

U

X

SOFTSW (in

MODECNFG

Register)

1

TXCNTL (in

MODECNFG

Register)

0

M

U

X

CLKOUT

Terminal

CLKOUTEN

(in

3.556 MHz

1

MODECNFG

Register)

CLKSLCT (in

MODECNFG

Register)

3.3 V

0

To

UART

Receiver

M

U

X

SIN

IR_RX

IR

Decoder

SIN/IR_SIN

Terminal

1

Figure 3−1. RS-232 and IR Mode Select

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SLLS519H—January 2010

TUSB3410, TUSB3410I

Detailed Controller Description

DB9

Connector

Transceivers

X1/CLKI

X2

12 MHz

4

7

DTR

RTS

RI/CP

DCD

DSR

CTS

1

Serial Port

6

8

3

2

SOUT

SIN

DP

USB-0

DM

TUSB3410

P3.0

P3.1

P3.3

P3.4

GPIO Terminals for

Other Onboard

Control Function

Figure 3−2. USB-to-Serial Implementation (RS-232)

X1/CLKI

12 MHz

RTS

RS-485 Bus

X2

SOUT

DTR

SIN

DP

USB-0

RS-485

Transceiver

DM

TUSB3410

2-Bit Time

1-Bit Max

SOUT

DTR

RTS

Receiver is Disabled if RCVE = 0

Figure 3−3. RS-485 Bus Implementation

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TUSB3410, TUSB3410I

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MCU Memory Map

4

MCU Memory Map

Figure 4−1 illustrates the MCU memory map under boot and normal operation.

NOTE:

The internal 256 bytes of RAM are not shown, since they are assumed to be in the standard

8052 location (0000h to 00FFh). The shaded areas represent the internal ROM/RAM.

•

When bit 0 (SDW) of the ROMS register is 0 (boot mode)

The 10K ROM is mapped to address (0x0000−0x27FF) and is duplicated in location (0x8000−0xA7FF) in

code space. The internal 16K RAM is mapped to address range (0x0000−0x3FFF) in data space. Buffers,

MMR, and I/O are mapped to address range (0xF800−0xFFFF) in data space.

When bit 0 (SDW) is 1 (normal mode)

The 10K ROM is mapped to (0x8000−0xA7FF) in code space. The internal 16K RAM is mapped to

address range (0x0000−0x3FFF) in code space. Buffers, MMR, and I/O are mapped to address range

(0xF800−0xFFFF) in data space.

Boot Mode (SDW = 0)

Normal Mode (SDW = 1)

CODE

XDATA

CODE

XDATA

0000h

10K Boot ROM

(16K)

16K

Read/Write

Code RAM

Read Only

27FFh

3FFFh

8000h

10K Boot ROM

A7FFh

F800h

2K Data

MMR

2K Data

MMR

FF7Fh

FF80h

FFFFh

Figure 4−1. MCU Memory Map

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TUSB3410, TUSB3410I

MCU Memory Map

4.1 Miscellaneous Registers

4.1.1 ROMS: ROM Shadow Configuration Register (Addr:FF90h)

This register is used by the MCU to switch from boot mode to normal operation mode (boot mode is set on

power-on reset only). In addition, this register provides the device revision number and the ROM/RAM

configuration.

7

6

5

4

3

2

1

0

ROA

R/O

S1

S0

RSVD

R/O

RSVD

R/O

RSVD

R/O

RSVD

R/O

SDW

R/W

R/O

BIT

NAME

SDW

RESET

FUNCTION

This bit enables/disables boot ROM. (Shadow the ROM).

0

SDW = 0 When clear, the MCU executes from the 10K boot ROM space. The boot ROM appears in two

locations: 0000h and 8000h. The 16K RAM is mapped to XDATA space; therefore, a read/write

operation is possible. This bit is set by the MCU after the RAM load is completed. The MCU

cannot clear this bit; it is cleared on power-up reset or watchdog time-out reset.

SDW = 1 When set by the MCU, the 10K boot ROM maps to location 8000h, and the 16K RAM is mapped

to code space, starting at location 0000h. At this point, the MCU executes from RAM, and the

write operation is disabled (no write operation is possible in code space).

4−1

6−5

RSVD

S[1:0]

No effect

These bits are always read as 0000b.

Code space size. These bits define the ROM or RAM code-space size (bit 7 (ROA) defines ROM or

RAM). These bits are permanently set to 10b, indicating 16K bytes of code space, and are not affected

by reset (see Table 4−1).

00 = 4K bytes code space size

01 = 8K bytes code space size

10 = 16K bytes code space size

11 = 32K bytes code space size

7

ROA

No effect

ROM or RAM version. This bit indicates whether the code space is RAM or ROM based. This bit is

permanently set to 1, indicating the code space is RAM, and is not affected by reset (see Table 4−1).

ROA = 0 Code space is ROM

ROA = 1 Code space is RAM

Table 4−1. ROM/RAM Size Definition Table

ROMS REGISTER

BOOT ROM

RAM CODE

ROM CODE

ROA

S1

0

S0

0

1

None

10K

None

4K

8K

0

1

0

16K (reserved)

32K (reserved)

None

1

0

1

10K

8K

None

†

1

0

10K

16K

None

1

10K

32K (reserved)

None

†

This is the hardwired setting.

4.1.2 Boot Operation (MCU Firmware Loading)

Since the code space is in RAM (with the exception of the boot ROM), the TUSB3410 firmware must be loaded

from an external source. Two sources are available for booting: one from an external serial EEPROM

2

connected to the I C bus and the other from the host via the USB. On device reset, bit 0 (SDW) in the ROMS

register (see Section 4.1.1) and bit 7 (CONT) in the USBCTL register (see Section 5.4) are cleared. This

configures the memory space to boot mode (see Table 4−3) and keeps the device disconnected from the host.

The first instruction is fetched from location 0000h (which is in the 10K ROM). The 16K RAM is mapped to

XDATA space (location 0000h). The MCU executes a read from an external EEPROM and tests whether it

contains the code (by testing for boot signature). If it contains the code, then the MCU reads from EEPROM

14

TUSB3410, TUSB3410I

SLLS519H—January 2010

MCU Memory Map

and writes to the 16K RAM in XDATA space. If it does not contain the code, then the MCU proceeds to boot

from the USB.

Once the code is loaded, the MCU sets the SDW bit to 1 in the ROMS register. This switches the memory map

to normal mode; that is, the 16K RAM is mapped to code space, and the MCU starts executing from location

0000h. Once the switch is done, the MCU sets the CONT bit to 1 in the USBCTL register. This connects the

device to the USB and results in normal USB device enumeration.

4.1.3 WDCSR: Watchdog Timer, Control, and Status Register (Addr:FF93h)

A watchdog timer (WDT) with 1-ms clock is provided. If this register is not accessed for a period of 128 ms,

then the WDT counter resets the MCU (see Figure 5−1). The watchdog timer is enabled by default and can

be disabled by writing a pattern of 101010b into the WDD[5:0] bits. The 1-ms clock for the watchdog timer is

generated from the SOF pulses. Therefore, in order for the watchdog timer to count, bit 7 (CONT) in the

USBCTL register (see Section 5.4) must be set.

7

6

5

4

3

2

1

0

WDD0

R/W

WDR

R/C

WDD5

R/W

WDD4

R/W

WDD3

R/W

WDD2

R/W

WDD1

R/W

WDT

W/O

BIT

NAME

WDT

RESET

FUNCTION

0

MCU must write a 1 to this bit to prevent the watchdog timer from resetting the MCU. If the MCU does not

write a 1 in a period of 128 ms, the watchdog timer resets the device. Writing a 0 has no effect on the

watchdog timer. (The watchdog timer is a 7-bit counter using a 1-ms CLK.) This bit is read as 0.

5−1 WDD[5:1]

00000

0

These bits disable the watchdog timer. For the timer to be disabled these bits must be set to 10101b and

bit 7 (WDD0) must also be set to 0. If any other pattern is present, then the watchdog timer is in operation.

6

WDR

Watchdog reset indication bit. This bit indicates if the reset occurred due to power-on reset or watchdog

timer reset.

WDR = 0 A power-up reset occurred

WDR = 1 A watchdog time-out reset occurred. To clear this bit, the MCU must write a 1. Writing a 0 has no

effect.

7

WDD0

1

This bit is one of the six disable bits for the watchdog timer. This bit must be cleared in order for the

watchdog timer to be disabled.

4.2 Buffers + I/O RAM Map

The address range from F800h to FFFFh (2K bytes) is reserved for data buffers, setup packet, endpoint

descriptors block (EDB), and all I/O. There are 128 locations reserved for memory-mapped registers (MMR).

Table 4−2 represents the XDATA space allocation and access restriction for the DMA, USB buffer manager

(UBM), and MCU.

Table 4−2. XDATA Space

DESCRIPTION

ADDRESS RANGE

UBM ACCESS

DMA ACCESS

MCU ACCESS

Internal MMRs

(Memory-Mapped Registers)

No

FFFFh−FF80h

Yes

(Only EDB-0)

(only data register and EDB-0)

EDB

FF7Fh−FF08h

Only for EDB update

Yes

(Endpoint Descriptors Block)

Setup Packet

Input Endpoint-0 Buffer

Output Endpoint-0 Buffer

Data Buffers

FF07h−FF00h

FEFFh−FEF8h

FEF7h−FEF0h

FEEFh−F800h

Yes

No

Yes

15

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TUSB3410, TUSB3410I

MCU Memory Map

Table 4−3. Memory-Mapped Registers Summary (XDATA Range = FF80h → FFFFh)

ADDRESS

REGISTER

DESCRIPTION

FFFFh

FUNADR

Function address register

FFFEh

USBSTA

USB status register

FFFDh

FFFCh

FFFBh

USBMSK

USBCTL

USB interrupt mask register

USB control register

MODECNFG

Mode configuration register

FFFAh−FFF4h Reserved

2

FFF3h

FFF2h

FFF1h

FFF0h

FFEFh

FFEEh

FFEDh

FFECh

FFEBh

FFEAh

FFE9h

FFE8h

I2CADR

I C-port address register

2

I2CDATI

I C-port data input register

2

I2CDATO

I2CSTA

I C-port data output register

2

I C-port status register

SERNUM7

SERNUM6

SERNUM5

SERNUM4

SERNUM3

SERNUM2

SERNUM1

SERNUM0

Serial number byte 7 register

Serial number byte 6 register

Serial number byte 5 register

Serial number byte 4 register

Serial number byte 3 register

Serial number byte 2 register

Serial number byte 1 register

Serial number byte 0 register

FFE7h−FFE6h Reserved

FFE5h

FFE4h

DMACSR3

DMACDR3

DMA-3: Control and status register

DMA-3: Channel definition register

FFE3h−FFE2h Reserved

FFE1h

FFE0h

DMACSR1

DMACDR1

DMA-1: Control and status register

DMA-1: Channel definition register

FFDFh−FFACh Reserved

FFABh

FFAAh

FFA9h

FFA8h

FFA7h

FFA6h

FFA5h

FFA4h

FFA3h

FFA2h

FFA1h

FFA0h

FF9Eh

MASK

XOFF

XON

DLH

UART: Interrupt mask register

UART: Xoff register

UART: Xon register

UART: Divisor high-byte register

UART: Divisor low-byte register

UART: Modem status register

UART: Line status register

UART: Modem control register

UART: Flow control register

UART: Line control registers

UART: Transmitter data registers

UART: Receiver data registers

GPIO: Pullup register for port 3

DLL

MSR

LSR

MCR

FCRL

LCR

TDR

RDR

PUR_3

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TUSB3410, TUSB3410I

SLLS519H—January 2010

MCU Memory Map

Table 4−3. Memory-Mapped Registers Summary (XDATA Range = FF80h → FFFFh) (Continued)

ADDRESS

REGISTER

DESCRIPTION

FF9Dh−FF94h Reserved

FF93h

FF92h

FF91h

FF90h

WDCSR

VECINT

Reserved

ROMS

Watchdog timer control and status register

Vector interrupt register

ROM shadow configuration register

FF8Fh−FF84h Reserved

FF83h

FF82h

FF81h

FF80h

OEPBCNT_0

Output endpoint_0: Byte count register

Output endpoint_0: Configuration register

Input endpoint_0: Byte count register

Input endpoint_0: Configuration register

OEPCNFG_0

IEPBCNT_0

IEPCNFG_0

Table 4−4. EDB Memory Locations

ADDRESS

REGISTER

DESCRIPTION

FF7Fh−FF60h Reserved

FF5Fh

FF5Eh

FF5Dh

FF5Ch

FF5Bh

FF5Ah

FF59h

FF58h

FF57h

FF56h

FF55h

FF54h

FF53h

FF52h

FF51h

FF50h

FF4Fh

FF4Eh

FF4Dh

FF4Ch

FF4Bh

FF4Ah

FF49h

FF48h

FF47h

↑

IEPSIZXY_3

IEPBCTY_3

IEPBBAY_3

−

Input endpoint_3: X-Y buffer size

Input endpoint_3: Y-byte count

Input endpoint_3: Y-buffer base address

Reserved

−

Reserved

IEPBCTX_3

IEPBBAX

IEPCNF_3

IEPSIZXY_2

IEPBCTY_2

IEPBBAY_2

−

Input endpoint_3: X-byte count

Input endpoint_3: X-buffer base address

Input endpoint_3: Configuration

Input endpoint_2: X-Y buffer size

Input endpoint_2: Y-byte count

Input endpoint_2: Y-buffer base address

Reserved

−

Reserved

IEPBCTX_2

IEPBBAX_2

IEPCNF_2

IEPSIZXY_1

IEPBCTY_1

IEPBBAY_1

−

Input endpoint_2: X-byte count

Input endpoint_2: X-buffer base address

Input endpoint_2: Configuration

Input endpoint_1: X-Y buffer size

Input endpoint_1: Y-byte count

Input endpoint_1: Y-buffer base address

Reserved

−

Reserved

IEPBCTX_1

IEPBBAX_1

IEPCNF_1

Input endpoint_1: X-byte count

Input endpoint_1: X-buffer base address

Input endpoint_1: Configuration

Reserved

FF20h

FF1Fh

FF1Eh

FF1Dh

FF1Bh−FF1Ch

OEPSIZXY_3

OEPBCTY_3

OEPBBAY_3

−

Output endpoint_3: X-Y buffer size

Output endpoint_3: Y-byte count

Output endpoint_3: Y-buffer base address

Reserved

17

SLLS519H—January 2010

TUSB3410, TUSB3410I

MCU Memory Map

Table 4−4. EDB Memory Locations (Continued)

ADDRESS

FF1Ah

FF19h

FF18h

FF17h

FF16h

FF15h

FF14h−FF13h

FF12h

FF11h

FF10h

FF0Fh

FF0Eh

FF0Dh

FF0Ch−FF0Bh

FF0Ah

FF09h

FF08h

FF07h

↑

REGISTER

OEPBCTX_3

OEPBBAX_3

OEPCNF_3

OEPSIZXY_2

OEPBCTY_2

OEPBBAY_2

−

DESCRIPTION

Output endpoint_3: X-byte count

Output endpoint_3: X-buffer base address

Output endpoint_3: Configuration

Output endpoint_2: X-Y buffer size

Output endpoint_2: Y-byte count

Output endpoint_2: Y-buffer base address

Reserved

OEPBCTX_2

OEPBBAX_2

OEPCNF_2

OEPSIZXY_1

OEPBCTY_1

OEPBBAY_1

−

Output endpoint_2: X-byte count

Output endpoint_2: X-buffer base address

Output endpoint_2: Configuration

Output endpoint_1: X-Y buffer size

Output endpoint_1: Y-byte count

Output endpoint_1: Y-buffer base address

Reserved

OEPBCTX_1

OEPBBAX_1

OEPCNF_1

Output endpoint_1: X-byte count

Output endpoint_1: X-buffer base address

Output endpoint_1: Configuration

(8 bytes)

Setup packet block

FF00h

FEFFh

↑

Input endpoint_0 buffer

FEF8h

FEF7h

↑

(8 bytes)

Output endpoint_0 buffer

Top of buffer space

Buffer space

FEF0h

FEEFh

TOPBUFF

↑

F800h

STABUFF

Start of buffer space

4.3 Endpoint Descriptor Block (EDB−1 to EDB−3)

Data transfers between the USB, the MCU, and external devices that are defined by an endpoint descriptor

block (EDB). Three input and three output EDBs are provided. With the exception of EDB-0 (I/O endpoint-0),

all EDBs are located in SRAM as per Table 4−3. Each EDB contains information describing the X- and

Y-buffers. In addition, each EDB provides general status information.

Table 4−5 describes the EDB entries for EDB−1 to EDB−3. EDB−0 registers are described in Table 4−6.

18

TUSB3410, TUSB3410I

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MCU Memory Map

Table 4−5. Endpoint Registers and Offsets in RAM (n = 1 to 3)

OFFSET

07

ENTRY NAME

EPSIZXY_n

EPBCTY_n

EPBBAY_n

SPARE

DESCRIPTION

I/O endpoint_n: X/Y-buffer size

I/O endpoint_n: Y-byte count

I/O endpoint_n: Y-buffer base address

Not used

06

05

04

03

SPARE

Not used

02

EPBCTX_n

EPBBAX_n

EPCNF_n

I/O endpoint_n: X-byte count

I/O endpoint_n: X-buffer base address

I/O endpoint_n: Configuration

01

00

Table 4−6. Endpoint Registers Base Addresses

BASE ADDRESS

FF08h

DESCRIPTION

Output endpoint 1

Output endpoint 2

Output endpoint 3

Input endpoint 1

Input endpoint 2

Input endpoint 3

FF10h

FF18h

FF48h

FF50h

FF58h

4.3.1 OEPCNF_n: Output Endpoint Configuration (n = 1 to 3) (Base Addr: FF08h, FF10h,

FF18h)

7

6

5

4

3

2

1

0

UBME

R/W

ISO=0

R/W

TOGLE

R/W

DBUF

R/W

STALL

R/W

USBIE

R/W

RSV

R/W

RSV

R/W

BIT

NAME

RSV

RESET

FUNCTION

1−0

2

x

Reserved = 0

USBIE

USB interrupt enable on transaction completion. Set/cleared by the MCU.

USBIE = 0 No interrupt on transaction completion

USBIE = 1 Interrupt on transaction completion

3

4

STALL

0

x

USB stall condition indication. Set/cleared by the MCU.

STALL = 0 No stall

STALL = 1 USB stall condition. If set by the MCU, then a STALL handshake is initiated and the bit is

cleared by the MCU.

DBUF

Double-buffer enable. Set/cleared by the MCU.

DBUF = 0 Primary buffer only (X-buffer only)

DBUF = 1 Toggle bit selects buffer

5

6

TOGLE

ISO

x

USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1.

ISO = 0 Nonisochronous transfer. This bit must be cleared by the MCU since only nonisochronous transfer

is supported.

7

UBME

x

USB buffer manager (UBM) enable/disable bit. Set/cleared by the MCU.

UBME = 0 UBM cannot use this endpoint

UBME = 1 UBM can use this endpoint

4.3.2 OEPBBAX_n: Output Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1)

7

6

5

4

3

2

1

0

A10

R/W

A9

A8

A7

A6

A5

A4

A3

R/W

BIT

7−0

NAME

RESET

FUNCTION

A[10:3]

x

A[10:3] of X-buffer base address (padded with 3 LSBs of zeros for a total of 11 bits). This value is set by

the MCU. The UBM or DMA uses this value as the start-address of a given transaction. Note that the UBM

or DMA does not change this value at the end of a transaction.

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MCU Memory Map

4.3.3 OEPBCTX_n: Output Endpoint X Byte Count (n = 1 to 3) (Offset 2)

7

6

5

4

3

2

1

0

NAK

R/W

C6

C5

C4

C3

C2

C1

C0

R/W

BIT

6−0

NAME

C[6:0]

RESET

x

FUNCTION

X-buffer byte count:

X000.0000b Count = 0

X000.0001b Count = 1 byte

:

X011.1111b Count = 63 bytes

X100.0000b Count = 64 bytes

Any value ≥ 100.0001b may result in unpredictable results.

7

NAK

x

NAK = 0 No valid data in buffer. Ready for host OUT

NAK = 1 Buffer contains a valid packet from host (gives NAK response to Host OUT request)

4.3.4 OEPBBAY_n: Output Endpoint Y-Buffer Base Address (n = 1 to 3) (Offset 5)

7

6

5

4

3

2

1

0

A10

R/W

A9

A8

A7

A6

A5

A4

A3

R/W

BIT

7−0

NAME

RESET

FUNCTION

A[10:3]

x

A[10:3] of Y-buffer base address (padded with 3 LSBs of zeros for a total of 11 bits). This value is set by

the MCU. The UBM or DMA uses this value as the start-address of a given transaction. Furthermore, UBM

or DMA does not change this value at the end of a transaction.

4.3.5 OEPBCTY_n: Output Endpoint Y-Byte Count (n = 1 to 3) (Offset 6)

7

6

5

4

3

2

1

0

NAK

R/W

C6

C5

C4

C3

C2

C1

C0

R/W

BIT

6−0

NAME

C[6:0]

RESET

x

FUNCTION

Y-byte count:

X000.0000b Count = 0

X000.0001b Count = 1 byte

:

X011.1111b Count = 63 bytes

X100.0000b Count = 64 bytes

Any value ≥ 100.0001b may result in unpredictable results.

7

NAK

x

NAK = 0 No valid data in buffer. Ready for host OUT

NAK = 1 Buffer contains a valid packet from host (gives NAK response to Host OUT request)

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MCU Memory Map

4.3.6 OEPSIZXY_n: Output Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7)

7

6

5

4

3

2

1

0

RSV

R/W

S6

S5

S4

S3

S2

S1

S0

R/W

BIT

6−0

NAME

S[6:0]

RESET

x

FUNCTION

X- and Y-buffer size:

0000.0000b Size = 0

0000.0001b Size = 1 byte

:

0011.1111b Size = 63 bytes

0100.0000b Size = 64 bytes

Any value ≥ 100.0001b may result in unpredictable results.

7

RSV

x

Reserved = 0

4.3.7 IEPCNF_n: Input Endpoint Configuration (n = 1 to 3) (Base Addr: FF48h, FF50h,

FF58h)

7

6

5

4

3

2

1

0

UBME

R/W

ISO=0

R/W

TOGLE

R/W

DBUF

R/W

STALL

R/W

USBIE

R/W

RSV

R/W

RSV

R/W

BIT

NAME

RSV

RESET

FUNCTION

1−0

2

x

Reserved = 0

USBIE

USB interrupt enable on transaction completion

USBIE = 0 No interrupt on transaction completion

USBIE = 1 Interrupt on transaction completion

3

4

STALL

0

x

USB stall condition indication. Set by the UBM but can be set/cleared by the MCU

STALL = 0 No stall

STALL = 1 USB stall condition. If set by the MCU, then a STALL handshake is initiated and the bit is

cleared automatically.

DBUF

Double buffer enable

DBUF = 0 Primary buffer only (X-buffer only)

DBUF = 1 Toggle bit selects buffer

5

6

TOGLE

ISO

x

USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1

ISO = 0 Nonisochronous transfer. This bit must be cleared by the MCU since only nonisochronous

transfer is supported

7

UBME

x

UBM enable/disable bit. Set/cleared by the MCU

UBME = 0 UBM cannot use this endpoint

UBME = 1 UBM can use this endpoint

4.3.8 IEPBBAX_n: Input Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1)

7

6

5

4

3

2

1

0

A10

R/W

A9

A8

A7

A6

A5

A4

A3

R/W

BIT

7−0

NAME

RESET

FUNCTION

A[10:3]

x

A[10:3] of X-buffer base address (padded with 3 LSBs of zeros for a total of 11 bits). This value is set by

the MCU. The UBM or DMA uses this value as the start-address of a given transaction, but note that the

UBM or DMA does not change this value at the end of a transaction.

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MCU Memory Map

4.3.9 IEPBCTX_n: Input Endpoint X-Byte Count (n = 1 to 3) (Offset 2)

7

6

5

4

3

2

1

0

NAK

R/W

C6

C5

C4

C3

C2

C1

C0

R/W

BIT

6−0

NAME

C[6:0]

RESET

x

FUNCTION

X-Buffer byte count:

X000.0000b Count = 0

X000.0001b Count = 1 byte

:

X011.1111b Count = 63 bytes

X100.0000b Count = 64 bytes

Any value ≥ 100.0001b may result in unpredictable results.

7

NAK

x

NAK = 0 Buffer contains a valid packet for host-IN transaction

NAK = 1 Buffer is empty (gives NAK response to host-IN request)

4.3.10 IEPBBAY_n: Input Endpoint Y-Buffer Base Address (n = 1 to 3) (Offset 5)

7

6

5

4

3

2

1

0

A10

R/W

A9

A8

A7

A6

A5

A4

A3

R/W

BIT

7−0

NAME

RESET

FUNCTION

A[10:3]

x

A[10:3] of Y-buffer base address (padded with 3 LSBs of zeros for a total of 11 bits). This value is set by

the MCU. The UBM or DMA uses this value as the start-address of a given transaction, but note that the

UBM or DMA does not change this value at the end of a transaction.

4.3.11 IEPBCTY_n: Input Endpoint Y-Byte Count (n = 1 to 3) (Offset 6)

7

6

5

4

3

2

1

0

NAK

R/W

C6

C5

C4

C3

C2

C1

C0

R/W

BIT

6−0

NAME

C[6:0]

RESET

x

FUNCTION

Y-Byte count:

X000.0000b Count = 0

X000.0001b Count = 1 byte

:

X011.1111b Count = 63 bytes

X100.0000b Count = 64 bytes

Any value ≥ 100.0001b may result in unpredictable results.

7

NAK

x

NAK = 0 Buffer contains a valid packet for host-IN transaction

NAK = 1 Buffer is empty (gives NAK response to host-IN request)

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MCU Memory Map

4.3.12 IEPSIZXY_n: Input Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7)

7

6

5

4

3

2

1

0

RSV

R/W

S6

S5

S4

S3

S2

S1

S0

R/W

BIT

6−0

NAME

S[6:0]

RESET

x

FUNCTION

X- and Y-buffer size:

0000.0000b Size = 0

0000.0001b Size = 1 byte

:

0011.1111b Size = 63 bytes

0100.0000b Size = 64 bytes

Any value ≥ 100.0001b may result in unpredictable results.

7

RSV

x

Reserved = 0

4.4 Endpoint-0 Descriptor Registers

Unlike registers EDB-1 to EDB-3, which are defined as memory entries in SRAM, endpoint-0 is described by

a set of four registers (two for output and two for input). The registers and their respective addresses, used

for EDB-0 description, are defined in Table 4−7. EDB-0 has no buffer base-address register, since these

addresses are hardwired to FEF8h and FEF0h. Note that the bit positions have been preserved to provide

consistency with EDB-n (n = 1 to 3).

Table 4−7. Input/Output EDB-0 Registers

ADDRESS

REGISTER NAME

DESCRIPTION

BUFFER BASE ADDRESS

FF83h

FF82h

OEPBCNT_0

OEPCNFG_0

Output endpoint_0: Byte count register

Output endpoint_0: Configuration register

FEF0h

FEF8h

FF81h

FF80h

IEPBCNT_0

IEPCNFG_0

Input endpoint_0: Byte count register

Input endpoint_0: Configuration register

4.4.1 IEPCNFG_0: Input Endpoint-0 Configuration Register (Addr:FF80h)

7

6

5

4

3

2

1

0

UBME

R/W

RSV

R/O

TOGLE

R/O

RSV

R/O

STALL

R/W

USBIE

R/W

RSV

R/O

RSV

R/O

BIT

NAME

RSV

RESET

FUNCTION

1−0

2

0

Reserved = 0

USBIE

USB interrupt enable on transaction completion. Set/cleared by the MCU.

USBIE = 0 No interrupt

USBIE = 1 Interrupt on transaction completion

3

STALL

0

USB stall condition indication. Set/cleared by the MCU

STALL = 0 No stall

STALL = 1 USB stall condition. If set by the MCU, then a STALL handshake is initiated and the bit is

cleared automatically by the next setup transaction.

4

5

6

7

RSV

0

Reserved = 0

TOGLE

RSV

USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1.

Reserved = 0

UBME

UBM enable/disable bit. Set/cleared by the MCU

UBME = 0 UBM cannot use this endpoint

UBME = 1 UBM can use this endpoint

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MCU Memory Map

4.4.2 IEPBCNT_0: Input Endpoint-0 Byte Count Register (Addr:FF81h)

7

6

5

4

3

2

1

0

NAK

R/W

RSV

R/O

RSV

R/O

RSV

R/O

C3

C2

C1

C0

R/W

BIT

NAME RESET

FUNCTION

3−0 C[3:0]

0h

Byte count:

0000b Count = 0

:

0111b Count = 7

1000b Count = 8

1001b to 1111b are reserved. (If used, they default to 8)

6−4 RSV

NAK

0

1

Reserved = 0

7

NAK = 0 Buffer contains a valid packet for host-IN transaction

NAK = 1 Buffer is empty (gives NAK response to host-IN request)

4.4.3 OEPCNFG_0: Output Endpoint-0 Configuration Register (Addr:FF82h)

7

6

5

4

3

2

1

0

UBME

R/W

RSV

R/O

TOGLE

R/O

RSV

R/O

STALL

R/W

USBIE

R/W

RSV

R/O

RSV

R/O

BIT

NAME RESET

FUNCTION

1−0 RSV

0

Reserved = 0

2

3

USBIE

USB interrupt enable on transaction completion. Set/cleared by the MCU.

USBIE = 0 No interrupt on transaction completion

USBIE = 1 Interrupt on transaction completion

STALL

0

USB stall condition indication. Set/cleared by the MCU

STALL = 0 No stall

STALL = 1 USB stall condition. If set by the MCU, a STALL handshake is initiated and the bit is cleared automatically.

4

5

6

7

RSV

0

Reserved = 0

TOGLE

RSV

USB \toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1.

Reserved = 0

UBME

UBM enable/disable bit. Set/cleared by the MCU

UBME = 0 UBM cannot use this endpoint

UBME = 1 UBM can use this endpoint

4.4.4 OEPBCNT_0: Output Endpoint-0 Byte Count Register (Addr:FF83h)

7

6

5

4

3

2

1

0

NAK

R/W

RSV

R/O

RSV

R/O

RSV

R/O

C3

C2

C1

C0

R/O

BIT

NAME RESET

FUNCTION

3−0 C[3:0]

0h

Byte count:

0000b Count = 0

:

0111b Count = 7

1000b Count = 8

1001b to 1111b are reserved

6−4 RSV

NAK

0

1

Reserved = 0

7

NAK =0

No valid data in buffer. Ready for host OUT

NAK = 1 Buffer contains a valid packet from host (gives NAK response to host-OUT request).

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USB Registers

5

USB Registers

5.1 FUNADR: Function Address Register (Addr:FFFFh)

This register contains the device function address.

7

6

5

4

3

2

1

0

RSV

R/O

FA6

R/W

FA5

R/W

FA4

R/W

FA3

R/W

FA2

R/W

FA1

R/W

FA0

R/W

BIT

NAME

RESET

FUNCTION

6−0

FA[6:0]

0

These bits define the current device address assigned to the function. The MCU writes a value to this

register because of the SET-ADDRESS host command.

7

RSV

0

Reserved = 0

5.2 USBSTA: USB Status Register (Addr:FFFEh)

All bits in this register are set by the hardware and are cleared by the MCU when writing a 1 to the proper bit

location (writing a 0 has no effect). In addition, each bit can generate an interrupt if its corresponding mask

bit is set (R/C notation indicates read and clear only by the MCU).

7

6

5

4

3

2

1

0

RSTR

R/C

SUSR

R/C

RESR

R/C

RSV

R/O

URRI

R/C

SETUP

R/C

WAKEUP

R/C

STPOW

R/C

BIT

NAME

RESET

FUNCTION

0

STPOW

0

SETUP overwrite bit. Set by hardware when a setup packet is received while there is already a packet

in the setup buffer.

STPOW = 0

STPOW = 1

MCU can clear this bit by writing a 1 (writing 0 has no effect).

SETUP overwrite

1

2

WAKEUP

SETUP

0

Remote wakeup bit

WAKEUP = 0 The MCU can clear this bit by writing a 1 (writing 0 has no effect).

WAKEUP = 1 Remote wakeup request from WAKEUP terminal

SETUP transaction received bit. As long as SETUP is 1, IN and OUT on endpoint-0 are NAKed,

regardless of their real NAK bits value.

SETUP = 0

SETUP = 1

MCU can clear this bit by writing a 1 (writing 0 has no effect).

SETUP transaction received

3

URRI

0

UART RI (ring indicate) status bit – a rising edge causes this bit to be set.

URRI = 0

URRI = 1

The MCU can clear this bit by writing a 1 (writing 0 has no effect).

Ring detected, which is used to wake the chip up (bring it out of suspend).

4

5

RSV

0

Reserved

RESR

Function resume request bit

RESR = 0

RESR = 1

The MCU can clear this bit by writing a 1 (writing 0 has no effect).

Function resume is detected

6

7

SUSR

RSTR

0

Function suspended request bit. This bit is set in response to a global or selective suspend condition.

SUSR = 0

SUSR = 1

The MCU can clear this bit by writing a 1 (writing 0 has no effect).

Function suspend is detected

Function reset request bit. This bit is set in response to the USB host initiating a port reset. This bit is

not affected by the USB function reset.

RSTR = 0

RSTR = 1

The MCU can clear this bit by writing a 1 (writing 0 has no effect).

Function reset is detected

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USB Registers

5.3 USBMSK: USB Interrupt Mask Register (Addr:FFFDh)

7

6

5

4

3

2

1

0

RSTR

R/W

SUSR

R/W

RESR

R/W

RSV

R/O

URRI

R/W

SETUP

R/W

WAKEUP

R/W

STPOW

R/W

BIT

NAME

RESET

FUNCTION

0

1

2

3

STPOW

0

SETUP overwrite interrupt-enable bit

STPOW = 0

STPOW = 1

STPOW interrupt disabled

STPOW interrupt enabled

WAKEUP

SETUP

URRI

Remote wakeup interrupt enable bit

WAKEUP = 0 WAKEUP interrupt disable

WAKEUP = 1 WAKEUP interrupt enable

SETUP interrupt enable bit

SETUP = 0

SETUP = 1

SETUP interrupt disabled

SETUP interrupt enabled

UART RI interrupt enable bit

URRI = 0

URRI = 1

UART RI interrupt disable

UART RI interrupt enable

4

5

RSV

0

Reserved

RESR

Function resume interrupt enable bit

RESR = 0

RESR = 1

Function resume interrupt disabled

Function resume interrupt enabled

6

7

SUSR

RSTR

0

Function suspend interrupt enable

SUSR = 0

SUSR = 1

Function suspend interrupt disabled

Function suspend interrupt enabled

Function reset interrupt bit. This bit is not affected by USB function reset.

RSTR = 0

RSTR = 1

Function reset interrupt disabled

Function reset interrupt enabled

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USB Registers

5.4 USBCTL: USB Control Register (Addr:FFFCh)

Unlike the rest of the registers, this register is cleared by the power-up reset signal only. The USB reset cannot

reset this register (see Figure 5−1).

7

6

5

4

3

2

1

0

CONT

R/W

IREN

R/W

RWUP

R/C

FRSTE

R/W

RSV

R/W

RSV

R/W

SIR

R/W

DIR

R/W

BIT

NAME

DIR

RESET

0

As a response to a setup packet, the MCU decodes the request and sets/clears this bit to reflect the data transfer

direction.

DIR = 0

DIR = 1

USB data-OUT transaction (from host to TUSB3410)

USB data-IN transaction (from TUSB3410 to host)

1

SIR

0

SETUP interrupt-status bit. This bit is controlled by the MCU to indicate to the hardware when the SETUP interrupt

is being serviced.

SIR = 0

SIR = 1

SETUP interrupt is not served. The MCU clears this bit before exiting the SETUP interrupt routine.

SETUP interrupt is in progress. The MCU sets this bit when servicing the SETUP interrupt.

2

3

4

RSV

0

1

Reserved = 0

RSV

This bit must always be written as 0.

FRSTE

Function reset-connection bit. This bit connects/disconnects the USB function reset to/from the MCU reset.

FRSTE = 0 Function reset is not connected to MCU reset

FRSTE = 1 Function reset is connected to MCU reset

5

6

7

RWUP

IREN

0

Device remote wakeup request. This bit is set by the MCU and is cleared automatically.

RWUP = 0

RWUP = 1

Writing a 0 to this bit has no effect

When MCU writes a 1, a remote-wakeup pulse is generated.

IR mode enable. This bit is set and cleared by firmware.

IREN = 0

IREN = 1

IR encoder/decoder is disabled, UART mode is selected

IR encoder/decoder is enabled, UART mode is deselected

CONT

Connect/disconnect bit

CONT = 0

CONT = 1

Upstream port is disconnected. Pullup disabled.

Upstream port is connected. Pullup enabled.

5.5 MODECNFG: Mode Configuration Register (Addr:FFFBh)

This register is cleared by the power-up reset signal only. The USB reset cannot reset this register.

7

6

5

4

3

2

1

0

RSV

R/O

RSV

R/O

RSV

R/O

RSV

R/O

CLKSLCT

R/W

CLKOUTEN

R/W

SOFTSW

R/W

TXCNTL

R/W

BIT

NAME

TXCNTL

RESET

FUNCTION

Transmit output control: Hardware or firmware switching select for 3-state serial output buffer.

0

1

2

3

0

TXCNTL = 0

TXCNTL = 1

Hardware automatic switching is selected

Firmware toggle switching is selected

SOFTSW

0

Soft switch: Firmware controllable 3-state output buffer enable for serial output terminal.

SOFTSW = 0

SOFTSW = 1

Serial output buffer is enabled

Serial output buffer is disabled

CLKOUTEN

CLKSLCT

Clock output enable: Enables/disables the clock output at CLKOUT terminal.

CLKOUTEN = 0 Clock output is disabled. Device drives low at CLKOUT terminal.

CLKOUTEN = 1 Clock output is enabled

Clock output source select: Selects between 3.556-MHz fixed clock or UART baud out clock as output

clock source.

CLKSLCT = 0

CLKSLCT = 1

UART baud out clock is selected as clock output

Fixed 3.556-MHz free running clock is selected as clock output

4−7

RSV

0

Reserved

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TUSB3410, TUSB3410I

USB Registers

Clock Output Control

Bit 2 (CLKOUTEN) in the MODECNFG register enables or disables the clock output at the CLKOUT terminal

of the TUSB3410. The power up default of CLKOUT is disabled. Firmware can write a 1 to enable the clock

output if needed.

Bit 3 (CLKSLCT) in the MODECNFG register selects the output clock source from either a fixed 3.556-MHz

free-running clock or the UART BaudOut clock.

5.6 Vendor ID/Product ID

USB−IF and Microsoft WHQL certification requires that end equipment makers use their own unique vendor

ID and product ID for each product (model). OEMs cannot use silicon vendor’s (for instance, TI’s default)

VID/PID in their end products. A unique VID/PID combination will avoid potential driver conflicts and enable

logo certification. See www.usb.org for more information.

5.7 SERNUM7: Device Serial Number Register (Byte 7) (Addr:FFEFh)

Each TUSB3410 device has a unique 64-bit serial die id number, which is generated during manufacturing.

The die id is incremented sequentially, however there is no assurance that numbers will not be skipped. The

device serial number registers mirror this unique 64-bit serial die id value.

After power-up reset, this read-only register (SERNUM7) contains the most significant byte (byte 7) of the

complete 64-bit device serial number. This register cannot be reset.

7

6

5

4

3

2

1

0

D63

R/O

D62

R/O

D61

R/O

D60

R/O

D59

R/O

D58

R/O

D57

R/O

D56

R/O

BIT

7−0

NAME

RESET

Device serial number byte 7 value

FUNCTION

Device serial number byte 7 value

D[63:56]

Procedure to load device serial number value in shared RAM:

•

After power-up reset, the boot code copies the predefined USB descriptors to shared RAM. As a result,

the default serial number hard-coded in the boot code (0x00 hex) is copied to the shared RAM data space.

2

•

The boot code checks to see if an EEPROM is present on the I C port. If an EEPROM is present and

contains a valid device serial number as part of the USB device descriptor information stored in EEPROM,

then the boot code overwrites the serial number value stored in shared RAM with the one found in

EEPROM. Otherwise, the device serial number value stored in shared RAM remains unchanged. If

firmware is stored in the EEPROM, then it is executed. This firmware can read the SERNUM7 through

SERNUM0 registers and overwrite the serial number stored in RAM or store a custom number in RAM.

•

In summary, the serial number value in external EEPROM has the highest priority to be loaded into shared

RAM data space. The serial number value stored in shared RAM is used as part of the valid device

descriptor information during normal operation.

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USB Registers

5.8 SERNUM6: Device Serial Number Register (Byte 6) (Addr:FFEEh)

The device serial number registers mirror the unique 64-bit die id value.

After power-up reset, this read-only register (SERNUM6) contains byte 6 of the complete 64-bit device serial

number. This register cannot be reset.

7

6

5

4

3

2

1

0

D55

R/O

D54

R/O

D53

R/O

D52

R/O

D51

R/O

D50

R/O

D49

R/O

D48

R/O

BIT

7−0

NAME

RESET

Device serial number byte 6 value

FUNCTION

Device serial number byte 6 value

D[55:48]

NOTE: See the procedure described in the SERNUM7 register (see Section 5.7) to load the device serial number into shared RAM.

5.9 SERNUM5: Device Serial Number Register (Byte 5) (Addr:FFEDh)

The device serial number registers mirror the unique 64-bit die id value.

After power-up reset, this read-only register (SERNUM5) contains byte 5 of the complete 64-bit device serial

number. This register cannot be reset.

7

6

5

4

3

2

1

0

D47

R/O

D46

R/O

D45

R/O

D44

R/O

D43

R/O

D42

R/O

D41

R/O

D40

R/O

BIT

7−0

NAME

RESET

Device serial number byte 5 value

FUNCTION

Device serial number byte 5 value

D[47:40]

NOTE: See the procedure described in the SERNUM7 register (see Section 5.7) to load the device serial number into shared RAM.

5.10 SERNUM4: Device Serial Number Register (Byte 4) (Addr:FFECh)

The device serial number registers mirror the unique 64-bit die id value.

After power-up reset, this read-only register (SERNUM4) contains byte 4 of the complete 64-bit device serial

number. This register cannot be reset.

7

6

5

4

3

2

1

0

D39

R/O

D38

R/O

D37

R/O

D36

R/O

D35

R/O

D34

R/O

D33

R/O

D32

R/O

BIT

7−0

NAME

RESET

Device serial number byte 4 value

FUNCTION

Device serial number byte 4 value

D[39:32]

NOTE: See the procedure described in the SERNUM7 register (see Section 5.7) to load the device serial number into shared RAM.

5.11 SERNUM3: Device Serial Number Register (Byte 3) (Addr:FFEBh)

The device serial number registers mirror the unique 64-bit die id value.

After power-up reset, this read-only register (SERNUM3) contains byte 3 of the complete 64-bit device serial

number. This register cannot be reset.

7

6

5

4

3

2

1

0

D31

R/O

D30

R/O

D29

R/O

D28

R/O

D27

R/O

D26

R/O

D25

R/O

D24

R/O

BIT

7−0

NAME

RESET

Device serial number byte 3 value

FUNCTION

Device serial number byte 3 value

D[31:24]

NOTE: See the procedure described in the SERNUM7 register (see Section 5.7) to load the device serial number into shared RAM.

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USB Registers

5.12 SERNUM2: Device Serial Number Register (Byte 2) (Addr:FFEAh)

The device serial number registers mirror the unique 64-bit die id value.

After power-up reset, this read-only register (SERNUM2) contains byte 2 of the complete 64-bit device serial

number. This register cannot be reset.

7

6

5

4

3

2

1

0

D23

R/O

D22

R/O

D21

R/O

D20

R/O

D19

R/O

D18

R/O

D17

R/O

D16

R/O

BIT

7−0

NAME

RESET

FUNCTION

Device serial number byte 2 value

D[23:16]

0

NOTE: See the procedure described in the SERNUM7 register (see Section 5.7) to load the device serial number into shared RAM.

5.13 SERNUM1: Device Serial Number Register (Byte 1) (Addr:FFE9h)

The device serial number registers mirror the unique 64-bit die id value.

After power-up reset, this read-only register (SERNUM1) contains byte 1 of the complete 64-bit device serial

number. This register cannot be reset.

7

6

5

4

3

2

1

0

D15

R/O

D14

R/O

D13

R/O

D12

R/O

D11

R/O

D10

R/O

D9

D8

R/O

BIT

7−0

NAME

RESET

Device serial number byte 1 value

FUNCTION

Device serial number byte 1 value

D[15:8]

NOTE: See the procedure described in the SERNUM7 register (see Section 5.7) to load the device serial number into shared RAM.

5.14 SERNUM0: Device Serial Number Register (Byte 0) (Addr:FFE8h)

The device serial number registers mirror the unique 64-bit die id value.

After power-up reset, this read-only register (SERNUM0) contains byte 0 of the complete 64-bit device serial

number. This register cannot be reset.

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

R/O

BIT

7−0

NOTE: See the procedure described in the SERNUM7 register (see Section 5.7) to load the device serial number into shared RAM.

NAME

RESET

FUNCTION

D[7:0]

Device serial number byte 0 value

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USB Registers

5.15 Function Reset And Power-Up Reset Interconnect

Figure 5−1 represents the logical connection of the USB-function reset (USBR) signal and the power-up reset

(RESET) terminal. The internal RESET signal is generated from the RESET terminal (PURS signal) or from

the USB reset (USBR signal). The USBR can be enabled or disabled by bit 4 (FRSTE) in the USBCTL register

(see Section 5.4) (on power up, FRSTE = 0). The internal RESET is used to reset all registers and logic, with

the exception of the USBCTL and MODECNFG registers which are cleared by the PURS signal only.

USBCTL Register

To Internal MMRs

MODECNFG Register

MCU

RESET

PURS

RESET

USBR

USB Function Reset

G2

FRSTE

WDT Reset

WDD[5:0]

Figure 5−1. Reset Diagram

5.16 Pullup Resistor Connect/Disconnect

The TUSB3410 enumeration can be activated by the MCU (there is no need to disconnect the cable

physically). Figure 5−2 represents the implementation of the TUSB3410 connect and disconnect from a USB

up-stream port. When bit 7 (CONT) is 1 in the USBCTL register (see Section 5.4), the CMOS driver sources

VDD to the pullup resistor (PUR terminal) presenting a normal connect condition to the USB host. When CONT

is 0, the PUR terminal is driven low. In this state, the 1.5-kΩ resistor is connected to GND, resulting in the device

disconnection state. The PUR driver is a CMOS driver that can provide (VDD − 0.1 V) minimum at 8-mA source

current.

CMOS

PUR

CONT Bit

1.5 kΩ

D+

D−

DP0

DM0

15 kΩ

HOST

TUSB3410

Figure 5−2. Pullup Resistor Connect/Disconnect Circuit

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DMA Controller

6

DMA Controller

Table 6−1 outlines the DMA channels and their associated transfer directions. Two channels are provided for

data transfer between the host and the UART.

Table 6−1. DMA Controller Registers

DMA CHANNEL

DMA−1

TRANSFER DIRECTION

Host to UART

COMMENTS

DMA writes to UART TDR register

DMA reads from UART RDR register

DMA−3

UART to host

6.1 DMA Controller Registers

Each DMA channel can point to one of three EDBs (EDB-1 to EDB-3) and transfer data to/from the UART

channel. The DMA can move data from a given out-point buffer (defined by the EDB) to the destination port.

Similarly, the DMA can move data from a port to a given input-endpoint buffer.

At the end of a block transfer, the DMA updates the byte count and bit 7 (NAK) in the EDB (see Section 4.3)

when receiving. In addition, it uses bit 4 (XY) in the DMACDR register to switch automatically, without

interrupting the MCU (the XY bit toggle is performed by the UBM). The DMA stops only when a time-out or

error condition occurs. When the DMA is transmitting (from the X/Y buffer) it continues alternating between

X/Y buffers until it detects a byte count smaller than the buffer size (buffer size is typically 64 bytes). At that

point it completes the transfer and stops.

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6.1.1 DMACDR1: DMA Channel Definition Register (UART Transmit Channel)

(Addr:FFE0h)

These registers define the EDB number that the DMA uses for data transfer to the UARTS. In addition, these

registers define the data transfer direction and selects X or Y as the transaction buffer.

7

6

5

4

3

2

1

0

EN

R/W

INE

R/W

CNT

R/W

XY

T/R

R/O

E2

E1

E0

R/W

BIT NAME RESET

FUNCTION

2−0 E[2:0]

0

Endpoint descriptor pointer. This field points to a set of EDB registers that is to be used for a given transfer.

3

T/R

This bit is always 1, indicating that the DMA data transfer is from SRAM to the UART TDR register (see Section 7.1.2).

(The MCU cannot change this bit.)

4

XY

0

X/Y buffer select bit.

XY = 0

XY = 1

Next buffer to transmit/receive is the X buffer

Next buffer to transmit/receive is the Y buffer

5

CNT

DMA continuous transfer control bit. This bit defines the mode of the DMA transfer. This bit must always be

written as 1.

In this mode, the DMA and UBM alternate between the X- and Y-buffers. The DMA sets bit 4 (XY) and the UBM uses

it for the transfer. The DMA alternates between the X-/Y-buffers and continues transmitting (from X-/Y-buffer) without

MCU intervention. The DMA terminates, and interrupts the MCU, under the following conditions:

1. When the UBM byte count < buffer size (in EDB), the DMA transfers the partial packet and interrupt the MCU on

completion.

2. Transaction timer expires. The DMA interrupts the MCU.

6

7

INE

EN

0

DMA Interrupt enable/disable bit. This bit enables/disables the interrupt on transfer completion.

INE = 0

Interrupt is disabled. In addition, bit 0 (PPKT) in the DMACSR1 register (see Section 6.1.2) does not clear

bit 7 (EN) and the DMAC is not disabled.

INE = 1

Enables the EN interrupt. When this bit is set, the DMA interrupts the MCU on a 1 to 0 transition of the

bit 7 (EN). (When transfer is completed, EN = 0.)

DMA channel enable bit. The MCU sets this bit to start the DMA transfer. When the transfer completes, or when it

is terminated due to error, this bit is cleared. The 1 to 0 transition of this bit generates an interrupt (if the interrupt is

enabled).

EN = 0

DMA is halted. The DMA is halted when the byte count reaches zero or transaction time-out occurs. When

halted, the DMA updates the byte count, sets NAK = 0 in the output endpoint byte count register, and

interrupts the MCU (if bit 6 (INE) = 1).

EN = 1

Setting this bit starts the DMA transfer.

6.1.2 DMACSR1: DMA Control And Status Register (UART Transmit Channel)

(Addr:FFE1h)

This register defines the transaction time-out value. In addition, it contains a completion code that reports any

errors or a time-out condition.

7

0

6

0

5

0

4

0

3

0

2

0

1

0

PPKT

R/C

R

BIT

NAME RESET

FUNCTION

Partial packet condition bit. This bit is set by the DMA and cleared by the MCU.

0

PPKT

0

PPKT = 0

PPKT = 1

No partial-packet condition

Partial-packet condition detected. When INE = 0, this bit does not clear bit 7 (EN) in the DMACDR1

register; therefore, the DMAC stays enabled, ready for the next transaction. Clears when MCU

writes a 1. Writing a 0 has no effect.

7−1

−

0

These bits are read-only and return 0s when read.

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DMA Controller

6.1.3 DMACDR3: DMA Channel Definition Register (UART Receive Channel)

(Addr:FFE4h)

These registers define the EDB number that the DMA uses for data transfer from the UARTS. In addition, these

registers define the data transfer direction and selects X or Y as the transaction buffer.

7

6

5

4

3

2

1

0

EN

R/W

INE

R/W

CNT

R/W

XY

T/R

R/O

E2

E1

E0

R/W

BIT

NAME

E[2:0]

RESET

FUNCTION

2−0

3

0

1

Endpoint descriptor pointer. This field points to a set of EDB registers that are used for a given transfer.

T/R

This bit is always read as 1. This bit must be written as 0 to update the X/Y buffer bit (bit 4 in this

register) which must only be performed in burst mode.

4

5

XY

0

X/Y buffer select bit.

XY = 0

XY = 1

Next buffer to transmit/receive is X

Next buffer to transmit/receive is Y

CNT

DMA continuous transfer control bit. This bit defines the mode of the DMA transfer. This bit must always

be written as 1.

In this mode, the DMA and UBM alternate between the X- and Y-buffers. The UBM sets bit 4 (XY) and the

DMA uses it for the transfer. The DMA alternates between the X-/Y-buffers and continues receiving (to

X-/Y-buffer) without MCU intervention. The DMA terminates the transfer and interrupts the MCU, under the

following conditions:

1. Transaction time-out expired: DMA updates EDB and interrupts the MCU. UBM transfers the partial

packet to the host.

2. UART receiver error condition: DMA updates EDB and does not interrupt the MCU. UBM transfers the

partial packet to the host.

6

7

INE

EN

0

DMA interrupt enable/disable bit. This bit enables/disables the interrupt on transfer completion.

INE = 0

Interrupt is disabled. In addition, bit 0 (OVRUN) and bit 1 (TXFT) in the DMACSR3 register (see

Section 6.1.4) do not clear bit 7 (EN) and the DMAC is not disabled.

INE = 1

Enables the EN interrupt. When this bit is set, the DMA interrupts the MCU on a 1-to-0 transition

of bit 7 (EN). (When transfer is completed, EN = 0).

DMA channel enable bit. The MCU sets this bit to start the DMA transfer. When transfer completes, or

when terminated due to error, this bit is cleared. The 1-to-0 transition of this bit generates an interrupt (if

the interrupt is enabled).

EN = 0

DMA is halted. The DMA is halted when transaction time-out occurs, or under a UART

receiver-error condition. When halted, the DMA updates the byte count and sets NAK = 0 in the

input endpoint byte count register. If the termination is due to transaction time-out, then the DMA

generates an interrupt. However, if the termination is due to a UART error condition, then the

DMA does not generate an interrupt. (The UART generates the interrupt.)

EN = 1

Setting this bit starts the DMA transfer.

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DMA Controller

6.1.4 DMACSR3: DMA Control And Status Register (UART Receive Channel)

(Addr:FFE5h)

This register defines the transaction time-out value. In addition, it contains a completion code that reports any

errors or a time-out condition.

7

6

5

4

3

2

1

0

TEN

R/W

C4

C3

C2

C1

C0

TXFT

R/C

OVRUN

R/C

R/W

BIT

NAME

RESET

FUNCTION

0

OVRUN

0

Overrun condition bit. This bit is set by DMA and cleared by the MCU (see Table 6−2)

OVRUN = 0 No overrun condition

OVRUN = 1 Overrun condition detected. When IEN = 0, this bit does not clear bit 7 (EN) in the DMACDR

register; therefore, the DMAC stays enabled, ready for the next transaction. Clears when the

MCU writes a 1. Writing a 0 has no effect.

1

TXFT

C[4:0]

0

Transfer time-out condition bit (see Table 6−2)

TXFT = 0

TXFT =1

DMA stopped transfer without time-out

DMA stopped due to transaction time-out. When IEN = 0, this bit does not clear bit 7 (EN) in the

DMACDR3 register (see Section 6.1.3); therefore, the DMAC stays enabled, ready for the next

transaction. Clears when the MCU writes a 1. Writing a 0 has no effect.

6−2

00000b This field defines the transaction time-out value in 1-ms increments. This value is loaded to a down counter every

time a byte transfer occurs. The down counter is decremented every SOF pulse (1 ms). If the counter decrements

to zero, then it sets bit 1 (TXFT) = 1 and halts the DMA transfer. The counter starts counting only when bit 7

(TEN) = 1 and bit 7 (EN) = 1 in the DMACDR3 register and the first byte has been received.

00000 = 0-ms time-out

:

11111 = 31-ms time-out

7

TEN

0

Transaction time-out counter enable/disable bit

TEN = 0

TEN = 1

Counter is disabled (does not time-out)

Counter is enabled

Table 6−2. DMA IN-Termination Condition

IN TERMINATION

UART error

TXFT

OVRUN

COMMENTS

0

1

0

UART error condition detected

UART partial packet

0

This condition occurs when UART receiver has no more data for the host (data

starvation).

UART overrun

1

This condition occurs when X- and Y-input buffers are full and the UART FIFO is full (host

is busy).

6.2 Bulk Data I/O Using the EDB

The UBM (USB buffer manager) and the DMAC (DMA controller) access the EDB to fetch buffer parameters

for IN and OUT transactions (IN and OUT are with respect to host). In this discussion, it is assumed that:

•

The MCU initialized the EDBs

DMA-continuous mode is being used

Double buffering is being used

The X/Y toggle is controlled by the UBM

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DMA Controller

6.2.1 IN Transaction (TUSB3410 to Host)

1. The MCU initializes the IEDB (64-byte packet, and double buffering is used) and the following DMA

registers:

•

DMACSR3: Defines the transaction time-out value.

DMACDR3: Defines the IEDB being used and the DMA mode of operation (continuous mode). Once

this register is set with EN = 1, the transfer starts.

2. The DMA transfers data from the UART to the X buffer. When a block of 64 bytes is transferred, the DMA

updates the byte count and sets NAK to 0 in the input endpoint byte count register (indicating to the UBM

that the X buffer is ready to be transferred to host). The UBM starts X-buffer transfer to host using the

byte-count value in the input endpoint byte count register and toggles the X/Y bit. The DMA continues

transferring data from a device to Y-buffer. At the end of the block transfer, the DMA updates the byte count

and sets NAK to 0 in the input endpoint byte count register (indicating to the UBM that the Y-buffer is ready

to be transferred to host). The DMA continues the transfer from the device to host, alternating between

X-and Y-buffers without MCU intervention.

3. Transfer termination: As mentioned, the DMA/UBM continues the data transfer, alternating between the

X- and Y-buffers. Termination of the transfer can happen under the following conditions:

•

Stop Transfer: The host notifies the MCU (via control-end-point) to stop the transfer. Under this

condition, the MCU sets bit 7 (EN) to 0 in the DMACDR register.

•

Partial Packet: The device receiver has no data to be transferred to host. Under this condition, the

byte-count value is less than 64 when the transaction timer time-out occurs. When the DMA detects

this condition, it sets bit 1 (TXFT) to 1 and bit 0 (OVRUN) to 0 in the DMACSR3 register, updates the

byte count and NAK bit in the the input endpoint byte count register, and interrupts the MCU. The UBM

transfers the partial packet to host.

•

Buffer Overrun: The host is busy, X- and Y-buffers are full (X-NAK = 0 and Y-NAK = 0), and the DMA

cannot write to these buffers. The transaction time-out stops the DMA transfer, the DMA sets bit 1

(TXFT) to 1 and bit 0 (OVRUN) to 1 in the DMACSR3 register, and interrupts the MCU.

UART Error Condition: When receiving from a UART, a receiver-error condition stops the DMA and

sets bit 1 (TXFT) to 1 and bit 0 (OVRUN) to 0 in the DMACSR3 register, but the EN bit remains set at 1.

Therefore, the DMA does not interrupt the MCU. However, the UART generates a status interrupt,

notifying the MCU that an error condition has occurred.

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DMA Controller

6.2.2 OUT Transaction (Host to TUSB3410)

1. The MCU initializes the OEDB (64-byte packet, and double buffering is used) and the following DMA

registers:

•

DMACSR1: Provides an indication of a partial packet.

DMACDR1: Defines the output endpoint being used, and the DMA mode of operation (continuous

mode). Once the EN bit is set to 1 in this register, the transfer starts.

2. The UBM transfers data from host to X-buffer. When a block of 64 bytes is transferred, the UBM updates

the byte count and sets NAK to 1 in the output endpoint byte count register (indicating to DMA that the

X-buffer is ready to be transferred to the UART). The DMA starts X-buffer transfer using the byte-count

value in the output endpoint byte count register. The UBM continues transferring data from host to Y-buffer.

At the end of the block transfer, the UBM updates the byte count and sets NAK to 1 in the output endpoint

byte count register (indicating to DMA that the Y-buffer is ready to be transferred to device). The DMA

continues the transfer from the X-/Y-buffers to the device, alternating between X- and Y-buffers without

MCU intervention.

3. Transfer termination: The DMA/UBM continues the data transfer alternating between X- and Y-buffers.

The termination of the transfer can happen under the following conditions:

•

Stop Transfer: The host notifies the MCU (via control-end point) to stop the transfer. Under this

condition, the MCU sets EN to 0 in the DMACDR1 register.

•

Partial-Packet: UBM receives a partial packet from host. Under this condition, the byte-count value is

less than 64. When the DMA detects this condition, it transfers the partial packet to the device, sets

PPKT to 1, updates NAK to 0 in the output endpoint byte count register, and interrupts the MCU.

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UART

7

UART

7.1 UART Registers

Table 7−1 summarizes the UART registers. These registers are used for data I/O, control, and status

information. UART setup is done by the MCU. Data transfer is typically performed by the DMAC. However,

the MCU can perform data transfer without a DMA; this is useful when debugging the firmware.

Table 7−1. UART Registers Summary

REGISTER ADDRESS

FFA0h

REGISTER NAME

RDR

ACCESS

R/O

FUNCTION

COMMENTS

UART receiver data register

UART transmitter data register

UART line control register

UART flow control register

UART modem control register

UART line status register

UART modem status register

UART divisor register (low byte)

UART divisor register (high byte)

UART Xon register

Can be accessed by MCU or DMA

FFA1h

TDR

W/O

R/W

R/O

FFA2h

LCR

FFA3h

FCRL

MCR

FFA4h

FFA5h

LSR

Can generate an interrupt

FFA6h

MSR

R/O

FFA7h

DLL

R/W

FFA8h

DLH

FFA9h

XON

FFAAh

XOFF

MASK

UART Xoff register

FFABh

UART interrupt mask register

Can control three interrupt sources

7.1.1 RDR: Receiver Data Register (Addr:FFA0h)

The receiver data register consists of a 32-byte FIFO. Data received via the SIN terminal is converted from

serial-to-parallel format and stored in this FIFO. Data transfer from this register to the RAM buffer is the

responsibility of the DMA controller.

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

R/O

BIT

7−0

NAME

D[7:0]

RESET

FUNCTION

0

Receiver byte

7.1.2 TDR: Transmitter Data Register (Addr:FFA1h)

The transmitter data register is double buffered. Data written to this register is loaded into the shift register,

and shifted out on SOUT. Data transfer from the RAM buffer to this register is the responsibility of the DMA

controller.

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

W/O

BIT

7−0

NAME

D[7:0]

RESET

FUNCTION

0

Transmit byte

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UART

7.1.3 LCR: Line Control Register (Addr:FFA2h)

This register controls the data communication format. The word length, number of stop bits, and parity type

are selected by writing the appropriate bits to the LCR.

7

6

5

4

3

2

1

0

FEN

R/W

BRK

R/W

FPTY

R/W

EPRTY

R/W

PRTY

R/W

STP

R/W

WL1

R/W

WL0

R/W

BIT

NAME

RESET

FUNCTION

1:0

WL[1:0]

0

Specifies the word length for transmit and receive

00b = 5 bits

01b = 6 bits

10b = 7 bits

11b = 8 bits

2

STP

0

Specifies the number of stop bits for transmit and receive

STP = 0

STP = 1

1 stop bit (word length = 5, 6, 7, 8)

1.5 stop bits (word length = 5)

2 stop bits (word length = 6, 7, 8)

3

4

5

6

7

PRTY

EPRTY

FPTY

BRK

0

Specifies whether parity is used

PRTY = 0

PRTY = 1

No parity

Parity is generated

Specifies whether even or odd parity is generated

EPRTY = 0 Odd parity is generated (if bit 3 (PRTY) = 1)

EPRTY = 1 Even parity is generated (if PRTY = 1)

Selects the forced parity bit

FPTY = 0

FPTY = 1

Parity is not forced

Parity bit is forced. If bit 4 (EPRTY) = 0, the parity bit is forced to 1

This bit is the break-control bit

BRK = 0

BRK = 1

Normal operation

Forces SOUT into break condition (logic 0)

FEN

FIFO enable. This bit disables/enables the FIFO. To reset the FIFO, the MCU clears and then sets this bit.

FEN = 0

FEN = 1

The FIFO is cleared and disabled. When disabled, the selected receiver flow control is activated.

The FIFO is enabled and it can receive data.

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UART

7.1.4 FCRL: UART Flow Control Register (Addr:FFA3h)

This register provides the flow-control modes of operation (see Table 7−3 for more details).

7

6

5

4

3

2

1

0

485E

R/W

DTR

R/W

RTS

R/W

RXOF

R/W

DSR

R/W

CTS

R/W

TXOA

R/W

TXOF

R/W

BIT

NAME RESET

FUNCTION

This bit controls the transmitter Xon/Xoff flow control.

0

1

2

TXOF

TXOA

CTS

0

TXOF = 0

TXOF = 1

Disable transmitter Xon/Xoff flow control

Enable transmitter Xon/Xoff flow control

This bit controls the transmitter Xon-on-any/Xoff flow control

TXOA = 0

TXOA = 1

Disable the transmitter Xon-on-any/Xoff flow control

Enable the transmitter Xon-on-any/Xoff flow control

Transmitter CTS flow-control enable bit

CTS = 0

CTS = 1

Disables transmitter CTS flow control

CTS flow control is enabled, that is, when CTS input terminal is high, transmission is halted; when

the CTS terminal is low, transmission resumes. When loopback mode is enabled, this bit must be

set if flow control is also required.

3

DSR

0

Transmitter DSR flow-control enable bit

DSR = 0

DSR = 1

Disables transmitter DSR flow control

DSR flow control is enabled, that is, when DSR input terminal is high, transmission is halted; when

the DSR terminal is low, transmission resumes. When loopback mode is enabled, this bit must be

set if flow control is also required.

4

5

RXOF

RTS

0

This bit controls the receiver Xon/Xoff flow control.

RXOF = 0

RXOF = 1

Receiver does not attempt to match Xon/Xoff characters

Receiver searches for Xon/Xoff characters

Receiver RTS flow control enable bit

RTS = 0

RTS = 1

Disables receiver RTS flow control

Receiver RTS flow control is enabled. RTS output terminal goes high when the receiver FIFO HALT

trigger level is reached; it goes low, when the receiver FIFO RESUME receiving trigger level is

reached.

6

7

DTR

0

Receiver DTR flow-control enable bit

DTR = 0

DTR = 1

Disables receiver DTR flow control

Receiver DTR flow control is enabled. DTR output terminal goes high when the receiver FIFO HALT

trigger level is reached; it goes low, when the receiver FIFO RESUME receiving trigger level is

reached.

485E

RS-485 enable bit. This bit configures the UART to control external RS-485 transceivers. When configured in

half-duplex mode (485E = 1), RTS or DTR can be used to enable the RS-485 driver or receiver. See

Figure 3−3.

485E = 0

485E = 1

UART is in normal operation mode (full duplex)

The UART is in half duplex RS-485 mode. In this mode, RTS and DTR are active with opposite

polarity (when RTS = 0, DTR = 1). When the DMA is ready to transmit, it drives RTS = 1 (and

DTR = 0) 2-bit times before the transmission starts. When the DMA terminates the transmission,

it drives RTS = 0 (and DTR = 1) after the transmission stops. When 485E is set to 1, bit 4 (DTR)

and bit 5 (RTS) in the MCR register (see Section 7.1.6) have no effect. Also, see bit 1 (RCVE) in

the MCR register.

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UART

7.1.5 Transmitter Flow Control

On reset (power up, USB, or soft reset) the transmitter defaults to the Xon state and the flow control is set to

mode-0 (flow control is disabled).

Table 7−2. Transmitter Flow-Control Modes

BIT 3

BIT 2

BIT 1

BIT 0

DSR

0

CTS

0

TXOA

TXOF

All flow control is disabled

Xon/Xoff flow control is enabled

Xon on any/ Xoff flow control

Not permissible (see Note 9)

CTS flow control

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

X

1

Combination flow control (see Note 10)

Combination flow control

DSR flow control

0

1

0

1

0

1

0

1

0

1

Combination flow control

1

NOTES: 9. This is a nonpermissible combination. If used, TXOA and TXOF are cleared.

10. Combination example: Transmitter stops when either CTS or Xoff is detected. Transmitter resumes when both CTS is negated and

Xon is detected.

Table 7−3. Receiver Flow-Control Possibilities

BIT 6

BIT 5

BIT 4

MODE

DTR

RTS

0

RXOF

0

1

2

3

4

5

6

7

All flow control is disabled

Xon/Xoff flow control is enabled

RTS flow control

0

1

0

1

0

1

0

1

0

1

0

1

Combination flow control (see Note 11)

DTR flow control

1

0

Combination flow control

0

Combination flow control (see Note 12)

Combination flow control

1

NOTES: 11. Combination example: Both RTS is asserted and Xoff transmitted when the FIFO is full. Both RTS is deasserted and Xon is

transmitted when the FIFO is empty.

12. Combination example: Both DTR and RTS are asserted when the FIFO is full. Both DTR and RTS are deasserted when the FIFO

is empty.

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UART

7.1.6 MCR: Modem-Control Register (Addr:FFA4h)

This register provides control for modem interface I/O and definition of the flow control mode.

7

6

5

4

3

2

1

0

LCD

R/W

LRI

R/W

RTS

R/W

DTR

R/W

RSV

R/W

LOOP

R/W

RCVE

R/W

URST

R/W

BIT

NAME

URST

RESET

FUNCTION

0

UART soft reset. This bit can be used by the MCU to reset the UART.

URST = 0 Normal operation. Writing a 0 by MCU has no effect.

URST = 1 When the MCU writes a 1 to this bit, a UART reset is generated (ORed with hard reset). When

the UART exits the reset state, URST is cleared. The MCU can monitor this bit to determine if the

UART completed the reset cycle.

1

RCVE

LOOP

0

Receiver enable bit. This bit is valid only when bit 7 (485E) in the FCRL register (see Section 7.1.4) is 1 (RS-485

mode). When 485E = 0, this bit has no effect on the receiver.

RCVE = 0 When 485E = 1, the UART receiver is disabled when RTS = 1, i.e., when data is being transmitted,

the UART receiver is disabled.

RCVE = 1 When 485E = 1, the UART receiver is enabled regardless of the RTS state, i.e., UART receiver

is enabled all the time. This mode can detect collisions on the RS-485 bus when received data

does not match transmitted data.

2

This bit controls the normal-/loop-back mode of operation (see Figure 7−1).

LOOP = 0 Normal operation

LOOP = 1 Enable loop-back mode of operation. In this mode the following occur:

S

SOUT is set high

SIN is disconnected from the receiver input.

The transmitter serial output is looped back into the receiver serial input.

The four modem-control inputs: CTS, DSR, DCD, and RI/CP are disconnected.

DTR, RTS, LRI and LCD are internally connected to the four modem-control inputs, and read

in the MSR register (see Section 7.1.8) as described below. Note: the FCRL register (see

Section 7.1.4) must be configured to enable bits 2 (CTS) and 3 (DSR) to maintain proper

operation with flow control and loop back.

S

DTR is reflected in MSR register bit 4 (LCTS)

RTS is reflected in MSR register bit 5 (LDSR)

LRI is reflected in MSR register bit 6 (LRI)

LCD is reflected in MSR register bit 7 (LCD)

3

4

RSV

DTR

0

Reserved

This bit controls the state of the DTR output terminal (see Figure 7−1). This bit has no effect when auto-flow

control is used or when bit 7 (485E) = 1 (in the FCRL register, see Section 7.1.4).

DTR = 0

DTR = 1

Forces the DTR output terminal to inactive (high)

Forces the DTR output terminal to active (low)

5

6

7

RTS

LRI

0

This bit controls the state of the RTS output terminal (see Figure 7−1). This bit has no effect when auto-flow

control is used or when bit 7 (485E) = 1 (in the FCRL register, see Section 7.1.4).

RTS = 0

RTS = 1

Forces the RTS output terminal to inactive (high)

Forces the RTS output terminal to active (low)

This bit is used for loop-back mode only. When in loop-back mode, this bit is reflected in bit 6 (LRI) in the MSR

register, see Section 7.1.8 (see Figure 7−1).

LRI = 0

LRI = 1

Clears the MSR register bit 6 to 0

Sets the MSR register bit 6 to 1

LCD

This bit is used for loop-back mode only. When in loop-back mode, this bit is reflected in bit 7 (LCD) in the MSR

register, see Section 7.1.8 (see Figure 7−1).

LCD = 0

LCD = 1

Clears the MSR register bit 7 to 0

Sets the MSR register bit 7 to 1

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UART

7.1.7 LSR: Line-Status Register (Addr:FFA5h)

This register provides the status of the data transfer. DMA transfer is halted when any of bit 0 (OVR), bit 1

(PTE), bit 2 (FRE), or bit 3 (BRK) is 1.

7

6

5

4

3

2

1

0

RSV

R/O

TEMT

R/O

TxE

R/O

RxF

R/O

BRK

R/C

FRE

R/C

PTE

R/C

OVR

R/C

BIT

NAME

OVR

RESET

FUNCTION

0

1

2

3

0

This bit indicates the overrun condition of the receiver. If set, it halts the DMA transfer and generates a

status interrupt (if enabled).

OVR = 0

OVR = 1

No overrun error

Overrun error has occurred. Clears when the MCU writes a 1. Writing a 0 has no effect.

PTE

FRE

BRK

This bit indicates the parity condition of the received byte. If set, it halts the DMA transfer and generates a

status interrupt (if enabled).

PTE = 0

PTE = 1

No parity error in data received

Parity error in data received. Clears when the MCU writes a 1. Writing a 0 has no effect.

This bit indicates the framing condition of the received byte. If set, it halts the DMA transfer and generates

a status interrupt (if enabled).

FRE = 0

FRE = 1

No framing error in data received

Framing error in data received. Clears when MCU writes a 1. Writing a 0 has no effect.

This bit indicates the break condition of the received byte. If set, it halts the DMA transfer and generates a

status interrupt (if enabled).

BRK = 0

BRK = 1

No break condition

A break condition in data received was detected. Clears when the MCU writes a 1. Writing a 0

has no effect.

4

5

RxF

TxE

0

1

This bit indicates the condition of the receiver data register. Typically, the MCU does not monitor this bit

since data transfer is done by the DMA controller.

RxF = 0

RxF = 1

No data in the RDR

RDR contains data. Generates Rx interrupt (if enabled).

This bit indicates the condition of the transmitter data register. Typically, the MCU does not monitor this bit

since data transfer is done by the DMA controller.

TxE = 0

TxE = 1

TDR is not empty

TDR is empty. Generates Tx interrupt (if enabled).

6

7

TEMT

RSV

1

0

This bit indicates the condition of both transmitter data register and shift register is empty.

TEMT = 0 Either TDR or TSR is not empty

TEMT = 1 Both TDR and TSR are empty

Reserved = 0

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UART

Device Terminals

CTS

DSR

RI/CP

DCD

Bit 4 LCTS

Bit 5 LDSR

Bit 6 LRI

Modem

Status

Register

Bit 7 LCD

FCRL Register Setting

DTR

Bit 4 DTR

Bit 5 RTS

Bit 6 LRI

RTS

Modem

Control

Register

Bit 7 LCD

Bit 2 LOOP

FCRL Register Setting

Figure 7−1. MSR and MCR Registers in Loop-Back Mode

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TUSB3410, TUSB3410I

UART

7.1.8 MSR: Modem-Status Register (Addr:FFA6h)

This register provides information about the current state of the control lines from the modem.

7

6

5

4

3

2

1

0

LCD

R/O

LRI

R/O

LDSR

R/O

LCTS

R/O

ΔCD

R/C

TRI

R/C

ΔDSR

R/C

ΔCTS

R/C

BIT

NAME RESET

FUNCTION

0

ΔCTS

0

This bit indicates that the CTS input has changed state. Cleared when the MCU writes a 1 to this bit. Writing a

0 has no effect.

1

ΔDSR

0

This bit indicates that the DSR input has changed state. Cleared when the MCU writes a 1 to this bit. Writing a

0 has no effect.

ΔDSR = 0 Indicates no change in the DSR input

ΔDSR = 1 Indicates that the DSR input has changed state since the last time it was read. Clears when the MCU

writes a 1. Writing a 0 has no effect.

2

3

4

5

6

7

TRI

0

Trailing edge of the ring indicator. This bit indicates that the RI/CP input has changed from low to high. This bit

is cleared when the MCU writes a 1 to this bit. Writing a 0 has no effect.

TRI = 0

TRI = 1

Indicates no applicable transition on the RI/CP input

Indicates that an applicable transition has occurred on the RI/CP input.

ΔCD

LCTS

LDSR

LRI

This bit indicates that the CD input has changed state. Cleared when the MCU writes a 1 to this bit. Writing a 0

has no effect.

ΔCD = 0

ΔCD = 1

Indicates no change in the CD input

Indicates that the CD input has changed state since the last time it was read.

During loopback, this bit reflects the status of bit 4 (DTR) in the MCR register, see Section 7.1.6 (see

Figure 7−1)

LCTS = 0 CTS input is high

LCTS = 1 CTS input is low

During loop back, this bit reflects the status of bit 5 (RTS) in the MCR register, see Section 7.1.6 (see

Figure 7−1)

LDSR = 0 DSR input is high

LDSR= 1

DSR input is low

During loop back, this bit reflects the status of bit 6 (LRI) in the MCR register, see Section 7.1.6 (see

Figure 7−1)

LRI = 0

LRI = 1

RI/CP input is high

RI/CP input is low

LCD

During loopback, this bit reflects the status of bit 7 (LCD) in the MCR register, see Section 7.1.6 (see

Figure 7−1)

LCD = 0

CD input is high

CD input is low

7.1.9 DLL: Divisor Register Low Byte (Addr:FFA7h)

This register contains the low byte of the baud-rate divisor.

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

R/W

BIT

7−0

NAME

D[7:0]

RESET

FUNCTION

08h

Low-byte value of the 16-bit divisor for generation of the baud clock in the baud-rate generator.

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UART

7.1.10 DLH: Divisor Register High Byte (Addr:FFA8h)

This register contains the high byte of the baud-rate divisor.

7

6

5

4

3

2

1

0

D15

R/W

D14

R/W

D13

R/W

D12

R/W

D11

R/W

D10

R/W

D9

D8

R/W

BIT

7−0

NAME

RESET

FUNCTION

High-byte value of the 16-bit divisor for generation of the baud clock in the baud-rate generator.

D[15:8]

00h

7.1.11 Baud-Rate Calculation

The following formulas calculate the baud-rate clock and the divisors. The baud-rate clock is derived from the

96-MHz master clock (dividing by 6.5). The table below presents the divisors used to achieve the desired baud

rates, together with the associate rounding errors.

96 MHz

Baud CLK +

Divisor +

+ 14.76923077 MHz

6.5

6

14.76923077 10

Desired Baud Rate 16

Table 7−4. DLL/DLH Values and Resulted Baud Rates

DLL/DLH VALUE

DECIMAL HEXADECIMAL

DESIRED BAUD

RATE

ACTUAL BAUD

RATE

ERROR %

1 200

2 400

769

385

192

128

96

64

48

24

16

8

0301

0181

00C0

0080

0060

0040

0030

0018

0010

0008

0004

0002

0001

1 200.36

2 397.60

0.03

0.01

0.16

4 800

4 807.69

7 200

7 211.54

9 600

9 615.38

14 400

19 200

38 400

57 600

115 200

230 400

460 800

921 600

14 423.08

19 230.77

38 461.54

57 692.31

115 384.62

230 769.23

461 538.46

923 076.92

4

2

1

NOTE: The TUSB3410 does support baud rates lower than 1200 bps, which are not

listed due to less interest.

7.1.12 XON: Xon Register (Addr:FFA9h)

This register contains a value that is compared to the received data stream. Detection of a match interrupts

the MCU (only if the interrupt enable bit is set). This value is also used for Xon transmission.

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

R/W

BIT

7−0

NAME

D[7:0]

RESET

FUNCTION

Xon value to be compared to the incoming data stream

0000

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TUSB3410, TUSB3410I

UART

7.1.13 XOFF: Xoff Register (Addr:FFAAh)

This register contains a value that is compared to the received data stream. Detection of a match halts the

DMA transfer, and interrupts the MCU (only if the interrupt enable bit is set). This value is also used for Xoff

transmission.

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

R/W

BIT

7−0

NAME

D[7:0]

RESET

FUNCTION

Xoff value to be compared to the incoming data stream

0000

7.1.14 MASK: UART Interrupt-Mask Register (Addr:FFABh)

This register controls the UARTs interrupt sources.

7

6

5

4

3

2

1

0

RSV

R/O

RSV

R/O

RSV

R/O

RSV

R/O

RSV

R/O

TRI

R/W

SIE

R/W

MIE

R/W

BIT

NAME

MIE

RESET

FUNCTION

0

This bit controls the UART-modem interrupt.

MIE = 0

MIE = 1

Modem interrupt is disabled

Modem interrupt is enabled

1

SIE

TRI

RSV

0

This bit controls the UART-status interrupt.

SIE = 0

SIE = 1

Status interrupt is disabled

Status interrupt is enabled

2

This bit controls the UART-TxE/RxF interrupts

TRI = 0

TRI = 1

TxE/RxF interrupts are disabled

TxE/RxF interrupts are enabled

7−3

Reserved = 0

7.2 UART Data Transfer

Figure 7−2 illustrates the data transfer between the UART and the host using the DMA controller and the USB

buffer manager (UBM). A buffer of 512 bytes is reserved for buffering the UART channel (transmit and receive

buffers). The UART channel has 64 bytes of double-buffer space (X- and Y-buffer). When the DMA writes to

the X-buffer, the UBM reads from the Y-buffer. Similarly, when the DMA reads from the X-buffer, the UBM writes

to the Y-buffer. The DMA channel is configured to operate in the continuous mode (by setting bit 5 (CNT) in

the DMACDR registers = 1). Once the MCU enables the DMA, data transfer toggles between the UMB and

the DMA without MCU intervention. See Section 6.2.1, IN Transaction (TUSB3410 to Host), for DMA

transfer-termination condition.

7.2.1 Receiver Data Flow

The UART receiver has a 32-byte FIFO. The receiver FIFO has two trigger levels. One is the high-level mark

(HALT), which is set to 12 bytes, and the other is the low-level mark (RESUME), which is set to 4 bytes. When

the HALT mark is reached, either the RTS terminal goes high or Xoff is transmitted (depending on the auto

setting). When the FIFO reaches the RESUME mark, then either the RTS terminal goes low or Xon is

transmitted.

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UART

Receiver

Halt on Error or Time-Out

64-Byte

Y-Buffer

RDR: 32-Byte FIFO

DMA

DMACDR3

SIN

4

8

64-Byte

X-Buffer

RTS/DTR = 1

X/Y

or Xoff Transmitted

RTS/DTR = 0

or Xon Transmitted

USB

Buffer

Host

Xoff/Xon

Manager

CTS/DTR = 1/0

Pause/Run

64-Byte

Y-Buffer

DMA

DMACDR1

SOUT

64-Byte

X-Buffer

TDR

Figure 7−2. Receiver/Transmitter Data Flow

7.2.2 Hardware Flow Control

Figure 7−3 illustrates the connection necessary to achieve hardware flow control. The CTS and RTS signals

are provided for this purpose. Auto CTS and auto RTS (and Xon/Xoff) can be enabled/disabled independently

by programming the UART flow control register (FCRL).

TUSB3410

SIN

External Device

SOUT

RTS

SOUT

CTS

SIN

RTS

Figure 7−3. Auto Flow Control Interconnect

7.2.3 Auto RTS (Receiver Control)

In this mode, the RTS output terminal signals the receiver-FIFO status to an external device. The RTS output

signal is controlled by the high- and low-level marks of the FIFO. When the high-level mark is reached, RTS

goes high, signaling to an external sending device to halt its transfer. Conversely, when the low-level mark is

reached, RTS goes low, signaling to an external sending device to resume its transfer.

Data transfer from the FIFO to the X-/Y-buffer is performed by the DMA controller. See Section 6.2.1, IN

Transaction (TUSB3410 to Host), for DMA transfer-termination condition.

7.2.4 Auto CTS (Transmitter Control)

In this mode, the CTS input terminal controls the transfer from internal buffer (X or Y) to the TDR. When the

DMA controller transfers data from the Y-buffer to the TDR and the CTS input terminal goes high, the DMA

controller is suspended until CTS goes low. Meanwhile, the UBM is transferring data from the host to the

X-buffer. When CTS goes low, the DMA resumes the transfer. Data transfer continues alternating between

the X- and Y-buffers, without MCU intervention. See Section 6.2.2, OUT Transaction (Host to TUSB3410), for

DMA transfer-termination condition.

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UART

7.2.5 Xon/Xoff Receiver Flow Control

To enable Xon/Xoff flow control, certain bits within the modem control register must be set as follows: MCR

bit 5 = 1 and MCR bits 6 and 7 = 00. In this mode, the Xon/Xoff bytes are transmitted to an external sending

device to control the device’s transmission. When the high-level mark (of the FIFO) is reached, the Xoff byte

is transmitted, signaling to an external sending device to halt its transfer. Conversely, when the low-level mark

is reached, the Xon byte is transmitted, signaling to an external sending device to resume its transfer. The data

transfer from the FIFO to X-/Y-buffer is performed by the DMA controller.

7.2.6 Xon/Xoff Transmit Flow Control

To enable Xon/Xoff flow control, certain bits within the modem control register must be set as follows: MCR

bit 5 = 1 and MCR bits 6 and 7 = 00. In this mode, the incoming data are compared to the XON and XOFF

registers. If a match to XOFF is detected, the DMA is paused. If a match to XON is detected, the DMA resumes.

Meanwhile, the UBM is transferring data from the host to the X-buffer. The MCU does not switch the buffers

unless the Y-buffer is empty and the X-buffer is full. When Xon is detected, the DMA resumes the transfer.

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Expanded GPIO Port

8

Expanded GPIO Port

8.1 Input/Output and Control Registers

The TUSB3410 has four general-purpose I/O terminals (P3.0, P3.1, P3.3, and P3.4) that are controlled by

firmware running on the MCU. Each terminal can be controlled individually and each is implemented with a

12-mA push/pull CMOS output with 3-state control plus input. The MCU treats the outputs as open drain types

in that the output can be driven low continuously, but a high output is driven for two clock cycles and then the

output is high impedance.

An input terminal can be read using the MOV instruction. For example, MOV C,P3.3 reads the input on P3.3.

As a precaution, be certain the associated output is high impedance before reading the input.

An output can be set high (and then high impedance) using the SETB instruction. For example, SETB P3.1

sets P3.1 high. An output can be set low using the CLR instruction, as in CLR P3.4, which sets P3.4 low (driven

continuously until changed).

Each GPIO terminal has an associated internal pullup resistor. It is strongly recommended that the pullup

resistor remain connected to the terminal to prevent oscillations in the input buffer. The only exception is if an

external source always drives the input.

8.1.1 PUR_3: GPIO Pullup Register For Port 3 (Addr:FF9Eh)

7

6

5

4

3

2

1

0

RSV

R/O

RSV

R/O

RSV

R/O

Pin4

R/W

Pin3

R/W

RSV

R/O

Pin1

R/W

Pin0

R/W

BIT

NAME

RESET

FUNCTION

0

1

3

4

Pin0

Pin1

Pin3

Pin4

0

The MCU may write to this register. If the MCU sets any of these bits to 1, then the pullup resistor is

disconnected from the associated terminal. If the MCU clears any of these bits to 0, then the pullup resistor

is connected from the terminal. The pullup resistor is connected to the V power supply.

CC

2, 5, 6,

7

RSV

0

Reserved

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Expanded GPIO Port

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TUSB3410, TUSB3410I

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Interrupts

9

Interrupts

9.1 8052 Interrupt and Status Registers

All 8052 standard, five interrupt sources are preserved. SIE is the standard interrupt-enable register that

controls the five interrupt sources. This is also known as IE0 located at S:A8h in the special function register

area. All the additional interrupt sources are ORed together to generate EX0.

Table 9−1. 8052 Interrupt Location Map

INTERRUPT SOURCE

DESCRIPTION

UART interrupt

START ADDRESS

0023h

COMMENTS

ES

ET1

EX1

ET0

EX0

Reset

Timer-1 interrupt

External interrupt-1

Timer-0 interrupt

External interrupt-0

001Bh

0013h

000Bh

0003h

Used for all internal peripherals

0000h

9.1.1 8052 Standard Interrupt Enable (SIE) Register

7

6

5

4

3

2

1

0

EA

R/W

RSV

R/W

RSV

R/W

ES

ET1

R/W

EX1

R/W

ET0

R/W

EX0

R/W

BIT

NAME

EX0

RESET

FUNCTION

0

1

2

3

4

0

Enable or disable external interrupt-0

EX0 = 0 External interrupt-0 is disabled

EX0 = 1 External interrupt-0 is enabled

ET0

EX1

ET1

ES

0

Enable or disable timer-0 interrupt

ET0 = 0

ET0 = 1

Timer-0 interrupt is disabled

Timer-0 interrupt is enabled

Enable or disable external interrupt-1

EX1 = 0 External interrupt-1 is disabled

EX1 = 1 External interrupt-1 is enabled

Enable or disable timer-1 interrupt

ET1 = 0

Timer-1 interrupt is disabled

EX1 = 1 Timer-1 interrupt is enabled

Enable or disable serial port interrupts

ES = 0

ES = 1

Serial-port interrupt is disabled

Serial-port interrupt is enabled

5, 6

7

RSV

EA

0

Reserved

Enable or disable all interrupts (global disable)

EA = 0

EA = 1

Disable all interrupts

Each interrupt source is individually controlled

9.1.2 Additional Interrupt Sources

2

All nonstandard 8052 interrupts (DMA, I C, etc.) are ORed to generate an internal INT0. Furthermore, the

INT0 must be programmed as an active low-level interrupt (not edge-triggered). After reset, if INT0 is not

changed, then it is an edge-triggered interrupt. A vector interrupt register is provided to identify all interrupt

sources (see Section 9.1.3, VECINT: Vector Interrupt Register). Up to 64 interrupt vectors are provided. It is

the responsibility of the MCU to read the vector and dispatch to the proper interrupt routine.

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9.1.3 VECINT: Vector Interrupt Register (Addr:FF92h)

This register contains a vector value, which identifies the internal interrupt source that is trapped to location

0003h. Writing (any value) to this register removes the vector and updates the next vector value (if another

interrupt is pending). Note: the vector value is offset; therefore, its value is in increments of two (bit 0 is set

to 0). When no interrupt is pending, the vector is set to 00h (see Table 9−2). As shown, the interrupt vector

is divided to two fields: I[2:0] and G[3:0]. The I field defines the interrupt source within a group (on a

first-come-first-served basis). In the G field, which defines the group number, group G0 is the lowest and G15

is the highest priority.

7

6

5

4

3

I2

2

I1

1

I0

0

G3

R/O

G2

R/O

G1

R/O

G0

R/O

BIT

NAME

RESET

FUNCTION

3−1

I[2:0]

0H

This field defines the interrupt source in a given group. See Table 9−2. Bit 0 = 0 always; therefore, vector values

are offset by two.

7−4

G[3:0]

0H

This field defines the interrupt group. I[2:0] and G[3:0] combine to produce the actual interrupt vector.

Table 9−2. Vector Interrupt Values

G[3:0]

(Hex)

I[2:0]

(Hex)

VECTOR

(Hex)

INTERRUPT SOURCE

0

00

No interrupt

1

0

1

2

3

4−7

10

12

14

16

18−1E

Not used

Output endpoint-1

Output endpoint-2

Output endpoint-3

Reserved

2

0

1

2

3

4−7

20

22

24

26

28−2E

Reserved

Input endpoint-1

Input endpoint-2

Input endpoint-3

Reserved

3

0

1

2

3

4

5

6

7

30

32

34

36

38

3A

3C

3E

STPOW packet received

SETUP packet received

Reserved

RESR interrupt

SUSR interrupt

RSTR interrupt

Wakeup

2

4

0

1

2

3

4−7

40

42

44

I C TXE interrupt

2

I C RXF interrupt

Input endpoint-0

Output endpoint-0

Reserved

46

48 → 4E

5

0

1

2−7

50

52

54 → 5E

UART status interrupt

UART modem interrupt

Reserved

6

0

1

2−7

60

62

64 → 6E

UART RXF interrupt

UART TXE interrupt

Reserved

7

0−7

70 → 7E

Reserved

8

0

2

3−7

80

84

86−8E

DMA1 interrupt

DMA3 interrupt

Reserved

9−15

X

90 → FE

Not used

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9.1.4 Logical Interrupt Connection Diagram (Internal/External)

Figure 9−1 shows the logical connection of the interrupt sources and its relationship to INT0. The priority

encoder generates an 8-bit vector, corresponding to 64 interrupt sources (not all are used). The interrupt

priorities are hardwired. Vector 0x88 is the highest and 0x12 is the lowest.

Interrupts

Priority

Encoder

IEO

Vector

IEO (INT0)

Figure 9−1. Internal Vector Interrupt

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10 I²C Port

10.1 I²C Registers

10.1.1 I2CSTA: I²C Status and Control Register (Addr:FFF0h)

This register controls the stop condition for read and write operations. In addition, it provides transmitter and

receiver handshake signals with their respective interrupt enable bits.

7

6

5

4

3

2

1

0

RXF

R/O

RIE

R/W

ERR

R/C

1/4

R/W

TXE

R/O

TIE

R/W

SRD

R/W

SWR

R/W

BIT

NAME

RESET

FUNCTION

2

0

SWR

0

Stop write condition. This bit determines if the I C controller generates a stop condition when data from the

I2CDAO register is transmitted to an external device.

SWR = 0

Stop condition is not generated when data from the I2CDAO register is shifted out to an external

device.

SWR = 1

Stop condition is generated when data from the I2CDAO register is shifted out to an external device.

2

1

SRD

0

Stop read condition. This bit determines if the I C controller generates a stop condition when data is received and

loaded into the I2CDAI register.

SRD = 0

Stop condition is not generated when data from the SDA line is shifted into the I2CDAI register.

Stop condition is generated when data from the SDA line are shifted into the I2CDAI register.

SRD = 1

2

3

TIE

0

1

I C transmitter empty interrupt enable

TIE = 0

TIE = 1

Interrupt disable

Interrupt enable

2

TXE

I C transmitter empty. This bit indicates that data can be written to the transmitter. It can be used for polling or it

can generate an interrupt.

TXE = 0

TXE = 1

Transmitter is full. This bit is cleared when the MCU writes a byte to the I2CDAO register.

2

Transmitter is empty. The I C controller sets this bit when the contents of the I2CDAO register are

copied to the SDA shift register.

4

5

1/4

0

Bus speed selection (see Note 13)

1/4 = 0

1/4 = 1

100-kHz bus speed

400-kHz bus speed

ERR

Bus error condition. This bit is set by the hardware when the device does not respond. It is cleared by the MCU.

ERR = 0

No bus error

ERR = 1

Bus error condition has been detected. Clears when the MCU writes a 1. Writing a 0 has no effect.

2

6

7

RIE

0

I C receiver ready interrupt enable

RIE = 0

RIE = 1

Interrupt disable

Interrupt enable

2

RXF

I C receiver full. This bit indicates that the receiver contains new data. It can be used for polling or it can generate

an interrupt.

RXF = 0

RXF = 1

Receiver is empty. This bit is cleared when the MCU reads the I2CDAI register.

2

Receiver contains new data. This bit is set by the I C controller when the received serial data has

been loaded into the I2CDAI register.

2

NOTE 13: The bootcode automatically sets the I C bus speed to 400 kHz. Only 400-kHz I C EEPROMs can be used.

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10.1.2 I2CADR: I²C Address Register (Addr:FFF3h)

This register holds the device address and the read/write command bit.

7

6

5

4

3

2

1

0

A6

A5

A4

A3

A2

A1

A0

R/W

BIT

NAME

R/W

RESET

FUNCTION

0

Read/write command bit

R/W = 0 Write operation

R/W = 1 Read operation

7−1

A[6:0]

0h

Seven address bits for device addressing

10.1.3 I2CDAI: I²C Data-Input Register (Addr:FFF2h)

This register holds the received data from an external device.

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

R/O

BIT

7−0

NAME

D[7:0]

RESET

FUNCTION

2

0

8-bit input data from an I C device

10.1.4 I2CDAO: I²C Data-Output Register (Addr:FFF1h)

This register holds the data to be transmitted to an external device. Writing to this register starts the transfer

on the SDA line.

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

W/O

BIT

7−0

NAME

D[7:0]

RESET

FUNCTION

2

0

8-bit output data to an I C device

10.2 Random-Read Operation

A random read requires a dummy byte-write sequence to load in the data word address. Once the

device-address word and the data-word address are clocked out and acknowledged by the device, the MCU

starts a current-address sequence. The following describes the sequence of events to accomplish this

transaction.

Device Address + EPROM [High Byte]

2

•

The MCU clears bit 1 (SRD) within the I2CSTA register. This forces the I C controller not to generate a

stop condition after the contents of the I2CDAI register are received.

2

•

The MCU clears bit 0 (SWR) within the I2CSTA register. This forces the I C controller not to generate a

stop condition after the contents of the I2CDAO register are transmitted.

•

The MCU writes the device address (bit 0 (R/W) = 0) to the I2CADR register (write operation)

The MCU writes the high byte of the EEPROM address into the I2CDAO register (this starts the transfer

on the SDA line).

•

Bit 3 (TXE) in the I2CSTA register is automatically cleared (indicates busy) by writing data to the I2CDAO

register.

The contents of the I2CADR register are transmitted to EEPROM (preceded by start condition on SDA).

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•

The contents of the I2CDAO register are transmitted to EEPROM (EPROM address).

Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register has

been transmitted.

•

A stop condition is not generated.

EPROM [Low Byte]

•

The MCU writes the low byte of the EEPROM address into the I2CDAO register.

Bit 3 (TXE) in the I2CSTA register is automatically cleared (indicates busy) by writing to the I2CDAO

register.

•

The contents of the I2CDAO register are transmitted to the device (EEPROM address).

Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register has

been transmitted.

•

This completes the dummy write operation. At this point, the EEPROM address is set and the MCU can

do either a single- or a sequential-read operation.

10.3 Current-Address Read Operation

Once the EEPROM address is set, the MCU can read a single byte by executing the following steps:

2

•

The MCU sets bit 1 (SRD) in the I2CSTA register to 1. This forces the I C controller to generate a stop

condition after the I2CDAI-register contents are received.

•

The MCU writes the device address (bit 0 (R/W) = 1) to the I2CADR register (read operation).

The MCU writes a dummy byte to the I2CDAO register (this starts the transfer on SDA line).

Bit 7 (RXF) in the I2CSTA register is cleared (RX is empty).

The contents of the I2CADR register are transmitted to the device (preceded by start condition on SDA).

The data from EEPROM are latched into the I2CDAI register (stop condition is transmitted).

Bit 7 (RXF) in the I2CSTA register is set and interrupts the MCU, indicating that the data are available.

The MCU reads the I2CDAI register. This clears bit 7 (RXF) in the I2CSTA register.

10.4 Sequential-Read Operation

Once the EEPROM address is set, the MCU can execute a sequential read operation by executing the

following (this example illustrates a 32-byte sequential read):

Device Address

2

•

The MCU clears bit 1 (SRD) in the I2CSTA register. This forces the I C controller to not generate a stop

condition after the I2CDAI register contents are received.

•

The MCU writes the device address (bit 0 (R/W) = 1) to the I2CADR register (read operation).

The MCU writes a dummy byte to the I2CDAO register (this starts the transfer on the SDA line).

Bit 7 (RXF) in the I2CSTA register is cleared (RX is empty).

The contents of the I2CADR register are transmitted to the device (preceded by start condition on

SDA).

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N-Byte Read (31 Bytes)

•

The data from the device is latched into the I2CDAI register (stop condition is not transmitted).

Bit 7 (RXF) in the I2CSTA register is set and interrupts the MCU, indicating that data is available.

The MCU reads the I2CDAI register. This clears bit 7 (RXF) in the I2CSTA register.

This operation repeats 31 times.

Last-Byte Read (Byte 32)

2

•

MCU sets bit 1 (SRD) in the I2STA register to 1. This forces the I C controller to generate a stop

condition after the I2CDAI register contents are received.

•

The data from the device is latched into the I2CDAI register (stop condition is transmitted).

Bit 7 (RXF) in the I2CSTA register is set and interrupts the MCU, indicating that data is available.

The MCU reads the I2CDAI register. This clears bit 7 (RXF) in the I2CSTA register.

10.5 Byte-Write Operation

The byte-write operation involves three phases: device address + EPROM [high byte] phase, EPROM [low

byte] phase, and EPROM [DATA] phase. The following describes the sequence of events to accomplish the

byte-write transaction.

Device Address + EPROM [High Byte]

2

•

The MCU sets clears the SWR bit in the I2CSTA register. This forces the I C controller to not generate

a stop condition after the contents of the I2CDAO register are transmitted.

•

The MCU writes the device address (bit 0 (R/W) = 0) to the I2CADR register (write operation).

The MCU writes the high byte of the EEPROM address into the I2CDAO register (this starts the

transfer on the SDA line).

•

Bit 3 (TXE) in the I2CSTA register is cleared (indicates busy).

The contents of the I2CADR register are transmitted to the device (preceded by start condition on

SDA).

•

The contents of the I2CDAO register are transmitted to the device (EEPROM high address).

Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register

contents have been transmitted.

EPROM [Low Byte]

•

The MCU writes the low byte of the EEPROM address into the I2CDAO register.

Bit 3 (TXE) in the I2CSTA register is cleared (indicating busy).

The contents of the I2CDAO register are transmitted to the device (EEPROM address).

Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register

contents have been transmitted.

EPROM [DATA]

2

•

The MCU sets bit 0 (SWR) in the I2CSTA register. This forces the I C controller to generate a stop

condition after the contents of the I2CDAO register are transmitted.

•

The data to be written to the EPROM is written by the MCU into the I2CDAO register.

Bit 3 (TXE) in the I2CSTA register is cleared (indicates busy).

The contents of the I2CDAO register are transmitted to the device (EEPROM data).

Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register

contents have been transmitted.

2

•

The I C controller generates a stop condition after the contents of the I2CDAO register are

transmitted.

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10.6 Page-Write Operation

The page-write operation is initiated in the same way as byte write, with the exception that a stop condition

is not generated after the first EPROM [DATA] is transmitted. The following describes the sequence of writing

32 bytes in page mode.

Device Address + EPROM [High Byte]

2

•

The MCU clears bit 0 (SWR) in the I2CSTA register. This forces the I C controller to not generate a

stop condition after the contents of the I2CDAO register are transmitted.

•

The MCU writes the device address (bit 0 (R/W) = 0) to the I2CADR register (write operation).

The MCU writes the high byte of the EEPROM address into the I2CDAO register

Bit 3 (TXE) in the I2CSTA register is cleared (indicating busy).

The contents of the I2CADR register are transmitted to the device (preceded by start condition on

SDA).

•

The contents of the I2CDAO register are transmitted to the device (EEPROM address).

Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register

contents have been transmitted.

EPROM [Low Byte]

•

The MCU writes the low byte of the EEPROM address into the I2CDAO register.

Bit 3 (TXE) in the I2CSTA register is cleared (indicates busy).

The contents of the I2CDAO register are transmitted to the device (EEPROM address).

Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register

contents have been transmitted.

EPROM [DATA]—31 Bytes

•

The data to be written to the EEPROM are written by the MCU into the I2CDAO register.

Bit 3 (TXE) in the I2CSTA register is cleared (indicates busy).

The contents of the I2CDAO register are transmitted to the device (EEPROM data).

Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register

contents have been transmitted.

•

This operation repeats 31 times.

EPROM [DATA]—Last Byte

2

•

The MCU sets bit 0 (SWR) in the I2CSTA register. This forces the I C controller to generate a stop

condition after the contents of the I2CDAO register are transmitted.

•

The MCU writes the last date byte to be written to the EEPROM, into the I2CDAO register.

Bit 3 (TXE) in the I2CSTA register is cleared (indicates busy).

The contents of the I2CDAO register are transmitted to EEPROM (EEPROM data).

Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register

contents have been transmitted.

2

•

The I C controller generates a stop condition after the contents of the I2CDAO register are

transmitted.

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11 TUSB3410 Bootcode Flow

11.1 Introduction

TUSB3410 bootcode is a program embedded in the 10k-byte boot ROM within the TUSB3410. This program

2

is designed to load application firmware from either an external I C memory device or USB host bootloader

device driver. After the TUSB3410 finishes downloading, the bootcode releases its control to the application

firmware.

This section describes how the bootcode initializes the TUSB3410 device in detail. In addition, the default USB

2

descriptor, I C device header format, USB host driver firmware downloading format, and supported built-in

USB vendor specific requests are listed for reference. Users should carefully follow the appropriate format to

interface with the bootcode. Unsupported formats may cause unexpected results.

The bootcode source code is also provided for programming reference.

11.2 Bootcode Programming Flow

2

After power-on reset, the bootcode initializes the I C and USB registers along with internal variables. The

2

bootcode then checks to see if an I C device is present and contains a valid signature. If an I C device is

present and contains a valid signature, the bootcode continues searching for descriptor blocks and then

processes them if the checksum is correct. If application firmware was found, then the bootcode downloads

it and releases the control to the application firmware. Otherwise, the bootcode connects to the USB and waits

for host driver to download application firmware. Once firmware downloading is complete, the bootcode

releases the control to the firmware.

The following is the bootcode step-by-step operation.

•

Check if bootcode is in the application mode. This is the mode that is entered after application code is

downloaded via either an I C device or the USB. If the bootcode is in the application mode, then the

bootcode releases the control to the application firmware. Otherwise, the bootcode continues.

2

Initialize all the default settings.

−

Call CopyDefaultSettings() routine.

2

Set I C to 400-kHz speed.

Call UsbDataInitialization() routine.

Set bFUNADR = 0

Disconnect from USB (bUSBCTL = 0x00)

Bootcode handles USB reset

Copy predefined device, configuration, and string descriptors to RAM

Disable all endpoints and enable USB interrupts (SETUP, RSTR, SUSR, and RESR)

•

Search for product signature

Check if valid signature is in I C. If not, skip the I C process.

2

−

Read 2 bytes from address 0x0000 with type III and device address 0. Stop searching if valid signature

is found.

Read 2 bytes from address 0x0000 with type II and device address 4. Stop searching if valid signature

is found.

If a valid I2C signature is found, then load the customized device, configuration and string descriptors from

2

I C EEPROM.

2

−

Process each descriptor block from I C until end of header is found

If the descriptor block contains device, configuration, or string descriptors, then the bootcode

overwrites the default descriptors.

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If the descriptor block contains binary firmware, then the bootcode sets the header pointer to the

2

beginning of the binary firmware in the I C EEPROM.

If the descriptor block is end of header, then the bootcode stops searching.

•

Enable global and USB interrupts and set the connection bit to 1.

−

Enable global interrupts by setting bit 7 (EA) within the SIE register (see Section 9.1.1) to 1.

Enable all internal peripheral interrupts by setting the EX0 bit within the SIE register to 1.

Connect to the USB by setting bit 7 (CONT) within the USBCNTL register (see Section 5.4) to 1.

Wait for any interrupt events until Get DEVICE DESCIPTOR setup packet arrives.

−

Suspend interrupt

The idle bit in the MCU PCON register is set and suspend mode is entered. USB reset wakes up the

microcontroller.

−

Resume interrupt

Bootcode wakes up and waits for new USB requests.

Reset interrupt

Call UsbReset() routine.

Setup interrupt

Bootcode processes the request.

USB reboot request

Disconnect from the USB by clearing bit 7 (CONT) in the USBCTL register and restart at address

0x0000.

2

•

Download firmware from I C EEPROM

−

Disable global interrupts by clearing bit 7 (EA) within the SIE register

Load firmware to XDATA space if available.

Download firmware from the USB.

2

−

If no firmware is found in an I C EEPROM, the USB host downloads firmware via output endpoint 1.

In the first data packet to output endpoint 1, the USB host driver adds 3 bytes before the application

firmware in binary format. These three bytes are the LSB and MSB indicating the firmware size and

followed by the arithmetic checksum of the binary firmware.

•

Release control to the application firmware.

−

Update the USB configuration and interface number.

Release control to application firmware.

Application firmware

Either disconnect from the USB or continue responding to USB requests.

−

11.3 Default Bootcode Settings

The bootcode has its own predefined device, configuration, and string descriptors. These default descriptors

should be used in evaluation only. They must not be used in the end-user product.

11.3.1 Device Descriptor

The device descriptor provides the USB version that the device supports, device class, protocol, vendor and

product identifications, strings, and number of possible configurations. The operation system (Windows,

MAC, or Linux) reads this descriptor to decide which device driver should be used to communicate with this

device.

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The bootcode uses 0x0451 (Texas Instruments) as the vendor ID and 0x3410 (TUSB3410) as the product ID.

It also supports three different strings and one configuration. Table 11−1 lists the device descriptor.

Table 11−1. Device Descriptor

OFFSET

(decimal)

FIELD

SIZE

VALUE

DESCRIPTION

0

1

bLength

bDescriptorType

bcdUSB

1

2

1

2

1

0x12

Size of this descriptor in bytes

Device descriptor type

USB spec 1.1

1

2

0x0110

4

bDeviceClass

bDeviceSubClass

bDeviceProtocol

bMaxPacketSize0

idVendor

0xFF

Device class is vendor−specific

We have no subclasses.

We use no protocols.

5

0

6

0

7

8

Max. packet size for endpoint zero

8

0x0451

USB−assigned vendor ID = TI

10

12

14

15

16

17

idProduct

0x3410

TI part number = TUSB3410

bcdDevice

0x100

Device release number = 1.0

iManufacturer

iProducct

1

2

3

1

Index of string descriptor describing manufacturer

Index of string descriptor describing product

Index of string descriptor describing device’s serial number

Number of possible configurations:

iSerialNumber

bNumConfigurations

11.3.2 Configuration Descriptor

The configuration descriptor provides the number of interfaces supported by this configuration, power

configuration, and current consumption.

The bootcode declares only one interface running in bus-powered mode. It consumes up to 100 mA at boot

time. Table 11−2 lists the configuration descriptor.

Table 11−2. Configuration Descriptor

OFFSET

(decimal)

FIELD

SIZE

VALUE

DESCRIPTION

0

1

bLength

1

9

2

Size of this descriptor in bytes.

Configuration descriptor type

bDescriptor Type

Total length of data returned for this configuration. Includes the combined length

2

wTotalLength

2

25 = 9 + 9 + 7 of all descriptors (configuration, interface, endpoint, and class- or

vendor-specific) returned for this configuration.

4

5

6

bNumInterfaces

bConfigurationValue

iConfiguration

1

0

Number of interfaces supported by this configuration

Value to use as an argument to the SetConfiguration() request to select this

configuration.

Index of string descriptor describing this configuration.

Configuration characteristics

D7:

D6:

Reserved (set to one)

Self-powered

7

8

bmAttributes

bMaxPower

1

0x80

0x32

D5:

D4−0:

Remote wakeup is supported

Reserved (reset to zero)

This device consumes 100 mA.

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11.3.3 Interface Descriptor

The interface descriptor provides the number of endpoints supported by this interface as well as interface

class, subclass, and protocol.

The bootcode supports only one endpoint and use its own class. Table 11−3 lists the interface descriptor.

Table 11−3. Interface Descriptor

OFFSET

FIELD

SIZE

VALUE

DESCRIPTION

(decimal)

0

1

2

bLength

1

9

4

0

Size of this descriptor in bytes

Interface descriptor type

bDescriptorType

bInterfaceNumber

Number of interface. Zero-based value identifying the index in the array of concurrent

interfaces supported by this configuration.

3

4

bAlternateSetting

bNumEndpoints

1

0

1

Value used to select alternate setting for the interface identified in the prior field

Number of endpoints used by this interface (excluding endpoint zero). If this value is

zero, this interface only uses the default control pipe.

5

6

7

8

bInterfaceClass

bInterfaceSubClass

bInterfaceProtocol

iInterface

1

0xFF

The interface class is vendor specific.

0

Index of string descriptor describing this interface

11.3.4 Endpoint Descriptor

The endpoint descriptor provides the type and size of communication pipe supported by this endpoint.

The bootcode supports only one output endpoint with the size of 64 bytes in addition to control endpoint 0

(required by all USB devices). Table 11−4 lists the endpoint descriptor.

Table 11−4. Output Endpoint1 Descriptor

OFFSET

FIELD

SIZE

VALUE

DESCRIPTION

(decimal)

0

1

2

bLength

1

7

5

Size of this descriptor in bytes

Endpoint descriptor type

bDescriptorType

bEndpointAddress

0x01

Bit 3…0: The endpoint number

Bit 7:

Direction

0 = OUT endpoint

1 = IN endpoint

3

bmAttributes

1

2

Bit 1…0: Transfer type

10 = Bulk

11 = Interrupt

4

6

wMaxPacketSize

bInterval

2

1

64

0

Maximum packet size this endpoint is capable of sending or receiving when this

configuration is selected.

Interval for polling endpoint for data transfers. Expressed in milliseconds.

11.3.5 String Descriptor

The string descriptor contains data in the unicode format. It is used to show the manufacturers name, product

model, and serial number in human readable format.

The bootcode supports three strings. The first string is the manufacturers name. The second string is the

product name. The third string is the serial number. Table 11−5 lists the string descriptor.

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Table 11−5. String Descriptor

OFFSET

FIELD

SIZE

VALUE

DESCRIPTION

(decimal)

0

bLength

bDescriptorType

wLANGID[0]

bLength

1

2

1

2

1

2

4

Size of string 0 descriptor in bytes

String descriptor type

English

1

0x03

2

0x0409

4

36 (decimal) Size of string 1 descriptor in bytes

5

bDescriptorType

bString

0x03

String descriptor type

Unicode, T is the first byte

Texas Instruments

6

‘T’,0x00

‘e’,0x00

‘x’,0x00

‘a’,0x00

‘s’,0x00

‘ ’,0x00

‘I’,0x00

‘n’,0x00

‘s’,0x00

‘t’,0x00

‘r’,0x00

‘u’,0x00

‘m’,0x00

‘e’,0x00

‘n’,0x00

‘t’,0x00

‘s’,0x00

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

41

42

44

46

48

50

52

54

56

58

60

62

64

66

bLength

bDescriptorType

bString

42 (decimal) Size of string 2 descriptor in bytes

0x03

STRING descriptor type

UNICODE, T is first byte

TUSB3410 boot device

‘T’,0x00

‘U’,0x00

‘S’,0x00

‘B’,0x00

‘3’,0x00

‘4’,0x00

‘1’,0x00

‘0’,0x00

‘ ‘,0x00

‘B‘,0x00

‘o’,0x00

‘t’,0x00

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Table 11−5. String Descriptor (Continued)

OFFSET

68

FIELD

SIZE

2

VALUE

‘ ’,0x00

‘D’,0x00

‘e‘,0x00

‘v’,0x00

‘I,0x00

DESCRIPTION

70

2

72

2

74

2

76

2

78

2

‘c’,0x00

‘e’,0x00

80

2

82

bLength

bDescriptorType

bString

1

34 (decimal) Size of string 3 descriptor in bytes

84

1

0x03

STRING descriptor type

86

2

r0,0x00

r1,0x00

r2,0x00

r3,0x00

r4,0x00

r5,0x00

r6,0x00

r7,0x00

r8,0x00

r9,0x00

rA,0x00

rB,0x00

rC,0x00

rD,0x00

rE,0x00

rF,0x00

UNICODE

88

2

R0 to rF are BCD of SERNUM0 to

SERNUM7 registers. 16 digit hex

16 digit hex numbers are created from

SERNUM0 to SERNUM7 registers

90

2

92

2

94

2

96

2

98

2

100

102

104

106

108

110

112

114

116

2

11.4 External I²C Device Header Format

A valid header should contain a product signature and one or more descriptor blocks. The descriptor block

contains the descriptor prefix and content. In the descriptor prefix, the data type, size, and checksum are

specified to describe the content. The descriptor content contains the necessary information for the bootcode

to process.

The header processing routine always counts from the first descriptor block until the desired block number

is reached. The header reads in the descriptor prefix with a size of 4 bytes. This prefix contains the type of

block, size, and checksum. For example, if the bootcode would like to find the position of the third descriptor

block, then it reads in the first descriptor prefix, calculates the position on the second descriptor prefix based

on the size specified in the prefix. bootcode, then repeats the same calculation to find out the position of the

third descriptor block.

11.4.1 Product Signature

2

The product signature must be stored at the first 2 bytes within the I C storage device. These 2 bytes must

match the product number. The order of these 2 bytes must be the LSB first followed by the MSB. For example,

the TUSB3410 is 0x3410. Therefore, the first byte must be 0x10 and the second byte must be 0x34.

2

The TUSB3410 bootcode searches the first 2 bytes of the I C device. If the first 2 bytes are not 0x10 and 0x34,

then the bootcode skips the header processing.

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11.4.2 Descriptor Block

Each descriptor block contains a prefix and content. The size of the prefix is always 4 bytes. It contains the

data type, size, and checksum for data integrity. The descriptor content contains the corresponding

information specified in the prefix. It could be as small as 1 byte or as large as 65535 bytes. The next descriptor

immediately follows the previous descriptor. If there are no more descriptors, then an extra byte with a value

of zero should be added to indicate the end of header.

11.4.2.1 Descriptor Prefix

The first byte of the descriptor prefix is the data type. This tells the bootcode how to process the data in the

descriptor content. The second and third bytes are the size of descriptor content. The second byte is the low

byte of the size and the third byte is the high byte. The last byte is the 8-bit arithmetic checksum of descriptor

content.

11.4.2.2 Descriptor Content

Information stored in the descriptor content can be the USB information, firmware, or other type of data. The

size of the content should be from 1 byte to 65535 bytes.

11.5 Checksum in Descriptor Block

Each descriptor prefix contains one checksum of the descriptor content. If the checksum is wrong, the

bootcode simply ignores the descriptor block.

11.6 Header Examples

The header can be specified in different ways. The following descriptors show examples of the header format

and the supported descriptor block.

11.6.1 TUSB3410 Bootcode Supported Descriptor Block

The TUSB3410 bootcode supports the following descriptor blocks.

•

USB Device Descriptor

USB Configuration Descriptor

USB String Descriptor

1

Binary Firmware

2

Autoexec Binary Firmware

11.6.2 USB Descriptor Header

Table 11−6 contains the USB device, configuration, and string descriptors for the bootcode. The last byte is

zero to indicate the end of header.

1

Binary firmware is loaded when the bootcode receives the first get device descriptor request from host. Downloading the firmware should

either continue that request in the data stage or disconnect from the USB and then reconnect to the USB as a new device.

2

The bootcode loads this autoexec binary firmware before it connects to the USB. The firmware should connect to the USB once it is

loaded.

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Table 11−6. USB Descriptors Header

OFFSET

TYPE

SIZE

VALUE

DESCRIPTION

0

Signature0

0x10

FUNCTION_PID_L

1

2

1

2

1

2

1

Signature1

Data Type

0x34

0x03

FUNCTION_PID_H

2

USB device descriptor

3

Data Size (low byte)

Data Size (high byte)

Check Sum

0x12

The device descriptor is 18 (decimal) bytes.

4

0x00

5

0xCC

0x12

Checksum of data below

6

bLength

Size of device descriptor in bytes

Device descriptor type

7

bDescriptorType

bcdUSB

0x01

8

0x0110

0xFF

0x00

USB spec 1.1

10

11

12

13

14

16

18

20

21

22

23

24

25

26

27

28

29

30

bDeviceClass

bDeviceSubClass

bDeviceProtocol

bMaxPacketSize0

idVendor

Device class is vendor-specific

We have no subclasses.

0x00

We use no protocols

0x08

Maximum packet size for endpoint zero

USB−assigned vendor ID = TI

TI part number = TUSB3410

Device release number = 1.0

Index of string descriptor describing manufacturer

Index of string descriptor describing product

Index of string descriptor describing device’s serial number

Number of possible configurations:

USB configuration descriptor

25 bytes

0x0451

0x3410

0x0100

0x01

idProduct

bcdDevice

iManufacturer

iProducct

0x02

iSerialNumber

bNumConfigurations

Data Type

0x03

0x01

0x04

Data Size (low byte)

Data Size (high byte)

Check Sum

0x19

0x00

0xC6

0x09

Checksum of data below

bLength

Size of this descriptor in bytes

CONFIGURATION descriptor type

bDescriptorType

wTotalLength

0x02

25(0x19) = Total length of data returned for this configuration. Includes the combined length of

9 + 9 + 7

all descriptors (configuration, interface, endpoint, and class- or vendor-specific)

returned for this configuration.

32

33

bNumInterfaces

1

0x01

Number of interfaces supported by this configuration

bConfigurationValue

Value to use as an argument to the SetConfiguration() request to select this

configuration

34

35

iConfiguration

bmAttributes

1

0x00

0xE0

Index of string descriptor describing this configuration.

Configuration characteristics

D7:

D6:

Reserved (set to one)

Self-powered

D5:

D4−0:

Remote wakeup is supported

Reserved (reset to zero)

36

37

38

39

bMaxPower

bLength

1

0x64

0x09

0x04

0x00

This device consumes 100 mA.

Size of this descriptor in bytes

INTERFACE descriptor type

bDescriptorType

bInterfaceNumber

Number of interface. Zero-based value identifying the index in the array of

concurrent interfaces supported by this configuration.

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Table 11−6. USB Descriptors Header (Continued)

OFFSET

40

TYPE

SIZE

VALUE

0x00

DESCRIPTION

bAlternateSetting

bNumEndpoints

1

Value used to select alternate setting for the interface identified in the prior field

41

0x01

Number of endpoints used by this interface (excluding endpoint zero). If this value

is zero, this interface only uses the default control pipe.

42

43

44

45

46

47

48

bInterfaceClass

bInterfaceSubClass

bInterfaceProtocol

iInterface

1

0xFF

0x00

0x07

0x05

0x01

The interface class is vendor specific.

Index of string descriptor describing this interface

Size of this descriptor in bytes

bLength

bDescriptorType

bEndpointAddress

ENDPOINT descriptor type

Bit 3…0: The endpoint number

Bit 7:

Direction

0 = OUT endpoint

1 = IN endpoint

49

50

bmAttributes

1

2

0x02

Bit 1…0: Transfer Type

10 = Bulk

11 = Interrupt

wMaxPacketSize

0x0040

Maximum packet size this endpoint is capable of sending or receiving when this

configuration is selected.

52

53

54

55

56

57

58

59

61

62

63

65

67

68

69

71

73

74

75

77

79

81

83

bInterval

Data Type

1

2

1

2

1

2

1

2

1

0x00

0x05

Interval for polling endpoint for data transfers. Expressed in milliseconds.

USB String descriptor

Data Size (low byte)

Data Size (high byte)

Check Sum

0x1A

26(0x1A) = 4 + 6 + 6 + 10

0x00

0x50

Checksum of data below

Size of string 0 descriptor in bytes

STRING descriptor type

English

bLength

0x04

bDescriptorType

wLANGID[0]

bLength

0x03

0x0409

0x06

Size of string 1 descriptor in bytes

STRING descriptor type

UNICODE, ‘T’ is the first byte.

TI = 0x54, 0x49

bDescriptorType

bString

0x03

‘T’,0x00

‘I’,0x00

0x06

bLength

bDescriptorType

bString

Size of string 2 descriptor in bytes

STRING descriptor type

UNICODE, ‘u’ is the first byte.

‘uC’ = 0x75, 0x43

0x03

‘u’,0x00

‘C’,0x00

0x0A

bLength

bDescriptorType

bString

Size of string 3 descriptor in bytes

STRING descriptor type

UNICODE, ‘T’ is the first byte.

‘3410’ = 0x33, 0x34, 0x31, 0x30

0x03

‘3’,0x00

‘4’,0x00

‘1’,0x00

‘0’,0x00

0x00

Data Type

End of header

11.6.3 Autoexec Binary Firmware

If the application requires firmware loaded prior to establishing a USB connection, then the following header

can be used. The bootcode loads the firmware and releases control to the firmware directly without connecting

to the USB. However, per the USB specification requirement, any USB device should connect to the bus and

respond to the host within the first 100 ms. Therefore, if downloading time is more than 100 ms, the USB and

header speed descriptor blocks should be added before the autoexec binary firmware. Table 11−7 shows an

example of autoexec binary firmware header.

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Table 11−7. Autoexec Binary Firmware

OFFSET

TYPE

SIZE

VALUE

DESCRIPTION

FUNCTION_PID_L

0x0000

Signature0

0x10

1

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x456d

Signature1

Data Type

1

0x34

0x07

0x67

0x45

0xNN

FUNCTION_PID_H

1

Autoexec binary firmware

0x4567 bytes of application code

Data Size (low byte)

Data Size (high byte)

Check Sum

1

0x4567

1

Checksum of the following firmware

Binary application code

End of header

Program

Data Type

0x00

11.7 USB Host Driver Downloading Header Format

If firmware downloading from the USB host driver is desired, then the USB host driver must follow the format

in Table 11−8. The Texas Instruments bootloader driver generates the proper format. Therefore, users only

need to provide the binary image of the application firmware for the Bootloader. If the checksum is wrong, then

the bootcode disconnects from the USB and waits before it reconnects to the USB.

Table 11−8. Host Driver Downloading Format

OFFSET

TYPE

SIZE

VALUE

DESCRIPTION

Application firmware size

0x0000 Firmware size (low byte)

0xXX

1

0x0001 Firmware size (low byte)

0x0002 Checksum

1

0xYY

0xZZ

Checksum of binary application code

Binary application code

0x0003 Program

0xYYXX

11.8 Built-In Vendor Specific USB Requests

The bootcode supports several vendor specific USB requests. These requests are primarily for internal testing

only. These functions should not be used in normal operation.

11.8.1 Reboot

The reboot command forces the bootcode to execute.

bmRequestType

USB_REQ_TYPE_DEVICE |

USB_REQ_TYPE_VENDOR |

USB_REQ_TYPE_OUT

01000000b

bRequest

wValue

wIndex

wLength

Data

BTC_REBOOT

None

0x85

0x0000

None

11.8.2 Force Execute Firmware

The force execute firmware command requests the bootcode to execute the downloaded firmware

unconditionally.

bmRequestType

USB_REQ_TYPE_DEVICE |

USB_REQ_TYPE_VENDOR |

USB_REQ_TYPE_OUT

01000000b

bRequest

wValue

wIndex

wLength

Data

BTC_FORCE_EXECUTE_FIRMWARE

0x8F

None

0x0000

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11.8.3 External Memory Read

The bootcode returns the content of the specified address.

bmRequestType

USB_REQ_TYPE_DEVICE |

USB_REQ_TYPE_VENDOR |

USB_REQ_TYPE_IN

11000000b

bRequest

wValue

wIndex

wLength

Data

BTC_EXETERNAL_MEMORY_READ

0x90

None

0x0000

Data address

0xNNNN (From 0x0000 to 0xFFFF)

1 byte

0x0001

0xNN

Byte in the specified address

11.8.4 External Memory Write

The external memory write command tells the bootcode to write data to the specified address.

bmRequestType

USB_REQ_TYPE_DEVICE |

USB_REQ_TYPE_VENDOR |

USB_REQ_TYPE_OUT

01000000b

bRequest

wValue

BTC_EXETERNAL_MEMORY_WRITE

0x91

HI: 0x00

LO: Data

0x00NN

wIndex

wLength

Data

Data address

None

0xNNNN (From 0x0000 to 0xFFFF)

0x0000

None

11.8.5 I²C Memory Read

2

The bootcode returns the content of the specified address in I C EEPROM.

2

In the wValue field, the I C device number is from 0x00 to 0x07 in the high byte. The memory type is from 0x01

to 0x03 for CAT I to CAT III devices. If bit 7 of bValueL is set, then the bus speed is 400 kHz. This request is

2

also used to set the device number and speed before the I C write request.

bmRequestType

USB_REQ_TYPE_DEVICE |

USB_REQ_TYPE_VENDOR |

USB_REQ_TYPE_IN

11000000b

bRequest

wValue

BTC_I2C_MEMORY_READ

0x92

2

HI:

I C device number

Memory type bit[1:0]

Speed bit[7]

0xXXYY

LO:

wIndex

wLength

Data

Data address

0xNNNN (From 0x0000 to 0xFFFF)

1 byte

0x0001

0xNN

Byte in the specified address

11.8.6 I²C Memory Write

2

The I C memory write command tells the bootcode to write data to the specified address.

bmRequestType

USB_REQ_TYPE_DEVICE |

USB_REQ_TYPE_VENDOR |

USB_REQ_TYPE_OUT

01000000b

bRequest

wValue

BTC_I2C_MEMORY_WRITE

0x93

HI: should be zero

LO: Data

0x00NN

wIndex

wLength

Data

Data address

None

0xNNNN (From 0x0000 to 0xFFFF)

0x0000

None

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11.8.7 Internal ROM Memory Read

The bootcode returns the byte of the specified address within the boot ROM. That is, the binary code of the

bootcode.

bmRequestType

USB_REQ_TYPE_DEVICE |

USB_REQ_TYPE_VENDOR |

USB_REQ_TYPE_OUT

01000000b

bRequest

wValue

wIndex

wLength

Data

BTC_INTERNAL_ROM_MEMORY_READ

0x94

None

0x0000

Data address

0xNNNN (From 0x0000 to 0xFFFF)

1 byte

0x0001

0xNN

Byte in the specified address

11.9 Bootcode Programming Consideration

11.9.1 USB Requests

For each USB request, the bootcode follows the steps below to ensure proper operation of the hardware.

1. Determine the direction of the request by checking the MSB of the bmRequestType field and set the DIR

bit within the USBCTL register accordingly.

2. Decode the command

3. If another setup is pending, then return. Otherwise, serve the request.

4. Check again, if another setup is pending then go to step 2.

5. Clear the interrupt source and then the VECINT register.

6. Exit the interrupt routine.

11.9.1.1

USB Request Transfers

The USB request consist of three types of transfers. They are control-read-with-data-stage, control-write-

without-data-stage, and control-write-with-data-stage transfer. In each transfer, arrows indicate interrupts

generated after receiving the setup packet, in or out token.

Figure 11−1 and Figure 11−2 show the USB data flow and how the hardware and firmware respond to the USB

requests. Table 11−9 and Table 11−10 lists the bootcode reposes to the standard USB requests.

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Setup Stage

Setup (0)

Data Stage

StatusStage

More

IN(1)

IN(0)

IN(0/1)

INT

OUT(1)

Packets

INT

1.Hardware generates interrupt

to MCU.

1.Hardware generates interrupt to

MCU.

1.Hardware does NOT generate

interrupt to MCU.

2.Hardware sets NAK on both

the IN and the OUT endpoints.

3.Set DIR bit in USBCTL to

indicate the data direction.

4.Decode the setup packet.

5.If another setup packet

arrives, abandon this one.

2.Copy data to IN buffer.

3.Clear the NAK bit.

4.If all data has been sent, stall input

endpoint.

6.Execute appropriate routine per

Table 11-9.

a) Clear NAK bit in OUT

endpoint.

b) Copy data to IN endpoint

buffer and set byte count.

Figure 11−1. Control Read Transfer

Table 11−9. Bootcode Response to Control Read Transfer

CONTROL READ

ACTION IN BOOTCODE

Return power and remote wakeup settings

Return 2 bytes of zeros

Return endpoint status

Return device descriptor

Return configuration descriptor

Return string descriptor

Stall

Get status of device

Get status of interface

Get status of endpoint

Get descriptor of device

Get descriptor of configuration

Get descriptor of string

Get descriptor of interface

Get descriptor of endpoint

Get configuration

Stall

Return bConfiguredNumber value

Return bInterfaceNumber value

Get interface

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Setup Stage

Setup (0)

Status Stage

IN(1)

INT

1.Hardware generates interrupt

to MCU.

1.Hardware does NOT generates

interrupt to MCU.

2.Hardware sets NAK on both the IN

and the OUT endpoints.

3.Set DIR bit in USBCTL to

indicate the data direction.

4.Decode the setup packet.

5.If another setup packet

arrives, abandon this one.

6.Execute appropriate routine per

Table 11−10.

Figure 11−2. Control Write Transfer Without Data Stage

Table 11−10. Bootcode Response to Control Write Without Data Stage

CONTROL WRITE WITHOUT DATA STAGE

Clear feature of device

Clear feature of interface

Clear feature of endpoint

Set feature of device

Set feature of interface

Set feature of endpoint

Set address

ACTION IN BOOTCODE

Stall

Clear endpoint stall

Stall

Stall endpoint

Set device address

Stall

Set descriptor

Set configuration

Set bConfiguredNumber

SetbInterfaceNumber

Stall

Set interface

Sync. frame

11.9.1.2

Interrupt Handling Routine

The higher-vector number has a higher priority than the lower-vector number. Table 11−11 lists all the

interrupts and source of interrupts.

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Table 11−11. Vector Interrupt Values and Sources

G[3:0]

(Hex)

I[2:0]

(Hex)

VECTOR

(Hex)

INTERRUPT SOURCE SHOULD BE

CLEARED

INTERRUPT SOURCE

0

1

0

1

00

12

No Interrupt

No Source

Output−endpoint−1

Output−endpoint−2

Output−endpoint−3

Reserved

VECINT register

1

2

14

1

3

16

1

4−7

1

18→1E

22

2

Input−endpoint−1

Input−endpoint−2

Input−endpoint−3

Reserved

VECINT register

2

24

2

3

26

2

4−7

0

28→2E

30

3

STPOW packet received

SETUP packet received

Reserved

USBSTA/ VECINT registers

3

1

32

3

2

34

3

36

Reserved

3

4

38

RESR interrupt

SUSR interrupt

RSTR interrupt

Wakeup interrupt

I2C TXE interrupt

Input−endpoint−0

Output−endpoint−0

Reserved

USBSTA/ VECINT registers

VECINT register

3

5

3A

3

6

3C

3

7

3E

4

0

40

4

1

42

VECINT register

4

2

44

VECINT register

4

3

46

VECINT register

4

4−7

0

48→4E

50

5

UART1 status interrupt

UART1 modern interrupt

Reserved

LSR/VECNT register

LSR/VECINT register

5

1

52

5

2−7

0

54→5E

60

6

UART1 RXF interrupt

UART1 TXE interrupt

Reserved

LSR/VECNT register

LSR/VECINT register

6

1

62

6

2−7

0−7

0

64→6E

70→7E

80

7

Reserved

8

DMA1 interrupt

Reserved

DMACSR/VECINT register

8

1

82

8

2

84

DMA3 interrupt

Reserved

8

3−7

0−7

86→7E

90→FE

9−15

Reserved

11.9.2 Hardware Reset Introduced by the Firmware

This feature can be used during a firmware upgrade. Once the upgrade is complete, the application firmware

disconnects from the USB for at least 200 ms to ensure the operating system has unloaded the device driver.

The firmware then enables the watchdog timer (enabled by default after power-on reset) and enters an

endless loop without resetting the watchdog timer. Once the watchdog timer times out, it resets the TUSB3410

similar to a power on reset. The bootcode takes control and executes the power-on boot sequence.

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11.10 File Listings

The TUSB3410 Bootcode Source Listing (SLLC139.zip) is available under the TUSB3410 product page on

the TI website. Look under the Related Software link. The files listed below are included in the zip file.

•

Types.h

USB.h

TUSB3410.h

Bootcode.h

Watchdog.h

Bootcode.c

Bootlsr.c

BootUSB.c

Header.h

Header.c

I2c.h

I2c.c

78

TUSB3410, TUSB3410I

SLLS519H—January 2010

Electrical Specifications

12 Electrical Specifications

12.1 Absolute Maximum Ratings^†

Supply voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V

CC

Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V

I

CC

Output voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V

O

CC

Input clamp current, I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

IK

Output clamp current, I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

OK

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

12.2 Commercial Operating Condition (3.3 V)

PARAMETER

MIN

TYP

MAX

UNIT

V

Supply voltage

Input voltage

3

3.3

3.6

CC

0

V

I

CC

TTL

2

V

High-level input voltage

Low-level input voltage

Operating temperature

V

IH

IL

CMOS

0.7 × V

CC

TTL

0

0.8

0.2 × V

70

V

CMOS

CC

Commercial range

Industrial range

0

°C

T

A

−40

85

12.3 Electrical Characteristics

T = 25°C, V = 3.3 V 5%, V = 0 V

A

CC

SS

PARAMETER

TEST CONDITIONS

MIN TYP

– 0.5

MAX

UNIT

TTL

V

CC

V

I

High-level output voltage

Low-level output voltage

Positive threshold voltage

Negative threshold voltage

I

_OH= −4 mA

V

OH

CMOS

TTL

– 0.5

CC

0.5

1.8

I

_OL= 4 mA

V

OL

CMOS

TTL

V = V

IT+

IT−

hys

I

IH

IL

CMOS

TTL

0.7 × V

CC

0.8

1.8

V = V

V

I

CMOS

TTL

0.2 × V

CC

0.3

0.7

Hysteresis (V_IT+−V

)

IT−

V = V

V

I

CMOS

TTL

0.17 × V

0.3 × V

CC

20

High-level input current

Low-level input current

V = V

μA

IH

I

CMOS

TTL

1

20

1

I

IL

V = V

I

CMOS

I

Output leakage current (Hi-Z)

Output low drive current

V = V or V

SS

20

μA

mA

μA

OZ

OL

OH

I

CC

0.1

Output high drive current

Supply current (operating)

Supply current (suspended)

Serial data at 921.6 k

15

I

CC

200

79

SLLS519H—January 2010

TUSB3410, TUSB3410I

Electrical Specifications

Electrical Characteristics (continued)

T = 25°C, V = 3.3 V 5%, V = 0 V

A

CC

SS

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

‡

Clock duty cycle

50%

‡

Jitter specification

Input capacitance

100

18

ppm

pF

C

I

Output capacitance

10

pF

O

‡

Applies to all clock outputs

80

TUSB3410, TUSB3410I

SLLS519H—January 2010

Application Notes

13 Application Notes

13.1 Crystal Selection

The TUSB3410 requires a 12-MHz clock source to work properly. This clock source can be a crystal placed across

the X1 and X2 terminals. A parallel resonant crystal is recommended. Most parallel resonant crystals are specified

at a frequency with a load capacitance of 18 pF. This load can be realized by placing 33-pF capacitors from each end

of the crystal to ground. Together with the input capacitance of the TUSB3410 and stray board capacitance, this

provides close to two 36-pF capacitors in series to emulate the 18-pF load requirement. Note, that when using a

crystal, it takes about 2 ms after power up for a stable clock to be produced.

When using a clock oscillator, the signal applied to the X1/CLKI terminal must not exceed 1.8 V. In this configuration,

the X2 terminal is unconnected.

TUSB3410

33 pF

X2

12 MHz

33 pF

X1/CLKI

Figure 13−1. Crystal Selection

13.2 External Circuit Required for Reliable Bus Powered Suspend Operation

TI has found a potential problem with the action of the SUSPEND output terminal immediately after power on. In some

cases the SUSPEND terminal can power up asserted high. When used in a bus powered application this can cause

a problem because the VREGEN input is usually connected to the SUSPEND output. This in turn causes the internal

1.8-V voltage regulator to shut down, which means an external crystal may not have time to begin oscillating, thus

the device will not initialize itself correctly.

TI has determined that using components R2 and D1 (rated to 25 mA) in the circuit shown below can be used as a

workaround. Note that R1 and C1 are required components for proper reset operation, unless the reset signal is

provided by another means.

Note that use of an external oscillator (1.8-V output) versus a crystal would avoid this situation. Self-powered

applications would probably not see this problem because the VREGEN input would likely be tied low, enabling the

internal 1.8-V regulator at all times.

3.3 V

TUSB3410

R1

15 kΩ

RESET

R2

32 kΩ

VREGEN

C1

1 μF

D1

SUSPEND

Figure 13−2. External Circuit

81

SLLS519H—January 2010

TUSB3410, TUSB3410I

Application Notes

13.3 Wakeup Timing (WAKEUP or RI/CP Transitions)

The TUSB3410 can be brought out of the suspended state, or woken up, by a command from the host. The TUSB3410

also supports remote wakeup and can be awakened by either of two input signals. A low pulse on the WAKEUP

terminal or a low-to-high transition on the RI/CP terminal wakes the device up. Note that for reliable operation, either

condition must persist for approximately 3 ms minimum. This allows time for the crystal to power up since in the

suspend mode the crystal interface is powered down. The state of the WAKEUP or RI/CP terminal is then sampled

by the clock to verify there was a valid wakeup event.

13.4 Reset Timing

There are three requirements for the reset signal timing. First, the minimum reset pulse duration is 100 μs. At power

up, this time is measured from the time the power ramps up to 90% of the nominal V until the reset signal exceeds

CC

1.2 V. The second requirement is that the clock must be valid during the last 60 μs of the reset window. The third

requirement is that, according to the USB specification, the device must be ready to respond to the host within 100 ms.

2

This means that within the 100-ms window, the device must come out of reset, load any pertinent data from the I C

EEPROM device, and transfer execution to the application firmware if any is present. Because the latter two events

can require significant time, the amount of which can change from system to system, TI recommends having the

device come out of reset within 30 ms, leaving 70 ms for the other events to complete. This means the reset signal

must rise to 1.8 V within 30 ms.

These requirements are depicted in Figure 13−3. Notice that when using a 12-MHz crystal, the clock signal may take

several milliseconds to ramp up and become valid after power up. Therefore, the reset window may need to be

elongated up to 10 ms or more to ensure that there is a 60-μs overlap with a valid clock.

3.3 V

V

CC

CLK

90%

RESET

1.8 V

1.2 V

0 V

t

>60 μs

100 μs < RESET TIME

RESET TIME < 30 ms

Figure 13−3. Reset Timing

82

TUSB3410, TUSB3410I

SLLS519H—January 2010

PACKAGE OPTION ADDENDUM

www.ti.com

12-Apr-2010

PACKAGING INFORMATION

Orderable Device

TUSB3410IRHB

TUSB3410IRHBG4

TUSB3410IRHBR

TUSB3410IRHBRG4

TUSB3410IRHBT

TUSB3410IVF

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

QFN

RHB

32

73 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

LQFP

QFN

LQFP

RHB

VF

73 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

TUSB3410IVFG4

TUSB3410RHB

VF

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

RHB

VF

73 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TUSB3410RHBG4

TUSB3410RHBR

TUSB3410RHBRG4

TUSB3410RHBT

TUSB3410VF

73 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

TUSB3410VFG4

VF

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

12-Apr-2010

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TUSB3410 :

Automotive: TUSB3410-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

13-Jan-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TUSB3410IRHBR

TUSB3410RHBR

QFN

RHB

32

3000

330.0

12.4

5.3

1.5

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

13-Jan-2010

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TUSB3410IRHBR

TUSB3410RHBR

QFN

RHB

32

3000

340.5

333.0

20.6

Pack Materials-Page 2

MECHANICAL DATA

MTQF002B – JANUARY 1995 – REVISED MAY 2000

VF (S-PQFP-G32)

PLASTIC QUAD FLATPACK

0,45

0,25

0,20

M

0,80

24

17

25

16

32

9

0,13 NOM

1

8

5,60 TYP

7,20

SQ

6,80

Gage Plane

9,20

8,80

SQ

0,25

0,05 MIN

0°–7°

1,45

1,35

0,75

0,45

Seating Plane

0,10

1,60 MAX

4040172/D 04/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

1

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型号：	TUSB3410_10
厂家：	TEXAS INSTRUMENTS
描述：	USB to Serial Port Controller USB转串口控制器控制器
文件：	总98页 (文件大小：1290K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TUSB3410_10 [TI]

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