TUSB4041IPAPR_技术文档

Support &

Community

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

TUSB4041I 四端口 USB 2.0 集线器

1 特性

•

兼容 Type C

无特殊驱动程序要求；可与任一支持 USB 堆叠的

操作系统无缝工作

1

•

四端口 USB 2.0 集线器

USB 2.0 集线器特性

•

64 引脚耐热增强型薄型四方扁平 (HTQFP) 封装

(PAP)

–

多事务转换器 (MTT) 集线器：四个事务转换器

每个事务转换器具有四个异步端点缓冲器

•

支持 USB 电池充电

2 应用

–

充电下行端口 (CDP) 模式（上行端口已连接）

专用充电端口 (DCP) 模式（上行端口未连接）

•

计算机系统

扩展坞

监视器

机顶盒

DCP 模式符合中国电信行业标准 YD/T 1591-

2009

–

支持 D+ 和 D– 分压器模式

•

支持每端口或成组电源开关以及过流告知输入

3 说明

可使用一次性可编程 (OTP) 只读存储器 (ROM)、

串行 EEPROM 或 I²C 和 SMBus 受控接口进行自

定义配置：

TUSB4041I 器件是一款四端口 USB 2.0 集线器。该器

件可在上行端口上提供 USB 高速或全速连接。该器件

还可在下行端口上提供 USB 高速、全速或者低速连

接。当上行端口连接至仅支持高速、全速和低速连接的

电气环境中时，下行端口上的高速、全速和低速 USB

连接被启用。当上行端口被连接到一个只支持全速或低

速连接的电气环境中时，下行端口上的 USB 高速连接

被禁用。

–

V_ID和 P_ID

可定制的端口

生产商和产品字串（OTP ROM 不支持）

序列号（OTP ROM 不支持）

可使用引脚选择或 EEPROM、I²C 或 SMBus 受控

•

接口选择应用特性

器件信息⁽¹⁾

•

提供 128 位通用唯一标识符 (UUID)

支持通过 USB 2.0 上行端口进行板载和系统内

OTP 与 EEPROM 编程

器件型号

TUSB4041I

封装

封装尺寸（标称值）

HTQFP (64)

10.00mm x 10.00mm

•

单时钟输入，24MHz 晶振或者振荡器

DM/DP 极性交换

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

Type A

Port

USB2

WebCAM

Personal

TUSB4041I

Computer

USB 1.1

Mouse

TI

USB 1.1

Keyboard

USB 2.0 Connection

USB 1.x Connection

USB 2.0 Hub

USB 2.0 Port

USB 2.0 Device

USB 1.1 Device

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLLSEK3

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

8.5 Register Maps......................................................... 16

Application and Implementation ........................ 29

9.1 Application Information............................................ 29

9.2 Typical Application .................................................. 29

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）.............................................................. 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 8

7.1 Absolute Maximum Ratings ...................................... 8

7.2 ESD Ratings ............................................................ 8

7.3 Recommended Operating Conditions....................... 9

7.4 Thermal Information.................................................. 9

7.5 3.3-V I/O Electrical Characteristics ........................... 9

7.6 Power-Up Timing Requirements............................. 10

7.7 Hub Input Supply Current ....................................... 10

Detailed Description ............................................ 11

8.1 Overview ................................................................. 11

8.2 Functional Block Diagram ....................................... 11

8.3 Feature Description................................................. 12

8.4 Device Functional Modes........................................ 15

9

10 Power Supply Recommendations ..................... 36

10.1 TUSB4041I Power Supply .................................... 36

10.2 Downstream Port Power ....................................... 36

10.3 Ground .................................................................. 36

11 Layout................................................................... 37

11.1 Layout Guidelines ................................................. 37

11.2 Layout Example .................................................... 38

12 器件和文档支持 ..................................................... 39

12.1 文档支持................................................................ 39

12.2 接收文档更新通知 ................................................. 39

12.3 社区资源................................................................ 39

12.4 商标....................................................................... 39

12.5 静电放电警告......................................................... 39

12.6 Glossary................................................................ 39

13 机械、封装和可订购信息....................................... 40

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision D (July 2017) to Revision E

Page

•

Changed smbusRst From: Bit 6 To: Bit 1, and cfgActive1 From: Bit 5 To: Bit 0 Table 25 ................................................. 28

Changes from Revision C (September 2016) to Revision D

Page

•

Deleted paragraph: "Each bit corresponds directly to a downstream port. For example: used0 corresponds to

downstream port 1, used1 corresponds to downstream port 2, and so on. All combinations are supported with the

exception of both ports 1 and 3 marked as disabled." from Table 12.................................................................................. 21

Changes from Revision B (December 2015) to Revision C

Page

•

Added SMBUS Programming current to Hub Input Supply Current .................................................................................... 10

Added NOTE to the SMBus Slave Operation section ......................................................................................................... 15

Added text "This device will always report the XORed PID LSB value of 0x42" to the Description of Table 7 .................. 18

Changes from Revision A (September 2015) to Revision B

Page

•

Changed the configuration of the PWRCTL_POL pin (R17) in the Clock, Reset, and Miscellaneous section.................... 34

Changes from Original (July 2015) to Revision A

Page

•

Changed pin number for USB_DP_DN1 and USB_DP_DN2 in the Pin Functions table ...................................................... 6

2

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

5 说明（续）

TUSB4041I 器件支持每端口或者成组电源开关和过流保护。该器件还支持电池充电应用。

单独控制端口电源型集线器会根据 USB 主机请求为每个下行端口开启或关闭电源。另外，当单独控制端口电源型

集线器感测到过流事件时，仅为受影响的下行端口关闭电源。

当任一端口需要电源时，成组集线器将开启所有下行端口的电源。只有当所有端口均处于可关闭电源的状态时，才

会关闭下行端口的电源。另外，当成组集线器感测到过流事件时，将关闭所有下行端口的电源。

TUSB4041I 器件下行端口可提供 USB 电池充电下行端口 (CDP) 握手支持，从而为电池充电应用提供支持。未连

接上行端口时，该器件还支持专用充电端口 (DCP) 模式。DCP 模式符合 USB 电池充电规范和中国电信行业标准

YD/T 1591-2009。此外，未连接上行端口时，自动模式能够为 BC 器件以及支持分压器模式充电解决方案的器件提

供透明支持。

TUSB4041I 器件能够为包括电池充电支持在内的部分功能提供引脚搭接配置，还能够通过 OTP ROM、I²C

EEPROM 或通过 I²C 和 SMBus 从设备接口为 P_ID、V_ID以及自定义端口和物理层配置提供定制支持。使用 I²C

EEPROM 或 I²C 和 SMBus 受控接口时，还可以提供定制字串支持。

该器件采用 64 引脚 PAP 封装，工业版的工作温度范围为 -40°C 到 85°C。

3

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

6 Pin Configuration and Functions

PAP Package

64-Pin HTQFP With PowerPAD™

Top View

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

USB_DP_DN3

USB_DM_DN3

RSVD

49

50

51

52

53

54

55

56

57

58

32

31

30

29

28

27

26

25

24

23

USB_R1

VDD33

XI

RSVD

XO

NC

V

DD

RSVD

USB_DP_DN4

USB_DM_DN4

RSVD

V

DD

RSVD

59

60

22

21

USB_DM_UP

USB_DP_UP

VDD33

V

DD

RSVD

61

62

20

19

V

DD

63

64

18

17

GRSTz

TEST

V

DD

PWRCTL4/BATEN4

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

NC = No internal connection

Pin Functions

I/O⁽¹⁾TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

CLOCK AND RESET SIGNALS

Global power reset. This reset brings all of the TUSB4041I device internal registers to

the default state. When the GRSTz pin is asserted, the device is completely

nonfunctional.

GRSTz

XI

18

30

I

PU

—

Crystal input. This pin is the crystal input for the internal oscillator. The input may

alternately be driven by the output of an external oscillator. When using a crystal, a 1-

MΩ feedback resistor is required between the XI and XO pins.

(1) I = Input, O = Output, I/O = Input/output, PU = Internal pullup resistor, PD = Internal pulldown resistor, and PWR = Power signal

4

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

Pin Functions (continued)

NAME

I/O⁽¹⁾TYPE⁽¹⁾

DESCRIPTION

NO.

Crystal output. This pin is the crystal output for the internal oscillator. If the XI pin is

driven by an external oscillator, this pin may be left unconnected. When using a

crystal, a 1-MΩ feedback resistor is required between the XI and XO pins.

XO

29

O

—

USB UPSTREAM SIGNALS

USB_DM_UP

USB_DP_UP

22

I/O

I

—

USB high-speed differential transceiver (negative)

USB high-speed differential transceiver (positive)

21

Precision resistor reference. Connect a 9.53-kΩ ±1% resistor between the USB_R1

pin and ground.

USB_R1

32

I

—

USB upstream port power monitor. The VBUS detection requires a voltage divider.

The signal USB_VBUS must be connected to VBUS through a 90.9-kΩ ±1% resistor

and to ground through a 10-kΩ ±1% resistor from the signal to ground.

USB_VBUS

16

USB DOWNSTREAM SIGNALS

USB port 1 overcurrent detection. This pin is used to connect the overcurrent output

of the downstream port power switch for port 1.

0 = An overcurrent event occurred.

OVERCUR1z

14

15

12

11

4

I

PU

1 = An overcurrent event has not occurred.

This pin can be left unconnected if power management is not implemented. If power

management is enabled, the necessary external circuitry should be determined by the

power switch.

USB port 2 overcurrent detection. This pin is used to connect the overcurrent output

of the downstream port power switch for port 2.

0 = An overcurrent event occurred.

OVERCUR2z

I

PU

PD

1 = An overcurrent event has not occurred.

If power management is not implemented, leave this pin unconnected. If power

management is enabled, the necessary external circuitry should be determined by the

power switch.

USB port 3 overcurrent detection. This pin is used to connect the overcurrent output

of the downstream port power switch for port 3.

0 = An overcurrent event occurred.

OVERCUR3z

1 = An overcurrent event has not occurred.

This pin can be left unconnected if power management is not implemented. If power

management is enabled, the necessary external circuitry should be determined by the

power switch.

USB port 4 overcurrent detection. This pin is used to connect the overcurrent output

of the downstream port power switch for port 4.

0 = An overcurrent event occurred.

OVERCUR4z

I

1 = An overcurrent event has not occurred.

This pin can be left unconnected if power management is not implemented. If power

management is enabled, the necessary external circuitry should be determined by the

power switch.

USB port 1 power-on control for downstream power and battery charging enable. The

pin is used for control of the downstream power switch for port 1.

The value of the pin is sampled at the deassertion of reset to determine the value of

the battery charging support for port 1 as indicated in the Battery Charging Support

Register:

PWRCTL1/BATEN1

PWRCTL2/BATEN2

I/O

0 = Battery charging not supported

1 = Battery charging supported

USB port 2 power-on control for downstream power and battery charging enable. The

pin is used for control of the downstream power switch for port 2.

The value of the pin is sampled at the deassertion of reset to determine the value of

the battery charging support for Port 2 as indicated in the Battery Charging Support

Register:

3

0 = Battery charging not supported

1 = Battery charging supported

5

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

Pin Functions (continued)

I/O⁽¹⁾TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

USB port 3 power-on control for downstream power and battery charging enable. The

pin is used for control of the downstream power switch for port 3.

The value of the pin is sampled at the deassertion of reset to determine the value of

the battery charging support for Port 3 as indicated in the Battery Charging Support

Register:

PWRCTL3/BATEN3

1

I/O

PD

0 = Battery charging not supported

1 = Battery charging supported

USB port 4 power-on control for downstream power and battery charging enable. The

pin is used for control of the downstream power switch for port 4.

The value of the pin is sampled at the deassertion of reset to determine the value of

the battery charging support for Port 4 as indicated in the Battery Charging Support

Register:

PWRCTL4/BATEN4

64

0 = Battery charging not supported

1 = Battery charging supported

USB_DM_DN1

USB_DM_DN2

USB_DM_DN3

USB_DM_DN4

USB_DP_DN1

USB_DP_DN2

USB_DP_DN3

USB_DP_DN4

34

42

50

57

33

41

49

56

I/O

—

USB high-speed differential transceiver (negative)

USB high-speed differential transceiver (positive)

I²C AND SMBus SIGNALS

I²C clock/SMBus clock. The function of this pin depends on the setting of the

SMBUSz input.

When SMBUSz = 1, this pin functions as the serial clock interface for an I²C

EEPROM.

SCL/SMBCLK

6

I/O

PD

When SMBUSz = 0, this pin functions as the serial clock interface for an SMBus

host.

This pin can be left unconnected if external interface not implemented.

I²C data/SMBus data. The function of this pin depends on the setting of the SMBUSz

input.

When SMBUSz = 1, this pin functions as the serial data interface for an I²C

EEPROM.

SDA/SMBDAT

5

When SMBUSz = 0, this pin functions as the serial data interface for an SMBus

host.

This pin can be left unconnected if the external interface is not implemented.

I²C/SMBus mode select. The value of the pin is sampled at the deassertion of reset

set I²C or SMBus mode as follows:

1 = I²C mode selected

0 = SMBus mode selected

SMBUSz

7

I/O

PU

This pin can be left unconnected if the external interface is not implemented.

After reset, this signal is driven low by the TUSB4041I. Because of this behavior, TI

recommends not to tie directly to supply, but instead pull up or pull down using

external resistor.

6

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

Pin Functions (continued)

NAME

I/O⁽¹⁾TYPE⁽¹⁾

DESCRIPTION

NO.

TEST AND MISCELLANEOUS SIGNALS

Automatic charge mode enable/HS suspend status

The value of the pin is sampled at the deassertion of reset to determine if automatic

mode is enabled as follows:

0 = Automatic mode is enabled on ports that are enabled for battery charging when

the hub is unconnected. Note that CDP is not supported on port 1 when operating

in automatic mode.

AUTOENz/

HS_SUSPEND

13

I/O

PU

1 = Automatic mode is disabled.

This value is also used to set the autoEnz bit in the Battery Charging Support

Register.

After reset, this signal indicates the high-speed USB Suspend status of the upstream

port if enabled through the Additional Feature Configuration Register. When enabled,

a value of 1 indicates the connection is suspended.

Full power management enable/SMBus address bit 1

The value of the pin is sampled at the deassertion of reset to set the power switch

control follows:

0 = Power switching and overcurrent inputs supported

1 = Power switching and overcurrent inputs not supported

Full power management is the ability to control power to the downstream ports of the

TUSB4041I device using PWRCTL[4:1]/BATEN[4:1].

FULLPWRMGMTz/

SMBA1

8

I/O

PD

When SMBus mode is enabled using SMBUSz, this pin sets the value of the SMBus

slave address bit 1.

This pin can be left unconnected if full power management and SMBus are not

implemented.

After reset, this signal is driven low by the TUSB4041I. Because of this behavior, TI

recommends not to tie directly to supply, but instead pull up or pull down using an

external resistor.

Note: Power switching must be supported for battery charging applications.

Ganged operation enable/SMBus address bit 2/HS connection status upstream port

The value of the pin is sampled at the deassertion of reset to set the power switch

and overcurrent detection mode as follows:

0 = Individual power control supported when power switching is enabled

1 = Power control gangs supported when power switching is enabled

GANGED/SMBA2/

HS_UP

When SMBus mode is enabled using SMBUSz, this pin sets the value of the SMBus

slave address bit 2.

10

I/O

PD

After reset, this signal indicates the high-speed USB connection status of the

upstream port if enabled through the Additional Feature Configuration Register. When

enabled, a value of 1 indicates the upstream port is connected to a high-speed USB

capable port.

Note: Individual power control must be enabled for battery charging applications.

Power control polarity.

The value of the pin is sampled at the deassertion of reset to set the polarity of

PWRCTL[4:1].

PWRCTL_POL

9

I/O

PU

0 = PWRCTL polarity is active low

1 = PWRCTL polarity is active high

23, 24,

26, 27,

35, 36,

38, 39,

43, 44,

46, 47,

51, 52,

54, 55,

58, 59,

61, 62

RSVD

Reserved. For internal use only and leave unconnected on the PCB.

7

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

Pin Functions (continued)

I/O⁽¹⁾TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

TEST

17

I

PD

This pin is reserved for factory test.

No connection, leave floating

POWER AND GROUND SIGNALS

28

NC

—

40

19

25

37

V_DD

45

53

60

63

2

—

PWR

1.1-V power rail

20

31

48

V_DD33

—

PWR

—

3.3-V power rail

Thermal Pad

Ground. The thermal pad must be connected to ground.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)⁽¹⁾

MIN

–0.3

–65

MAX

1.4

UNIT

V

V_DDsteady-state supply voltage

Supply voltage

V_DD33steady-state supply voltage

3.8

V

USB_VBUS pin

1.4

V

Voltage

XI pins

2.45

3.8

V

All other pins

V

Storage temperature, T_stg

150

°C

(1) Stresses beyond those listed as Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated as Recommended Operating Conditions

is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±4000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

0.99

3

NOM

1.1

MAX

1.26

3.6

UNIT

V

(1)

V_DD

1.1-V supply voltage

V_DD33

3.3-V supply voltage

3.3

V

V_{(USB_VBUS)}

Voltage at USB_VBUS pin

Operating free-air temperature

Operating junction temperature

0

1.155

85

V

T_A

T_J

–40

°C

105

(1) A 1.05-V, 1.1-V, or 1.2-V supply may be used as long as minimum and maximum supply conditions are met.

7.4 Thermal Information

TUSB4041I

PAP (HTQFP)

64 PINS

26.2

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

11.5

10.4

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

10.3

R_θJC(bot)

0.6

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 3.3-V I/O Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

High-level input voltage⁽¹⁾

OPERATION

V_DD33

TEST CONDITIONS

MIN

2

TYP

MAX UNIT

V_IH

V_IL

V_DD33

0.55

V

JTAG pins only

0

Low-level input voltage⁽¹⁾

V_DD33

V

Other pins

0

0.8

V_I

Input voltage

Output voltage⁽²⁾

0

V_DD33

V

V_O

t_t

0

V_DD33

Input transition time (t_rand t_f)

Input hysteresis⁽³⁾

0

25

ns

V

V_hys

V_OH

V_OL

I_OZ

0.13 x V_DD33

High-level output voltage

Low-level output voltage

High-impedance, output current⁽²⁾V_DD33

V_DD33

I_OH= –4 mA

I_OL= 4 mA

2.4

V

0.4

V

V_I= 0 to V_DD33

±20

µA

High-impedance, output current

I_OZ(P)with internal pullup or pulldown

resistor⁽⁴⁾

V_DD33

V_I= 0 to V_DD33

±250

±15

µA

I_I

Input current⁽⁵⁾

(1) Applies to external inputs and bidirectional buffers.

(2) Applies to external outputs and bidirectional buffers.

(3) Applies to GRSTz.

(4) Applies to pins with internal pull-ups and pull-downs.

(5) Applies to external input buffers.

9

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

7.6 Power-Up Timing Requirements

MIN

NOM

MAX UNIT

(2)

t_d1

VDD33 stable before VDD stable⁽¹⁾

See

ms

µs

t_d2

VDD and VDD33 stable before deassertion of GRSTz

Setup for MISC inputs⁽³⁾sampled at the deassertion of GRSTz

Hold for MISC inputs⁽³⁾sampled at the deassertion of GRSTz

VDD33 supply ramp requirements

3

0.1

0.2

t_{su_io}

t_{hd_io}

µs

t_{VDD33_RAMP}

t_{VDD_RAMP}

100

ms

VDD supply ramp requirements

(1) An active reset is required if the VDD33 supply is stable before the VDD11 supply. This active Reset shall meet the 3ms power-up delay

counting from both power supplies being stable to the de-assertion of GRSTz.

(2) The VDD33 and VDD have no power-on relationship unless GRSTz is only connected to a capacitor to GND. Then VDD must be stable

minimum of 10 μs before the VDD33.

(3) MISC pins sampled at de-assertion of GRSTz: FULLPWRMGMTz, GANGED, PWRCTL_POL, SMBUSz, BATEN[4:1], and AUTOENz.

t

d2

GRSTz

VDD33

t

d1

VDD

t

hd_io

su_io

MISC_IO

Figure 1. Power-Up Timing Requirements

7.7 Hub Input Supply Current

Typical values measured at T_A= 25°C

V_DD33

3.3 V

V_DD

PARAMETER

UNIT

1.1 V

LOW POWER MODES

Power on (after reset)

Upstream disconnect

Suspend

2.3

2.5

28

33

mA

ACTIVE MODES (US STATE AND DS STATE)

2.0 host / 1 HS device

45

76

79

63

86

mA

2.0 host / 4 HS devices

SMBUS Programming current

225

10

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

8 Detailed Description

8.1 Overview

The TUSB4041I device is a four-port USB 2.0 hub. The device provides USB high-speed and full-speed

connections on the upstream port and provides USB high-speed, full-speed, or low-speed connections on the

downstream ports. When the upstream port is connected to an electrical environment that only supports high-

speed connections. USB high-speed connectivity is enabled on the downstream ports. When the upstream port

is connected to an electrical environment that only supports full-speed and low-speed connections. USB high-

speed connectivity is disabled on the downstream ports.

8.2 Functional Block Diagram

VDD33

VDD

VSS

VBUS

Detect

Power

Distribution

USB 2.0 Hub

XI

Oscillator

XO

Clock

and

Reset

GRSTz

TEST

Distribution

GANGED/SMBA2/HS_UP

FULLPWRMGMTz/SMBA1

PWRCTL_POL

SMBUSz

AUTOENz/HS_SUSPEND

SCL/SMBCLK

OTP

ROM

Control

Registers

SDA/SMBDAT

OVERCUR1z

PWRCTL1/BATEN1

GPIO

I²C

SMBUS

OVERCUR2z

PWRCTL2/BATEN2

OVERCUR3z

PWRCTL3/BATEN3

OVERCUR4z

PWRCTL4/BATEN4

11

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

8.3 Feature Description

8.3.1 Battery Charging Features

The TUSB4041I device provides support for USB battery charging. Battery charging support may be enabled on

a per port basis through the REG_6h(batEn[3:0]).

Battery charging support includes both CDP and DCP modes. The DCP mode is compliant with the Chinese

Telecommunications Industry Standard YD/T 1591-2009.

In addition to standard DCP mode, the TUSB4041I device provides a mode (AUTOMODE), which automatically

provides support for DCP devices and devices that support custom charging indication. When in AUTOMODE,

the port automatically switches between a divider mode and the DCP mode depending on the portable device

connected. The divided mode places a fixed DC voltage on the ports DP and DM signals, which allows some

devices to identify the capabilities of the charger. The default divider mode indicates support for up to 10 W. The

divider mode can be configured to report

REG_Ah(HiCurAcpModeEn).

a

legacy current setting (up to

5

W) through

The battery charging mode for each port is dependent on the state of Reg_6h(batEn[n]), the status of the VBUS

input, and the state of REG_Ah(autoModeEnz) upstream port as identified in Table 1.

Table 1. TUSB4041I Battery Charging Modes

BC MODE PORT x

batEn[n]

VBUS

autoModeEnz

(x = n + 1)

Don’t Care

Automode⁽¹⁾⁽²⁾

DCP⁽³⁾⁽⁴⁾

0

Don’t care

0

1

<4 V

>4 V

1

Don’t care

CDP⁽³⁾

(1) Auto-mode automatically selects divider-mode or DCP mode.

(2) Divider mode can be configured for legacy current mode through register settings.

(3) Attached USB device is USB battery-charging specification revision 1.2 compliant

(4) Chinese Telecommunications Industry Standard YD/T 1591-2009

8.3.2 USB Power Management

The TUSB4041I device can be configured for power-switched applications using either per-port or ganged

power-enable controls and overcurrent status inputs.

Power switch support is enabled by REG_5h(fullPwrMgmtz), and the per-port or ganged mode is configured by

REG_5h(ganged).

The TUSB4041I device supports both active-high and active-low power-enable controls. The PWRCTL[4:1]

polarity is configured by REG_Ah(pwrctlPol).

12

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

8.3.3 One-Time Programmable Configuration

The TUSB4041I device allows device configuration through one-time programmable (OTP) non-volatile memory.

The programming of the OTP is supported using vendor-defined USB device requests. Contact TI for details

using the OTP features

Table 2 lists features that can be configured using the OTP.

Table 2. OTP Configurable Features

CONFIGURATION REGISTER

BIT FIELD

DESCRIPTION

OFFSET

REG_01h

REG_02h

REG_03h

REG_04h

[7:0]

Vendor ID LSB

Vendor ID MSB

Product ID LSB

Product ID MSB

Port-removable configuration for downstream ports 1. OTP configuration is

inverse of rmbl[3:0], that is 1 = not removable, 0 = removable.

REG_07h

[0]

[1]

[2]

[3]

Port-removable configuration for downstream ports 2. OTP configuration is

inverse of rmbl[3:0], that is 1 = not removable, 0 = removable.

Port-removable configuration for downstream ports 3. OTP configuration is

inverse of rmbl[3:0], that is 1 = not removable, 0 = removable.

Port-removable configuration for downstream ports 4. OTP configuration is

inverse of rmbl[3:0], that is 1 = not removable, 0 = removable.

REG_0Ah

REG_0Bh

REG_F0h

[3]

[4]

Enable device attach detection

High-current divider mode enable

[0]

USB 2.0 port polarity configuration for downstream ports 1

USB 2.0 port polarity configuration for downstream ports 2

USB 2.0 port polarity configuration for downstream ports 3

USB 2.0 port polarity configuration for downstream ports 4

USB power switch power-on delay

[1]

[2]

[3]

[3:1]

13

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

8.3.4 Clock Generation

The TUSB4041I device accepts a crystal input to drive an internal oscillator or an external clock source. If a clock

is provided to the XI pin instead of a crystal, the XO pin is left open. Otherwise, if a crystal is used, the

connection must follow these guidelines. Because the XI and XO pins are coupled to other leads and supplies on

the PCB, keep traces as short as possible and away from any switching leads. Minimize the capacitance

between the XI and XO pins by shielding C1 and C2 with the clean ground lines.

R1

10 Mꢀ

XI

XO

24 MHz

CL1

CL2

Figure 2. TUSB4041I Clock

8.3.5 Crystal Requirements

The crystal must be fundamental mode with load capacitance of 12 to 24 pF and frequency stability rating of

±100 PPM or better. To ensure proper startup oscillation condition, TI recommends a maximum crystal

equivalent series resistance (ESR) of 50 Ω. If a crystal source is used, use a parallel load capacitor. The exact

load capacitance value used depends on the crystal vendor. Refer to application note Selection and Specification

for Crystals for Texas Instruments USB 2.0 Devices (SLLA122) for details on how to determine the load

capacitance value.

8.3.6 Input Clock Requirements

When using an external clock source such as an oscillator, the reference clock should have a frequency stability

of ±100 PPM or better and have less than 50-ps absolute peak-to-peak jitter. Tie XI to the 1.8-V clock source,

and leave XO floating.

8.3.7 Power-Up and Reset

The TUSB4041I device does not have specific power-sequencing requirements with respect to the core power

(V_DD) or I/O and analog power (V_DD33). The core power (V_DD) or I/O power (V_DD33) can be powered up for an

indefinite period of time while the other is not powered up if all of the following constraints are met:

•

Observe all maximum ratings and recommended operating conditions.

Observe all warnings about exposure to maximum rated and recommended conditions, particularly junction

temperature. These apply to power transitions and normal operation.

•

Limit bus contention to 100 hours over the projected lifetime of the device while V_DD33is powered-up.

Do not exceed the ratings listed in the Absolute Maximum Ratings table for bus contention while V_DD33is

powered-down.

A supply bus is powered-up when the voltage is within the recommended operating range. A supply bus is

powered-down when it is below that range, and either stable or in transition.

The device requires a minimum reset duration of 3 ms. This reset duration is defined as the time when the power

supplies are in the recommended operating range to the deassertion of the GRSTz pin. Generate the reset pulse

using a programmable-delay supervisory device or using an RC circuit.

14

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

8.4 Device Functional Modes

8.4.1 External Configuration Interface

The TUSB4041I device supports a serial interface for configuration register access. The device can be

configured by an attached I²C EEPROM or accessed as a slave by an SMBus-capable host controller. The

external interface is enabled when both the SCL/SMBCLK and SDA/SMBDAT pins are pulled up to 3.3 V at the

deassertion of reset. The mode, I²C master or SMBus slave, is determined by the state of SMBUSz pin at reset.

8.4.2 I²C EEPROM Operation

The TUSB4041I device supports a single-master, standard mode (100 kb/s) connection to a dedicated I²C

EEPROM when the I²C interface mode is enabled. In I²C mode, the TUSB4041I device reads the contents of the

EEPROM at bus address 1010000b using 7-bit addressing starting at address 0.

If the value of the EEPROM contents at byte 00h equals 55h, the TUSB4041I device loads the configuration

registers according to the EEPROM map. If the first byte is not 55h, the TUSB4041I device exits the I²C mode

and continues execution with the default values in the configuration registers. The hub does not connect on the

upstream port until the configuration is completed. If the hub detected an unprogrammed EEPROM (value other

than 55h), the hub enters programming mode and a programming endpoint within the hub is enabled.

NOTE

The bytes located above offset Ah are optional. The requirement for data in those

addresses is dependent on the options configured in the Device Configuration Register

and Device Configuration Register 2.

For details on I²C operation, refer to the UM10204 I²C-bus Specification and User Manual.

8.4.3 SMBus Slave Operation

When the SMBus interface mode is enabled, the TUSB4041I device supports read block and write block

protocols as a slave-only SMBus device.

The TUSB4041I device slave address is 1000 1xyz, where:

•

x is the state of GANGED/SMBA2/HS_UP pin at reset

y is the state of FULLPWRMGMTz/SMBA1 pin at reset

z is the read-write (R/W) bit; 1 = read access, 0 = write access

If the TUSB4041I device is addressed by a host using an unsupported protocol, the device does not respond.

The TUSB4041I device waits indefinitely for configuration by the SMBus host and does not connect on the

upstream port until the SMBus host indicates configuration is complete by clearing the CFG_ACTIVE bit.

For details on SMBus requirements, refer to the System Management Bus (SMBus) Specification.

NOTE

During the SMBUS configuration the hub may draw an extra current, this extra current

consumption will end as soon as the CFG_ACTIVE bit is cleared. For more information

refer to Hub Input Supply Current section in this datasheet.

15

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

8.5 Register Maps

8.5.1 Configuration Registers

The internal configuration registers are accessed on byte boundaries. The configuration register values are

loaded with defaults, but can be overwritten when the TUSB4041I device is in I²C or SMBus mode.

Table 3. Memory Map

BYTE ADDRESS

00h

CONTENTS

ROM Signature Register

EEPROM CONFIGURABLE

No

01h

Vendor ID LSB

Yes

02h

Vendor ID MSB

Yes

03h

Product ID LSB

Yes

04h

Product ID MSB

Yes

05h

Device Configuration Register

Battery Charging Support Register

Device Removable Configuration Register

Port Used Configuration Register

Reserved

Yes

06h

Yes

07h

Yes

08h

Yes

09h

Yes, program to 00h

0Ah

Device Configuration Register 2

USB 2.0 Port Polarity Control Register

Reserved

Yes

0Bh

Yes

0Ch to 0Fh

10h to 1Fh

20h to 21h

22h

No

UUID Byte [15:0]

No

LangID Byte [1:0]

Yes, if customStrings is set

Serial Number String Length

Manufacturer String Length

Product String Length

Reserved

Yes, if customSerNum is set

23h

Yes, if customStrings is set

24h

Yes, if customStrings is set

25h to 2Fh

30h to 4Fh

50h to 8Fh

90h to CFh

D0 to DFh

F0h

No

Serial Number String Byte [31:0]

Manufacturer String Byte [63:0]

Product String Byte [63:0]

Reserved

Yes, if customSerNum is set

Yes, if customStrings is set

No

Yes

No

Additional Feature Configuration Register

Reserved

F1 to F7h

F8h

Device Status and Command Register

Reserved

No

F9 to FFh

No

16

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

8.5.2 ROM Signature Register

Offset = 0h

Figure 3. ROM Signature Register

7

6

5

4

3

2

1

0

romSignature

RW-0

Table 4. ROM Signature Register Field Descriptions

Bit

Field

Type

Reset Description

ROM signature register

The TUSB4041I device uses this register in I²C mode to validate whether the

attached EEPROM has been programmed. The first byte of the EEPROM is

compared to the mask 55h and if not a match, the TUSB4041I device aborts the

EEPROM load and executes with the register defaults.

7:0

romSignature

RW

0

8.5.3 Vendor ID LSB Register

Offset = 1h, reset = 51h

Figure 4. Vendor ID LSB Register

7

6

5

4

3

2

1

0

vendorIdLsb[7] vendorIdLsb[6] vendorIdLsb[5] vendorIdLsb[4]

vendorIdLsb[3:1]

R/RW-0

vendorIdLsb[0]

R/RW-1

R/RW-0

R/RW-1

R/RW-0

R/RW-1

Table 5. Vendor ID LSB Register Field Descriptions

Bit

7

Field

Type

R/RW

Reset

Description

vendorIdLsb[7]

vendorIdLsb[6]

vendorIdLsb[5]

vendorIdLsb[4]

vendorIdLsb[3:1]

vendorIdLsb[0]

0

1

0

1

0

1

Vendor ID LSB

6

Least significant byte of the unique vendor ID assigned by the USB-IF; the

default value of this register is 51h representing the LSB of the TI Vendor ID

0451h. The value may be overwritten to indicate a customer vendor ID.

5

4

This field is R/W unless the OTP ROM VID and OTP ROM PID values are non-

zero. If both values are non-zero, the value when reading this register will

reflect the OTP ROM value.

3:1

0

8.5.4 Vendor ID MSB Register

Offset = 2h, reset = 04h

Figure 5. Vendor ID MSB Register

7

6

5

4

3

2

1

0

vendorIdMsb[7:3]

R/RW-0

vendorIdMsb[2]

R/RW-1

vendorIdMsb[1:0]

R/RW-0

Table 6. Vendor ID MSB Register Field Descriptions

Bit

7:3

2

Field

Type

R/RW

Reset Description

vendorIdMsb[7:3]

vendorIdMsb[2]

0

Vendor ID MSB

1

Most significant byte of the unique vendor ID assigned by the USB-IF; the default

value of this register is 04h representing the MSB of the TI Vendor ID 0451h. The

value may be overwritten to indicate a customer vendor ID.

1:0

vendorIdMsb[1:0]

R/RW

0

This field is R/W unless the OTP ROM VID and OTP ROM PID values are non-zero.

If both values are non-zero, the value when reading this register shall reflect the

OTP ROM value.

17

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

8.5.5 Product ID LSB Register

Offset = 3h, reset = 40h

Figure 6. Product ID LSB Register

7

6

5

4

3

2

1

0

productIdLsb[7] productIdLsb[6]

productIdLsb[5:0]

R/RW-0

R/RW-1

Table 7. Product ID LSB Register Field Descriptions

Bit

7

Field

Type

R/RW

Reset

Description

productIdLsb[7]

productIdLsb[6]

0

1

Product ID LSB.

6

The default value of this register is 40h representing the LSB of the product

ID assigned by TI. The value reported in the USB 2.0 device descriptor is

the value of this register bit wise XORed with 00000010b. This device will

always report the XORed PID LSB value of 0x42. The value may be

overwritten to indicate a customer product ID.

5:0

productIdLsb[5:0]

R/RW

0

This field is R/W unless the OTP ROM VID and OTP ROM PID values are

non-zero. If both values are non-zero, the value when reading this register

will reflect the OTP ROM value.

8.5.6 Product ID MSB Register

Offset = 4h, reset = 81h

Figure 7. Product ID MSB Register

7

6

5

4

3

2

1

0

productIdMsb[7]

R/RW-1

productIdMsb[6:1]

R/RW-0

productIdMsb[0]

R/RW-1

Table 8. Product ID MSB Register Field Descriptions

Bit

7

Field

Type

R/RW

Reset Description

productIdMsb[7]

1

Product ID MSB

6:1

productIdMsb[6:1]

0

Most significant byte of the product ID assigned by TI; the default value of this

register is 81h representing the MSB of the product ID assigned by TI. The

value may be overwritten to indicate a customer product ID.

0

productIdMsb[0]

R/RW

1

This field is R/W unless the OTP ROM VID and OTP ROM PID values are

non-zero. If both values are non-zero, the value when reading this register will

reflect the OTP ROM value.

18

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

8.5.7 Device Configuration Register

Offset = 5h

Figure 8. Device Configuration Register

7

6

5

4

3

2

1

0

customStrings customSernum

RW-0 RW-0

RSVD

RW-0

RSVD

R-1

ganged

RW-X

fullPwrMgmtz

RW-X

RSVD

RW-0

RSVD

R-0

Table 9. Device Configuration Register Field Descriptions

Bit

Field

Type

Reset Description

Custom strings enable

This bit controls the ability to write to the Manufacturer String Length, Manufacturer

String, Product String Length, Product String, and Language ID registers

0 = The Manufacturer String Length, Manufacturer String, Product String

Length, Product String, and Language ID registers are read only.

7

customStrings

RW

0

1 = The Manufacturer String Length, Manufacturer String, Product String

Length, Product String, and Language ID registers may be loaded by

EEPROM or written by SMBus.

The default value of this bit is 0.

Custom serial number enable

This bit controls the ability to write to the serial number registers.

0 = The Serial Number String Length and Serial Number String registers are

read only.

6

customSernum

RW

0

1 = Serial Number String Length and Serial Number String registers may be

loaded by EEPROM or written by SMBus.

The default value of this bit is 0.

5

4

RSVD

RW

R

0

1

Reserved.

Reserved. This bit is reserved and returns 1 when read.

Ganged

This bit is loaded at the deassertion of reset with the value of the

GANGED/SMBA2/HS_UP pin.

0 = Each port is individually power switched and enabled by the

PWRCTL[4:1]/BATEN[4:1] pins.

3

ganged

RW

X

1 = The power switch control for all ports is ganged and enabled by the

PWRCTL[4:1]/BATEN1 pin.

When the TUSB4041I device is in I²C mode, the TUSB4041I device loads this bit

from the contents of the EEPROM.

When the TUSB4041I device is in SMBUS mode, the value may be overwritten by

an SMBus host.

Full power management

This bit is loaded at the deassertion of reset with the value of the

FULLPWRMGMTz/SMBA1 pin.

0 = Port power switching status reporting is enabled

1 = Port power switching status reporting is disabled

2

fullPwrMgmtz

RW

X

When the TUSB4041I device is in I²C mode, the TUSB4041I device loads this bit

from the contents of the EEPROM.

When the TUSB4041I device is in SMBUS mode, the value may be overwritten by

an SMBus host.

Reserved

1

0

RSVD

RW

R

0

This field is reserved and should not be altered from the default.

Reserved

This field is reserved and returns 0 when read.

19

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

8.5.8 Battery Charging Support Register

Offset = 6h

Figure 9. Battery Charging Support Register

7

6

5

4

3

2

1

0

RSVD

R-0

batEn[3:0]

RW-X

Table 10. Battery Charging Support Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

7:4

RSVD

R

0

Read only, returns 0 when read.

Battery Charger Support. The bits in this field indicate whether the downstream port

implements the charging port features.

0 = The port is not enabled for battery charging support features

1 = The port is enabled for battery charging support features

3:0

batEn[3:0]

RW

X

Each bit corresponds directly to a downstream port, that is batEn0 corresponds to

downstream port 1, and batEN1 corresponds to downstream port 2.

The default value for these bits are loaded at the deassertion of reset with the value

of PWRCTL/BATEN[3:0].

When in I²C/SMBus mode the bits in this field may be overwritten by EEPROM

contents or by an SMBus host.

8.5.9 Device Removable Configuration Register

Offset = 7h

Figure 10. Device Removable Configuration Register

7

6

5

4

3

2

1

0

customRmbl

RW-0

RSVD

R-0

rmbl[3:0]

RW-X

Table 11. Device Removable Configuration Register Field Descriptions

Bit

Field

Type

Reset

Description

Custom removable

This bit controls the ability to write to the port removable bits.

7

customRmbl

RSVD

RW

0

0 = rmbl[3:0] are read only, and the values are loaded from the OTP ROM.

1 = rmbl[3:0] are R/W and can be loaded by EEPROM or written by SMBus.

This bit may be written simultaneously with rmbl[3:0].

Reserved

6:4

3:0

R

0

Read only, returns 0 when read

Removable

The bits in this field indicate whether a device attached to downstream ports 4

through 1 are removable or permanently attached.

0 = The device attached to the port is not removable.

1 = The device attached to the port is removable.

rmbl[3:0]

RW

X

Each bit corresponds directly to a downstream port n + 1, For example: rmbl0

corresponds to downstream port 1, rmbl1 corresponds to downstream port 2, and

so on.

This field is read only unless the customRmbl bit is set to 1. Otherwise, the value of

this field reflects the inverted values of the OTP ROM non_rmb[3:0] field.

20

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

8.5.10 Port Used Configuration Register

Offset = 8h

Figure 11. Port Used Configuration Register

7

6

5

4

3

2

1

0

RSVD

R-0

used[3:0]

RW-1

Table 12. Port Used Configuration Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

Read only

7:4

RSVD

R

0

Used

The bits in this field indicate whether a port is enabled.

3:0

used[3:0]

RW

1

0 = The port is disabled.

1 = The port is enabled.

8.5.11 Device Configuration Register 2

Offset = Ah

Figure 12. Device Configuration Register 2

7

6

5

4

3

2

1

0

RSVD

customBCfeatu

res

pwrctlPol

HiCurAcpMode

En

cpdEN

RSVD

autoModeEnz

RSVD

R-0

RW-0

RW-X

R/RW-0

RW-0

RW-X

R-0

Table 13. Device Configuration Register 2 Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

7

RSVD

R

0

Read only, returns 0 when read.

Custom battery charging feature enable

This bit controls the ability to write to the battery charging feature configuration

controls.

0 = The HiCurAcpModeEn and cpdEN bits are read only and the values

are loaded from the OTP ROM.

6

customBCfeatures

RW

0

1 = The HiCurAcpModeEn and cpdEN, bits are R/W and can be loaded

by EEPROM or written by SMBus from this register.

This bit may be written simultaneously with HiCurAcpModeEn and cpdEN.

Power enable polarity

This bit is loaded at the deassertion of reset with the value of the

PWRCTL_POL pin.

0 = PWRCTL polarity is active low.

1 = PWRCTL polarity is active high.

5

pwrctlPol

RW

X

When the TUSB4041I device is in I²C mode, the TUSB4041I device loads this

bit from the contents of the EEPROM.

When the TUSB4041I device is in SMBUS mode, the value may be

overwritten by an SMBus host.

21

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

Table 13. Device Configuration Register 2 Field Descriptions (continued)

Bit

Field

Type

Reset

Description

High-current ACP mode enable

This bit enables the high-current tablet charging mode when the automatic

battery charging mode is enabled for downstream ports.

0 = High-current divider mode disabled. Legacy current divider mode

enabled.

4

HiCurAcpModeEn

R/RW

0

1 = High-current divider mode enabled

This bit is read only unless the customBCfeatures bit is set to 1. If

customBCfeatures is 0, the value of this bit reflects the value of the

OTP ROM HiCurAcpModeEn bit.

Enable device attach detection

This bit enables device attach detection (such as a cell-phone detect) when

auto mode is enabled.

0 = Device attach detect is disabled in auto mode.

1 = Device attach detect is enabled in auto mode.

3

2

1

cpdEN

RRW

RW

0

X

This bit is read only unless the customBCfeatures bit is set to 1. If

customBCfeatures is 0, the value of this bit reflects the value of the OTP ROM

cpdEN bit.

RSVD

Reserved

Automatic mode enable⁽¹⁾

This bit is loaded at the deassertion of reset with the value of the

AUTOENz/HS_SUSPEND pin.

The automatic mode only applies to downstream ports with battery charging

enabled when the upstream port is not connected. Under these conditions:

autoModeEnz

RW

0 = Automatic mode battery charging features are enabled.

1 = Automatic mode is disabled; only battery-charging DCP mode is

supported.

Reserved

0

RSVD

R

0

Read only, returns 0 when read.

(1) When the upstream port is connected, battery charging 1.2 CDP mode will be supported on all ports that are enabled for battery

charging support regardless of the value of this bit, with the exception of port 1. CDP on port 1 is not supported when automatic mode is

enabled.

22

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

8.5.12 USB 2.0 Port Polarity Control Register

Offset = Bh

Figure 13. USB 2.0 Port Polarity Control Register

7

6

5

4

3

2

1

0

customPolarity

RW-0

RSVD

R-0

p4_usb2pol

R/RW-0

p3_usb2pol

R/RW-0

p2_usb2pol

R/RW-0

p1_usb2pol

R/RW-0

p0_usb2pol

R/RW-0

Table 14. USB 2.0 Port Polarity Control Register Field Descriptions

Bit

Field

Type

Reset

Description

Custom USB 2.0 polarity

This bit controls the ability to write the p[4:0]_usb2pol bits.

0 = The p[4:0]_usb2pol bits are read only, and the values are loaded from the

OTP ROM.

7

customPolarity

RW

0

1 = The p[4:0]_usb2pol bits are R/W and can be loaded by EEPROM or written

by SMBus from this register.

This bit may be written simultaneously with the p[4:0]_usb2pol bits

Reserved

6:5

RSVD

R

0

Read only, returns 0 when read

Downstream port 4 DM/DP polarity

This bit controls the polarity of the port.

0 = USB 2.0 port polarity is as shown in the pinout.

4

p4_usb2pol

R/RW

1 = USB 2.0 port polarity is swapped from that shown in the pinout (that is, DM

becomes DP, and DP becomes DM).

This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0, the

value of this bit reflects the value of the OTP ROM p4_usb2pol bit.

Downstream port 3 DM/DP polarity

This bit controls the polarity of the port.

0 = USB 2.0 port polarity is as shown in the pinout.

3

2

1

p3_usb2pol

p2_usb2pol

p1_usb2pol

R/RW

RRW

0

1 = USB 2.0 port polarity is swapped from that shown in the pinout (that is, DM

becomes DP, and DP becomes DM).

This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0, the

value of this bit reflects the value of the OTP ROM p3_usb2pol bit.

Downstream port 2 DM/DP polarity

This bit controls the polarity of the port.

0 = USB 2.0 port polarity is as shown in the pinout.

1 = USB 2.0 port polarity is swapped from that shown in the pinout (that is, DM

becomes DP, and DP becomes DM).

This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0, the

value of this bit reflects the value of the OTP ROM p2_usb2pol bit.

Downstream port 1 DM/DP polarity

This bit controls the polarity of the port.

0 = USB 2.0 port polarity is as shown in the pinout.

1 = USB 2.0 port polarity is swapped from that shown in the pinout (that is, DM

becomes DP, and DP becomes DM).

This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0, the

value of this bit reflects the value of the OTP ROM p1_usb2pol bit.

23

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

Table 14. USB 2.0 Port Polarity Control Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

Upstream port DM/DP polarity

This bit controls the polarity of the port.

0 = USB 2.0 port polarity is as shown in the pinout.

0

p0_usb2pol

R/RW

0

1 = USB 2.0 port polarity is swapped from that shown in the pinout (that is, DM

becomes DP, and DP becomes DM).

This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0, the

value of this bit reflects the value of the OTP ROM p0_usb2pol bit.

8.5.13 UUID Byte N Register

Offset = 10h-1Fh

Figure 14. UUID Byte N Register

7

6

5

4

3

2

1

0

uuidByte[n]

R-X

Table 15. UUID Byte N Register Field Descriptions

Bit

Field

Type

Reset

Description

UUID byte N

The UUID returned in the Container ID descriptor. The value of this register is

provided by the device and meets the UUID requirements of the Internet

Engineering Task Force (IETF) RFC 4122 A UUID URN Namespace.

7:0

uuidByte[n]

R

X

8.5.14 Language ID LSB Register

Offset = 20h, reset = 09h

Figure 15. Language ID LSB Register

7

6

5

4

3

2

1

0

langIdLsb[7:4]

R/RW-0

langIdLsb[3]

R/RW-1

langIdLsb[2:1]

R/RW-0

langIdLsb[0]

R/RW-1

Table 16. Language ID LSB Register Field Descriptions

Bit

7:4

3

Field

Type

R/RW

Reset

Description

langIdLsb[7:4]

langIdLsb[3]

0

1

0

Language ID least significant byte

This register contains the value returned in the LSB of the LANGID code in string

index 0. The TUSB4041I device only supports one language ID. The default

value of this register is 09h representing the LSB of the LangID 0409h indicating

English United States.

2:1

langIdLsb[2:1]

0

langIdLsb[0]

R/RW

1

When the customStrings bit is set to 1, this field may be overwritten by the

contents of an attached EEPROM or by an SMBus host.

24

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

8.5.15 Language ID MSB Register

Offset = 21h, reset = 04h

Figure 16. Language ID MSB Register

7

6

5

4

3

2

1

0

langIdMsb[7:3]

R/RW-0

langIdMsb[2]

R/RW-1

langIdMsb[1:0]

R/RW-0

Table 17. Language ID MSB Register Field Descriptions

Bit

7:3

2

Field

Type

R/RW

Reset

Description

langIdMsb[7:3]

langIdMsb[2]

0

1

Language ID most significant byte

This register contains the value returned in the MSB of the LANGID code in

string index 0. The TUSB4041I device only supports one language ID. The

default value of this register is 04h representing the MSB of the LangID 0409h

indicating English United States.

1:0

langIdMsb[1:0]

R/RW

0

When the customStrings bit is set to 1, this field may be overwritten by the

contents of an attached EEPROM or by an SMBus host.

8.5.16 Serial Number String Length Register

Offset = 22h

Figure 17. Serial Number String Length Register

7

6

5

4

3

2

1

0

RSVD

R-0

serNumStringL

en[5]

serNumStringLen[4:3]

serNumStringLen[2:0]

R/RW-0

R/RW-1

R/RW-0

Table 18. Serial Number String Length Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

7:6

RSVD

R

0

Read only, returns 0 when read.

5

serNumStringLen[5]

serNumStringLen[4:3]

R/RW

0

1

Serial number string length

4:3

The string length in bytes for the serial number string. The default value is

18h indicating that a 24-byte serial number string is supported. The

maximum string length is 32 bytes.

When the customSernum bit is set to 1, this field may be overwritten by the

contents of an attached EEPROM or by an SMBus host.

2:0

serNumStringLen[2:0]

R/RW

0

When the field is non-zero, a serial number string of serNumbStringLen

bytes is returned at string index 1 from the data contained in the Serial

Number String registers.

25

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

8.5.17 Manufacturer String Length Register

Offset = 23h

Figure 18. Manufacturer String Length Register

7

6

5

4

3

2

1

0

RSVD

R-0

mfgStringLen

R/RW-0

Table 19. Manufacturer String Length Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

7

RSVD

R

0

Read only, returns 0 when read

Manufacturer string length

The string length in bytes for the manufacturer string. The default value is 0,

indicating that a manufacturer string is not provided. The maximum string length is 64

bytes.

6:0

mfgStringLen

R/RW

0

When the customStrings bit is set to 1, this field may be overwritten by the contents of

an attached EEPROM or by an SMBus host.

When the field is non-zero, a manufacturer string of mfgStringLen bytes is returned at

string index 3 from the data contained in the Manufacturer String registers.

8.5.18 Product String Length Register

Offset = 24h

Figure 19. Product String Length Register

7

6

5

4

3

2

1

0

RSVD

R-0

prodStringLen

R/RW-0

Table 20. Product String Length Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

7

RSVD

R

0

Read only, returns 0 when read.

Product string length

The string length in bytes for the product string. The default value is 0, indicating

that a product string is not provided. The maximum string length is 64 bytes.

6:0

prodStringLen

R/RW

0

When the customStrings bit is set to 1, this field may be overwritten by the contents

of an attached EEPROM or by an SMBus host.

When the field is non-zero, a product string of prodStringLen bytes is returned at

string index 3 from the data contained in the Product String registers.

26

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

8.5.19 Serial Number String Registers

Offset = 30h-4Fh

Figure 20. Serial Number String Registers

7

6

5

4

3

2

1

0

serialNumber[n]

R/RW-X

Table 21. Serial Number String Registers Field Descriptions

Bit

Field

Type

Reset Description

Serial Number byte N

The serial number returned in the Serial Number string descriptor at string index 1.

The default value of these registers is assigned by TI. When customSernum is 1,

these registers may be overwritten by EEPROM contents or by an SMBus host.

7:0

serialNumber[n]

R/RW

X

8.5.20 Manufacturer String Registers

Offset = 50h-8Fh

Figure 21. Manufacturer String Registers

7

6

5

4

3

2

1

0

mfgStringByte[n]

R/W-0

Table 22. Manufacturer String Registers Field Descriptions

Bit

Field

Type

Reset

Description

Manufacturer string byte N

These registers provide the string values returned for string index 3 when

mfgStringLen is greater than 0. The number of bytes returned in the string is

equal to mfgStringLen.

7:0

mfgStringByte[n]

R/W

0

The programmed data should be in UNICODE UTF-16LE encodings as defined

by the Unicode Standard, Worldwide Character Encoding, Version 5.0.

8.5.21 Product String Byte N Register

Offset = 90h-CFh

Figure 22. Product String Byte N Register

7

6

5

4

3

2

1

0

prodStringByte[n]

R/RW-0

Table 23. Product String Byte N Register Field Descriptions

Bit

Field

Type

Reset

Description

Product string byte N

These registers provide the string values returned for string index 2 when

prodStringLen is greater than 0. The number of bytes returned in the string is

equal to prodStringLen.

7:0

prodStringByte[n]

R/RW

0

The programmed data should be in UNICODE UTF-16LE encodings as defined by

the Unicode Standard, Worldwide Character Encoding, Version 5.0.

27

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

8.5.22 Additional Feature Configuration Register

Offset = F0h

Figure 23. Additional Feature Configuration Register

7

6

5

4

3

2

1

0

RSVD

R-0

stsOutputEn

R/RW-0

pwronTime

R/W-0

RSVD

R/W-0

Table 24. Additional Feature Configuration Register Field Descriptions

Bit

7:5

4

Field

Type

Reset

Description

Reserved

RSVD

R

0

Read only, returns 0 when read.

Reserved.

R/RW

Power-on delay time

When OTP ROM pwronTime field is all 0, this field sets the delay time from the

removal disable of PWRCTL to the enable of PWRCTL when transitioning battery

charging modes. For example, when disabling the power on a transition from a

custom charging mode to dedicated charging port mode. The nominal timing is

defined as follows:

3:1

0

pwronTime

RSVD

RW

0

TPWRON_EN = (pwronTime + 1) x 200 ms

This field may be overwritten by EEPROM contents or by an SMBus host.

Reserved

(1)

RW

0

8.5.23 Device Status and Command Register

Offset = F8h

Figure 24. Device Status and Command Register

7

6

5

4

3

2

1

0

RSVD

R-0

smbusRst

W1S-0

cfgActive

W1C-0

Table 25. Device Status and Command Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

7:2

RSVD

R

0

Read only, returns 0 when read

SMBus interface reset

This bit loads the registers back to their GRSTz values.

1

0

smbusRst

cfgActive

W1S

W1C

0

This bit is set by writing a 1 and is cleared by hardware on completion of the reset. A

write of 0 has no effect.

Configuration active

This bit indicates that configuration of the TUSB4041I device is currently active. The

bit is set by hardware when the device enters the I²C or SMBus mode. The

TUSB4041I device does not connect on the upstream port while this bit is 1.

When in the SMBus mode, this bit must be cleared by the SMBus host to exit the

configuration mode and allow the upstream port to connect.

The bit is cleared by a writing 1. A write of 0 has no effect.

28

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TUSB4041I device is a four-port USB 2.0 hub. The provides USB high-speed and full-speed connections on

the upstream port and provides USB high-speed, full-speed, or low-speed connections on the downstream port.

The TUSB4041I device can be used in any application that requires additional USB-compliant ports. For

example, a specific notebook may only have two downstream USB ports. By using the TUSB4041I device, the

notebook can increase the downstream port count to five.

9.2 Typical Application

A common application for the TUSB4041I device is as a self-powered standalone USB-hub product. The product

is powered by an external 5-V DC power adapter. In this application, using a USB cable, the upstream port of the

TUSB4041I device is plugged into a USB host controller. The downstream ports of the TUSB4041I device are

exposed to users for connecting USB hard drives, cameras, flash drives, and so forth.

USB

Type B

Connector

DC

Power

US Port

TUSB4041I

USB

Power Switch

DS Port 1

DS Port 2

DS Port 3

DS Port 4

USB Type A

Connector

USB Type A

Connector

USB Type A

Connector

USB Type A

Connector

Figure 25. Discrete USB Hub Product

29

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

Typical Application (continued)

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 26.

Table 26. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

V_DDsupply

1.1 V

VDD33 supply

3.3 V

Upstream port USB support (HS, FS)

HS, FS

Downstream port 1 USB support (HS, FS, LS)

Downstream port 2 USB support (HS, FS, LS)

Downstream port 3 USB support (HS, FS, LS)

Downstream port 4 USB support (HS, FS, LS)

Number of removable downstream ports

Number of non-removable downstream ports

Full power management of downstream ports

Individual control of downstream port power switch

Power switch enable polarity

HS, FS, LS

4

0

Yes (FULLPWRMGMTZ = 0)

Yes (GANGED = 0)

Active high (PWRCTL_POL = 1)

Battery charge support for downstream port 1

Battery charge support for downstream port 2

Battery charge support for downstream port 3

Battery charge support for downstream port 4

I²C EEPROM support

Yes

No

24-MHz clock source

Crystal

9.2.2 Detailed Design Procedure

9.2.2.1 Upstream Port Implementation

R1

90.9 KΩ

U1A

10

8

GANGED/SMBA2/HS_UP

0402

1%

R2

C1

10 µF

10 KΩ 1%

0402

1%

FULLPWRMGMTZ/SMBA1

16

Type B USB-Shield

USB_VBUS

R3

R4

+5V

6

1

2

3

4

VBUS

4.7 KΩ

DM

DP

USB_DM_UP

USB_DP_UP

22

USB_DM_UP

21

USB_DP_UP

GND

5

TUSB4041I_PAP

J1

C2

0.1 µF

C3

0.001 µF

R5

1 MΩ

Figure 26. Upstream Port Implementation

The upstream of the TUSB4041I device is connected to a USB2 Type B connector. This particular example has

GANGED pin and FULLPWRMGMTZ pin pulled low, which results in individual power support each downstream

port. The VBUS signal from the USB2 Type B connector is feed through a voltage divider. The purpose of the

voltage divider is to make sure the level meets USB_VBUS input requirements

30

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

9.2.2.2 Downstream Port 1 Implementation

BOARD_3P3V

FB1

R6

POPULATE

FOR BC SUPPORT

DN1_VBUS

VBUS_DS1

4.7K

DN1_VBUS

220 @ 100MHZ C4

0.1uF

J2

1

U1B

VBUS

34

USB_DM_DN1

USB_DP_DN1

2

USB_DM_DN1

USB_DP_DN1

DM

33

3

DP

4

GND

5

SHIELD1

4

PWRCTRL1_BATEN1

OVERCUR1Z

PWRCTL1/BATEN1

OVERCUR1Z

6

SHIELD2

14

USB2_TYPEA

R7

1M

C5

0.001uF

C6

0.1uF

TUSB4041I_PAP

Figure 27. Downstream Port 1 Implementation

The downstream port 1 of the TUSB4041I device is connected to a USB2 type A connector. With BATEN1 pin

pulled up, battery charge support is enabled for Port 1. If battery charge support is not needed, then uninstall the

pullup resistor on BATEN1.

9.2.2.3 Downstream Port 2 Implementation

BOARD_3P3V

FB2

DN2_VBUS

VBUS_DS2

R8

DN2_VBUS

POPULATE

FOR BC SUPPORT

4.7 KΩ

220 at 100 MHz

C7

0.1 µF

J3

1

2

3

4

5

6

U1C

VBUS

42

USB_DM_DN2

USB_DP_DN2

USB_DM_DN2

DM

41

USB_DP_DN2

DP

GND

SHIELD1

SHIELD2

3

PWRCTRL2_BATEN2

OVERCUR2Z

PWRCTL2/BATEN2

OVERCUR2Z

15

R9

C9

0.001 µF

USB2_TYPEA

C8

0.1 µF

1 MΩ

TUSB4041I_PAP

Figure 28. Downstream Port 2 Implementation

The downstream port 2 of the TUSB4041I device is connected to a USB2 type A connector. With BATEN2 pin

pulled up, battery charge support is enabled for port 2. If battery charge support is not needed, then uninstall the

pullup resistor on BATEN2.

31

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

9.2.2.4 Downstream Port 3 Implementation

BOARD_3P3V

FB3

VBUS_DS3

R10

DN3_VBUS

POPULATE

FOR BC SUPPORT

4.7 KΩ

220 at 100 MHz

C10

0.1 µF

J4

1

2

3

4

5

6

U1D

VBUS

50

USB_DM_DN3

USB_DP_DN3

USB_DM_DN3

DM

49

USB_DP_DN3

DP

GND

SHIELD1

SHIELD2

1

PWRCTRL3_BATEN3

OVERCUR3Z

PWRCTL3/BATEN3

OVERCUR3Z

12

R11

C11

0.001 µF

USB2_TYPEA

C12

0.1 µF

1 MΩ

TUSB4041I_PAP

Figure 29. Downstream Port 3 Implementation

The downstream port3 of the TUSB4041I device is connected to a USB2 type A connector. With BATEN3 pin

pulled up, battery charge support is enabled for port 3. If battery charge support is not needed, then uninstall the

pullup resistor on BATEN3.

9.2.2.5 Downstream Port 4 Implementation

BOARD_3P3V

FB4

VBUS_DS4

R12

DN4_VBUS

POPULATE

FOR BC SUPPORT

4.7 KΩ

220 at 100 MHZ

C13

0.1 µF

J5

1

2

3

4

5

6

U1E

VBUS

57

USB_DM_DN4

USB_DP_DN4

USB_DM_DN4

DM

56

USB_DP_DN4

DP

GND

SHIELD1

SHIELD2

64

PWRCTRL4_BATEN4

OVERCUR4Z

PWRCTL4/BATEN4

OVERCUR4Z

11

R13

C15

0.001 µF

USB2_TYPEA

C14

0.1 µF

1 MΩ

TUSB4041I_PAP

Figure 30. Downstream Port 4 Implementation

The downstream port 4 of the TUSB4041I device is connected to a USB2 Type A connector. With BATEN4 pin

pulled up, Battery Charge support is enabled for Port 4. If Battery Charge support is not needed, then uninstall

the pullup resistor on BATEN4.

32

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

9.2.2.6 VBUS Power Switch Implementation

BOARD_3P3V

BOARD_5V

R19

10K

0402

5%

R20

10K

0402

5%

C42

0.1uF

U2

2

9

DN1_VBUS

DN2_VBUS

ILIM1

DN1_VBUS

OVERCUR1Z

DN2_VBUS

OVERCUR2Z

IN

OUT1

3

4

5

10

8

FAULT1Z

OUT2

PWRCTRL1_BATEN1

PWRCTRL2_BATEN2

PWRCTRL1_BATEN1

PWRCTRL2_BATEN2

EN1

EN2

6

FAULT2Z

ILIM

1

11

GND

PAD

7

C43

C45

0.1uF

+

C44

150uF

0.1uF

+

C46

150uF

TPS2561

R21

25.5K

0402

5%

Limiting DS Port VBUS current to 2.2A per port.

BOARD_3P3V

BOARD_5V

R22

10K

0402

5%

R23

10K

0402

5%

C47

0.1uF

U3

2

9

DN3_VBUS

DN4_VBUS

ILIM2

DN3_VBUS

IN

OUT1

FAULT1Z

OUT2

3

4

5

10

8

OVERCUR3Z

DN4_VBUS

PWRCTRL3_BATEN3

PWRCTRL4_BATEN4

EN1

EN2

6

OVERCUR4Z

FAULT2Z

ILIM

1

11

GND

PAD

7

C48

0.1uF

C50

+

C49

150uF

0.1uF

+

C51

150uF

TPS2561

R24

25.5K

0402

5%

Limiting DS Port VBUS current to 2.2A per port.

Figure 31. VBUS Power Switch Implementation

This particular example uses TI's TPS2561 dual-channel precision adjustable current-limited power switch. For

details on this power switch or other power switches available from TI, refer to www.ti.com.

33

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

9.2.2.7 Clock, Reset, and Miscellaneous

The PWRCTL_POL is left unconnected which results in active-high power enable (PWRCTL1, PWRCTL2,

PWRCTL3, and PWRCTL4) for a USB VBUS power switch. The 1-µF capacitor on the GRSTN pin can only be

used if the VDD11 supply is stable before the VDD33 supply. Depending on the supply ramp of the two supplies,

the user may need to adjust the capacitor.

U1F

5

C29

SDA/SMBDAT

SCL/SMBDAT

SMBUSZ

18

GRSTZ

6

1 µF

7

30

13

9

XI

AUTOENZ/HS_SUSPEND

PWRCTL_POL

TEST

R14

1M

17

32

29

Y1

XO

USB_R1

R15

R16

4.7 KΩ

R18

9.53 KΩ

0402

1%

TUSB4041I_PAP

4.7 KΩ

24 MHz

C30

C31

18 pF

Figure 32. Clock, Reset, and Miscellaneous

9.2.2.8 TUSB4041I Power Implementation

BOARD_1P1V

VDD11

FB5

C16

C17

C18

C19

C20

C21

C22

C23

10 µF

220 at 100 MHz

0.1 µF

U1G

23

RSVD

24

RSVD

26

RSVD

27

RSVD

35

RSVD

36

RSVD

38

RSVD

39

RSVD

43

RSVD

44

RSVD

46

47

51

52

54

55

58

59

61

62

2

RSVD

VDD33

20

31

48

VDD33

BOARD_3P3V

FB6

C24

C25

C26

C27

C28

10 µF

220 at 100 MHz

0.1 µF

28

40

NC

TUSB4041I_PAP

Figure 33. TUSB4041I Power Implementation

34

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

9.2.3 Application Curves

Figure 34. High-Speed Upstream Port

Figure 35. High-Speed Downstream Port 1

Figure 36. High-Speed Downstream Port 2

Figure 37. High-Speed Downstream Port 3

Figure 38. High-Speed Downstream Port 4

35

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

10 Power Supply Recommendations

10.1 TUSB4041I Power Supply

The user should implement V_DDas a single power plane, as well as V_DD33

.

•

The V_DDpins of the TUSB4041I supply 1.1-V (nominal) power to the core of the TUSB4041I device. This

power rail can be isolated from all other power rails by a ferrite bead to reduce noise.

•

The DC resistance of the ferrite bead on the core power rail can affect the voltage provided to the device

because of the high current draw on the power rail. The user may need to adjust the output of the core

voltage regulator to account for this, or select a ferrite bead with low DC resistance (less than 0.05 Ω).

•

The V_DD33pins of the TUSB4041I device supply 3.3-V power rail to the I/O of the TUSB4041I device. This

power rail can be isolated from all other power rails by a ferrite bead to reduce noise.

All power rails require a 10-µF capacitor or 1-µF capacitors for stability and noise immunity. These bulk

capacitors can be placed anywhere on the power rail. Place the smaller decoupling capacitors as close to the

TUSB4041I power pins as possible with an optimal grouping of two capacitors of differing values per pin.

10.2 Downstream Port Power

•

A source capable of supplying 5 V and up to 500 mA per port must supply the downstream port power,

VBUS. The TUSB4041I signals can control the downstream port power switches. Leaving the downstream

port power as always enabled is also possible.

•

The VBUS of each downstream port requires a large-bulk low-ESR capacitor of 22 µF or larger to limit in-rush

current.

TI recommends the ferrite beads on the VBUS pins of the downstream USB port connections for both ESD

and EMI reasons. A 0.1-µF capacitor on the USB connector side of the ferrite provides a low-impedance path

to ground for fast rise time ESD current that might have coupled onto the VBUS trace from the cable.

10.3 Ground

TI recommends to use only one board ground plane in the design which provides the best image plane for signal

traces running above the plane. Connect the thermal pad of the TUSB4041I and any of the voltage regulators to

this plane with vias. An earth or chassis ground is implemented only near the USB port connectors on a different

plane for EMI and ESD purposes.

36

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

11 Layout

11.1 Layout Guidelines

Use the layout guidelines listed in this section for proper PCB layout design.

11.1.1 Placement

•

Place a 9.53-kΩ ±1% resistor connected to pin USB_R1 as close as possible to the TUSB4041I device.

Place a 0.1-µF capacitor as close as possible on each V_DDand VDD33 power pin.

The ESD and EMI protection devices (if used) should also be placed as close as possible to the USB

connector.

•

If a crystal is used, it must be placed as close as possible to the XI and XO pins of the TUSB4041I device.

Place voltage regulators as far away as possible from the TUSB4041I device, the crystal, and the differential

pairs.

•

In general, the user should place the large bulk capacitors associated with each power rail as close as

possible to the voltage regulators.

11.1.2 Package Specific

•

The TUSB4041I device package has a 0.5-mm pin pitch.

The TUSB4041I device package has a 4.64-mm × 4.64-mm thermal pad. This thermal pad must be

connected to ground through a system of vias.

•

Solder mask all vias under device, except for those connected to the thermal pad, to avoid any potential

issues with thermal pad layouts.

11.1.3 Differential Pairs

This section describes the layout recommendations for all the TUSB4041I device differential pairs: USB_DP_XX,

USB_DM_XX.

•

The differential pairs must be designed with a differential impedance of 90 Ω ± 10%.

To minimize crosstalk, TI recommends to keep high-speed signals away from each other. Each pair should

be separated by at least 5 times the signal trace width. Separating with ground as depicted in the layout

example also helps minimize crosstalk.

•

Route all differential pairs on the same layer adjacent to a solid ground plane.

Do not route differential pairs over any plane split.

Adding test points causes impedance discontinuity and therefore negatively impacts signal performance. If

test points are used, place them in series and symmetrically. Do not place them in a manner that causes stub

on the differential pair.

•

Avoid 90° turns in trace. Keep the use of bends in differential traces to a minimum. When bends are used, the

number of left and right bends should be as equal as possible and the angle of the bend should be ≥135°.

This guideline minimizes any length mismatch caused by the bends and therefore minimize the impact bends

have on EMI.

Minimize the trace lengths of the differential pair traces. Eight inches is the maximum recommended trace

length for USB 2.0 differential pair signals. Longer trace lengths require very careful routing to assure proper

signal integrity.

•

Match the etch lengths of the differential pair traces (that is DP and DM). The USB 2.0 differential pairs

should not exceed 50 mils relative trace length difference.

Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure

that the same via type and placement are used for both signals in a pair. Place any vias used as close as

possible to the TUSB4041I device.

•

To ease routing of the USB 2.0 DP and DM pair, the polarity of these pins can be swapped. If this is done,

set the appropriate Px_usb2pol register, where x = 0, 1, 2, 3, or 4.

Do not place power fuses across the differential pair traces.

37

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

11.2 Layout Example

TI USB2 HUB

USB2 DP/DM

USB2 TYPE B

Connector

Figure 39. Example Routing of Upstream Port

USB2 DP/DM

TI USB2 HUB

USB2 TYPE A

Connector

Figure 40. Example Routing of Downstream Port

38

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档

请参阅如下相关文档：

•

《德州仪器 (TI) USB 2.0 器件晶振的选择和规范》，SLLA122

《TPS2561 双通道精密可调节限流电源开关》，SLVS930

《TUSB4041PAP 评估模块》，SLLU227

12.2 接收文档更新通知

要接收文档更新通知，请转至 ti.com 上您的器件的产品文件夹。请在右上角单击通知我按钮进行注册，即可收到

产品信息更改每周摘要（如有）。有关更改的详细信息，请查看任意已修订文档的修订历史记录。

12.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.4 商标

PowerPAD, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

39

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知

和修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。

40

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

PACKAGE OUTLINE

PAP0064M

PowerPAD ^TM- 1.2 mm max height

SCALE 1.500

PPLLAASSTTICICQQUUAADDFFLLAATTPPAACCKK

10.2

9.8

PIN 1 ID

B

64

49

A

48

1

12.2

TYP

11.8

10.2

9.8

16

33

17

32

0.27

0.17

64X

60X 0.5

4X 7.5

0.08

C A

B

SEE DETAIL A

1.2 MAX

C

SEATING PLANE

0.08

0.09-0.20

TYP

0

MIN

(0.15) TYP

NOTE 4

0.25

GAGE PLANE

(1)

4.44

3.64

0.15

0.05

0 -7

0.75

0.45

D

E

T

A

I

L

C

A

DETAIL A

TYPICAL

EXPOSED

THERMAL PAD

(0.15) TYP

NOTE 4

4221602/A 07/2014

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Reference JEDEC registration MS-026, variation ACD.

4. Strap features may not be present,

www.ti.com

41

TUSB4041I

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

EXAMPLE BOARD LAYOUT

PAP0064M

PowerPAD ^TM- 1.2 mm max height

PLASTIC QUAD FLATPACK

(

8) NOTE 7

4.44)

(

SOLDER MASK

OPENING

SYMM

SOLDER MASK

49

64

DEFINED PAD

64X (1.5)

1

48

64X (0.3)

SYMM

(0.5)

TYP

(11.4)

60X (0.5)

(1)

TYP

16

33

(

0.2) TYP

VIA

METAL COVERED

BY SOLDER MASK

32

(1) TYP

17

SEE DETAIL

(0.5) TYP

(11.4)

LAND PATTERN EXAMPLE

SCALE:6X

0.05 MAX

ALL AROUND

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

4221602/A 07/2014

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slm002) and SLMA004 (www.ti.com/lit/slma004).

8. Size of metal pad may vary due to creepage requirement.

www.ti.com

42

TUSB4041I

www.ti.com.cn

ZHCSDY6E –JULY 2015–REVISED SEPTEMBER 2017

EXAMPLE STENCIL DESIGN

PAP0064M

PowerPAD ^TM- 1.2 mm max height

PLASTIC QUAD FLATPACK

(

4.44)

BASED ON

0.127 THICK STENCIL

SEE TABLE FOR

DIFFERENT OPENINGS

SYMM

FOR OTHER STENCIL

THICKNESSES

64

49

64X (1.5)

1

48

64X (0.3)

SYMM

(11.4)

60X (0.5)

16

33

METAL COVERED

BY SOLDER MASK

17

32

(11.4)

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:6X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

5 X 5

4.44 X 4.44 (SHOWN)

4.06 X 4.06

0.127

0.152

0.178

3.75 X 3.75

4221602/A 07/2014

NOTES: (continued)

9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

10. Board assembly site may have different recommendations for stencil design.

www.ti.com

43

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TUSB4041IPAPR

HTQFP

PAP

64

1000

330.0

24.4

13.0

1.5

16.0

24.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTQFP PAP 64

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 55.0

TUSB4041IPAPR

1000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TRAY

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

W

K0

P1

CL

CW

Name

Type

(mm) (µm) (mm) (mm) (mm)

TUSB4041IPAP

PAP

HTQFP

64

160

8 X 20

150

322.6 135.9 7620 15.2

13.1

13

Pack Materials-Page 3

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TUSB4041IPAPR
厂家：	TEXAS INSTRUMENTS
描述：	4 端口高速 480Mbps USB 2.0 集线器 \| PAP \| 64 \| -40 to 85
文件：	总49页 (文件大小：1666K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TUSB4041IPAPR [TI]

相关型号：

TUSB4041IPAPRQ1

TUSB422

TUSB422IYFPR

TUSB422IYFPT

TUSB501

TUSB501-Q1

TUSB501DRFR

TUSB501TDRFRQ1

TUSB5052

TUSB5052B

TUSB5052PZ

TUSB5052PZ