TUSB542 [TI]
5Gbps USB 3.1 1 代 Type-C 2:1 多路复用器和线性转接驱动器;
| 型号： | TUSB542 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 5Gbps USB 3.1 1 代 Type-C 2:1 多路复用器和线性转接驱动器 驱动 复用器 驱动器 |
| 文件： | 总30页 (文件大小：3134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TUSB542
ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
TUSB542 USB Type-C 5Gbps 转接驱动器 2:1 MUX
1 特性
3 说明
1
•
可为 USB Type-C™ 端口提供 USB 3.1 Gen-1
TUSB542 是一款具有 USB Type-C™ 连接器的双通道
5Gbps 超高速 (SS) 2:1 多路复用器
支持 USB Type-C 电缆和连接器规范
超低功耗架构
USB 3.1 Gen1 (5Gbps)（也称为 USB-C）转接驱动器
支持系统。
•
•
该器件具有信号调节功能，并且能够为 USB Type-C™
可换向连接器转换 USB SS 信号。可以使用外部配置
通道逻辑控制器通过 SEL 引脚来控制 TUSB542，以
便正确复用信号。
–
–
–
工作电流 100mA
U2/U3 1.3mA
未连接时的电流为 300μA
•
高达 9dB 的可选择均衡、去加重功能和高达 6dB
的输出摆幅
TUSB542 包含接收器均衡和发送器去加重功能，用以
保持发送和接收数据路径上的信号完整性。接收器均衡
包含多种增益设置，用以克服插入损耗和码间串扰造成
的通道性能退化。为了补偿下行传输线路损耗，输出驱
动器还支持去加重配置。此外，自动 LFPS 去加重控
制有助于实现完全兼容性。
•
•
•
•
集成型终端
接收检测功能
通过监视信号进行电源管理
无主机/器件侧要求 – 支持 USB-C DFP、UFP 或
DRP 端口
•
•
单电源电压 1.8V ±10%
TUSB542 采用超低功耗架构，在由 1.8V 电源供电运
行时功耗较低。该转接驱动器支持低功耗模式，可进一
步降低空闲状态下的功耗。
工业温度范围：–40°C 至 85°C
2 应用
USB Type-C™ 转接驱动器采用小型超薄封装，适用于
许多便携式 应用。
•
USB 3.1 Gen 1 SS 应用
–
–
–
电话
器件信息(1)
平板电脑、平板手机和笔记本电脑
扩展坞
器件型号
TUSB542
封装
封装尺寸（标称值）
X2QFN (18)
2.00mm x 2.40mm
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
中的 TX_AP 和 RX_AP 引脚
示例应用
简化原理图
Type-C
Connector
RX_AP
RX_CON_1
TX_CON_1
RX_CON_2
TX_CON_2
TUSB542
TX_AP
SEL
Host
Processor
(USB Device)
CC1
CC2
CC/PD
Controller
Copyright © 2016, Texas Instruments Incorporate
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSER3
TUSB542
ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
目录
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Applications, USB Type-C Port SS MUX ... 16
Power Supply Recommendations...................... 22
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics, Power Supply Currents.... 6
6.6 Electrical Characteristics, DC ................................... 6
6.7 Electrical Characteristics, Dynamic........................... 7
6.8 Electrical Characteristics, AC.................................... 7
6.9 Timing Requirements................................................ 8
6.10 Switching Characteristics........................................ 8
6.11 Typical Characteristics............................................ 9
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
8
9
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
11 器件和文档支持 ..................................................... 23
11.1 文档支持 ............................................................... 23
11.2 接收文档更新通知 ................................................. 23
11.3 社区资源................................................................ 23
11.4 商标....................................................................... 23
11.5 静电放电警告......................................................... 23
11.6 Glossary................................................................ 23
12 机械、封装和可订购信息....................................... 23
7
4 修订历史记录
Changes from Revision D (March 2017) to Revision E
Page
•
•
•
•
•
•
•
•
将特性 中的“可选择均衡、去加重功能和输出摆幅”更改为“高达 9dB 的可选择均衡、去加重功能和高达 6dB 的输出摆幅” ... 1
删除了特性 中的“自动 LFPS 去加重控制，符合 USB 3.1 标准” ............................................................................................. 1
将特性 中的“可支持 USB DFP、UFP 或 DRP 端口”更改为“支持 USB-C DFP、UFP 或 DRP 端口” ..................................... 1
将应用部分的“USB Type-C SS 应用”更改为“USB 3.1 Gen 1 SS 应用”.................................................................................. 1
更改了简化原理图................................................................................................................................................................... 1
Changed the first five paragraghs of the Overview section.................................................................................................. 12
Changed Figure 15 .............................................................................................................................................................. 16
Changed the Design Requirements and the Detailed Design Procedure section of Typical Applications, USB Type-C
Port SS MUX section............................................................................................................................................................ 17
•
Changed the Design Requirements and the Detailed Design Procedure section of Typical Application: Switching
USB SS Host or Device Ports .............................................................................................................................................. 20
Changes from Revision C (August 2016) to Revision D
Page
•
Added a MIN value of –65 to the Storage temperature in the Absolute Maximum Ratings table.......................................... 5
Changes from Revision B (January 2016) to Revision C
Page
•
Changed Pin 15 To: TX_AP+ and Pin 14 To: TX_AP- in the RWQ Package image............................................................. 4
Changes from Revision A (January 2016) to Revision B
Page
•
•
Changed the RX_AP+ (pin 18) and RX_AP- (pin 17) I/O Type and Description to Diff output ............................................. 4
Changed the TX_AP+ (pin 15) and RX_AP- (pin 14) I/O Type and Description to Diff input ............................................... 4
2
版权 © 2015–2017, Texas Instruments Incorporated
TUSB542
www.ti.com.cn
ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
Changes from Original (December 2015) to Revision A
Page
•
•
•
•
•
•
•
•
•
•
已更改简化电路原理图............................................................................................................................................................ 1
Changed the RX_AP+, RX_AP- and TX_AP+, TX_PA- pins in the RWQ Package image ................................................... 4
Changed pin RX_AP+ number From: 15 To: 18 .................................................................................................................... 4
Changed pin RX_AP- number From: 14 To: 17 ..................................................................................................................... 4
Changed pin TX_AP+ number From: 18 To: 15..................................................................................................................... 4
Changed pin TX_AP- number From: 17 To: 14 ..................................................................................................................... 4
Changed Table 1 ................................................................................................................................................................. 12
Changed Figure 13 .............................................................................................................................................................. 12
Changed the Functional Block Diagram .............................................................................................................................. 13
Changed location of pins SSTXP, SSTXN and SSRXP, SSRXN in Figure 16 ................................................................... 18
Copyright © 2015–2017, Texas Instruments Incorporated
3
TUSB542
ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
5 Pin Configuration and Functions
RWQ Package
18 Pins (X2QFN)
Top View
18
17
16
GND
7
15
14
1
2
3
4
13
CNFG_A1
RX_CON_1+
RX_CON_1–
CNFG_B1
CNFG_A2
TX_CON_2+
12
11
10
TX_CON_2–
CNFG_B2
5
6
8
9
Pin Functions
PIN
I/O
DESCRIPTION
NAME
VDD18
GND
NO.
5
P
1.8 V Power Supply
Reference Ground Thermal Pad. Must connect to GND on the board.
PAD
G
2:1 SS MUX control. See Table 1 for signal path settings.210KΩ internal pullup resistor.
H: AP SS signals are connected to Type-C position 1 signals.
L: AP SS signals are connected to Type-C position 2 signals
SEL
16
1
Input
Tri-level configuration input pin A1 (for Ch 1): sets channel 1 (AP to redriver) EQ, DE and OS
Tri-level Input configurations. Pin has integrated pull-up and pull-down resistors of 105 kΩ. Refer to Table 2
CNFG_A1
CNFG_B1
CNFG_A2
CNFG_B2
for configuration settings.
Tri-level configuration input pin B1 (for Ch 1): sets channel 1 (AP to redriver) EQ, DE and OS
Tri-level Input configurations. Pin has integrated pull-up and pull-down resistors of 105 kΩ. Refer to Table 2
for configuration settings.
4
Tri-level configuration input pin A2 (for Ch 2): sets channel 2 (redriver to device) EQ, DE and
Tri-level Input OS configurations. Pin has integrated pull-up and pull-down resistors of 10 5 kΩ. Refer to
Table 2 for configuration settings.
13
10
Tri-level configuration input pin B2 (for Ch 2): sets channel 2 (redriver to device) EQ, DE and
Tri-level Input OS configurations. Pin has integrated pull-up and pull-down resistors of 105 kΩ. Refer to
Table 2 for configuration settings.
RX_AP+
18
17
15
14
2
Diff output
Diff output
Diff input
Diff input
Diff input
Diff input
Diff output
Diff output
Diff input
Differential output to Application Processor (AP), 5 Gbps SS positive signal
Differential output to AP, 5 Gbps SS negative signal
RX_AP-
TX_AP+
Differential input from AP, 5 Gbps SS positive signal
TX_AP-
Differential input from AP, 5 Gbps SS negative signal
Rx_Con_1+
Rx_Con_1-
Tx_Con_1+
Tx_Con_1-
Rx_Con_2-
Differential input from Type-C Connector, Position 1, SS positive signal
Differential input from Type-C Connector, Position 1, SS negative signal
Differential output to Type-C Connector, Position 1, SS positive signal
Differential output to Type-C Connector, Position 1, SS negative signal
Differential input from Type-C Connector, Position 2, SS negative signal
3
6
7
8
4
Copyright © 2015–2017, Texas Instruments Incorporated
TUSB542
www.ti.com.cn
ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
9
Rx_Con_2+
Tx_Con_2+
Tx_Con_2-
Diff input
Diff output
Diff output
Differential input from Type-C Connector, Position 2, SS positive signal
Differential output to Type-C Connector, Position 2, SS positive signal
Differential output to Type-C Connector, Position 2, SS negative signal
12
11
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
65
MAX
2.3
UNIT
V
Supply voltage range, VCC
Differential I/O
Voltage range at any input or output terminal
CMOS Inputs
1.5
V
2.3
V
Junction temperature, TJ
Storage temperature, Tstg
150
105
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.62
–40
75
NOM
MAX
1.98
85
UNIT
V
VCC
Main power supply
1.8
TA
Operating free-air temperature
°C
C(AC)
AC coupling capacitor required for TX pins
AC coupling capacitor required for TX pins
VCC supply ramp requirement
200
100
40
nF
V(PSN)
mV
ms
kΩ
t(VCC_RAMP)
R(pullup-down)
0.2
Pull-up/down resistor to control CNF pins
2.2
6.4 Thermal Information
TUSB542
THERMAL METRIC(1)
X2QFN (RWQ)
UNIT
18 PINS
83.4
52
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-board thermal resistance
49.1
0.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
49.1
n/a
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2015–2017, Texas Instruments Incorporated
5
TUSB542
ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
6.5 Electrical Characteristics, Power Supply Currents
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
100
1.3
MAX
UNIT
mA
ICC(ACTIVE Average active current; link in U0 with SuperSpeed data transmission; OS = 0.9 V; DE
130
)
= 0 dB
ICC(U2/U3) Average current in U2/U3
Average current with no connection
mA
ICC(NC)
0.3
mA
No SuperSpeed device is connected to TXP/TXN
6.6 Electrical Characteristics, DC
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TRI-STATE CMOS INPUTS (CNFG_A1, CNFG_B1, CNFG_A2 and CNFG_B2)
VIH
VIM
VIL
High-level input voltage
Mid-level input voltage
Mid-level input voltage
Floating voltage
VCC x 0.75
V
V
VCC / 2
VCC x 0.25
V
VF
VIN = High impedance
VCC / 2
105
V
R(PU)
R(PD)
IIH
Internal pull-up resistance
Internal pull-down resistance
High-level input current
Low-level input current
kΩ
kΩ
µA
µA
105
VIN = 1.98 V
VIN = GND
26
1
IIL
–26
–1
External leakage current (from
application board + Application
Processor pin high impedance)
tolerance
Ilkg
VIN = GND or VIN = 1.98 V
µA
CMOS INPUT – SEL
VIH
VIL
IIH
High-level input voltage
VCC x 0.7
V
V
Mid-level input voltage
High-level input current
Low-level input current
VCC x 0.3
5
VIN = 1.98 V
VIN = GND
µA
µA
IIL
–16
6
Copyright © 2015–2017, Texas Instruments Incorporated
TUSB542
www.ti.com.cn
ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
6.7 Electrical Characteristics, Dynamic
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Differential Receiver
V(RX-DC-CM)
RX DC common mode voltage
0
2
V
Measured at connector. Present when
SuperSpeed USB device detected on TX
pins.
Receiver DC common mode
impedance
R(RX-CM-DC)
18
30
Ω
Measured at connector. Present when
R(RX-DIFF-DC)
Receiver DC differential impedance SuperSpeed USB device detected on TX
pins.
72
120
Ω
Measured at connector. Present when no
DC input CM input impedance when
Z(RX-HIGH-IMP-DC-POS)
SuperSpeed USB device detected on TX
termination is disabled.
25
KΩ
pins or while VCC is ramping.
LFPS Detect threshold. Below min is Measured at connector. Below min is
V(RX-LFPS-DET-DIFF-P-P)
0.1
0.3
V
noise.
squelched.
V(RX-CM-AC-P)
Peak RX AC common mode voltage Measured at package pin.
Rx Input capacitance for return loss At package pin to AC GND.
150
1.1
mV
pF
C(RX-PARASITIC)
Differential Transmitter
OS Low, 0 dB DE
0.9
1.1
V
V
Differential peak-to-peak TX voltage
swing
V(TX-DIFF-PP)
OS High, 0 dB DE
V(TX-DIFF- PP-LFPS)
LFPS differential voltage swing
Transmitter de-emphasis
OS Low, High
Low
0.8
1.2
V
0
3.5
6
dB
dB
dB
V(TX-DE- RATIO)
Mid
High
The amount of voltage change
allowed during Receiver Detection.
V(TX-RCV-DETECT)
0.6
2
V
V
The instantaneous allowed DC common-
mode voltage at connector side of AC
coupling capacitor.
V(TX-DC-CM)
TX DC common mode voltage
0
AC Electrical Idle differential peak-
to-peak output voltage
V(TX-IDLE-DIFF-AC-PP)
V(TX-IDLE-DIFF_DC)
At package pin.
0
0
10
10
mV
nV
V
DC Electrical Idle differential output
voltage
At package pin. After low pass filter to
remove AC component.
V(TX-CM-DC-ACTIVE-IDLE-
Absolute DC common mode voltage
between U1 and U0.
At package pin.
0.2
DELTA)
I(TX-SHORT)
R(TX-DC)
TX short-circuit current limit
60
30
mA
Ω
TX DC common mode impedance
TX DC differential impedance
At package pins
18
72
R(TX-DIFF-DC)
C(TX-PARASTIC)
T(jitter)
120
1.25
Ω
TX input capacitance for return loss At package pins to AC GND
Total Residual Jitter (peak to peak)
pF
ps
12
6.8 Electrical Characteristics, AC
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
–45
MAX
UNIT
Differential Cross talk between TX and
RX Signal Pairs
Xtalk
at 2.5 Ghz, TX to RX
dB
Copyright © 2015–2017, Texas Instruments Incorporated
7
TUSB542
ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
6.9 Timing Requirements
MIN
NOM
MAX
UNIT
tIDLEEntry
Delay from U0 to electrical idle.
See Figure 2
See Figure 2
6
ns
U1 exit time: break in electrical idle to the
transmission of LFPS
tIDLEExit_U1
6
1
ns
µs
µs
U2/U3 exit time: break in electrical idle to
transmission of LFPS
From the time when the far end
terminations detected for both ports
tIDLEExit_U2U3
tIDLEExit_DISC
U2/U3 exit time: break in electrical idle to
transmission of LFPS
From the time when the far end
terminations detected for both ports
2
tDIFF-DLY
Differential propagation delay.
See Figure 1
225
ps
tPWRUPACTIVE
Time when VCC reach 80% to device active
30
ms
6.10 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
20% to 80% of differential output. At
device pins.
tTX-RISE-FALL
tRF-MISMATCH
Transmitter rise/fall time (see Figure 3)
80
ps
20% to 80% of differential output. At
device pins
Transmitter rise/fall mismatch
2.3
ps
IN
tDIFF_DLY
tDIFF_DLY
OUT
Figure 1. Propagation Delay Timing
VEID_TH
IN+
Vcm
INœ
tidleExit
tidleEntry
OUT+
Vcm
OUTœ
Figure 2. Electrical Idle Mode Exit and Entry Delay Timing
80%
20%
tr
tf
Figure 3. Output Rise and Fall Times
8
Copyright © 2015–2017, Texas Instruments Incorporated
TUSB542
www.ti.com.cn
ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
6.11 Typical Characteristics
6.11.1 1-Inch Pre Channel
880 mV
5 Gbps
Figure 4. Input Signal: 1-Inch Input Trace
Figure 5. Output Signal: 12-Inches Output Trace
Figure 6. Output Signal: 16-Inches Output Trace
Copyright © 2015–2017, Texas Instruments Incorporated
9
TUSB542
ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
6.11.2 24-Inch Pre Channel
880 mV
5 Gbps
Figure 7. Input Signal: 24-Inch Input Trace
Figure 9. Output Signal: 24-Inches Output Trace
Figure 8. Output Signal: 12-Inches Output Trace
10
Copyright © 2015–2017, Texas Instruments Incorporated
TUSB542
www.ti.com.cn
ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
6.11.3 32-Inch Pre Channel
880 mV
5 Gbps
Figure 10. Input Signal: 32-Inch Input Trace
Figure 12. Output Signal: 24-Inches Output Trace
Figure 11. Output Signal: 12-Inches Output Trace
Copyright © 2015–2017, Texas Instruments Incorporated
11
TUSB542
ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
7 Detailed Description
7.1 Overview
TUSB542 is an active re-driver for USB 3.1 Gen1 applications; it supports Type-C applications, as well as
switching between two Hosts and one device (or vice versa). The device is a dual channel USB 3.1 Gen1 (5
Gbps) re-driver supporting systems with USB Type-C connectors. The TUSB542 can be controlled through the
SEL, ideal to be controlled using an external Configuration Channel Logic or Power Delivery Controller to
properly mux the signals in Type-C applications.
When 5 Gbps Super Speed USB signals travel across a PCB or cable, signal integrity degrades due to loss and
inter-symbol interference. The TUSB542 recovers incoming data by applying equalization that compensates for
channel loss, and drives out signals with a high differential voltage. This extends the possible channel length,
and enables systems to pass USB 3.1 compliance.
The TUSB542 advanced state machine makes it transparent to hosts and devices. After power up, the TUSB542
periodically performs receiver detection on the TX pair. If it detects a SS USB receiver, the RX termination is
enabled, and the TUSB542 is ready to re-drive.
The TUSB542 operates over the industrial temperature range of –40ºC to 85ºC in the 2 mm x 2.4 mm X2QFN
package. The device ultra-low power architecture operates at a 1.8-V power supply. The automatic LFPS
DeEmphasis control further enables the system to be USB 3.0 compliant. An advanced state machine inside the
device monitors the USB SS traffic to perform enhanced power management to operate in no-connect, U2, U3
and active modes.
The USB Type-C connector is designed to allow insertion either upside-up or downside-up. The TUSB542
supports this feature by routing the AP signals to one of two output channels. The SEL input control defines the
way that the AP side signals is routed on the re-driver device side. Table 1 lists the active MUX configurations
based on the SEL input.
Table 1. USB SS MUX Control
SEL
H
Tx_Con_1
TX_AP
GND
Rx_Con_1
Tx_Con_2
GND
Rx_Con_2
(1)
RX_AP
GND
(1)
L
GND
TX_AP
RX_AP
(1) Terminated through 50 K (minimum) resistors
The TUSB542 has flexible configurations to optimize the device using GPIO control pins. Figure 13 shows a
typical signal chain for mobile applications. Channel 1 is between Application Processor (AP) and TUSB542,
Channel 2 is between the TUSB542 redriver and the downstream device. The CNFG_A1 and CNFG_B1 pins
provide signal integrity configuration settings for channel 1, while CNFG_A2 and CNFG_B2 pins control the
operation of Channel 2. as depicted in Table 2.
Main Board
Flexible Cable + Sub-Board
EQ_AP
DE_CON
OS_CON
Ch. 1
TUSB542
Ch. 2
EQ_CON
DE_AP
OS_AP
Figure 13. Typical Channels
The receiver (RX) of the device provides the flexibility of 0, 3, 6 and 9 dB of equalization, while the transmitter
(TX) provides the options of 0, 3.5 or 6 dB De-Emphasis. The transmitter also supports output swing settings of
900 mV and 1.1 V.
12
Copyright © 2015–2017, Texas Instruments Incorporated
TUSB542
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ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
Table 2. Device Signal Conditioning Configuration Settings for TUSB542
Ch1 (AP-Redriver)
Ch2 (Redriver-Conn)
CNFG_A2 CNFG_B2
DE_AP (dB)
OS_AP (V)
EQ_AP (dB)
DE_Conn (dB)
OS_Conn (V)
EQ_Conn (dB)
CNFG_A1
CNFG_B1
Low
3.5
3.5
0
1.1
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
3
3
3
3
0
0
0
0
6
Low
Float
High
Low
6
3.5
3.5
6
1.1
1.1
0.9
0.9
1.1
0.9
1.1
0.9
1.1
0
0
0
0
6
6
6
6
9
Low
Float
High
Low
Float
High
Low
0
Float
High
Float
High
3.5
.35
0
Float
High
Low
3.5
3.5
6
Low
Float
High
0
Float
High
6
6
6
7.2 Functional Block Diagram
VDD18
TUSB542
RX Det
TX
TX_CON_2
DE_CON
OS_CON
TX_AP
EQ
LOS
LOS
EQ_AP
EQ
RX_CON_2
SEL_TX
EQ_CON
RX Det
TX
TX_CON_1
RX_CON_1
RX_AP
TX
DE_CON
OS_CON
LOS
RX Det
DE_AP
OS_AP
EQ
SEL_RX
EQ_CON
EQ_AP
EQ_CON
DE_AP
CNFG_[Ax and Bx]
Configuration
Controller
DE_CON
OS_AP
Advanced
State Machine
LFPS
Controller
OS_CON
SEL
SEL_TX
SEL_RX
GND
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2015–2017, Texas Instruments Incorporated
13
TUSB542
ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
7.3 Feature Description
7.3.1 Receiver Equalization
The purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference in
the system before the input of the TUSB542 receiver. The receiver overcomes these losses by providing gain to
the high frequency components of the signals with respect to the low frequency components. The proper gain
setting should be selected to match the channel insertion loss before the receiver input of the TUSB542.
7.3.2 De-Emphasis Control and Output Swing
The output differential drivers of the TUSB542 provide selectable De-Emphasis and output swing in order to
achieve USB3.1 compliance, these options are configurable by means of 3-state control pins, and its available
settings are listed on the Table 2. The level of de-emphasis required in the system depends on the channel
length after the output of the re-driver. Figure 14 shows transmit bits with De-Emphasis.
Transition Bit
Consecutive Bits
Transition Bit
Consecutive Bits
DE = 0 dB
0.5 V
DE =
DE =
œ
œ
3.5 dB
6 dB
VTX-DIFF-PP
0 V
DE =
DE =
œ
œ
6 dB
3.5 dB
DE = 0 dB
œ 0.5 V
0ps
200ps
400ps
600ps
800ps
1000ps
1200ps
Figure 14. Transmitter Differential Voltage in Presence of De-Emphasis
7.3.3 Automatic LFPS Detection
The TUSB542 features an intelligent low frequency periodic signaling (LFPS) controller. The controller senses
the low frequency signals and automatically disables the driver de-emphasis, for full USB3.1 compliance.
7.3.4 Automatic Power Management
The TUSB542 deploys RX detect, LFPS signal detection and signal monitoring to implement an automatic power
management scheme to provide active, U2/U3 and disconnect modes. The automatic power management is
driven by an advanced state machine, which is implemented to manage the device such that the re-driver
operates smoothly in the links.
14
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TUSB542
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ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
7.4 Device Functional Modes
7.4.1 Disconnect Mode
The Disconnect mode is the lowest power state of the TUSB542. In this state, the TUSB542 periodically checks
for far-end receiver termination on both TX. Upon detection of the far-end receiver’s termination on both ports,
the TUSB542 will transition to U0 mode.
7.4.2 U Modes
7.4.2.1 U0 Mode
The U0 mode is the highest power state of the TUSB542. Anytime super-speed traffic is being received, the
TUSB542 remains in this mode.
7.4.2.2 U2/U3 Mode
Next to the disconnect mode, the U2/U3 mode is next lowest power state. While in this mode, the TUSB542
periodically performs far-end receiver detection.
Copyright © 2015–2017, Texas Instruments Incorporated
15
TUSB542
ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
TUSB542 is a USB 3.1 G1 5 Gbps super speed 1:2 or 2:1 redriver de-multiplexer/multiplexer for RX and TX
differential pairs. The device is host/device side agnostic and can be used for host or device switching.
8.2 Typical Applications, USB Type-C Port SS MUX
TUSB542 is optimized for USB Type-C port. The device provide multiplexing to select appropriate super speed
RX and TX signal pairs resulting from Type-C plug orientation flipping. A companion USB PD or CC controller
provides the MUX selection. The device can be used part of UFP, DFP or DRP Type-C port. Figure 15 illustrates
typical Type-C applications.
Type-C
Connector
RX_AP
TX_AP
RX_CON_1
TX_CON_1
RX_CON_2
TX_CON_2
TUSB542
SEL
Host
Processor
(USB Device)
CC1
CC2
CC/PD
Controller
Copyright © 2016, Texas Instruments Incorporate
Figure 15. USB Type-C Host (Device) Application
16
Copyright © 2015–2017, Texas Instruments Incorporated
TUSB542
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ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
Typical Applications, USB Type-C Port SS MUX (continued)
8.2.1 Design Requirements
For this design example, use the parameters shown in Table 3.
The configured value depends on the physical channel (PCB layout) Equalization 0, 3, 6, 9 dB (5 Gbps) The
configured value depends on the physical channel (PCB layout) De-Emphasis 0, –3.5, –6 dB The configured
value depends on the physical channel (PCB layout) Differential impedance 72 - 120 Ω.
Table 3. Design Parameters
PARAMETER
VALUE
COMMENT
VDD18
1.8 V
75-200nF range allowed.
TUSB542 biases both input and output common mode
voltage, hence ac-coupling caps as required on both
sides.
AC Coupling Capacitors for SS signals
100 nF
Note: TX pairs need to be biased at the connector.
Pull-up/down resistor to control CNF pins
Input voltage range
4.7 kΩ
100 mV to 1200 mV
900 mV to 1100 mV
Output voltage range
8.2.2 Detailed Design Procedure
Figure 16 shows an example implementation of a USB Type-C DRP port using TUSB542. Texas Instruments
TUSB322 is shown here as channel configuration (CC) controller. Note connections for CNFG pins of TUSB542
is example only. The connection of the CNFG pins is application dependent; refer to theTable 2, where the user
can find the available settings.
It is recommended to run an overall system signal integrity analysis, in order to estimate the channel loss and
configure the re-driver. It is also recommended to have pull-up and pull-down option on the configuration pins for
debug and testing purposes.
The signal integrity analysis must determine the following:
•
•
•
Equalization (EQ) setting
De-Emphasis (DE) setting
Output Swing Amplitude (OS) setting
The equalization must be set based on the insertion loss in the pre-channel (channel before the TUSB542
device). The input voltage to the device is able to have a large range because of the receiver sensitivity and the
available EQ settings.
The De-emphasis setting must be set based on the length and characteristics of the post channel (channel after
the TUSB542 device).
Copyright © 2015–2017, Texas Instruments Incorporated
17
TUSB542
ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
SCL
SDA
USB VBUS Switch
(Optional BC 1.2 Support for Legacy)
DM_OUT
DP_OUT
DM
DP
DM_IN
DP_IN
VOUT
System VBUS
VIN
EN
PS_EN
PS_FAULT#
VBUS
FAULT#
I2C I/O
1.8V or 3.3V
VDD_5V
DM
DP
VCONN
Bulk Cap
150µF
100nF
100µF
VBUS
A12
B1
900kO
RXP2
RXN2
TXP 2
TXN 2
VBUS _DET
A11
A10
A9
B2
B3
B4
B5
B6
4.7kO 4.7kO
200kO
200kO
PORT
INT_N/OUT3
CC1
CC2
INT#
A8
CC2
CC1
USB3
A7
TUSB322
ID
ID
SCL
SDA
and
A6
B7
A5
A4
A3
A2
B8
B9
PMIC
SCL / OUT2
SDA / OUT1
TXN1
TXP1
RXN1
RXP1
B10
B11
A1
B12
VDD18
Note
Connection Flip
for CC1 and CC2
VDD18
47kO
100nF
SEL
TXP2
TXN2
TX_CON_2+
TX_CON_2–
100nF
RXP2
RXN2
100nF
RX_CON_2+
RX_CON_2–
RX_AP+
RX_AP–
SSRXP
SSRXN
100nF
100nF
100nF
TXN1
TXP1
TX_AP+
TX_AP–
SSTXP
SSTXN
TX_CON_1+
TX_CON_1–
100nF
RXN1
RXP1
VDD18
4.7kO
100nF
RX_CON_1+
RX_CON_1–
CNFG_A1
CNFG_B1
CNFG_A2
CNFG_B2
4.7kO
Copyright © 2016, Texas Instruments Incorporated
Figure 16. USB-C DRP Implementation Using TUSB542 and TUSB322/TUSB321
18
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TUSB542
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ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
8.2.3 Application Curves
1-ft SMA-SMP Cable
1-ft SMP-SMA Cable
TUSB542
MP1800 BERT 5Gbps
880mVpp PRBS7
Intput PCB Trace
Output PCB Trace
DCAX35GHz BWPTB
1-ft SMP-SMP Cable
1-ft SMP-SMP Cable
Figure 17. Measurement Setup
Figure 19. Output Signal: 12 Inch Output Trace
(Eye Diagram at the DCAX)
Figure 18. Input Signal: 12 Inch Input Trace
(Eye Diagram at the Re-driver input)
Figure 20. Input Signal: 24 Inch Input Trace
(Eye Diagram at the Re-driver input)
Figure 21. Output Signal: 24 Inch Output Trace
(Eye Diagram at the DCAX)
Copyright © 2015–2017, Texas Instruments Incorporated
19
TUSB542
ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
8.2.4 Typical Application: Switching USB SS Host or Device Ports
TUSB542, being USB SS mux/demux, can be used for host or device switching. Figure 22 illustrates how the
device can be used:
RX_CON_1
USB Host 1
TX_CON_1
(Device 1)
RX_AP
TX_AP
USB
Device
(Host)
TUSB542
RX_CON_2
TX_CON_2
USB Host 2
(Device 2)
SEL
Copyright © 2016, Texas Instruments Incorporated
Figure 22. Muxing Two Host (Device) Port
8.2.4.1 Design Requirements
For this design example, use the design parameters shown in Table 4.
The configured value depends on the physical channel (PCB layout) Equalization 0, 3, 6, 9 dB (5 Gbps) The
configured value depends on the physical channel (PCB layout) De-Emphasis 0, –3.5, –6 dB The configured
value depends on the physical channel (PCB layout) Differential impedance 72 - 120 Ω
Table 4. Design Parameters
PARAMETER
VALUE
COMMENT
VDD18
1.8 V
75-200nF range allowed.
TUSB542 biases both input and output common mode
voltage, hence ac-coupling caps as required on both
sides.
AC Coupling Capacitors for SS signals
100 nF
Note: TX pairs need to be biased at the connector.
Pull-up/down resistor to control CNF pins
Input voltage range
4.7 kΩ
100 mV to 1200 mV
900 mV to 1100 mV
Output voltage range
8.2.4.2 Detailed Design Procedure
Figure 16 shows an example implementation of a USB Type-C DRP port using TUSB542. Texas Instruments
TUSB322 is shown here as channel configuration (CC) controller. Note connections for CNFG pins of TUSB542
is example only. The connection of the CNFG pins is application dependent; refer to the Table 2, where the user
can find the available settings.
It is recommended to run an overall system signal integrity analysis, in order to estimate the channel loss and
configure the re-driver. It is also recommended to have pull-up and pull-down option on the configuration pins for
debug and testing purposes.
The signal integrity analysis must determine the following:
•
•
•
Equalization (EQ) setting
De-Emphasis (DE) setting
Output Swing Amplitude (OS) setting
20
Copyright © 2015–2017, Texas Instruments Incorporated
TUSB542
www.ti.com.cn
ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
The equalization must be set based on the insertion loss in the pre-channel (channel before the TUSB542
device). The input voltage to the device is able to have a large range because of the receiver sensitivity and the
available EQ settings.
The De-emphasis setting must be set based on the length and characteristics of the post channel (channel after
the TUSB542 device).
The output swing setting can also be configured based on the amplitude needed to pass the compliance test.
This setting is also based on the length of interconnect or cable the TUSB542 is driving.
Refer to the Table 2 for a detailed description on how to configure the CONFIG_A1/A2 and CONFIG_B1/A2
terminals, in order to achieve the desired EQ, OS and DE settings.
8.2.4.3 Application Curves
For this design example, use the application curves shown in Application Curves.
Copyright © 2015–2017, Texas Instruments Incorporated
21
TUSB542
ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
9 Power Supply Recommendations
TUSB542 has internal power on reset circuit to provide clean reset for state machine provided supply ramp and
level recommendations are met.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
RXP/N and TXP/N pairs should be routed with controlled 90-Ohm differential impedance (±15%).
Keep away from other high speed signals.
Intra-pair routing should be kept to within 2 mils.
Length matching should be near the location of mismatch.
Each pair should be separated at least by 3 times the signal trace width.
The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left
and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This will
minimize any length mismatch causes by the bends and therefore minimize the impact bends have on EMI.
•
•
•
•
•
Route all differential pairs on the same of layer.
The number of VIAS should be kept to a minimum. It is recommended to keep the VIAS count to 2 or less.
Keep traces on layers adjacent to ground plane.
Do NOT route differential pairs over any plane split.
Adding Test points will cause impedance discontinuity, and therefore; negatively impacts signal performance.
If test points are used, they should be placed in series and symmetrically. They must not be placed in a
manner that causes a stub on the differential pair.
10.2 Layout Example
Figure 23. Example Layout
22
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TUSB542
www.ti.com.cn
ZHCSEG8E –DECEMBER 2015–REVISED JUNE 2017
11 器件和文档支持
11.1 文档支持
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。请单击右上角的通知我进行注册，即可收到任意产品
信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
版权 © 2015–2017, Texas Instruments Incorporated
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TUSB542RWQR
ACTIVE
X2QFN
RWQ
18
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
54
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TUSB542RWQR
X2QFN
RWQ
18
3000
179.0
8.4
2.25
2.65
0.53
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
X2QFN RWQ 18
SPQ
Length (mm) Width (mm) Height (mm)
213.0 191.0 35.0
TUSB542RWQR
3000
Pack Materials-Page 2
PACKAGE OUTLINE
RWQ0018A
X2QFN - 0.4 mm max height
S
C
A
L
E
5
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.5
2.3
0.4 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.6
1
0.1
PKG
(0.05)
ALL AROUND
5
9
EXPOSED
THERMAL PAD
14X 0.4
4
10
13
2X
SYMM
2.05
TYP
1.2
1.4 0.1
1
0.25
0.15
18X
18
14
0.1
C A B
PIN 1 ID
(OPTIONAL)
0.3
0.2
18X
0.05
1.65 TYP
4221962/B 06/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RWQ0018A
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1)
(R0.05) TYP
18X (0.3)
SYMM
18
14
13
1
18X (0.2)
SYMM
(0.45)
(2.1)
(1.4)
14X (0.4)
10
4
(
0.2) TYP
VIA
5
9
(1.7)
LAND PATTERN EXAMPLE
SCALE:25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4221962/B 06/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RWQ0018A
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.95)
(R0.05) TYP
18X (0.3)
18
14
1
13
18X (0.2)
SYMM
(1.3)
(2.1)
14X (0.4)
10
4
METAL
TYP
5
9
SYMM
(1.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
88% PRINTED SOLDER COVERAGE BY AREA
SCALE:30X
4221962/B 06/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
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