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TUSB544

ZHCSG75E –APRIL 2017–REVISED APRIL 2018

TUSB544 USB TYPE-C™ 8.1 Gbps 多协议线性转接驱动器

1 特性

2 应用

1

•

支持高达 8.1 Gbps 的协议无关正反两用式 4 通道

线性转接驱动器。

•

平板电脑

笔记本电脑

台式机

–

带有 USB 3.1 第 1 代和 DisplayPort 1.4 作为交

替模式的 USB Type-C。

扩展坞

•

支持集成有 USB 3.1 和 DisplayPort 多路复用器，

适用于 Type-C 应用的处理器

3 说明

•

支持信号调节内部 Type-C 线缆

TUSB544 是一种 USB Type-C 交替模式转接驱动器开

关，可支持高达 8.1Gbps 的数据速率。此协议无关线

性转接驱动器能够支持包括 VESA DisplayPort 在内的

USB Type-C 交替模式接口。

适用于 SBU 信号的交叉点多路复用器

频率为 4.05GHz 时，支持高达 11dB 的线性均衡功

能

用于通道方向和均衡的 GPIO 和 I²C 控制

•

TUSB544 提供多个接收线性均衡级别，用于补偿因线

缆或电路板线迹损耗产生的码间串扰 (ISI)。该器件由

3.3V 单电源供电运行，支持商业级温度范围和工业级

温度范围。

通过监控 USB 功耗状态和嗅探 DP 链路训练可实

现高级电源管理

可通过 GPIO 或 I²C 进行配置

•

支持热插拔

3.3V 单电源

TUSB544 的全部四个通道均为正反两用式，这使其成

为可用于诸多应用的多用途信号调节器。

工业级温度范围：–40ºC 至 85ºC (TUSB544I)

商业级温度范围：0ºC 至 70ºC (TUSB544)

4mm × 6mm、0.4mm 间距、40 引脚 QFN 封装

器件信息⁽¹⁾

器件型号

TUSB544

TUSB544I

封装

封装尺寸（标称值）

WQFN (40)

4.00mm x 6.00mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

简化原理图

D+/-

TUSB544

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

TUSB544

USB/DP/

Custom

Source

AUXp

AUXn

SBU1

SBU2

CTL

0 1

FLIP

HPD

Control

CC1

CC2

USB PD

Controller

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLLSEZ0

TUSB544

ZHCSG75E –APRIL 2017–REVISED APRIL 2018

www.ti.com.cn

7.4 Device Functional Modes........................................ 19

7.5 Programming .......................................................... 33

7.6 Register Maps ........................................................ 34

Application and Implementation ........................ 43

8.1 Application Information............................................ 43

8.2 Typical Application ................................................. 43

8.3 System Examples .................................................. 47

Power Supply Recommendations...................... 54

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 4

Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 7

6.5 Power Supply Characteristics ................................... 7

6.6 DC Electrical Characteristics .................................... 7

6.7 AC Electrical Characteristics..................................... 8

6.8 Timing Requirements.............................................. 10

6.9 Switching Characteristics........................................ 10

6.10 Typical Characteristics.......................................... 13

Detailed Description ............................................ 16

7.1 Overview ................................................................. 16

7.2 Functional Block Diagram ....................................... 17

7.3 Feature Description................................................. 18

8

9

10 Layout................................................................... 55

10.1 Layout Guidelines ................................................. 55

10.2 Layout Example .................................................... 55

11 器件和文档支持 ..................................................... 56

11.1 文档支持 ............................................................... 56

11.2 接收文档更新通知 ................................................. 56

11.3 社区资源................................................................ 56

11.4 商标....................................................................... 56

11.5 静电放电警告......................................................... 56

11.6 术语表 ................................................................... 56

12 机械、封装和可订购信息....................................... 56

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision D (November 2017) to Revision E

Page

•

更改了简化原理图................................................................................................................................................................... 1

Changes from Revision C (October 2017) to Revision D

Page

•

更改了说明部分第二段中的文本，将“..因码间串扰 (ISI) 产生的线缆或电路板迹线损耗”更改成了“..因线缆或电路板线

迹损耗产生的码间串扰 (ISI)。” ............................................................................................................................................... 1

•

Changed Pin 2 and Pin 35 text From: "When I2C_EN !=0,.." To: "In I2C mode,.." in the Pin Functions............................... 4

Changed Pin 14 text From: "..levels for the GPIO configuration.." To: "..levels for the 2-level GPIO configuration.." in

the Pin Functions.................................................................................................................................................................... 5

•

Changed Pin 17 in the text From: 0 = GPIO Mode (I²C disabled) To: 0 = GPIO Mode AUX Snoop enabled (I²C

disabled) in the Pin Functions ................................................................................................................................................ 5

•

Changed Pins 21, 22, and 23 From: "When I2C_EN !=0,.." To: "In GPIO mode,.." in the Pin Functions.............................. 5

Removed "When I2C_EN = 0" from pin 32. .......................................................................................................................... 5

In pin 32, changed 2ms to t_{CTL1_DEBOUNCE}............................................................................................................................... 5

From: DEQ1 sets the high-frequency equalizer gain for downstream facing URX1, URX2, UTX1, UTX2 receivers.

To: DEQ1 sets the high-frequency equalizer gain for downstream facing DRX1, DRX2, DTX1, DTX2 receivers ............... 5

•

Deleted the MAX value of 10 ms from t_{CTL1_DEBOUNCE}in the Switching Characteristics ....................................................... 10

Added test Condition " DP lanes will be disabled if low for greater than min value" for t_{CTL1_DEBOUNCE}in the Switching

Characteristics...................................................................................................................................................................... 10

•

Changed text From: "There is an internal 30 kΩ pull-up and a 94kΩ pull-down." To: "There are internal pull-up and a

pull-down resisters." in 4-Level Inputs.................................................................................................................................. 18

Changed text From: "..when I2C_EN = “0”." To: "..when I2C_EN = “0” or "F"." in the first paragraph of Device

Configuration in GPIO Mode ................................................................................................................................................ 19

•

Changed 表 4 ....................................................................................................................................................................... 21

Changed text From: "..when I2C_EN is not equal to “0”." To: "..when I2C_EN is equal to “1”. " in Device

2

TUSB544

www.ti.com.cn

ZHCSG75E –APRIL 2017–REVISED APRIL 2018

Configuration in I2C Mode.................................................................................................................................................... 28

Changed text From: "When I2C_EN is ‘0’,.." To: :In I2C mode,.." in DisplayPort Mode...................................................... 29

Changed text From: "When I2C_EN is ‘0’,.." To: :In GPIO mode,.." in Custom Alternate Mode ......................................... 29

Deleted the Cable Mode section and all "cable mode" from datasheet. ............................................................................. 29

Changed Table 12 ................................................................................................................................................................ 35

Changed Bit 5-2 Type From: R/WU To: R/W in Table 15 .................................................................................................... 36

Changed Bit 7-0 Type From: R/WU To: R/W in Figure 25 and Table 16............................................................................. 37

Changed Bit 7-0 Type From: R/WU To: R/W in Figure 26 and Table 17............................................................................. 37

Changed Bit 6-0 Type From: RU To: RH in Figure 27 and Table 18................................................................................... 38

Changed Figure 29 and Table 20......................................................................................................................................... 40

Changed Bit 7-0 Type From: R/WU To: R/W in Figure 30 and Table 21............................................................................. 40

Changed Bit 3-0 Type From: R/WU To: R/W in Figure 31 and Table 22............................................................................. 41

Changed bit 7 From: R/WU To: RH in Figure 32 and Table 23 ........................................................................................... 41

USB3.1_# register default changed to 4h from 0h. .............................................................................................................. 41

Changed USB3.1_4 register default to 23h from 00h. ........................................................................................................ 42

Changed SBU1, and SBU2 pin labels on the Sink side of 图 40 ......................................................................................... 48

Changed SBU1, and SBU2 pin labels on the Sink side of 图 41 ......................................................................................... 49

Changed SBU1, and SBU2 pin labels on the Sink side of 图 42 ......................................................................................... 49

Changed SBU1, and SBU2 pin labels on the Sink side of 图 48 ......................................................................................... 52

Changed SBU1, and SBU2 pin labels on the Sink side of 图 49 ......................................................................................... 53

Changed SBU1, and SBU2 pin labels on the Sink side of 图 50 ......................................................................................... 53

•

Changes from Revision B (Mayl 2017) to Revision C

Page

•

Changed T_{cfg_su}From: 350 ms To: 350 µs in 表 9................................................................................................................ 33

Changes from Revision A (April 2017) to Revision B

Page

•

Added a MIN value of 0.5 pF to C_{I_I2C}in the DC Electrical Characteristics table .................................................................. 8

Changed V_RX-DC-CM, deleted the MIN and MAX values and added TYP = 0 V in the AC Electrical Characteristics table...... 8

Changed EQ_SSDescription From: "Receiver equalization" To: "Receiver equalization at maximum setting" in the AC

Electrical Characteristics table ............................................................................................................................................... 8

•

Changed EQ_SSFrom: MAX = 9.8 dB To: MAX = 9 dB in the AC Electrical Characteristics table ......................................... 8

Changed V_TX-DC-CM, deleted the MIN and MAX values and added TYP = 1.75 V in the AC Electrical Characteristics table. 8

Changed RL_TX-DIFFFrom: TYP = -14 dB To: TYP = -13 dB in the AC Electrical Characteristics table................................... 9

Changed RL_TX-CMFrom: TYP = -13 dB To: TYP = -11 dB in the AC Electrical Characteristics table .................................... 9

Changed G_LFFrom: MAX = 2.5 dB To: MAX = 1 dB in the AC Electrical Characteristics table ............................................ 9

Changed V_IC, deleted the MIN and MAX values and added TYP = 0 V in the AC Electrical Characteristics table............... 9

Changed the EQ_DPentry in the AC Electrical Characteristics table....................................................................................... 9

Changed V_TX(DC-CM), deleted the MIN and MAX values and added TYP = 1.75 V in the AC Electrical Characteristics table 9

Changed the t_{IDLEExit_DISC}value From: TYP = 10 µs To TYP = 15 ms in the Timing Requirements table............................ 10

Changed the t_{CTL1_DEBOUNCE}value From: MIN = 2 ms To: MIN = 3 ms in the Switching Characteristics table ................... 10

Changes from Original (April 2017) to Revision A

Page

•

Changed SBU1, SBU2, AUXn, and AUXp pin labels on the Sink side of 图 45 .................................................................. 51

Changed SBU1, SBU2, AUXn, and AUXp pin labels on the Sink side of 图 46 .................................................................. 51

3

TUSB544

ZHCSG75E –APRIL 2017–REVISED APRIL 2018

www.ti.com.cn

5 Pin Configuration and Functions

RNQ Package

40-Pin (WQFN)

Top View

VCC

1

28

27

26

25

24

23

22

21

VCC

UEQ1/A1

CFG0

2

3

SBU1

SBU2

CFG1

SWAP

VCC

4

5

6

7

8

AUXn

Thermal

Pad

AUXp

CTL1

SLP_S0#

DIR0

CTL0/SDA

FLIP/SCL

Not to scale

Pin Functions

NAME

VCC

I/O

DESCRIPTION

NO.

1

P

3.3 V Power Supply

This pin along with UEQ0 sets the high-frequency equalizer gain for upstream facing URX1, URX2, UTX1,

UTX2 receivers. Up to 9.4 dB of EQ available. In I²C mode, this pin will also set TUSB544 I²C address.

Refer to 表 10.

2

UEQ1/A1

4 Level I

CFG0. This pin along with CFG1 will select VOD linearity range and DC gain for all the downstream and

upstream channels. Refer to 表 8 for VOD linearity range and DC gain options.

3

4

CFG0

CFG1

4 Level I

CFG1. This pin along with CFG0 will set VOD linearity range and DC gain for all the downstream and

upstream channels. Refer to 表 8 for VOD linearity range and DC gain options.

This pin swaps all the channel directions and EQ settings of downstream facing and upstream facing data

path inputs.

0 – Do not swap channel directions and EQ settings (Default)

1. – Swap channel directions and EQ settings.

5

6

SWAP

VCC

2 Level I

P

3.3V Power Supply

This pin when asserted low will disable Receiver Detect functionality. While this pin is low and TUSB544 is

in U2/U3, TUSB544 will disable LOS and LFPS detection circuitry and RX termination for both channels

will remain enabled. If this pin is low and TUSB544 is in Disconnect state, the RX detect functionality will

be disabled and RX termination for both channels will be disabled.

0 – RX Detect disabled

7

8

SLP_S0#

2 Level I

1 – RX Detect enabled (Default)

This pin along with DIR1 sets the data path signal direction format. Refer to 表 4 for signal direction

formats.

DIR0

2 Level I

9

URX2p

URX2n

Diff I/O

Differential positive input/output for upstream facing RX2 port.

Differential negative input/output for upstream facing RX2 port.

10

This pin along with DIR0 sets the data path signal direction format. Refer to 表 4 for signal direction

formats.

11

DIR1

2 Level I/O

12

13

UTX2p

UTX2n

Diff I/O

Differential positive input/output for upstream facing TX2 port.

Differential negative input/output for upstream facing TX2 port.

4

TUSB544

www.ti.com.cn

ZHCSG75E –APRIL 2017–REVISED APRIL 2018

Pin Functions (continued)

I/O

DESCRIPTION

NO.

NAME

This pin selects I/O voltage levels for the 2-level GPIO configuration pins and the I²C interface:

0 = 3.3-V configuration I/O voltage, 3.3-V I²C interface (Default)

R = 3.3-V configuration I/O voltage, 1.8-V I²C interface

14

VIO_SEL

4 Level I/O

F = 1.8-V configuration I/O voltage, 3.3-V I²C interface

1 = 1.8-V configuration I/O voltage, 1.8-V I²C interface.

15

16

UTX1n

UTX1p

Diff I/O

Differential negative input/output for upstream facing TX1 port.

Differential positive input/output for upstream facing TX1 port.

I²C Programming or Pin Strap Programming Select.

0 = GPIO Mode AUX Snoop enabled (I²C disabled)

R = TI Test Mode (I²C enabled)

F = GPIO Mode, AUX Snoop Disabled (I²C disabled)

1 = I²C enabled.

17

I2C_EN

4 Level I

18

19

20

URX1n

URX1p

VCC

Diff I/O

P

Differential negative input/output for upstream facing RX1 port.

Differential positive input/output for upstream facing RX1 port.

3.3V Power Supply

2 Level I

(Failsafe)

In GPIO mode, this is Flip control pin, otherwise this pin is I²C clock.

21

22

FLIP/SCL

2 Level I

(Failsafe)

In GPIO mode, this is a USB3.1 Switch control pin, otherwise this pin is I²C data.

CTL0/SDA

DP Alt mode Switch Control Pin. In GPIO mode, this pin will enable or disable DisplayPort functionality.

Otherwise DisplayPort functionality is enabled and disabled through I²C registers.

L = DisplayPort Disabled.

H = DisplayPort Enabled.

In I²C mode, this pin is not used by device.

2 Level I

(PD)

23

24

CTL1

AUXp

AUXp. DisplayPort AUX positive I/O connected to the DisplayPort source or sink through an AC coupling

capacitor. In addition to AC coupling capacitor, this pin also requires a 100-kΩ resistor to GND between

the AC coupling capacitor and the AUXp pin if the TUSB544 is used on the DisplayPort source side, or a

1-MΩ resistor to DP_PWR (3.3V) between the AC coupling capacitor and the AUXp pin if TUSB544 is

used on the DisplayPort sink side. This pin along with AUXn is used by the TUSB544 for AUX snooping

and is routed to SBU1/2 based on the orientation of the Type-C plug.

I/O,

CMOS

AUXn. DisplayPort AUX I/O connected to the DisplayPort source or sink through an AC coupling

capacitor. In addition to AC coupling capacitor, this pin also requires a 100-kΩ resistor to DP_PWR (3.3V)

between the AC coupling capacitor and the AUXn pin if the TUSB544 is used on the DisplayPort source

side, or a 1-MΩ resistor to GND between the AC coupling capacitor and the AUXn pin if TUSB544 is used

on the DisplayPort sink side. This pin along with AUXp is used by the TUSB544 for AUX snooping and is

routed to SBU1/2 based on the orientation of the Type-C plug.

I/O,

CMOS

25

AUXn

SBU2. When the TUSB544 is used on the DisplayPort source side, this pin should be DC coupled to the

SBU2 pin of the Type-C receptacle. When the TUSB544 is used on the DisplayPort sink side, this pin

should be DC coupled to the SBU1 pin of the Type-C receptacle. A 2-MΩ resistor to GND is also

recommended.

I/O,

CMOS

26

27

SBU2

SBU1

SBU1. When the TUSB544 is used on the DisplayPort source side, this pin should be DC coupled to the

SBU1 pin of the Type-C receptacle. When the TUSB544 is used on the DisplayPort sink side, this pin

should be DC coupled to the SBU2 pin of the Type-C receptacle. A 2-MΩ resistor to GND is also

recommended.

I/O,

CMOS

28

29

VCC

P

3.3V Power Supply

This pin along with DEQ0 sets the high-frequency equalizer gain for downstream facing DRX1, DRX2,

DTX1, DTX2 receivers.

DEQ1

4 Level I

Up to 11 dB of EQ available.

30

31

DRX1p

DRX1n

Diff I/O

Differential positive input/output for downstream facing RX1 port.

Differential negative input/output for downstream facing RX1 port.

This pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN is low for greater

than t_{CTL1_DEBOUNCE}, all DisplayPort lanes are disabled and AUX to SBU switch will remain closed.

32

HPDIN

2 Level I (PD)

33

34

DTX1p

DTX1n

Diff I/O

Differential positive input/output for downstream facing TX1 port.

Differential negative input/output for downstream facing TX1 port.

This pin along with UEQ1 sets the high-frequency equalizer gain for upstream facing URX1, URX2, UTX1,

UTX2 receivers. Up to 9.4 dB of EQ available. In I²C mode, this pin will also set TUSB544 I²C address.

Refer to 表 10.

35

UEQ0/A0

4 Level I

36

37

DTX2n

DTX2p

Diff I/O

Differential negative input/output for downstream facing TX2 port.

Differential positive input/output for downstream facing TX2 port.

This pin along with DEQ1 sets the high-frequency equalizer gain for downstream facing DRX1, DRX2,

38

DEQ0

4 Level I

DTX1, DTX2 receivers.

Up to 11 dB of EQ available.

5

TUSB544

ZHCSG75E –APRIL 2017–REVISED APRIL 2018

www.ti.com.cn

Pin Functions (continued)

I/O

DESCRIPTION

NO.

39

NAME

DRX2n

Diff I/O

GND

Differential negative input/output for downstream facing RX2 port.

Differential positive input/output for downstream facing RX2 port.

Ground

40

DRX2p

Thermal Pad

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Supply Voltage

V_CC

–0.3

4

V

Differential voltage between positive and

negative inputs

–2.5

2.5

V

Voltage Range at any input or output pin

Voltage at differential inputs

CMOS Inputs

–0.5

V_CC+ 0.5

125

V

Maximum junction temperature, T_J

Storage temperature ,T_STG

°C

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±6

kV

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1500

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

3.6

100

3.6

100

70

UNIT

V

Main power supply

3

3.3

V_CC

Supply ramp requirement

ms

V

V_I2C

Supply that external resistors on SDA and SCL are pulled up to.

Supply Noise on V_CCterminals

1.70

V_PSN

mV

°C

TUSB544

Operating free-air temperature

0

T_A

TUSB544I

–40

85

°C

6

TUSB544

www.ti.com.cn

ZHCSG75E –APRIL 2017–REVISED APRIL 2018

6.4 Thermal Information

TUSB544

THERMAL METRIC⁽¹⁾

RNQ (QFN)

40 PINS

37.6

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

20.7

9.5

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

9.4

R_θJC(bot)

2.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Power Supply Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Link in U0 with GEN1 data transmission.

EQ control pins = NC, K28.5 pattern at 5

Gbps, V_ID= 1000 mV_p-p; VOD Linearity =

900 mV_p-p; CTL1 = L; CTL0 = H

Average active power

USB Only

P_{CC-ACTIVE-USB}

297

mW

Link in U0 with GEN1 data transmission.

EQ control pins = NC, K28.5 pattern at 5

Gbps, V_ID= 1000 mV_p-p; VOD Linearity =

900 mV_p-p; CTL1 = H; CTL0 = H

Average active power

USB + 2 Lane DP

P_{CC-ACTIVE-USB-DP1}

578

mW

Link in U0 with GEN1 data transmission.

EQ control pins = NC, K28.5 pattern at 5

Gbps, V_ID= 1000 mV_p-p; VOD Linearity =

900 mV_p-p; CTL1 = H; CTL0 = H

Average active power

USB + 2 Channel

Custom Alt Mode

P_{CC-ACTIVE-USB-CUSTOM}

Four active DP lanes operating at 8.1

Gbps; EQ control pins = NC, K28.5 pattern

at 5 Gbps, V_ID= 1000 mV_p-p; VOD

Linearity = 900 mV_p-p; CTL1 = H; CTL0 =

L;

Average active power

4 Lane DP Only

P_CC-Active-DP

564

2.5

mW

No GEN1 device is connected to

TXP/TXN; CTL1 = L; CTL0 = H;

P_CC-NC-USB

Average power with no connection

Link in U2 or U3 USB Mode Only; CTL1 =

L; CTL0 = H;

P_CC-U2U3

Average power in U2/U3

Device Shutdown

2.0

mW

P_CC-SHUTDOWN

CTL1 = L; CTL0 = L; I2C_EN = 0;

0.65

6.6 DC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

4-State CMOS Inputs(UEQ[1:0];DEQ[1:0], CFG[1:0], A[1:0], I2C_EN, VIO_SEL)

I_IH

I_IL

High level input current

Low level input current

Threshold 0 / R

V_CC= 3.6 V_IN= 3.6 V

V_CC= 3.6 V; V_IN= 0 V

V_CC= 3.3 V

20

80

µA

V

–160

–40

0.55

1.65

2.7

35

4-Level V_TH

Threshold R/ Float

V_CC= 3.3 V

V

Threshold Float / 1

V_CC= 3.3 V

V

R_PU

R_PD

Internal pull-up resistance

Internal pull-down resistance

kΩ

95

2-State CMOS Input (CTL0, CTL1, FLIP, HPDIN, SLP_S0#, SWAP, DIR[1:0]).

V_IH

V_IL

R_PD

I_IH

High-level input voltage

0.7×V_IO

0

3.6

V

Low-level input voltage

0.3×V_IO

V

Internal pull-down resistance for CTL1

High-level input current

500

kΩ

µA

V_IN= 3.6 V

–25

25

I_IL

Low-level input current

V_IN= GND, V_CC= 3.6 V

I²C Control Pins SCL, SDA

7

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ZHCSG75E –APRIL 2017–REVISED APRIL 2018

www.ti.com.cn

DC Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

V_IH

High-level input voltage

Low-level input voltage

Low-level output voltage

Low-level output current

Input current on SDA pin

Input capacitance

I2C_EN = 0

0.7 x V_I2C

3.6

0.3 x V_I2C

0.4

V_IL

I2C_EN = 0

0

V

V_OL

I_OL

I2C_EN = 0; I_OL= 3 mA

I2C_EN = 0; V_OL= 0.4 V

0.1 x V_I2C< Input voltage < 3.3 V

V

20

mA

µA

pF

I_{I_I2C}

C_{I_I2C}

–10

0.5

10

6.7 AC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

USB Gen 1 Differential Receiver (UTX1P/N, UTX2P/N, DRX1P/N, DRX2P/N)

AC-coupled differential peak-to-peak

signal measured post CTLE through a

reference channel

Input differential peak-peak voltage

swing linear dynamic range

V_RX-DIFF-PP

2000

0

mVpp

Common-mode voltage bias in the

receiver (DC)

V_RX-DC-CM

R_RX-DIFF-DC

R_RX-CM-DC

V

Ω

Present after a GEN1 device is

detected on receiver pins

Differential input impedance (DC)

72

18

120

30

Receiver DC common mode

impedance

Present after a GEN1 device is

detected on receiver pins

Present when no GEN1 device is

detected on receiver pins. Measured

over the range of 0-500mV with

respect to GND.

Common-mode input impedance with

termination disabled (DC)

Z_{RX-HIGH-IMP-DC-POS}

25

kΩ

Input differential peak-to-peak signal

detect assert level

At 5 Gbps, no loss at the input,

PRBS7 pattern

V_{SIGNAL-DET-DIFF-PP}

V_{RX-IDLE-DET-DIFF-PP}

V_{RX-LFPS-DET-DIFF-PP}

80

60

mV

Input differential peak-to-peak signal

detect de-assert Level

At 5 Gbps, no loss at the input,

PRBS7 pattern

Low frequency periodic signaling

(LFPS) detect threshold

Below the minimum is squelched.

100

300

V_RX-CM-AC-P

C_RX

Peak RX AC common-mode voltage

RX input capacitance to GND

Measured at package pin

At 2.5 GHz

150

1

mV

pF

dB

0.5

–16

–14

–13

50 MHz – 1.25 GHz at 90 Ω

2.5 GHz at 90 Ω

RL_RX-DIFF

Differential return Loss

RL_RX-CM

EQ_SS

Common-mode return loss

50 MHz – 2.5 GHz at 90 Ω

Receiver equalization at maximum

setting

UEQ[1:0] and

DEQ[1:0]. at 2.5 GHz

9

dB

USB Gen 1 Differential Transmitter (DTX1P/N, DTX2P/N, URX1P/N, URX2P/N)

V_TX-DIFF-PP

Transmitter dynamic differential voltage swing range.

1600

1.75

mV_PP

mV

V_{TX-RCV-DETECT}

Amount of voltage change allowed during receiver detection

600

Transmitter idle common-mode voltage change while in U2/U3 and not actively

transmitting LFPS

V_{TX-CM-IDLE-DELTA}

V_TX-DC-CM

–600

mV

V

Common-mode voltage bias in the transmitter (DC)

Max mismatch from Txp + Txn for both

Tx AC common-mode voltage active

V_{TX-CM-AC-PP-ACTIVE}

100

10

mV_PP

time and amplitude

AC electrical idle differential peak-to-

At package pins

V_{TX-IDLE-DIFF-AC-PP}

V_{TX-IDLE-DIFF-DC}

0

mV

peak output voltage

DC electrical idle differential output

voltage

At package pins after low pass filter to

remove AC component

14

V_{TX-CM-DC-ACTIVE-IDLE-}Absolute DC common-mode voltage

At package pin

200

between U1 and U0

DELTA

R_TX-DIFF

Differential impedance of the driver

AC coupling capacitor

75

120

265

Ω

C_AC-COUPLING

nF

Measured with respect to AC ground

over

0–500 mV

Common-mode impedance of the

driver

R_TX-CM

18

30

Ω

8

TUSB544

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AC Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

mA

dB

I_TX-SHORT

RL_TX-DIFF

TX short circuit current

TXP/N shorted to GND

50 MHz – 1.25 GHz at 90 Ω

2.5 GHz at 90 Ω

67

–16

–13

–11

Differential return loss

dB

RL_TX-CM

Common-mode return loss

50 MHz – 2.5 GHz at 90 Ω

dB

AC Characteristics

Differential crosstalk between any

signal pairs

Crosstalk

G_LF

at 4.05 GHz

–30

0

dB

at 10 MHz, 200 mV_PP< V_ID

< 2000 mV_PP; 0-dB low-frequency gain

setting

Low frequency voltage gain

–1

1

at 10 MHz, 200 mV_PP< V_ID

< 2000 mV_PP; VOD linearity setting =

1100mV_PP

Low frequency 1-dB compression

point

CP_1dB-LF

1100

1200

mV_PP

at 4.05 GHz, 200 mV_PP< V_ID

< 2000 mV_PP; VOD linearity setting =

1100mV_PP

High frequency 1-dB compression

point

CP_1dB-HF

f_LF

Low frequency cutoff

200 mV_PP< V_ID< 2000 mV_PP

25

50

kHz

200 mV_PP< V_ID< 2000 mV_PP, PRBS7,

5 Gbps

0.05

UIpp

DJ

TJ

TX output deterministic jitter

200 mV_PP< V_ID< 2000 mV_PP, PRBS7,

8.1 Gbps

0.08

UIpp

200 mV_PP< V_ID< 2000 mV_PP, PRBS7,

5 Gbps

TX output total jitter

200 mV_PP< V_ID< 2000 mV_PP, PRBS7,

8.1 Gbps

0.135

DisplayPort Receiver UTX1P/N, UTX2P/N, URX1P/N, URX2P/N

V_{ID_PP}Peak-to-peak input differential dynamic voltage range

V_IC

2000

0

mV_pp

V

Input common mode voltage

C_AC

EQ_DP

d_R

AC coupling capacitance

75

80

200

nF

Receiver equalizer at maximum setting DEQ[1:0],UEQ[1:0] at 4.05 GHz

9.5

100

dB

Data rate

HBR3

8.1

Gbps

Ω

R_ti

Input termination resistance

120

DisplayPort Transmitter DTX1P/N, DTX2P/N, DRX1P/N, DRX2P/N

V_TX-DIFFPP

VOD dynamic range

1500

1.75

mV

mA

V

I_TX-SHORT

TX short circuit current

TXP/N shorted to GND

67

V_TX(DC-CM)

Common-mode voltage bias in the transmitter (DC)

AUXP/N and SBU1/2

V_CC= 3.3 V; V_I= 0 to

R_ON

Output ON resistance

0.4 V for AUXP;

V_I= 2.7 V to 3.6 V for AUXN

5

10

1

Ω

V_CC= 3.3 V; V_I= 0 to

0.4V for AUXP;

V_I= 2.7V to 3.6V for AUXN

ΔR_ON

ON resistance mismatch within pair

ON resistance flatness (R_ONmax –

R_ONmin) measured at identical V_CC

and temperature

V_CC= 3.3 V; V_I= 0 to

0.4V for AUXP;

V_I= 2.7V to 3.6 V for AUXN

R_{ON_FLAT}

2

AUX Channel DC common mode

voltage for AUXP and SBU1.

V_{AUXP_DC_CM}

V_{AUXN_DC_CM}

C_{AUX_ON}

V_CC= 3.3 V

0

0.4

3.6

7

V

AUX Channel DC common mode

voltage for AUXN and SBU2

2.7

V_CC= 3.3V; CTL1 = 1;

V_I= 0V or 3.3V

ON-state capacitance

OFF-state capacitance

4

3

pF

V_CC= 3.3V; CTL1 = 0;

V_I= 0V or 3.3V

C_{AUX_OFF}

6

9

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6.8 Timing Requirements

MIN

NOM

MAX

UNIT

USB Gen 2

t_IDLEEntry

Delay from U0 to electrical idle

See 图 4

10

6

ns

U1 exist time: break in electrical idle to

the transmission of LFPS

t_{IDELExit_U1}

t_{IDLEExit_U2U3}

t_{RXDET_INTVL}

t_{IDLEExit_DISC}

t_{Exit_SHTDN}

t_{DIFF_DLY}

U2/U3 exit time: break in electrical idle to transmission of LFPS

RX detect interval while in Disconnect

Disconnect Exit Time

10

µs

ms

ps

12

15

1

Shutdown Exit Time

Differential Propagation Delay

See 图 3

300

20%-80% of differential

voltage measured 1 inch

from the output pin

t_R,t_F

Output Rise/Fall time (see 图 5)

40

ps

20%-80% of differential

voltage measured 1 inch

from the output pin

t_{RF_MM}

Output Rise/Fall time mismatch

2.6

6.9 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

AUXP/N and SBU1/2

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_{AUX_PD}

Switch propagation delay

400

500

ps

ns

Switching time CTL1 to switch

OFF

t_{AUX_SW_OFF}

Not including t_{CTL1_DEBOUNCE}

t_{AUX_SW_ON}

t_{AUX_INTRA}

Switching time CTL1 to switch ON

Intra-pair output skew

500

100

ns

ps

USB3.1 and DisplayPort mode transition requirement GPIO mode

Min overlap of CTL1 and CTL1 when transitioning from USB 3.1 only

mode to 4-Lane DisplayPort mode or vice versa.

t_{GP_USB_4DP}

4

3

µs

CTL1 and HPDIN

t_{CTL1_DEBOUNCE}

CTL1 and HPDIN debounce time DP Lanes will be disabled if low

ms

when transitioning from H to L.

for greater than min value.

I²C (Refer to 图 1)

f_SCL

t_BUF

I²C clock frequency

1

MHz

µs

Bus free time between START and STOP conditions

0.5

Hold time after repeated START After this period, the first clock

t_HDSTA

0.26

µs

condition.

pulse is generated

t_LOW

t_HIGH

t_SUSTA

t_HDDAT

t_SUDAT

t_R

Low period of the I²C clock

High period of the I²C clock

0.5

0.26

0

µs

μs

ns

μs

pF

Setup time for a repeated START condition

Data hold time

Data setup time

50

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Setup time for STOP condition

Capacitive load for each bus line

120

t_F

20 × (V_I2C/5.5 V)

0.26

t_SUSTO

C_b

100

10

TUSB544

www.ti.com.cn

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70%

30%

SDA

t

F

HDSTA

R

t_HIGH

t

LOW

BUF

70%

30%

SCL

P

S

P

S

t

SUDAT

HDDAT

SUSTO

HDSTA

t

SUSTA

图 1. I²C Timing Diagram Definitions

4us

(min)

CTL1 pin

CTL0 pin

图 2. USB3.1 to 4-Lane DisplayPort in GPIO Mode

IN

T

DIFF_DLY

OUT

图 3. Propagation Delay

11

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ZHCSG75E –APRIL 2017–REVISED APRIL 2018

www.ti.com.cn

IN+

V

Vcm

RX-LFPS-DET-DIFF-PP

IN-

T

IDLEEntry

IDLEExit

OUT+

Vcm

OUT-

图 4. Electrical Idle Mode Exit and Entry Delay

80%

20%

t

r

t

f

图 5. Output Rise and Fall Times

50%

CTL1

OUT

90%

10%

V

T

AUX_SW_ON

T

+ T

CTL1_DEBOUNCE

AUX_SW_OFF

图 6. AUX and SBU Switch ON and OFF Timing Diagram

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6.10 Typical Characteristics

0

-5

0

-5

-10

-15

-20

-25

-30

-35

-40

-45

-10

-15

-20

-25

-30

-35

0

5

10

15

20

0

5

10

15

20

Frequency (GHz)

D001

D002

图 7. Input Return Loss Performance of the Downstream

图 8. Output Return Loss Performance of the Downstream

Ports

0

-5

0

-5

-10

-15

-20

-25

-30

-35

-40

-45

-10

-15

-20

-25

-30

-35

-40

-45

0

5

10

15

20

0

5

10

15

20

Frequency (GHz)

D003

D004

图 9. Input Return Loss Performance of the Upstream Ports

图 10. Output Return Loss Performance of the Upstream

Ports

1800

1600

1400

1200

1000

1800

1600

1400

1200

1000

800

600

400

200

0

EQ 0

EQ 2

EQ 4

EQ 6

EQ 8

EQ 10

EQ 12

EQ 15

EQ 0

EQ 2

EQ 4

EQ 6

EQ 8

EQ 10

EQ 12

EQ 15

800

600

400

200

0

200 400 600 800 1000 1200 1400 1600 1800 2000

0

200 400 600 800 1000 1200 1400 1600 1800 2000

Differential Input Voltage (mVpp)

D010

D008

2.5 GHz

4.05 GHz

图 11. Downstream-to-Upstream Linearity Performance at

图 12. Downstream-to-Upstream Linearity Performance at

2.5 GHz

4.05 GHz

13

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Typical Characteristics (接下页)

1600

1400

1200

1000

800

600

400

200

0

1800

1600

1400

1200

1000

800

600

400

200

0

EQ 0

EQ 2

EQ 4

EQ 6

EQ 8

EQ 10

EQ 12

EQ 15

EQ 0

0

200 400 600 800 1000 1200 1400 1600 1800 2000

0

200 400 600 800 1000 1200 1400 1600 1800 2000

Differential Input Voltage (mVpp)

D009

D010

100 MHz

2.5 GHz

图 13. Downstream-to-Upstream Linearity Performance at

图 14. Upstream-to-Downstream Linearity Performance at

100 MHz

2.5 GHz

1600

1400

1200

1000

1600

1400

1200

1000

800

EQ 0

EQ 2

EQ 4

600

EQ 6

EQ 8

EQ 10

EQ 12

EQ 15

400

200

0

400

200

EQ 0

0

200 400 600 800 1000 1200 1400 1600 1800 2000

0

200 400 600 800 1000 1200 1400 1600 1800 2000

Differential Input Voltage (mVpp)

D011

D012

4.05 GHz

100 MHz

图 15. Upstream-to-Downstream Linearity Performance at

图 16. Upstream-to-Downstream Linearity Performance at

4.05 GHz

100 MHz

Source

Data Rate: 8.1 Gbps

Data Pattern: PRBS7

Swing: 1 Vpp

Source

Data Rate: 5 Gbps

Swing: 1 Vpp

Data Pattern: PRBS7

Channel

Settings

Upstream-to-Downstream, 12 in 6 mil Input PCB

Channel

EQ Setting: 7 DC Gain Setting: 0 dB

Linear Range Setting: 1100 mVpp

Channel

Settings

Upstream-to-Downstream, 12 in 6 mil Input PCB

Channel

EQ Setting: 7

DC Gain Setting: 0 dB

Linear Range Setting: 1100 mVpp

图 18. Output Eye-Pattern Performance at 8.1 Gbps

图 17. Output Eye-Pattern Performance at 5 Gbps

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Typical Characteristics (接下页)

15

EQ0

EQ1

EQ2

EQ3

EQ4

EQ5

EQ6

EQ7

EQ8

EQ9

EQ10

EQ11

EQ12

EQ13

EQ14

EQ15

10

5

0

-5

-10

0.01

0.1

1

10

20

Frequency (GHz)

D005

图 19. Upstream-to-Downstream EQ Settings Curves

15

10

5

EQ0

EQ1

EQ2

EQ3

EQ4

EQ5

EQ6

EQ7

EQ8

EQ9

EQ10

EQ11

EQ12

EQ13

EQ14

EQ15

0

-5

-10

0.01

0.1

1

10

20

Frequency (GHz)

D006

图 20. Downstream-to-Upstream EQ Settings Curves

15

TUSB544

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www.ti.com.cn

7 Detailed Description

7.1 Overview

The TUSB544 is a USB Type-C Alt Mode redriver switch supporting data rates up to 8.1 Gbps. This device

implements 5th generation USB redriver technology. The device is utilized for configurations C, D, E, and F from

the VESA DisplayPort Alt Mode on USB Type-C Standard. It can also be configured to support custom USB

Type-C alternate modes.

The TUSB544 provides several levels of receive equalization to compensate for cable and board trace loss due

to inter-symbol interference (ISI) when USB 3.1 Gen 1 or DisplayPort (or other Alt modes) signals travel across a

PCB or cable. This device requires a 3.3V power supply. It comes for both commercial temperature range and

industrial temperature range operation.

For host (source) or device (sink) applications the TUSB544 enables the system to pass both transmitter

compliance and receiver jitter tolerance tests for USB 3.1 Gen 1 and DisplayPort version 1.4 HBR3. The re-driver

recovers incoming data by applying equalization that compensates for channel loss, and drives out signals with a

high differential voltage. Each channel has a receiver equalizer with selectable gain settings. Equalization control

for upstream and downstream facing ports can be set using UEQ[1:0], and DEQ[1:0] pins respectively or through

the I²C interface.

Moreover, the CFG[1:0] or the equivalent I²C registers provide the ability to control the EQ DC gain and the

voltage linearity range for all the channels (Refer to 表 8). This flexible control makes it easy to set up the device

to pass various standard compliance requirements.

The TUSB544 advanced state machine makes it transparent to hosts and devices. After power up, the

TUSB544. periodically performs receiver detection on the TX pairs. If it detects a USB 3.1 Gen 1 receiver, the

RX termination is enabled, and the TUSB544 is ready to re-drive.

The TUSB544 provides extremely flexible data path signal direction control using the CTL[1:0], FLIP, DIR[1:0],

and SWAP pins or through the I²C interface. Refer to 表 4 for detailed information on the input to output signal

pin mapping.

The device ultra-low-power architecture operates at a 3.3 V power supply and achieves enhanced performance.

The automatic LFPS De-Emphasis control further enables the system to be USB 3.1 compliant.

16

TUSB544

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7.2 Functional Block Diagram

DRX2EQ_SEL

Driver

EQ

URX2EQ_SEL

URX2p

CHANNEL 0

URX2n

DRX2p

DRX2n

Driver

EQ

CHANNEL 0

DTX2EQ_SEL

DTX1EQ_SEL

DRX1EQ_SEL

Driver

EQ

UTX2EQ_SEL

UTX2p

DTX2p

DTX2n

Driver

EQ

CHANNEL 1

CHANNEL 2

UTX2n

Driver

EQ

UTX1EQ_SEL

UTX1n

CHANNEL 2

UTX1p

DTX1n

DTX1p

Driver

EQ

Driver

EQ

URX1EQ_SEL

URX1n

CHANNEL 3

URX1p

DRX1n

DRX1p

Driver

EQ

CHANNEL 3

DTX[2:1]EQ_SEL

DRX[2:1]EQ_SEL

UTX[2:1]EQ_SEL

URX[2:1]EQ_SEL

UEQ1/A1

UEQ0/A0

I2C_EN

DEQ[1:0]

SWAP

DIR[1:0]

FSM, Control Logic &

Registers

FLIP/SCL

CTL0/SDA

CTL1

I2C

Slave

SLP_S0#

VIO_SEL

CFG[1:0]

M

U

X

SBU1

SBU2

AUXp

AUXn

VREG

VCC

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7.3 Feature Description

7.3.1 USB 3.1

The TUSB544 supports USB 3.1 data rates up to 5 Gbps. The TUSB544 supports all the USB defined power

states (U0, U1, U2, and U3). Because the TUSB544 is a linear redriver, it can’t decode USB3.1 physical layer

traffic. The TUSB544 monitors the actual physical layer conditions like receiver termination, electrical idle, LFPS,

and SuperSpeed signaling rate to determine the USB power state of the USB3.1 interface.

The TUSB544 features an intelligent low frequency periodic signaling (LFPS) detector. The LFPS detector

automatically senses the low frequency signals and disables receiver equalization functionality. When not

receiving LFPS, the TUSB544 will enable receiver equalization based on the UEQ[1:0] and DEQ[1:0] pins or

values programmed into UEQ[3:0]_SEL, and DEQ[3:0]_SEL registers.

7.3.2 DisplayPort

The TUSB544 supports up to 4 DisplayPort lanes at data rates up to 8.1Gbps (HBR3). The TUSB544, when

configured in DisplayPort mode, monitors the native AUX traffic as it traverses between DisplayPort source and

DisplayPort sink. For the purposes of reducing power, the TUSB544 will manage the number of active

DisplayPort lanes based on the content of the AUX transactions. The TUSB544 snoops native AUX writes to

DisplayPort sink’s DPCD registers 00101h (LANE_COUNT_SET) and 00600h (SET_POWER_STATE).

TUSB544 will disable/enable lanes based on value written to LANE_COUNT_SET. The TUSB544 will disable all

lanes when SET_POWER_STATE is in the D3. Otherwise active lanes will be based on value of

LANE_COUNT_SET.

DisplayPort AUX snooping is enabled by default but can be disabled by changing the AUX_SNOOP_DISABLE

register. Once AUX snoop is disabled, management of TUSB544’s DisplayPort lanes are controlled through

various configuration registers.

7.3.3 4-Level Inputs

The TUSB544 has (I2C_EN, UEQ[1:0], DEQ[1:0], CFG[1:0], and A[1:0]) 4-level inputs pins that are used to

control the equalization gain, voltage linearity range, and place TUSB544 into different modes of operation.

These 4-level inputs utilize a resistor divider to help set the 4 valid levels and provide a wider range of control

settings. There are internal pull-up and a pull-down resisters. These resistors together with the external resistor

connection combine to achieve the desired voltage level.

表 1. 4-Level Control Pin Settings

LEVEL

SETTINGS

Option 1: Tie 1 KΩ 5% to GND.

Option 2: Tie directly to GND.

0

R

F

Tie 20 KΩ 5% to GND.

Float (leave pin open)

Option 1: Tie 1 KΩ 5%to V_CC

.

1

Option 2: Tie directly to V_CC

.

注

All four-level inputs are latched on rising edge of internal reset. After T_{cfg_hd}, the internal

pull-up and pull-down resistors will be isolated in order to save power.

7.3.4 Receiver Linear Equalization

The purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference in

the system. The receiver overcomes these losses by attenuating the low frequency components of the signals

with respect to the high frequency components. The proper gain setting should be selected to match the channel

insertion loss. Two 4-level input pins enable up to 16 possible equalization settings. The upstream path, and the

downstream path each have their own two 4-level inputs for equalization settings; UEQ[1:0] and DEQ[1:0]

respectively. The TUSB544 also provides the flexibility of adjusting equalization settings through I²C registers

URX[2:1]EQ_SEL, UTX[2:1]EQ_SEL, DRX[2:1]EQ_SEL, and DTX[2:1]EQ_SEL for each individual channel and

for each direction (upstream or downstream) .

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7.4 Device Functional Modes

7.4.1 Device Configuration in GPIO Mode

The TUSB544 is in GPIO configuration when I2C_EN = “0” or "F". The TUSB544 supports operational

combinations with USB and two different Type-C Alternate Modes.. One combination includes USB and Alternate

Mode DisplayPort, and the other combination includes USB and custom Alternate Mode. For each operational

combination the data path directions can be further set using the DIR[1:0] pins or through I2C to enable the

device to operate in the source or sink sides. Please refer to 表 2 for all the configuration of all the operational

modes.

When the device is set to operate in a USB and Alternate Mode DisplayPort the following configurations can be

further set: USB3.1 only, 2 DisplayPort lanes + USB3.1, or 4 DisplayPort lanes (no USB3.1). The CTL1 pin

controls whether DisplayPort is enabled. The combination of CTL1 and CTL0 selects between USB3.1 only, 2

lanes of DisplayPort, or 4-lanes of DisplayPort as detailed in 表 2. The AUXP/N to SBU1/2 mapping is controlled

based on 表 3..

When the device is set to operate in a USB and custom Alternate Mode the following configurations can be

further set: USB3.1 only, 2 Channels of custom Alternate Mode + USB3.1, or 4 Channels of custom Alternate

Mode (no USB3.1). The CTL1 pin controls whether custom Alternate Mode is enabled. The combination of CTL1

and CTL0 selects between USB3.1 only, 2 channels of custom Alternate Mode, or 4 channels of custom

Alternate Mode as detailed in 表 2. The AUXP/N to SBU1/2 mapping is controlled based on 表 3.

Further data path direction control can be achieved using the SWAP pin. When set high, the SWAP pin reverses

the data path direction on all the channels and swaps the equalization settings of the upstream and downstream

facing input ports. This pin may be found useful in active cable application with TUSB544 installed on only one

end. The SWAP pin can be set based on which cable end is plugged to the source or sink side receptacle

After power-up (VCC from 0 V to 3.3 V), the TUSB544 will default to USB3.1 mode. The USB PD controller,

upon detecting no device attached to Type-C port or USB3.1 operation not required by attached device, must

take TUSB544 out of USB3.1 mode by transitioning the CTL0 pin from L to H and back to L.

表 2. GPIO Configuration Control

VESA DisplayPort ALT

MODE

DFP_D Configuration

DIR1

DIR0

CTL1

CTL0

FLIP

TUSB544 CONFIGURATION

USB + DisplayPort Alternate Mode (Source Side)

L

H

L

Power Down

—

Power Down

L

H

L

One Port USB 3.1 - No Flip

One Port USB 3.1 – With Flip

4 Lane DP - No Flip

—

L

H

L

—

H

C and E

L

H

4 Lane DP – with Flip

One Port USB 3.1 + 2 Lane DP- No

Flip

L

H

L

D and F

One Port USB 3.1 + 2 Lane DP– with

Flip

H

USB + DisplayPort Alternate Mode (Sink Side)

L

H

L

H

L

Power Down

–

Power Down

–

L

H

L

One Port USB 3.1 - No Flip

One Port USB 3.1 – With Flip

4 Lane DP - No Flip

4 Lane DP – With Flip

–

L

H

L

–

H

C and E

L

H

One Port USB 3.1 + 2 Lane DP- No

Flip

L

H

L

D and F

One Port USB 3.1 + 2 Lane DP– With

Flip

H

19

TUSB544

ZHCSG75E –APRIL 2017–REVISED APRIL 2018

www.ti.com.cn

Device Functional Modes (接下页)

表 2. GPIO Configuration Control (接下页)

VESA DisplayPort ALT

MODE

DFP_D Configuration

DIR1

DIR0

CTL1

CTL0

FLIP

TUSB544 CONFIGURATION

USB + Custom Alternate Mode (Source Side)

H

L

H

L

Power Down

–

L

H

L

H

L

One Port USB 3.1 - No Flip

One Port USB 3.1 – With Flip

4 Channel Custom Alt Mode - No Flip

H

L

4 Channel Custom Alt Mode– With

Flip

H

L

H

L

H

L

–

One Port USB 3.1 + 2 Channel

Custom Alt Mode- No Flip

H

One Port USB 3.1 + 2 Channel

Custom Alt Mode – With Flip

H

USB + Custom Alternate Mode (Sink Side)

H

L

H

L

Power Down

-

L

H

L

H

L

One Port USB 3.1 - No Flip

One Port USB 3.1 – With Flip

4 Channel Custom Alt Mode - No Flip

H

L

4 Channel Custom Alt Mode– With

Flip

H

L

H

L

-

One Port USB 3.1 + 2 Channel

Custom Alt Mode- No Flip

H

One Port USB 3.1 + 2 Channel

Custom Alt Mode – With Flip

H

表 3. GPIO AUXP/N to SBU1/2 Mapping

CTL1 pin

FLIP pin

Mapping

AUXP -> SBU1

AUXN -> SBU2

H

L

AUXP -> SBU2

AUXN -> SBU1

H

X

L > 2ms

Open

20

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ZHCSG75E –APRIL 2017–REVISED APRIL 2018

details the TUSB544 mux routing. This table is valid for GPIO mode. This table is also valid for I²C mode for the

case where CH_SWAP_SEL = 4'b0000 or 4'b1111.

表 4. INPUT to OUTPUT Mapping

SWAP = L

From

SWAP = H

From

To

From

To

Rx EQ

Control

PINS

Rx EQ

Control

PINS

DIR1

DIR0 CTL1

PIN PIN

CTL0

FLIP

Input

Output

Input

Output

USB + DisplayPort Alternate Mode (Source Side)

L

NA

H

URX1P

(SSRXP)

URX1P

(SSTXP)

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DRX1P

DRX1N

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DRX1P

DRX1N

URX1N

(SSRXN)

URX1N

(SSTXN)

L

H

L

UTX1P

(SSTXP)

UTX1P

(SSRXP)

DTX1P

DTX1N

DTX1P

DTX1N

UTX1N

(SSTXN)

UTX1N

(SSRXN)

URX2P

(SSRXP)

URX2P

(SSTXP)

DRX2P

DRX2N

DRX2P

DRX2N

URX2N

(SSRXN)

URX2N

(SSTXN)

L

H

UTX2P

(SSTXP)

UTX2P

(SSRXP)

DTX2P

DTX2N

DRX2P

DRX2N

DTX2P

DTX2N

DTX1P

DTX1N

DRX1P

DRX1N

DTX2P

DTX2N

DRX2P

DRX2N

DTX2P

DTX2N

DTX1P

DTX1N

DRX1P

DRX1N

UTX2N

(SSTXN)

UTX2N

(SSRXN)

URX2P

(DP0P)

URX2P

(DP0P)

URX2N

(DP0N)

URX2N

(DP0N)

UTX2P

(DP1P)

UTX2P (DP1P)

UTX2N

(DP1N)

UTX2N

(DP1N)

L

H

L

UTX1P

(DP2P)

UTX1P (DP2P)

UTX1N

(DP2N)

UTX1N

(DP2N)

URX1P

(DP3P)

URX1P

(DP3P)

URX1N

(DP3N)

URX1N

(DP3N)

21

TUSB544

ZHCSG75E –APRIL 2017–REVISED APRIL 2018

www.ti.com.cn

表 4. INPUT to OUTPUT Mapping (接下页)

SWAP = L

SWAP = H

From

To

From

To

Rx EQ

Control

PINS

Rx EQ

Control

PINS

DIR1

DIR0 CTL1

CTL0

FLIP

Input

Output

Input

Output

URX1P

(DP0P)

URX1P

(DP0P)

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DRX1P

DRX1N

DTX1P

DTX1N

DTX2P

DTX2N

DRX2P

DRX2N

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DRX1P

DRX1N

DTX1P

DTX1N

DTX2P

DTX2N

DRX2P

DRX2N

URX1N

(DP0N)

URX1N

(DP0N)

UTX1P

(DP1P)

UTX1P (DP1P)

UTX1N

(DP1N)

UTX1N

(DP1N)

L

H

L

H

UTX2P

(DP2P)

UTX2P (DP2P)

UTX2N

(DP2N)

UTX2N

(DP2N)

URX2P

(DP3P)

URX2P

(DP3P)

URX2N

(DP3N)

URX2N

(DP3N)

URX1P

(SSRXP)

URX1P

(SSTXP)

DRX1P

DRX1N

DRX1P

DRX1N

URX1N

(SSRXN)

URX1N

(SSTXN)

UTX1P

(SSTXP)

UTX1P

(SSRXP)

DTX1P

DTX1N

DRX2P

DRX2N

DTX2P

DTX2N

DTX1P

DTX1N

DRX2P

DRX2N

DTX2P

DTX2N

UTX1N

(SSTXN)

UTX1N

(SSRXN)

L

H

L

URX2P

(DP0P)

URX2P

(DP0P)

URX2N

(DP0N)

URX2N

(DP0N)

UTX2P

(DP1P)

UTX2P (DP1P)

UTX2N

(DP1N)

UTX2N

(DP1N)

URX2P

(SSRXP)

URX2P

(SSTXP)

DRX2P

DRX2N

DRX2P

DRX2N

URX2N

(SSRXN)

URX2N

(SSTXN)

UTX2P

(SSTXP)

UTX2P

(SSRXP)

DTX2P

DTX2N

DRX1P

DRX1N

DTX1P

DTX1N

DTX2P

DTX2N

DRX1P

DRX1N

DTX1P

DTX1N

UTX2N

(SSTXN)

UTX2N

(SSRXN)

L

H

URX1P

(DP0P)

URX1P

(DP0P)

URX1N

(DP0N)

URX1N

(DP0N)

UTX1P

(DP1P)

UTX1P (DP1P)

UTX1N

(DP1N)

UTX1N

(DP1N)

USB + DisplayPort Alternate Mode (Sink Side)

L

H

L

NA

H

22

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ZHCSG75E –APRIL 2017–REVISED APRIL 2018

表 4. INPUT to OUTPUT Mapping (接下页)

SWAP = L

SWAP = H

From

To

From

To

Rx EQ

Control

PINS

Rx EQ

Control

PINS

DIR1

DIR0 CTL1

CTL0

FLIP

Input

Output

Input

Output

DTX2P

(SSRXP)

DTX2P

(SSTXP)

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

UTX2P

UTX2N

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

UTX2P

UTX2N

DTX2N

(SSRXN)

DTX2N

(SSTXN)

L

H

L

H

L

DRX2P

(SSTXP)

DRX2P

(SSRXP)

URX2P

URX2N

URX2P

URX2N

DRX2N

(SSTXN)

DRX2N

(SSRXN)

DTX1P

(SSRXP)

DTX1P

(SSTXP)

UTX1P

UTX1N

UTX1P

UTX1N

DTX1N

(SSRXN)

DTX1N

(SSTXN)

L

H

L

H

DRX1P

(SSTXP)

DRX1P

(SSRXP)

URX1P

URX1N

URX1P

URX1N

DRX1N

(SSTXN)

DRX1N

(SSRXN)

DRX2P

(DP3P)

DRX2P

(DP3P)

URX2P

URX2N

UTX2P

UTX2N

UTX1P

UTX1N

URX1P

URX1N

UTX1P

UTX1N

UTX2P

UTX2N

URX2P

URX2N

URX2P

URX2N

UTX2P

UTX2N

UTX1P

UTX1N

URX1P

URX1N

URX1P

URX1N

UTX1P

UTX1N

UTX2P

UTX2N

URX2P

URX2N

DRX2N

(DP3N)

DRX2N

(DP3N)

DTX2P

(DP2P)

DTX2P

(DP2P)

DTX2N

(DP2N)

DTX2N

(DP2N)

L

H

L

DTX1P

(DP1P)

DTX1P

(DP1P)

DTX1N

(DP1N)

DTX1N

(DP1N)

DRX1P

(DP0P)

DRX1P

(DP0P)

DRX1N

(DP0P)

DRX1N

(DP0N)

DRX1P

(DP3P)

DRX1P

(DP3P)

DRX1N

(DP3N)

DRX1N

(DP3N)

DTX1P

(DP2P)

DTX1P

(DP2P)

DTX1N

(DP2N)

DTX1N

(DP2N)

L

H

L

H

DTX2P

(DP1P)

DTX2P

(DP1P)

DTX2N

(DP1N)

DTX2N

(DP1N)

DRX2P

(DP0P)

DRX2P

(DP0P)

DRX2N

(DP0N)

DRX2N

(DP0N)

23

TUSB544

ZHCSG75E –APRIL 2017–REVISED APRIL 2018

www.ti.com.cn

表 4. INPUT to OUTPUT Mapping (接下页)

SWAP = L

SWAP = H

From

To

From

To

Rx EQ

Control

PINS

Rx EQ

Control

PINS

DIR1

DIR0 CTL1

CTL0

FLIP

Input

Output

Input

Output

DRX2P

(SSRXP)

DRX2P

(SSRXP)

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

URX2P

URX2N

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

URX2P

URX2N

DRX2N

(SSRXN)

DRX2N

(SSRXN)

DTX2P

(SSTXP)

DTX2P

(SSTXP)

UTX2P

UTX2N

URX1P

URX1N

UTX1P

UTX1N

UTX2P

UTX2N

URX1P

URX1N

UTX1P

UTX1N

DTX2N

(SSTXN)

DTX2N

(SSTXN)

L

H

L

DRX1P

(DP0P)

DRX1P

(DP0P)

DRX1N

(DP0N)

DRX1N

(DP0N)

DTX1P

(DP1P)

DTX1P

(DP1P)

DTX1N

(DP1N)

DTX1N

(DP1N)

DRX1P

(SSRXP)

DRX1P

(SSRXP)

URX1P

URX1N

URX1P

URX1N

DRX1N

(SSRXN)

DRX1N

(SSRXN)

DTX1P

(SSTXP)

DTX1P

(SSTXP)

UTX1P

UTX1N

URX2P

URX2N

UTX2P

UTX2N

UTX1P

UTX1N

URX2P

URX2N

UTX2P

UTX2N

DTX1N

(SSTXN)

DTX1N

(SSTXN)

L

H

DRX2P

(DP0P)

DRX2P

(DP0P)

DRX2N

(DP0N)

DRX2N

(DP0N)

DTX2P

(DP1P)

DTX2P

(DP1P)

DTX2N

(DP1N)

DTX2N

(DP1N)

USB + Custom Alternate Mode (Source Side)

H

L

NA

H

URX1P

(SSRXP)

URX1P

(SSTXP)

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DRX1P

DRX1N

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DRX1P

DRX1N

URX1N

(SSRXN)

URX1N

(SSTXN)

H

L

H

L

UTX1P

(SSTXP)

UTX1P

(SSRXP)

DTX1P

DTX1N

DTX1P

DTX1N

UTX1N

(SSTXN)

UTX1N

(SSRXN)

URX2P

(SSRXP)

URX2P

(SSTXP)

DRX2P

DRX2N

DRX2P

DRX2N

URX2N

(SSRXN)

URX2N

(SSTXN)

H

L

H

UTX2P

(SSTXP)

UTX2P

(SSRXP)

DTX2P

DTX2N

DTX2P

DTX2N

UTX2N

(SSTXN)

UTX2N

(SSRXN)

24

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ZHCSG75E –APRIL 2017–REVISED APRIL 2018

表 4. INPUT to OUTPUT Mapping (接下页)

SWAP = L

SWAP = H

From

To

From

To

Rx EQ

Control

PINS

Rx EQ

Control

PINS

DIR1

DIR0 CTL1

CTL0

FLIP

Input

Output

Input

Output

URX2P

(LN1RXP)

URX2P

(LN1RXP)

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

DRX2P

DRX2N

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

DRX2P

DRX2N

URX2N

(LN1RXN)

URX2N

(LN1RXN)

UTX2P

(LN1TXP)

UTX2P

(LN1TXP)

DTX2P

DTX2N

DTX1P

DTX1N

DTX2P

DTX2N

DTX1P

DTX1N

UTX2N

(LN1TXN)

UTX2N

(LN1TXN)

H

L

H

L

UTX1P

(LN0TXP)

UTX1P

(LN0TXP)

UTX1N

(LN0TXN)

UTX1N

(LN0TXN)

URX1P

(LN0RXP)

URX1P

(LN0RXP)

DRX1P

DRX1N

DRX1P

DRX1N

DRX1P

DRX1N

DRX1P

DRX1N

URX1N

(LN0RXN)

URX1N

(LN0RXN)

URX1P

(LN1RXP)

URX1P

(LN1RXP)

URX1N

(LN1RXN)

URX1N

(LN1RXN)

UTX1P

(LN1TXP)

UTX1P

(LN1TXP)

DTX1P

DTX1N

DTX2P

DTX2N

DTX1P

DTX1N

DTX2P

DTX2N

H

L

H

L

H

UTX1N

(LN1TXN)

UTX1N

(LN1TXN)

UTX2P

(LN0TXP)

UTX2P

(LN0TXP)

UTX2N

(LN0TXN)

UTX2N

(LN0TXN)

URX2P

(LN0RXP)

URX2P

(LN0RXP)

DRX2P

DRX2N

DRX1P

DRX1N

DRX2P

DRX2N

DRX1P

DRX1N

URX2N

(LN0RXN)

URX2N

(LN0RXN)

URX1P

(SSRXP)

URX1P

(SSTXP)

URX1N

(SSRXN)

URX1N

(SSTXN)

UTX1P

(SSTXP)

UTX1P

(SSRXP)

DTX1P

DTX1N

DTX2P

DTX2N

DTX1P

DTX1N

DTX2P

DTX2N

H

L

H

L

UTX1N

(SSTXN)

UTX1N

(SSRXN)

UTX2P

(LN0TXP)

UTX2P

(LN0TXP)

UTX2N

(LN0TXN)

UTX2N

(LN0TXN)

URX2P

(LN0RXP)

URX2P

(LN0RXP)

DRX2P

DRX2N

DRX2P

DRX2N

URX2N

(LN0RXN)

URX2N

(LN0RXN)

25

TUSB544

ZHCSG75E –APRIL 2017–REVISED APRIL 2018

www.ti.com.cn

表 4. INPUT to OUTPUT Mapping (接下页)

SWAP = L

SWAP = H

From

To

From

To

Rx EQ

Control

PINS

Rx EQ

Control

PINS

DIR1

DIR0 CTL1

CTL0

FLIP

Input

Output

Input

Output

URX2P

(SSRXP)

URX2P

(SSTXP)

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

DRX2P

DRX2N

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

DRX2P

DRX2N

URX2N

(SSRXN)

URX2N

(SSTXN)

UTX2P

(SSTXP)

UTX2P

(SSRXP)

DTX2P

DTX2N

DTX1P

DTX1N

DTX2P

DTX2N

DTX1P

DTX1N

UTX2N

(SSTXN)

UTX2N

(SSRXN)

H

L

H

UTX1P

(LN0TXP)

UTX1P

(LN0TXP)

UTX1N

(LN0TXN)

UTX1N

(LN0TXN)

URX1P

(LN0RXP)

URX1P

(LN0RXP)

DRX1P

DRX1N

DRX1P

DRX1N

URX1N

(LN0RXN)

URX1N

(LN0RXN)

USB + Custom Alternate Mode (Sink Side)

H

L

NA

H

DTX2P

(SSRXP)

DTX2P

(SSTXP)

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UTX2P

UTX2N

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UTX2P

UTX2N

DTX2N

(SSRXN)

DTX2N

(SSTXN)

H

L

H

L

DRX2P

(SSTXP)

DRX2P

(SSRXP)

URX2P

URX2N

URX2P

URX2N

DRX2N

(SSTXN)

DRX2N

(SSRXN)

DTX1P

(SSRXP)

DTX1P

(SSTXP)

UTX1P

UTX1N

UTX1P

UTX1N

DTX1N

(SSRXN)

DTX1N

(SSTXN)

H

L

H

DRX1P

(SSTXP)

DRX1P

(SSRXP)

URX1P

URX1N

URX1P

URX1N

DRX1N

(SSTXN)

DRX1N

(SSRXN)

URX2P

(LN1TXP)

URX2P

(LN1TXP)

DRX2P

DRX2N

DRX2P

DRX2N

URX2N

(LN1TXN)

URX2N

(LN1TXN)

UTX2P

(LN1RXP)

UTX2P

(LN1RXP)

DTX2P

DTX2N

DTX1P

DTX1N

DTX2P

DTX2N

DTX1P

DTX1N

UTX2N

(LN1RXN)

UTX2N

(LN1RXN)

H

L

UTX1P

(LN0RXP)

UTX1P

(LN0RXP)

UTX1N

(LN0RXN)

UTX1N

(LN0RXN)

URX1P

(LN0RXP)

URX1P

(LN0RXP)

DRX1P

DRX1N

DRX1P

DRX1N

URX1N

(LN0RXN)

URX1N

(LN0RXN)

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表 4. INPUT to OUTPUT Mapping (接下页)

SWAP = L

SWAP = H

From

To

From

To

Rx EQ

Control

PINS

Rx EQ

Control

PINS

DIR1

DIR0 CTL1

CTL0

FLIP

Input

Output

Input

Output

URX2P

(LN0RXP)

URX2P

(LN0RXP)

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DRX2P

DRX2N

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DEQ[1:0]

UEQ[1:0]

DRX2P

DRX2N

URX2N

(LN0RXN)

URX2N

(LN0RXN)

UTX2P

(LN0RXP)

UTX2P

(LN0RXP)

DTX2P

DTX2N

DTX1P

DTX1N

DTX2P

DTX2N

DTX1P

DTX1N

UTX2N

(LN0RXN)

UTX2N

(LN0RXN)

H

L

H

UTX1P

(LN0RXP)

UTX1P

(LN0RXP)

UTX1N

(LN0RXN)

UTX1N

(LN0RXN)

URX1P

(LN0TXP)

URX1P

(LN0TXP)

DRX1P

DRX1N

UTX2P

UTX2N

DRX1P

DRX1N

UTX2P

UTX2N

URX1N

(LN0TXN)

URX1N

(LN0TXN)

DTX2P

(SSRXP)

DTX2P

(SSTXP)

DTX2N

(SSRXN)

DTX2N

(SSTXN)

DRX2P

(SSTXP)

DRX2P

(SSRXP)

URX2P

URX2N

URX2P

URX2N

DRX2N

(SSTXN)

DRX2N

(SSRXN)

H

L

DTX1P

(LN0RXP)

DTX1P

(LN0RXP)

UTX1P

UTX1N

UTX1P

UTX1N

DTX1N(LN0R

XN)

DTX1N(LN0R

XN)

DRX1P

(LN0TXP)

DRX1P

(LN0TXP)

URX1P

URX1N

URX1P

URX1N

DRX1N

(LN0TXN)

DRX1N

(LN0TXN)

DTX1P

(SSRXP)

DTX1P

(SSSXP)

UTX1P

UTX1N

UTX1P

UTX1N

DTX1N

(SSRXN)

DTX1N

(SSSXN)

DRX1P

(SSTXP)

DRX1P

(SSRXP)

URX1P

URX1N

URX1P

URX1N

DRX1N

(SSTXN)

DRX1N

(SSRXN)

H

URX2P

(LN0TXP)

URX2P

(LN0TXP)

DRX2P

DRX2N

DRX2P

DRX2N

URX2N

(LN0TXN)

URX2N

(LN0TXN)

UTX2P

(LN0RXP)

UTX2P

(LN0RXP)

DTX2P

DTX2N

DTX2P

DTX2N

UTX2N

(LN0RXN)

UTX2N

(LN0RXN)

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7.4.2 Device Configuration in I²C Mode

The TUSB544 is in I²C mode when I2C_EN is equal to “1”. The same configurations defined in GPIO mode are

also available in I²C mode. The TUSB544’s USB3.1, DisplayPort, and custom Alternate Mode configuration is

controlled based on 表 5. The AUXP/N to SBU1/2 mapping control is based on 表 5.

表 5. I²C Configuration Control

Registers

CTLSEL1

VESA DisplayPort Alt Mode

DFP_D Configuration

TUSB544 Configuration

DIRSEL1

DIRSEL0

CTLSEL0

FLIPSEL

USB + DisplayPort Alternate Mode (Source Side)

L

H

L

Power Down

–

Power Down

–

L

H

L

One Port USB 3.1 - No Flip

One Port USB 3.1 – With Flip

4 Lane DP - No Flip

4 Lane DP – With Flip

–

L

H

L

–

H

C and E

L

H

One Port USB 3.1 + 2 Lane

DP- No Flip

L

H

L

D and F

One Port USB 3.1 + 2 Lane

DP– With Flip

H

USB + DisplayPort Alternate Mode (Sink Side)

L

H

L

H

L

Power Down

–

Power Down

–

L

H

L

One Port USB 3.1 - No Flip

One Port USB 3.1 – With Flip

4 Lane DP - No Flip

4 Lane DP – With Flip

–

L

H

L

–

H

C and E

L

H

One Port USB 3.1 + 2 Lane

DP- No Flip

L

H

L

D and F

One Port USB 3.1 + 2 Lane

DP– With Flip

H

USB + Custom Alternate Mode (Source Side)

H

L

H

L

Power Down

–

Power Down

H

One Port USB 3.1 - No Flip

One Port USB 3.1 – With Flip

H

4 Channel Custom Alt Mode -

No Flip

H

L

H

L

–

4 Channel Custom Alt Mode–

With Flip

H

One Port USB 3.1 + 2

Channel Custom Alt Mode-

No Flip

H

L

H

L

–

One Port USB 3.1 + 2

Channel Custom Alt Mode –

With Flip

H

USB + Custom Alternate Mode (Sink Side)

H

L

H

L

Power Down

–

Power Down

H

One Port USB 3.1 - No Flip

One Port USB 3.1 – With Flip

H

4 Channel Custom Alt Mode -

No Flip

H

L

–

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表 5. I²C Configuration Control (接下页)

Registers

CTLSEL1

VESA DisplayPort Alt Mode

TUSB544 Configuration

DFP_D Configuration

DIRSEL1

DIRSEL0

CTLSEL0

FLIPSEL

4 Channel Custom Alt Mode–

With Flip

H

L

H

–

One Port USB 3.1 + 2

Channel Custom Alt Mode-

No Flip

H

L

–

One Port USB 3.1 + 2

Channel Custom Alt Mode –

With Flip

H

表 6. I²C Mode AUXP/N to SBU1/2 Mapping

Registers

AUX_SBU_OVR

CTLSEL1

FLIPSEL

Mapping

AUXp -> SBU1

AUXn -> SBU2

00

H

L

AUXp -> SBU2

AUXn -> SBU1

00

01

H

L

H

X

Open

AUXp -> SBU1

AUXn -> SBU2

X

AUXp -> SBU2

AUXn -> SBU1

10

11

X

Open

7.4.3 DisplayPort Mode

The TUSB544 supports up to four DisplayPort lanes at datarates up to 8.1Gbps. TUSB544 can be enabled for

DisplayPort through GPIO control or through I²C register control. In GPIO mode, DisplayPort is controlled based

on 表 2. When not in GPIO mode, enable of DisplayPort functionality is controlled through I²C registers.

7.4.4 Custom Alternate Mode

The TUSB544 supports up to two lanes (or 4 channels) of custom Alternate Mode at datarates up to 8.1Gbps.

TUSB544 can be enabled for custom Alternate Mode through GPIO control or through I²C register control. in

GPIO mode, custom Alternate Mode is controlled based on 表 2. When not in GPIO mode, enable of custom

Alternate Mode functionality is controlled through I²C registers. In I²C mode, the operation of this mode requires

setting AUX_SNOOP_DISABLE register 13h bit 7 to 0.

7.4.5 Linear EQ Configuration

TUSB544 receiver lanes have controls for receiver equalization for upstream and downstream facing ports. The

receiver equalization gain value can be controlled either through I²C registers or through GPIOs. 表 7 details the

gain value for each available combination when TUSB544 is in GPIO mode. These same options are also

available per channel and for upstream and downstream facing ports in I²C mode by updating registers

URX[2:1]EQ_SEL, UTX[2:1]EQ_SEL, DRX[2:1]EQ_SEL, and DTX[2:1]EQ_SEL.

表 7. TUSB544 Receiver Equalization GPIO Control

Downstream Facing Ports

Upstream Facing Port

DEQ1

Level

DEQ0

Level

EQ GAIN

2.5GHz

(dB)

EQ GAIN

4.05GHz

(dB)

UEQ1

Level

UEQ0

Level

EQ GAIN

2.5GHz

(dB)

EQ GAIN

4.05GHz

(dB)

0

R

F

1

-1.0

0.1

1.0

2.1

-1.4

0.4

1.7

3.2

0

R

F

1

-2.2

-1.1

-0.2

0.9

-3.3

-1.5

0.0

1.4

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表 7. TUSB544 Receiver Equalization GPIO Control (接下页)

Downstream Facing Ports

Upstream Facing Port

R

F

1

0

R

F

1

2.9

3.8

4.6

5.4

6.1

6.8

7.3

7.9

8.4

8.9

9.3

9.8

4.1

5.2

R

F

1

0

R

F

1

1.8

2.7

3.4

4.3

5.0

5.7

6.2

6.8

7.3

7.8

8.2

8.7

2.4

3.5

4.3

5.2

6.0

6.6

7.2

7.7

8.1

8.6

9.0

9.4

6.1

6.9

0

7.7

0

R

F

1

8.3

R

F

1

8.8

9.4

0

9.8

0

1

R

F

1

10.3

10.6

11.0

1

R

F

1

7.4.6 Adjustable VOD Linear Range and DC Gain

The CFG0 and CFG1 pins can be used to adjust the TUSB544 differential output voltage (VOD) swing linear

range and receiver equalization DC gain for both downstream and upstream data path directions. 表 8 details the

available options.

表 8. VOD Linear Range and DC Gain

Downstream

VOD Linear

Range

Upstream

VOD Linear

Range

Downstream

DC Gain

(dB)

Setting

#

CFG1 pin

Level

CFG0 pin

Level

Upstream

DC Gain (dB)

(mVpp)

1

2

0

R

F

1

0

900

0

1

3

0

900

4

0

1

900

5

R

F

1

0

1100

6

R

F

1

0

1100

7

0

1

1100

8

2

1100

9

0

Reserved

10

11

12

13

14

15

16

R

F

1

0

1

R

F

1

7.4.7 USB3.1 modes

The TUSB544 monitors the physical layer conditions like receiver termination, electrical idle, LFPS, and

SuperSpeed signaling rate to determine the state of the USB3.1 interface. Depending on the state of the USB

3.1 interface, the TUSB544 can be in one of four primary modes of operation when USB 3.1 is enabled (CTL0 =

H or CTLSEL0 = 1b1): Disconnect, U2/U3, U1, and U0.

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The Disconnect mode is the state in which TUSB544 has not detected far-end termination on both upstream

facing port (UFP) or downstream facing port (DFP). The disconnect mode is the lowest power mode of each of

the four modes. The TUSB544 will remain in this mode until far-end receiver termination has been detected on

both UFP and DFP. The TUSB544 will immediately exit this mode and enter U0 once far-end termination is

detected.

Once in U0 mode, the TUSB544 will redrive all traffic received on UFP and DFP. U0 is the highest power mode

of all USB3.1 modes. The TUSB544 will remain in U0 mode until electrical idle occurs on both UFP and DFP.

Upon detecting electrical idle, the TUSB544 will immediately transition to U1.

The U1 mode is the intermediate mode between U0 mode and U2/U3 mode. In U1 mode, the TUSB544’s UFP

and DFP receiver termination will remain enabled. The UFP and DFP transmitter DC common mode is

maintained. The power consumption in U1 will be similar to power consumption of U0.

Next to the disconnect mode, the U2 and U3 mode is next lowest power state. While in this mode, the TUSB544

will periodically perform far-end receiver detection. Anytime the far-end receiver termination is not detected on

either UFP or DFP, the TUSB544 will leave the U2 and U3 mode and transition to the Disconnect mode. It will

also monitor for a valid LFPS. Upon detection of a valid LFPS, the TUSB544 will immediately transition to the U0

mode. In U2 and U3 mode, the TUSB544’s receiver terminations will remain enabled but the TX DC common

mode voltage will not be maintained.

When SLP_S0# is asserted low it will disable Receiver Detect functionality. While SLP_S0# is low and TUSB544

is in U2 and U3, TUSB544 will disable LOS and LFPS detection circuitry and RX termination for both channels

will remain enabled. This allows even lower TUSB544 power consumption while in the U2 and U3 mode. Once

SLP_S0# is asserted high, the TUSB544 will again start performing far-end receiver detection as well as monitor

LFPS so it can know when to exit the U2 and U3 mode.

When SLP_S0# is asserted low and the TUSB544 is in Disconnect mode, the TUSB544 will remain in

Disconnect mode and never perform far-end receiver detection. This allows even lower TUSB544 power

consumption while in the Disconnect mode. Once SLP_S0# is asserted high, the TUSB544 will again start

performing far-end receiver detection so it can know when to exit the Disconnect mode.

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7.4.8 Operation Timing – Power Up

T_{ctl_db}

Mode of operation

determined by value of

FLIPSEL bit and CTLSEL[1:0]

bits at offset 0x0A. Default

is USB3.1-only no Flip.

TUSB544

In I2C mode

USB3.1-only

FLIP = 0

DISABLED

If ((CTL[1:0] == 2'b00 | CTL[1:0] == 2'b01) & FLIP == 0 ) {

USB3.1-only no FLIP;

} ELSEIF ((CTL[1:0] == 2'b00 | CTL[1:0] == 2'b01) & FLIP == 1 ) {

USB3.1-only with FLIP;

} ELSEIF (CTL[1:0] == 2'b10 & FLIP == 0) {

4-Lane DP no FLIP;

} ELSEIF (CTL[1:0] == 2'b10 & FLIP == 1) {

4-Lane DP with FLIP;

TUSB544

In GPIO mode

USB3.1-only

FLIP = 0

DISABLED

} ELSEIF (CTL[1:0] == 2'b11 & FLIP == 0) {

2-Lane DP USB3.1 no FLIP;

}ELSE {

2-lane DP USB3.1 with FLIP;

};

CTL[1:0] pins

FLIP pin

V_{CC (min)}

V_CC

T_{d_pg}

Internal

Power

Good

T_{cfg_hd}

T_{cfg_su}

CFG pins

图 21. Power-Up Timing

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表 9. Power-Up Timing

PARAMETER

MIN

MAX

UNIT

µs

T_{d_pg}

T_{cfg_su}

V_CC(min) to Internal Power Good asserted high

500

(2)

CFG⁽¹⁾pins setup

CFG⁽¹⁾pins hold

350

10

µs

T_{cfg_hd}

µs

T_{CTL_DB}

T_{VCC_RAMP}

CTL[1:0] and FLIP pin debounce

VCC supply ramp requirement

16

ms

100

(1) Following pins comprise CFG pins: I2C_EN, UEQ[1:0], DEQ[1:0], CFG[1:0], DIR[1:0],VIO_SEL, SLP_S0#, and SWAP.

(2) Recommend CFG pins are stable when VCC is at min.

7.5 Programming

For further programmability, the TUSB544 can be controlled using I²C. The SCL and SDA terminals are used for

I²C clock and I²C data respectively.

表 10. I²C Slave Address

TUSB544 I²C Slave Address

UEQ1/A1

Pin Level

UEQ0/A0

Pin Level

Bit 0

(W/R)

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0

R

F

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0/1

0

R

F

1

0

R

F

1

0

R

F

1

0

1

R

F

1

7.5.1 The Following Procedure Should be Followed to Write to TUSB544 I²C Registers:

1. The master initiates a write operation by generating a start condition (S), followed by the TUSB544 7-bit

address and a zero-value “W/R” bit to indicate a write cycle .

2. The TUSB544 acknowledges the address cycle.

3. The master presents the sub-address (I²C register within TUSB544) to be written, consisting of one byte of

data, MSB-first.

4. The TUSB544 acknowledges the sub-address cycle.

5. The master presents the first byte of data to be written to the I²C register.

6. The TUSB544 acknowledges the byte transfer.

7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing

with an acknowledge from the TUSB544.

8. The master terminates the write operation by generating a stop condition (P).

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7.5.2 The Following Procedure Should be Followed to Read the TUSB544 I²C Registers:

1. The master initiates a read operation by generating a start condition (S), followed by the TUSB544 7-bit

address and a one-value “W/R” bit to indicate a read cycle

2. The TUSB544 acknowledges the address cycle.

3. The TUSB544 transmit the contents of the memory registers MSB-first starting at register 00h or last read

sub-address+1. If a write to the TUSB544 I2C register occurred prior to the read, then the TUSB544 shall

start at the sub-address specified in the write.

4. The TUSB544 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master

after each byte transfer; the I²C master acknowledges reception of each data byte transfer.

5. If an ACK is received, the TUSB544 transmits the next byte of data.

6. The master terminates the read operation by generating a stop condition (P).

7.5.3 The Following Procedure Should be Followed for Setting a Starting Sub-Address for I²C Reads:

1. The master initiates a write operation by generating a start condition (S), followed by the TUSB544 7-bit

address and a zero-value “W/R” bit to indicate a write cycle.

2. The TUSB544 acknowledges the address cycle.

3. The master presents the sub-address (I²C register within TUSB544) to be written, consisting of one byte of

data, MSB-first.

4. The TUSB544 acknowledges the sub-address cycle.

5. The master terminates the write operation by generating a stop condition (P).

注

If no sub-addressing is included for the read procedure, and reads start at register offset

00h and continue byte by byte through the registers until the I²C master terminates the

read operation. If a I²C address write occurred prior to the read, then the reads start at the

sub-address specified by the address write.

7.6 Register Maps

7.6.1 TUSB544 Registers

Table 11 lists the memory-mapped registers for the TUSB544. All register offset addresses not listed in Table 11

should be considered as reserved locations and the register contents should not be modified.

Table 11. TUSB544 Registers

Offset

Ah

Acronym

Register Name

Section

Go

GENERAL_4

GENERAL_5

GENERAL_6

DISPLAYPORT_1

DISPLAYPORT_2

DISPLAYPORT__3

DISPLAYPORT_4

DISPLAYPORT_5

USB3.1_1

General Registers 4

Bh

General Register 5

Go

Ch

General Register 6

Go

10h

11h

12h

13h

1Bh

20h

21h

22h

23h

DisplayPort Control/Status Registers 1

DisplayPort Control/Status Registers 2

DisplayPort Control/Status Registers 3

DisplayPort Control/Status Registers 4

DisplayPort Control/Status Registers 5

USB3.1 Control/Status Registers 1

USB3.1 Control/Status Registers 2

USB3.1 Control/Status Registers 3

USB3.1 Control/Status Registers 4

Go

USB3.1_2

Go

USB3.1_3

Go

USB3.1_4

Go

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Complex bit access types are encoded to fit into small table cells. Table 12 shows the codes that are used for

access types in this section.

Table 12. TUSB544 Access Type Codes

Access Type

Code

R

Description

Read Type

The field can be read by software

H

The field can be read by software but hardware

may autonomously update the field.

Write Type

W

The field can be written by software.

1S

The field can only be set by a write of one. Writes of

zero to the field have no effect.

1C

The field can only be cleared by a write of one.

Writes of zero to the field have no effect.

1SH

The field can only be set by a write of one but

hardware will later autonomously clear the field.

Writes of zero to the field have no effect.

Reset or default value

-n

Value after reset or the default value

7.6.1.1 GENERAL_4 Register (Offset = Ah) [reset = 1h]

GENERAL_4 is shown in Figure 22 and described in Table 13.

Return to Summary Table.

Figure 22. GENERAL_4 Register

7

6

5

4

3

2

1

0

RESERVED

SWAP_SEL

EQ_OVERIDE HPDIN_OVER

RIDE

FLIPSEL

CTLSEL[1:0]

R/W-1h

R-0h

R/W-0h

Table 13. GENERAL_4 Register Field Descriptions

Bit

7

Field

Type

R

Reset

0h

Description

RESERVED

Reserved

6

R/W

0h

Setting of this field performs global direction swap on all the

channels

0 – Channel directions and EQ settings are in normal mode (Default)

1 – Reverse all channel directions and EQ settings for the input ports

5

4

SWAP_SEL

R/W

0h

Setting of this field will allow software to use EQ settings from

registers instead of value sample from pins.

0 – EQ settings based on sampled state of the EQ pins.

1 – EQ settings based on programmed value of each of the EQ

registers

EQ_OVERIDE

0 – HPD IN based on state of HPD_IN pin (Default)

1 – HPD_IN high.

3

2

HPDIN_OVERRIDE

FLIPSEL

R/W

0h

FLIPSEL. Refer to 表 5 and 表 6 for this field functionality.

00 – Disabled. All RX and TX for USB3 and DisplayPort are

disabled.

1-0

CTLSEL[1:0]

R/W

1h

01 – USB3.1 only enabled. (Default)

10 – Four DisplayPort lanes enabled.

11 – Two DisplayPort lanes and one USB3.1

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7.6.1.2 GENERAL_5 Register (Offset = Bh) [reset = 0h]

GENERAL_5 is shown in Figure 23 and described in Table 14.

Return to Summary Table.

Figure 23. GENERAL_5 Register

7

6

5

4

3

2

1

0

RESERVED

R-0h

RESERVED

R-0h

CH_SWAP_SEL

R/W-0h

Table 14. GENERAL_5 Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

7-6

5-4

RESERVED

R

0h

R

0h

Setting of this field swaps direction (TX to RX and RX to TX) and EQ

settings of individual channels. Channels are numbered 0 to 3 from

top to bottom (see block diagram on Figure 8.1).

0 – Channel direction and EQ setting are in normal mode (Default)

1 – Reverse channel direction and EQ setting for the input port. For

example, setting 0x0B[3:0] to 4b1100 swaps directions and EQ

settings only on channels 2 and 3

3-0

CH_SWAP_SEL

R/W

7.6.1.3 GENERAL_6 Register (Offset = Ch) [reset = 0h]

GENERAL_6 is shown in Figure 24 and described in Table 15.

Return to Summary Table.

Figure 24. GENERAL_6 Register

7

6

5

4

3

2

1

0

RESERVED

VOD_DCGAIN

_OVERRIDE

VOD_DCGAIN_SEL

DIR_SEL[1:0]

R/W-0h

R-0h

R/W-0h

Table 15. GENERAL_6 Register Field Descriptions

Bit

Field

RESERVED

Type

Reset

Description

7

R

0h

Reserved

6

VOD_DCGAIN_OVERRID R/W

E

0h

Setting of this field will allow software to use VOD linearity range and

DC gain settings from registers instead of value sampled from pins.

0 – VOD linearity range and DC gain settings based on sampled

state of CFG[2:1] pins.

1 – EQ settings based on programmed value of each of the VOD

linearity range and DC gain registers

5-2

VOD_DCGAIN_SEL

R/W

0h

Field selects VOD linearity range and DC gain for all the channels

and in all directions. When VOD_DCGAIN_OVERRIDE = 1’b0, this

field reflects the sampled state of CFG[1:0] pins. When

VOD_DCGAIN_OVERRIDE = 1’b1, software can change the VOD

linearity range and DC gain for all the channels and in all directions

based on value written to this field. Refer to Table 8 8. Each CFG is

a 2-bit value. The register-to-CFG1/0 mapping is: [5:2] = {CFG1[1:0],

CFG0[1:0]} where CFGx[1:0] mapping is:

00 = 0

01 = R

10 = F

11 = 1

1-0

DIR_SEL[1:0]

R/W

0h

DIR_SEL[1:0]. Sets operation mode

00 – USB + DP Alt Mode (source) (Default)

01 – USB + DP Alt Mode (sink)

10 – USB + Custom Alt Mode (source)

11 – USB + Custom Alt Mode (sink)

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7.6.1.4 DISPLAYPORT_1 Register (Offset = 10h) [reset = 0h]

DISPLAYPORT is shown in Figure 25 and described in Table 16.

Return to Summary Table.

Figure 25. DISPLAYPORT Register

7

6

5

4

3

2

1

0

UTX2EQ_SEL

R/W-0h

URX2EQ_SEL

R/W-0h

Table 16. DISPLAYPORT Register Field Descriptions

Bit

Field

Type

Reset

Description

Field selects between 0 to 9.4 dB of EQ for UTX2P/N pins. When

EQ_OVERRIDE = 1’b0, this field reflects the sampled state of

UEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can change

the EQ setting for UTX2P/N pins based on value written to this field.

7-4

3-0

UTX2EQ_SEL

URX2EQ_SEL

RW

0h

Field selects between 0 to 9.4 dB of EQ for URX2P/N pins. When

EQ_OVERRIDE = 1’b0, this field reflects the sampled state of

UEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can change

the EQ setting for URX2P/N pins based on value written to this field.

RW

0h

7.6.1.5 DISPLAYPORT_2 Register (Offset = 11h) [reset = 0h]

DISPLAYPORT_2 is shown in Figure 26 and described in Table 17.

Return to Summary Table.

Figure 26. DISPLAYPORT_2 Register

7

6

5

4

3

2

1

0

UTX1EQ_SEL

R/W-0h

URX1EQ_SEL

R/W-0h

Table 17. DISPLAYPORT_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

Field selects between 0 to 9.4 dB of EQ for UTX1P/N pins. When

EQ_OVERRIDE = 1’b0, this field reflects the sampled state of

UEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can change

the EQ setting for UTX1P/N pins based on value written to this field.

7-4

3-0

UTX1EQ_SEL

URX1EQ_SEL

R/W

0h

Field selects between 0 to 9.4 dB of EQ for URX1P/N pins. When

EQ_OVERRIDE = 1’b0, this field reflects the sampled state of

UEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can change

the EQ setting for URX1P/N pins based on value written to this field.

R/W

0h

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7.6.1.6 DISPLAYPORT_3 Register (Offset = 12h) [reset = 0h]

DISPLAYPORT__3 is shown in Figure 27 and described in Table 18.

Return to Summary Table.

Figure 27. DISPLAYPORT_3 Register

7

6

5

4

3

2

1

0

RESERVED

R-0h

SET_POWER_STATE

RH-0h

LANE_COUNT_SET

RH-0h

Table 18. DISPLAYPORT_3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESERVED

R

0h

Reserved

This field represents the snooped value of the AUX write to DPCD

address 0x00600. When AUX_SNOOP_DISABLE = 1’b0, the

TUSB544 will enable/disable DP lanes based on the snooped value.

When AUX_SNOOP_DISABLE = 1’b1, then DP lane enable/disable

are determined by state of DPx_DISABLE registers, where x = 0, 1,

2, or 3. This field is reset to 2’b00 by hardware when CTLSEL1

changes from a 1’b1 to a 1’b0.

6-5

4-0

SET_POWER_STATE

LANE_COUNT_SET

RH

0h

This field represents the snooped value of AUX write to DPCD

address 0x00101 register. When AUX_SNOOP_DISABLE = 1’b0,

TUSB544 will enable DP lanes specified by the snoop value. Unused

DP lanes will be disabled to save power. When

AUX_SNOOP_DISABLE = 1’b1, then DP lanes enable/disable are

determined by DPx_DISABLE registers, where x = 0, 1, 2, or 3. This

field is reset to 0x0 by hardware when CTLSEL1 changes from a

1’b1 to a 1’b0.

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7.6.1.7 DISPLAYPORT_4 Register (Offset = 13h) [reset = 0h]

DISPLAYPORT_4 is shown in Figure 28 and described in Table 19.

Return to Summary Table.

Figure 28. DISPLAYPORT_4 Register

7

6

5

4

3

2

1

0

AUX_SNOOP_

DISABLE

RESERVED

AUX_SBU_OVR

DP3_DISABLE DP2_DISABLE DP1_DISABLE DP0_DISABLE

R/W-0h

R-0h

R/W-0h

R/W-0h R/W-0h R/W-0h R/W-0h

Table 19. DISPLAYPORT_4 Register Field Descriptions

Bit

Field

Type

Reset

Description

0 – AUX snoop enabled. (Default)

1 – AUX snoop disabled.

7

AUX_SNOOP_DISABLE

RESERVED

R/W

0h

6

R

0h

Reserved

This field overrides the AUXP/N to SBU1/2 connect and disconnect

based on CTL1 and FLIP. Changing this field to 1’b1 will allow traffic

to pass through AUX to SBU regardless of the state of CTLSEL1

and FLIPSEL register.

00 – AUX to SBU connect/disconnect determined by CTLSEL1 and

FLIPSEL (Default)

5-4

AUX_SBU_OVR

R/W

0h

01 – AUXP -> SBU1 and AUXN -> SBU2 connection always

enabled.

10 – AUXP -> SBU2 and AUXN -> SBU1 connection always

enabled. 1

1 = AUX to SBU open.

When AUX_SNOOP_DISABLE = 1b1, this field can be used to

enable or disable DP lane 3. When AUX_SNOOP_DISABLE = 1b0,

changes to this field will have no effect on lane 3 functionality.

0 – DP Lane 3 Enabled (default)

3

2

1

0

DP3_DISABLE

DP2_DISABLE

DP1_DISABLE

DP0_DISABLE

R/W

0h

1 – DP Lane 3 Disabled.

When AUX_SNOOP_DISABLE = 1 'b1, this field can be used to

enable or disable DP lane 2. When AUX_SNOOP_DISABLE = 1b0,

changes to this field will have no effect on lane 2 functionality.

0 – DP Lane 2 Enabled (default)

1 – DP Lane 2 Disabled.

When AUX_SNOOP_DISABLE = 1’b1, this field can be used to

enable or disable DP lane 1. When AUX_SNOOP_DISABLE = 1’b0,

changes to this field will have no effect on lane 1 functionality.

0 – DP Lane 1 Enabled (default)

1 – DP Lane 1 Disabled.

When AUX_SNOOP_DISABLE = 1’b1, this field can be used to

enable or disable DP lane 0. When AUX_SNOOP_DISABLE = 1’b0,

changes to this field will have no effect on lane 0 functionality.

0 – DP Lane 0 Enabled (default)

1 – DP Lane 0 Disabled.

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7.6.1.8 DISPLAYPORT_5 Register (Offset = 1Bh) [reset = 0h]

DISPLAYPORT_5 is shown in Figure 29 and described in Table 20.

Return to Summary Table.

Figure 29. DISPLAYPORT_5 Register

7

6

5

4

3

2

1

0

I2C_RST

R/WSH-0h

DPCD_RST

R/WSH-0h

RESERVED

R-00h

Table 20. DISPLAYPORT_5 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

I2C_RST

R/WSH

0h

Resets I2C registers to default values. This field is self- clearing.

6

DPCD_RST

Reserved

R/WSH

R

0h

Resets DPCD registers to default values. This field is self- clearing.

Reserved

5:0

00h

7.6.1.9 USB3.1_1 Register (Offset = 20h) [reset = 0h]

USB3.1 is shown in Figure 30 and described in Table 21.

Return to Summary Table.

Figure 30. USB3.1 Register

7

6

5

4

3

2

1

0

DTX2EQ_SEL

R/W-0h

DRX2EQ_SEL

R/W-0h

Table 21. USB3.1 Register Field Descriptions

Bit

Field

Type

Reset

Description

Field selects between 0 to 11 dB of EQ for DTX2P/N pins. When

EQ_OVERRIDE = 1’b0, this field reflects the sampled state of

DEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can change

the EQ setting for DTX2P/N pins based on value written to this field.

7-4

3-0

DTX2EQ_SEL

DRX2EQ_SEL

R/W

0h

Field selects between 0 to 11 dB of EQ for DRX2P/N pins. When

EQ_OVERRIDE = 1’b0, this field reflects the sampled state of

DEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can change

the EQ setting for DRX2P/N pins based on value written to this field.

R/W

0h

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7.6.1.10 USB3.1_2 Register (Offset = 21h) [reset = 0h]

USB3.1_2 is shown in Figure 31 and described in Table 22.

Return to Summary Table.

Figure 31. USB3.1_2 Register

7

6

5

4

3

2

1

0

DTX1EQ_SEL

R/W-0h

DRX1EQ_SEL

R/W-0h

Table 22. USB3.1_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

Field selects between 0 to 11 dB of EQ for DTX1P/N pins. When

EQ_OVERRIDE = 1’b0, this field reflects the sampled state of

DEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can change

the EQ setting for DTX1P/N pins based on value written to this field.

7-4

3-0

DTX1EQ_SEL

DRX1EQ_SEL

R/W

0h

Field selects between 0 to 11 dB of EQ for DRX1P/N pins. When

EQ_OVERRIDE = 1’b0, this field reflects the sampled state of

DEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can change

the EQ setting for DRX1P/N pins based on value written to this field.

R/W

0h

7.6.1.11 USB3.1_3 Register (Offset = 22h) [reset = 0h]

USB3.1_3 is shown in Figure 32 and described in Table 23.

Return to Summary Table.

Figure 32. USB3.1_3 Register

7

6

5

4

3

2

1

0

CM_ACTIVE

LFPS_EQ

U2U3_LFPS_D DISABLE_U2U

DFP_RXDET_INTERVAL

USB3_COMPLIANCE_CTRL

EBOUNCE

3_RXDET

RH-0h

R/W-0h

R/W-1h

R/W-0h

Table 23. USB3.1_3 Register Field Descriptions

Bit

Field

CM_ACTIVE

Type

Reset

Description

0 - device not in USB 3.1 compliance mode. (Default)

1 - device in USB 3.1 compliance mode

7

RH

0h

Controls whether settings of EQ based on URX[2:1]EQ_SEL,

UTX[2:1]EQ_SEL, DRX[2:1]EQ_SEL, and DTX[2:1]EQ_SEL applies

to received LFPS signal.

6

LFPS_EQ

R/W

0h

0 - EQ set to zero when receiving LFPS (default)

1 - EQ set by the related registers when receiving LFPS.

0 - No debounce of LFPS before U2/U3 exit. (Default)

1 - 200us debounce of LFPS before U2/U3 exit.

5

4

U2U3_LFPS_DEBOUNCE R/W

DISABLE_U2U3_RXDET R/W

0h

0 - Rx.Detect in U2/U3 enabled. (Default)

1 - Rx.Detect in U2/U3 disabled.

This field controls the Rx.Detect interval for the Downstream facing

port (TX1P/N and TX2P/N).

00 - 8 ms

01 - 12 ms (default)

10 - Reserved

3-2

1-0

DFP_RXDET_INTERVAL R/W

1h

0h

11 - Reserved

00 - FSM determined compliance mode. (Default)

01 - Compliance Mode enabled in DFP direction (UTX1/UTX2

DTX1/DTX2)

10 - Compliance Mode enabled in UFP direction (DRX1/DRX2

URX1/URX2)

USB3_COMPLIANCE_CT

R/W

RL

11 - Compliance Mode Disabled.

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7.6.1.12 USB3.1_4 Register (Offset = 23h) [reset = 23h]

USB3.1_4 is shown in Figure 33 and described in Table 24.

Return to Summary Table.

Figure 33. USB3.1_4 Register

7

6

5

4

3

2

1

0

RESERVED

R-0h

CFG_LOS_HYST

R/W-4h

CFG_LOS_VTH

R/W-3h

Table 24. USB3.1_4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

RESERVED

R

0h

Reserved

Controls LOS hysteresis defined as 20 log (LOS de-assert

threshold/LOS assert threshold).

000 - 0.15 dB

001 - 0.85 dB

010 - 1.45 dB

011 - 2.00 dB

5-3

CFG_LOS_HYST

R/W

4h

100 - 2.70 dB (default)

101 - 3.00 dB

110 - 3.40 dB

111 - 3.80 dB

Controls LOS assert threshold voltage

000 - 67 mV

001 - 72 mV

010 - 79 mV

2-0

CFG_LOS_VTH

R/W

3h

011 - 85 mV (default)

100 - 91 mV

101 - 97 mV

110 - 105 mV

111 - 112 mV

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TUSB544 is a linear redriver designed specifically to compensate for intersymbol interference (ISI) jitter

caused by signal attenuation through a passive medium like PCB traces and cables. Because the TUSB544 has

four independent inputs, it can be optimized to correct ISI on all those seven inputs through 16 different

equalization choices. Placing the TUSB544 between a USB3.1 Host/DisplayPort 1.4 GPU and a USB3.1 Type-C

receptacle can correct signal integrity issues resulting in a more robust system.

8.2 Typical Application

A

B

F

E

PCB Trace of Length X_AB

PCB Trace of Length X_EF

URX2P

RX2P

URX2N

UTX2P

RX2N

TX2P

DRX2P

DRX2N

UTX2N

TX2N

DTX2P

DTX2N

USB3.1/

DP1.4

Host

TUSB544

DTX1N

DTX1P

UTX1N

TX1N

DRX1N

DRX1P

UTX1P

URX1N

URX1P

TX1P

RX1N

RX1P

PCB Trace of Length X_CD

PCB Trace of Length X_GH

G

H

C

D

图 34. TUSB544 in a Host Application

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Typical Application (接下页)

8.2.1 Design Requirements

For this design example, use the parameters shown in 表 25.

表 25. Design Parameters

PARAMETER

A to B PCB trace length, X_AB

C to D PCB trace length, X_CD

E to F PCB trace length, X_EF

G to H PCB trace length, X_GH

PCB trace width

VALUE

12 inches

2 inches

4 mils

AC-coupling capacitor (75 nF to 265 nF)

VCC supply (3 V to 3.6 V)

I²C Mode or GPIO Mode

100 nF

3.3 V

I²C Mode. (I2C_EN pin != "0")

3.3V I²C. Pull-up the I2C_EN pin to 3.3V with a 1K

ohm resistor.

1.8V or 3.3V I²C Interface

8.2.2 Detailed Design Procedure

A typical usage of the TUSB544 device is shown in 图 35. The device can be controlled either through its GPIO

pins or through its I²C interface. In the example shown below, a Type-C PD controller is used to configure the

device through the I²C interface. In I²C mode, the equalization settings for each receiver can be independently

controlled through I²C registers. For this reason, all of the equalization pins (UEQ[1:0] and DEQ[1:0]) can be left

unconnected. If these pins are left unconnected, the TUSB544 7-bit I²C slave address will be 12h because both

UEQ1/A1 and UEQ0/A0 will be at pin level "F". If a different I²C slave address is desired, UEQ1/A1 and

UEQ0/A0 pins should be set to a level which produces the desired I²C slave address.

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3.3 V

10uF

100nF

100 nF

DRX2P

DRX2N

DTX2P

DTX2N

RX2P

RX2N

TX2P

TX2N

URX2P

URX2N

UTX2P

UTX2N

100 nF

USB Type-C

Receptacle

100 nF

A12

A11

A10

A9

GND

URXP2

URXN2

VBUS

SBU1

DN1

100 nF

B1

B2

GND

TXP2

TXN2

100K

100 nF

AUXP

AUXN

AUXP

AUXN

B3

B4

VBUS

CC2

A8

100K

SBU1

SBU2

DP_PWR (3.3V)

B5

USB 3.1/DP1.4

Host

A7

B6

DP2

DN2

2M

DP1

A6

2M

B7

A5

CC1

B8

SBU2

VBUS

100 nF

A4

100 nF

DTX1N

TX1N

UTX1N

UTX1P

URX1N

B9

A3

TXN1

TXP1

DTX1P

DRX1N

TX1P

RX1N

B10

B11

B12

URXN1

URXP1

GND

A2

DRX1P

RX1P

URX1P

3.3V

A1

GND

SWAP

I2C_EN

3.3V

UEQ0/A0

UEQ1/A1

V_I2C

3.3V

R

VIO_SEL

FLIP/SCL

CTL0/SDA

CTL1

CFG0

CFG1

DEQ0

Type-C

PD

Controller

3.3V

SLP_S0#

HPDIN

DEQ1

3.3V

DIR0

DIR1

GPIO Mode Only Connections

GPIO/I2C Mode Connections

图 35. Typical Application Circuit

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8.2.3 Application Curve

0

-5

-10

-15

-20

-25

-30

-35

-40

-45

-50

-55

-60

Length=12in, Width=6mil

Length=16in, Width=6mil

Length=20in, Width=6mil

Length=24in, Width=6mil

Length=4in, Width=4mil

Length=8in, Width=10mil

Length=8in, Width=6mil

0

2

4

6

8

10

12

14

16

Frequency (GHz)

D009

图 36. Insertion Loss of FR4 PCB Traces

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8.3 System Examples

8.3.1 USB 3.1 only (USB/DP Alternate Mode)

The TUSB544 will be in USB3.1 only when the CTL1 pin is low and CTL0 pin is high.

USB/DP Source (USB

USB/DP Sink

Only œ No Flip)

(USB Only œ No Flip)

D+/-

TUSB544

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

Type-C Cable

TX1

RX1

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

TX1

RX1

USB/DP

Source

USB/DP

Sink

TX1

RX1

TX1

RX1

AUXp

AUXn

SBU1

SBU2

SBU1

AUXn

AUXp

HPDIN

CTL

0 1

FLIP

0

CTL

1

FLIP

HPD

Control

CC1

CC2

CC1

CC2

PD Controller

Control

DIR1/DIR0/CTL1/CTL0/FLIP = L/L/L/H/L

DIR1/DIR0/CTL1/CTL0/FLIP = L/H/L/H/L

图 37. USB3.1 Only – No Flip

USB/DP Source (USB

USB/DP Sink

Only œ Flip)

(USB Only œ Flip)

D+/-

TUSB544

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

Type-C Cable

RX2

TX2

RX2

TX2

TX1

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

USB/DP

Source

DP/USB

Sink

RX2

TX2

RX2

TX2

AUXp

AUXn

SBU1

SBU2

SBU1

AUXn

AUXp

HPDIN

CTL

0 1

FLIP

0

CTL

1

FLIP

HPD

Control

CC1

CC2

CC1

CC2

PD Controller

Control

DIR1/DIR0/CTL1/CTL0/FLIP = L/L/L/H/H

DIR1/DIR0/CTL1/CTL0/FLIP = L/H/L/H/H

图 38. USB3.1 Only – With Flip

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System Examples (接下页)

8.3.2 USB3.1 and 2 lanes of DisplayPort

USB/DP Source

USB/DP Sink

(USB + 2 Lane DP œ No Flip)

D+/-

USB/DP

Sink

TUSB544

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

Type-C Cable

ML0

ML1

TX1

RX1

RX2

TX2

TX1

RX1

TX1

RX1

RX2

TX2

URX2

UTX2

DRX2

DTX2

TX1

RX1

USB/DP

Source

DTX1

DRX1

UTX1

URX1

ML1

ML0

AUXp

AUXn

SBU1

SBU2

SBU1

AUXn

AUXp

SBU1

SBU2

AUXp

SBU1

SBU2

AUXn

AUXp

AUXn

HPDIN

CTL

1

CTL

FLIP 0 1

FLIP 0

HPD

Control

CC1

CC2

CC1

CC2

PD Controller

Control

DIR1/DIR0/CTL1/CTL0/FLIP = L/H/H/H/L

DIR1/DIR0/CTL1/CTL0/FLIP = L/L/H/H/L

图 39. USB3.1 + 2 Lane DP – No Flip

USB/DP Source

USB/DP Sink

(USB + 2 Lane DP œ Flip)

D+/-

USB/DP

Sink

TUSB544

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

Type-C Cable

DRX2

DTX2

DTX1

DRX1

URX2

UTX2

UTX1

URX1

RX2

TX2

RX2

TX2

TX1

RX1

TX1

RX1

RX2

TX2

ML0

ML1

RX2

TX2

USB/DP

Source

ML1

ML0

SBU2

SBU1

AUXn

AUXp

AUXn

SBU1

SBU2

SBU1

SBU2

AUXp

SBU1

SBU2

AUXn

AUXp

AUXn

HPDIN

CTL

1

CTL

FLIP 0 1

FLIP 0

HPD

Control

CC1

CC2

CC1

CC2

PD Controller

Control

DIR1/DIR0/CTL1/CTL0/FLIP = L/L/H/H/H

DIR1/DIR0/CTL1/CTL0/FLIP = L/H/H/H/H

图 40. USB 3.1 + 2 Lane DP – Flip

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TUSB544

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ZHCSG75E –APRIL 2017–REVISED APRIL 2018

System Examples (接下页)

8.3.3 DisplayPort Only

USB/DP Source

USB/DP Sink

(4 Lane DP œ No Flip)

D+/-

USB/DP

Sink

TUSB544

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

Type-C Cable

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

ML0

ML1

ML2

ML3

RX2

TX2

TX1

RX1

TX1

RX1

RX2

TX2

ML3

ML2

USB/DP

Source

ML1

ML0

SBU2

SBU1

AUXn

AUXp

SBU1

SBU2

AUXp

SBU1

SBU2

AUXp

AUXn

SBU1

SBU2

AUXn

AUXp

AUXn

HPDIN

CTL

1

CTL

FLIP 0 1

FLIP 0

HPD

Control

CC1

CC2

CC1

CC2

PD Controller

Control

DIR1/DIR0/CTL1/CTL0/FLIP = L/H/H/L/L

DIR1/DIR0/CTL1/CTL0/FLIP = L/L/H/L/L

图 41. Four Lane DP – No Flip

USB/DP Source

USB/DP Sink

(4 Lane DP œ Flip)

D+/-

USB/DP

Sink

TUSB544

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

Type-C Cable

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

ML3

ML2

ML1

ML0

RX2

TX2

TX1

RX1

TX1

ML0

RX1

RX2

TX2

ML1

ML2

ML3

USB/DP

Source

SBU2

SBU1

AUXn

AUXp

AUXn

SBU1

SBU2

SBU1

SBU2

AUXp

SBU1

SBU2

AUXn

AUXp

HPDIN

CTL

1

CTL

FLIP 0 1

FLIP 0

HPD

Control

CC1

CC2

CC1

CC2

PD Controller

Control

DIR1/DIR0/CTL1/CTL0/FLIP = L/L/H/

L/H

DIR1/DIR0/CTL1/CTL0/FLIP = L/H/H/L/H

图 42. Four Lane DP – With Flip

49

TUSB544

ZHCSG75E –APRIL 2017–REVISED APRIL 2018

www.ti.com.cn

System Examples (接下页)

8.3.4 USB 3.1 only (USB/Custom Alternate Mode)

USB/Custom Source

USB/Custom Sink

(USB Only œ No Flip)

D+/-

TUSB544

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

Type-C Cable

TX1

RX1

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

TX1

RX1

USB/Custom

Source

USB/Custom

TX1

RX1

TX1

RX1

Sink

AUXp

AUXn

SBU1

SBU2

SBU1

AUXn

AUXp

HPDIN

CTL

1

CTL

FLIP 0 1

FLIP 0

HPD

Control

CC1

CC2

CC1

CC2

PD Controller

Control

DIR1/DIR0/CTL1/CTL0/FLIP = H/L/L/H/L

DIR1/DIR0/CTL1/CTL0/FLIP = H/H/L/H/L

图 43. USB3.1 Only – No Flip

USB/Custom Source

USB/Custom Sink

(USB Only œ Flip)

D+/-

TUSB544

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

Type-C Cable

RX2

TX2

RX2

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

TX2

USB/Custom

Source

Custom/USB

Sink

TX1

RX2

TX2

RX2

TX2

AUXp

AUXn

SBU1

SBU2

SBU1

AUXn

AUXp

HPDIN

CTL

1

CTL

FLIP 0 1

FLIP 0

HPD

Control

CC1

CC2

CC1

CC2

PD Controller

Control

DIR1/DIR0/CTL1/CTL0/FLIP = H/L/L/H/H

DIR1/DIR0/CTL1/CTL0/FLIP = H/H/L/H/H

图 44. USB3.1 Only – With Flip

50

TUSB544

www.ti.com.cn

ZHCSG75E –APRIL 2017–REVISED APRIL 2018

System Examples (接下页)

8.3.5 USB3.1 and 1 Lane of Custom Alt Mode

USB/Custom Sink

USB/Custom Source

(USB + 1 Lane Custom œ No Flip)

D+/-

USB/Custom

TUSB544

Sink

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

Type-C Cable

RX2

TX2

TX1

RX1

RX2

TX2

TX1

RX1

TX1

RX1

RX2

TX2

URX2

UTX2

DRX2

DTX2

TX1

RX1

RX2

TX2

USB/Custom

Source

DTX1

DRX1

UTX1

URX1

SBU2

SBU1

AUXn

AUXp

AUXn

SBU1

SBU2

SBU1

SBU2

AUXp

SBU1

SBU2

AUXn

AUXp

AUXn

HPDIN

CTL

1

CTL

FLIP 0 1

FLIP 0

HPD

Control

CC1

CC2

CC1

CC2

PD Controller

Control

DIR1/DIR0/CTL1/0/FLIP = H/L/H/H/L

DIR1/DIR0/CTL1/0/FLIP = H/H/H/H/L

图 45. USB3.1 + 1 Lane Custom Alt Mode – No Flip

USB/Custom Source

USB/Custom Sink

(USB + 1 Lane Custom œ Flip)

D+/-

USB/Custom

Sink

TUSB544

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

Type-C Cable

DRX2

DTX2

DTX1

DRX1

URX2

UTX2

UTX1

URX1

RX2

TX2

TX1

RX1

RX2

TX2

TX1

RX1

TX1

RX1

RX2

TX2

TX1

RX1

RX2

TX2

USB/Custom

Source

SBU2

SBU1

AUXn

AUXp

AUXn

SBU1

SBU2

SBU1

SBU2

AUXp

SBU1

SBU2

AUXn

AUXp

AUXn

HPDIN

CTL

1

CTL

FLIP 0 1

FLIP 0

CC1

CC2

HPD

CC1

CC2

HPD

PD Controller

Control

DIR1/DIR0/CTL1/0/FLIP = H/L/H/H/H

DIR1/DIR0/CTL1/0/FLIP = H/H/H/H/H

图 46. USB 3.1 + 1 Lane Custom Alt. Mode – Flip

51

TUSB544

ZHCSG75E –APRIL 2017–REVISED APRIL 2018

www.ti.com.cn

System Examples (接下页)

8.3.6 USB3.1 and 2 Lane of Custom Alt Mode

USB/Custom Source

USB/Custom Sink

(USB + 2 Lane Custom œ No Flip)

D+/-

USB/Custom

Sink

TUSB544

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

Type-C Cable

LN0

LN1

TX1

RX1

RX2

TX2

TX1

RX1

TX1

RX1

RX2

TX2

URX2

UTX2

DRX2

TX1

RX1

DTX2

DTX1

DRX1

USB/Custom

Source

UTX1

URX1

LN1

LN0

AUXp

AUXn

SBU1

SBU2

SBU1

AUXn

AUXp

SBU1

SBU2

AUXp

SBU1

SBU2

AUXn

AUXp

AUXn

HPDIN

CTL

1

CTL

FLIP 0 1

FLIP 0

HPD

Control

CC1

CC2

CC1

CC2

PD Controller

Control

DIR1/DIR0/CTL1/CTL0/FLIP = H/L/H/H/L

DIR1/DIR0/CTL1/CTL0/FLIP = H/H/H/H/L

图 47. Two Lane Custom Alternate Mode – No Flip

USB/Custom Source

USB/Custom Sink

(USB + 2 Lane Custom œ Flip)

D+/-

USB/Custom

Sink

TUSB544

DRX2

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

Type-C Cable

URX2

UTX2

UTX1

URX1

RX2

TX2

LN1

LN0

RX2

TX2

TX1

RX1

TX1

RX1

RX2

TX2

LN0

LN1

DTX2

DTX1

DRX1

USB/Custom

Source

RX2

TX2

SBU2

SBU1

AUXn

AUXp

AUXn

SBU1

SBU2

SBU1

SBU2

AUXp

SBU1

SBU2

AUXn

AUXp

AUXn

HPDIN

CTL

1

CTL

FLIP 0 1

FLIP 0

HPD

Control

CC1

CC2

CC1

CC2

PD Controller

Control

DIR1/DIR0/CTL1/CTL0/FLIP = H/L/H/H/H

DIR1/DIR0/CTL1/CTL0/FLIP = H/H/H/H/H

图 48. Two Lane Custom Alternate Mode – With Flip

52

TUSB544

www.ti.com.cn

ZHCSG75E –APRIL 2017–REVISED APRIL 2018

System Examples (接下页)

8.3.7 USB3.1 and 4 Lane of Custom Alt Mode

USB/Custom Source

USB/Custom Sink

(4 Lane Custom œ No Flip)

D+/-

USB/Custom

Sink

TUSB544

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

Type-C Cable

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

LN0

LN1

LN2

LN3

RX2

TX2

TX1

RX1

TX1

RX1

RX2

TX2

LN3

LN2

USB/Custom

Source

LN1

LN0

SBU2

SBU1

AUXn

AUXp

SBU1

SBU2

AUXp

SBU1

SBU2

AUXp

AUXn

SBU1

SBU2

AUXn

AUXp

AUXn

HPDIN

CTL

1

CTL

FLIP 0 1

FLIP 0

HPD

Control

CC1

CC2

CC1

CC2

PD Controller

Control

DIR1/DIR0/CTL1/CTL0/FLIP = H/L/H/L/L

DIR1/DIR0/CTL1/CTL0/FLIP = H/H/H/L/L

图 49. Four Lane Custom Alternate Mode – No Flip

USB/Custom Source

USB/Custom Sink

(4 Lane Custom œ Flip)

D+/-

USB/Custom

Sink

TUSB544

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

Type-C Cable

URX2

UTX2

UTX1

URX1

DRX2

DTX2

DTX1

DRX1

LN3

LN2

LN1

LN0

RX2

TX2

TX1

RX1

TX1

RX1

RX2

TX2

LN0

LN1

USB/Custom

Source

LN2

LN3

SBU2

SBU1

AUXn

AUXp

AUXn

SBU1

SBU2

SBU1

SBU2

AUXp

SBU1

SBU2

AUXn

AUXp

HPDIN

CTL

1

CTL

FLIP 0 1

FLIP 0

HPD

Control

CC1

CC2

DIR1/DIR0/CTL1/CTL0/FLIP = H/L/H/L/H

CC1

CC2

PD Controller

Control

DIR1/DIR0/CTL1/CTL0/FLIP = H/H/H/L/H

图 50. Four Lane Custom Alternate Mode – With Flip

53

TUSB544

ZHCSG75E –APRIL 2017–REVISED APRIL 2018

www.ti.com.cn

9 Power Supply Recommendations

The TUSB544 is designed to operate with a 3.3 V power supply. Levels above those listed in the Absolute

Maximum Ratings table should not be used. If using a higher voltage system power supply, a voltage regulator

can be used to step down to 3.3 V. Decoupling capacitors should be used to reduce noise and improve power

supply integrity. A 0.1-µF capacitor should be used on each power pin.

54

TUSB544

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ZHCSG75E –APRIL 2017–REVISED APRIL 2018

10 Layout

10.1 Layout Guidelines

1. RXP/N and TXP/N pairs should be routed with controlled 90-Ohm differential impedance (+/- 15%).

2. Keep away from other high speed signals.

3. Intra-pair routing should be kept to within 2 mils.

4. Length matching should be near the location of mismatch.

5. Each pair should be separated at least by 3 times the signal trace width.

6. The use of bends in differential traces should be kept to a minimum. When bends are used, the number of

left and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This

will minimize any length mismatch causes by the bends and therefore minimize the impact bends have on

EMI.

7. Route all differential pairs on the same of layer.

8. The number of VIAS should be kept to a minimum. It is recommended to keep the VIAS count to 2 or less.

9. Keep traces on layers adjacent to ground plane.

10. Do NOT route differential pairs over any plane split.

11. Adding Test points will cause impedance discontinuity; and therefore, negatively impacts signal

performance. If test points are used, the test points should be placed in series and symmetrically. The test

points must not be placed in a manner that causes a stub on the differential pair.

10.2 Layout Example

AC Coupling

capacitors

DRX2

DTX2

URX2

UTX2

UTX1

GND

DTX1

DRX1

URX1

图 51.

55

TUSB544

ZHCSG75E –APRIL 2017–REVISED APRIL 2018

www.ti.com.cn

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

本节标识的文档均在本规范中引用。为简化文本，文中的大多数参考文献均用文档标签 [文档标签] 标识，而不使用

完整的文档标题。


型号：	TUSB544IRNQR
厂家：	TEXAS INSTRUMENTS
描述：	USB Type-C™ 8.1 Gbps 多协议线性转接驱动器 \| RNQ \| 40 \| -40 to 85 驱动驱动器
文件：	总64页 (文件大小：2008K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TUSB544IRNQR [TI]

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