TUSB546AI-DCIRNQR [TI]
USB Type-C™ 8.1Gbps 多协议拉电流侧线性转接驱动器交叉点开关 | RNQ | 40 | -40 to 85;
| 型号： | TUSB546AI-DCIRNQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | USB Type-C™ 8.1Gbps 多协议拉电流侧线性转接驱动器交叉点开关 | RNQ | 40 | -40 to 85 开关 驱动 驱动器 |
| 文件： | 总49页 (文件大小：1598K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TUSB546A-DCI
ZHCSGH4B –JUNE 2017–REVISED MAY 2019
TUSB546A-DCI USB Type-C™ DP 交替模式线性转接驱动器交叉点开关
1 特性
3 说明
1
•
USB Type-C 交叉点开关支持
TUSB546-DCI 是一种 VESA USB Type-C™ 交替模式
转接驱动开关，对于下行端口（主机），支持高达
5Gbps 的 USB 3.1 数据传输速率以及高达 8.1Gbps 的
DisplayPort 1.4 数据传输速率。这款 VESA
DisplayPort Alt 模式器件支持基于 USB Type-C 标准
1.1 版本的配置 C、D、E 和 F。此线性转接驱动器与
协议无关，并且还支持其他 USB Type-C Alt 模式接
口。
–
–
USB 3.1 SS + 2 条 DP 信道
4 条 DP 信道
•
•
•
USB 3.1 第 1 代高达 5Gbps
DisplayPort™1.4 高达 8.1Gbps (HBR3)
支持 c、d、e 和 f 配置的 VESA DisplayPort 交替
模式 DFP 转接驱动交叉点开关
•
•
•
•
•
•
超低功耗架构
具有高达 14dB 均衡功能的线性转接驱动器
透明呈现 DisplayPort 链路训练
自动 LFPS 去加重控制，满足 USB 3.1 认证要求
可通过 GPIO 或 I2C 进行配置
TUSB546A-DCI 提供有多个接收线性均衡级别，用于
补偿由于线缆或电路板走线损耗产生的码间串扰
(ISI)。该器件由 3.3V 单电源供电运行，支持商业级温
度范围和工业级温度范围。
基于 USB Type-C™ 的 Intel 专有 DCI 功能，可实
现不开箱调试
器件信息(1)
•
•
•
•
支持热插拔
器件型号
TUSB546A-DCI
TUSB546AI-DCI
封装
封装尺寸（标称值）
工业温度范围：-40ºC 至 85ºC (TUSB546AI-DCI)
商业级温度范围：0ºC 至 70ºC (TUSB546A-DCI)
4mm x 6mm、0.4mm 间距 WQFN 封装
WQFN (40)
4.00mm x 6.00mm
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
2 应用
•
•
•
•
平板电脑
笔记本电脑
台式机
扩展坞
简化电路原理图
TUSB546A-DCI 眼图
D+/-
TUSB546A-DCI
USB Host
SSTX
SSRX
TUSB546A-DCI
RX2
TX2
TX1
RX1
DP0
DP1
DP2
GPU
DP3
SBU1
SBU2
AUXp
AUXn
HPDIN
FLIP 0 1 CTL
PD Controller
CC1
CC2
HPD
Control
Copyright © 2017, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSF14
TUSB546A-DCI
ZHCSGH4B –JUNE 2017–REVISED MAY 2019
www.ti.com.cn
目录
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 17
8.5 Programming........................................................... 22
8.6 Register Maps......................................................... 24
Application and Implementation ........................ 29
9.1 Application Information............................................ 29
9.2 Typical Application ................................................. 29
9.3 System Examples .................................................. 33
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Power Supply Characteristics ................................... 6
6.6 DC Electrical Characteristics .................................... 6
6.7 AC Electrical Characteristics..................................... 7
6.8 DCI Specific Electrical Characteristics...................... 8
6.9 Timing Requirements................................................ 9
6.10 Switching Characteristics........................................ 9
6.11 Typical Characteristics.......................................... 10
Parameter Measurement Information ................ 12
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 15
9
10 Power Supply Recommendations ..................... 38
11 Layout................................................................... 39
11.1 Layout Guidelines ................................................. 39
11.2 Layout Example .................................................... 39
12 器件和文档支持 ..................................................... 40
12.1 器件支持 ............................................................... 40
12.2 相关链接................................................................ 40
12.3 接收文档更新通知 ................................................. 40
12.4 社区资源................................................................ 40
12.5 商标....................................................................... 40
12.6 静电放电警告......................................................... 40
12.7 术语表 ................................................................... 40
13 机械、封装和可订购信息....................................... 41
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (April 2018) to Revision B
Page
•
Added following to pin 11 description: If I2C_EN = “F”, then this pin must be set to “F” or “0”. ........................................... 4
Changes from Original (June 2017) to Revision A
Page
•
•
•
•
Changed the appearance of the pinout image in the Pin Configuration and Function section.............................................. 3
Added Note 1 to the Pin Functions table................................................................................................................................ 3
Changed the USB3.1 Control/Status Registers reset value From: 00000000 To: 00000100.............................................. 28
Changed the Reset value of bit 3:2 From: 00 To: 01 in Table 18 ....................................................................................... 28
2
Copyright © 2017–2019, Texas Instruments Incorporated
TUSB546A-DCI
www.ti.com.cn
ZHCSGH4B –JUNE 2017–REVISED MAY 2019
5 Pin Configuration and Functions
RNQ Package
40-Pin (WQFN)
Top View
VCC
1
28
27
26
25
24
23
22
21
VCC
DPEQ1
SSEQ1
2
3
SBU1
SBU2
SSRXn
SSRXp
VCC
4
5
6
7
8
AUXn
Thermal
Pad
AUXp
CTL1/HPDIN
CTL0/SDA
FLIP/SCL
SSTXn
SSTXp
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
DP0p
DP0n
DP1p
DP1n
DP2p
DP2n
DP3p
DP3n
NO.
9
Diff I
Diff I
Diff I
Diff I
Diff I
Diff I
Diff I
Diff I
DP Differential positive input for DisplayPort Lane 0.
DP Differential negative input for DisplayPort Lane 0.
DP Differential positive input for DisplayPort Lane 1.
DP Differential negative input for DisplayPort Lane 1.
DP Differential positive input for DisplayPort Lane 2.
DP Differential negative input for DisplayPort Lane 2.
DP Differential positive input for DisplayPort Lane 3.
DP Differential negative input for DisplayPort Lane 3.
10
12
13
15
16
18
19
Differential negative output for DisplayPort or differential negative input for USB3.1 Downstream
Facing port.
RX1n
RX1p
31
30
Diff I/O
Diff I/O
Differential positive output for DisplayPort or differential positive input for USB3.1 Downstream
Facing port.
TX1n
TX1p
TX2p
TX2n
34
33
37
36
Diff O
Diff O
Diff O
Diff O
Differential negative output for DisplayPort or USB3.1 downstream facing port.
Differential positive output for DisplayPort or USB 3.1 downstream facing port.
Differential positive output for DisplayPort or USB 3.1 downstream facing port.
Differential negative output for DisplayPort or USB 3.1 downstream facing port.
Differential positive output for DisplayPort or differential positive input for USB3.1 Downstream
Facing port.
RX2p
RX2n
40
39
Diff I/O
Diff I/O
Differential negative output for DisplayPort or differential negative input for USB3.1 Downstream
Facing port.
Copyright © 2017–2019, Texas Instruments Incorporated
3
TUSB546A-DCI
ZHCSGH4B –JUNE 2017–REVISED MAY 2019
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
SSTXp
SSTXn
SSRXp
SSRXn
NO.
8
Diff I
Diff I
Differential positive input for USB3.1 upstream facing port.
Differential negative input for USB3.1 upstream facing port.
Differential positive output for USB3.1 upstream facing port.
Differential negative output for USB3.1 upstream facing port.
7
5
Diff O
Diff O
4
This pin along with EQ0 sets the USB receiver equalizer gain for downstream facing RX1 and RX2
when USB used. Up to 11dB of EQ available.
EQ1
EQ0
35
38
4 Level I
4 Level I
This pin along with EQ1 sets the USB receiver equalizer gain for downstream facing RX1 and RX2
when USB used. Up to 11 dB of EQ available.
When I2C_EN ! = 0, this pin functions as DCI data output Leave open if not used. When I2C_EN =
0 , this pin is CAD_SNK (L = AUX snoop enabled and H = AUX snoop disabled with all lanes
active).
I/O
(PD)
CAD_SNK/DCI_DAT(1)
HPDIN/DCI_CLK(1)
29
32
When I2C_EN ! = 0, this pin is functions as DCI clock output Leave open if not used. When
I2C_EN = 0, this pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN
is Low for greater than 2ms, all DisplayPort lanes are disabled while the AUX to SBU switch will
remain closed.
I/O
(PD)
I2C Programming Mode or GPIO Programming Select. I2C is only disabled when this pin is ‘0".
0 = GPIO mode (I2C disabled)
R = TI Test Mode (I2C enabled at 3.3 V)
F = I2C enabled at 1.8 V
1 = I2C enabled at 3.3 V.
I2C_EN
17
4 Level I
SBU1. This pin should be DC coupled to the SBU1 pin on the Type-C receptacle. A 2-M ohm
resistor to GND is also recommended.
SBU1
SBU2
27
26
I/O, CMOS
I/O, CMOS
SBU2. This pin should be DC coupled to the SBU2 pin on the Type-C receptacle. A 2-M ohm
resistor to GND is also recommended.
AUXp. DisplayPort AUX positive I/O connected to the DisplayPort source through a AC coupling
capacitor. In addition to AC coupling capacitor, this pin also requires a 100K resistor to GND. This
pin along with AUXN is used by the TUSB546A-DCI for AUX snooping and is routed to SBU1/2
based on the orientation of the Type-C.
AUXp
24
I/O, CMOS
AUXn. DisplayPort AUX negative I/O connected to the DisplayPort source through a AC coupling
capacitor. In addition to AC coupling capacitor, this pin also requires a 100K resistor to DP_PWR
(3.3V). This pin along with AUXP is used by the TUSB546A-DCI for AUX snooping and is routed to
SBU1/2 based on the orientation of the Type-C.
AUXn
25
2
I/O, CMOS
4 Level I
DisplayPort Receiver EQ. This along with DPEQ0 will select the DisplayPort receiver equalization
gain.
DPEQ1
DisplayPort Receiver EQ. This along with DPEQ1 will select the DisplayPort receiver equalization
gain. When I2C_EN is not ‘0’, this pin will also set the TUSB546A-DCI I2C address.
DPEQ0/A1
SSEQ1
14
3
4 Level I
4 Level I
Along with SSEQ0, sets the USB receiver equalizer gain for upstream facing SSTXP/N.
Along with SSEQ1, sets the USB receiver equalizer gain for upstream facing SSTXP/N. When
I2C_EN is not ‘0’, this pin will also set the TUSB546A-DCI I2C address. If I2C_EN = “F”, then this
pin must be set to “F” or “0”.
SSEQ0/A0
11
4 Level I
When I2C_EN=’0’ this is Flip control pin, otherwise this pin is I2C clock. . When used for I2C clock
pullup to I2C master's VCC I2C supply.
FLIP/SCL
21
22
2 Level I
2 Level I
When I2C_EN=’0’ this is a USB3.1 Switch control pin, otherwise this pin is I2C data. When used
for I2C data pullup to I2C master's VCC I2C supply.
CTL0/SDA
DP Alt mode Switch Control Pin. When I2C_EN = ‘0’, this pin will enable or disable DisplayPort
functionality. Otherwise, when I2C_EN is not "0", DisplayPort functionality is enabled and disabled
through I2C registers.
L = DisplayPort Disabled.
H = DisplayPort Enabled.
When I2C_EN is not "0" this pin is an input for Hot Plug Detect received from DisplayPort sink.
When this HPDIN is Low for greater than 2 ms, all DisplayPort lanes are disabled and AUX to SBU
switch will remain closed.
2 Level I
(Failsafe)
(PD)
CTL1/HPDIN
23
VCC
1, 6, 20, 28
P
3.3-V Power Supply
Ground
Thermal Pad
G
(1) Not a fail-safe I/O. Actively driving pin high while VCC is removed results in leakage voltage on VCC pins.
4
Copyright © 2017–2019, Texas Instruments Incorporated
TUSB546A-DCI
www.ti.com.cn
ZHCSGH4B –JUNE 2017–REVISED MAY 2019
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply Voltage Range(2), VCC
–0.3
4
V
Differential voltage between positive and
negative inputs
±2.5
V
Voltage Range at any input or output pin
Voltage at differential inputs
CMOS Inputs
–0.5
–0.5
VCC + 0.5
VCC + 0.5
125
V
V
Maximum junction temperature, TJ
Storage temperature, Tstg
°C
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND terminals.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±5000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
3.6
100
3.6
100
70
UNIT
V
Main power supply
3
3.3
VCC
Supply Ramp Requirement
ms
V
V(12C)
V(PSN)
Supply that external resistors are pulled up to on SDA and SCL
Supply Noise on VCC pins
1.7
mV
°C
TUSB546A-DCI
Operating free-air temperature
0
TA
TUSB546I-DCI
–40
85
°C
6.4 Thermal Information
TUSB546A-DCI
THERMAL METRIC(1)
RNQ (WQFN)
UNIT
40 PINS
37.6
20.7
9.5
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
9.4
RθJC(bot)
2.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017–2019, Texas Instruments Incorporated
5
TUSB546A-DCI
ZHCSGH4B –JUNE 2017–REVISED MAY 2019
www.ti.com.cn
6.5 Power Supply Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Link in U0 with GEN1 data transmission.
EN, EQ cntrl pins = NC, k28.5 pattern at
Average active power
USB Only
PCC(ACTIVE-USB)
335
mW
5 Gbps, VID = 1000 mVPP
CTL1 = L; CTL0 = H
;
Link in U0 with GEN1 data transmission.
EN, EQ cntrl pins = NC, k28.5 pattern at
Average active power
USB + 2 Lane DP
PCC(ACTIVE-USB-DP1)
634
mW
5 Gbps, VID = 1000 mVPP
;
CTL1 = H; CTL0 = H
Four active DP lanes operating at
8.1Gbps;
CTL1 = H; CTL0 = L;
Average active power
4 Lane DP Only
PCC(ACTIVE--DP)
660
2.4
mW
mW
No GEN1 device is connected to
TXP/TXN;
PCC(NC-USB)
Average power with no connection
CTL1 = L; CTL0 = H;
Link in U2 or U3 USB Mode Only;
CTL1 = L; CTL0 = H;
PCC(U2U3)
Average power in U2/U3
Device Shutdown
3.0
mW
mW
PCC(SHUTDOWN)
CTL1 = L; CTL0 = L; I2C_EN = 0;
0.85
6.6 DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4-State CMOS Inputs(EQ[1:0], SSEQ[1:0], DPEQ[1:0], I2C_EN)
IIH
IIL
High level input current
Low level input current
Threshold 0 / R
VCC = 3.6 V; VIN = 3.6 V
VCC = 3.6 V; VIN = 0 V
VCC = 3.3 V
20
80
µA
µA
V
–160
-40
0.55
1.65
2.7
35
4-Level VTH
Threshold R/ Float
VCC = 3.3 V
V
Threshold Float / 1
VCC = 3.3 V
V
RPU
RPD
Internal pull-up resistance
Internal pull-down resistance
kΩ
kΩ
95
2-State CMOS Input (CTL0, CTL1, FLIP, CAD_SNK, HPDIN) CTL1, CTL0 and FLIP are Failsafe.
VIH
VIL
High-level input voltage
2
0
3.6
0.8
V
V
Low-level input voltage
RPD
Internal pull-down resistance for CTL1
500
150
kΩ
Internal pull-down resistance for
CAD_SNK (pin 29), and HPDIN (pin 32)
R(ENPD)
kΩ
IIH
IIL
High-level input current
Low-level input current
VIN = 3.6 V
–25
–25
25
25
µA
µA
VIN = GND, VCC = 3.6 V
I2C Control Pins SCL, SDA
VIH
High-level input voltage
I2C_EN = 0
0.7 x V(I2C)
3.6
0.3 x V(I2C)
0.4
V
V
VIL
Low-level input voltage
Low-level output voltage
Low-level output current
Input current on SDA pin
Input capacitance
I2C_EN = 0
0
0
VOL
IOL
I2C_EN = 0; IOL = 3 mA
I2C_EN = 0; VOL = 0.4 V
0.1 x V(I2C) < Input voltage < 3.3 V
V
20
mA
µA
pF
pF
pF
II(I2C)
CI(I2C)
–10
10
10
C(I2C_FM+_BUS) I2C bus capacitance for FM+ (1MHz)
150
150
C(I2C_FM_BUS)
R(EXT_I2C_FM+)
I2C bus capacitance for FM (400kHz)
External resistors on both SDA and SCL
when operating at FM+ (1MHz)
C(I2C_FM+_BUS) = 150 pF
C(I2C_FM_BUS) = 150 pF
620
620
820
910
Ω
Ω
External resistors on both SDA and SCL
when operating at FM (400kHz)
R(EXT_I2C_FM)
1500
2200
6
Copyright © 2017–2019, Texas Instruments Incorporated
TUSB546A-DCI
www.ti.com.cn
ZHCSGH4B –JUNE 2017–REVISED MAY 2019
6.7 AC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
USB Gen 1 Differential Receiver (RX1P/N, RX2P/N, SSTXP/N)
AC-coupled differential peak-to-peak
signal measured post CTLE through a
reference channel
Input differential peak-peak voltage
V(RX-DIFF-PP)
2000
0
mVpp
swing linear dynamic range
Common-mode voltage bias in the
receiver (DC)
V(RX-DC-CM)
V
Ω
Ω
Present after a GEN1 device is
detected on TXP/TXN
R(RX-DIFF-DC)
R(RX-CM-DC)
Differential input impedance (DC)
72
18
120
30
Receiver DC common mode
impedance
Present after a GEN1 device is
detected on TXP/TXN
Present when no GEN1 device is
detected on TXP/TXN. Measured over
the range of 0-500mV with respect to
GND.
Common-mode input impedance with
termination disabled (DC)
Z(RX-HIGH-IMP-DC-POS)
25
kΩ
Input differential peak-to-peak signal
detect assert level
At 5 Gbps, no input loss, PRBS7
pattern
V(SIGNAL-DET-DIFF-PP)
V(RX-IDLE-DET-DIFF-PP)
V(RX-LFPS-DET-DIFF-PP)
80
60
mV
mV
mV
Input differential peak-to-peak signal
detect de-assert Level
At 5 Gbps, no input loss, PRBS7
pattern
Low frequency periodic signaling
(LFPS) detect threshold
Below the minimum is squelched
100
300
V(RX-CM-AC-P)
C(RX)
Peak RX AC common-mode voltage
RX input capacitance to GND
Measured at package pin
At 2.5 GHz
150
1
mV
pF
dB
dB
dB
dB
0.5
–19
–14
–13
50 MHz – 1.25 GHz at 90 Ω
2.5 GHz at 90 Ω
RL(RX-DIFF)
Differential return Loss
RL(RX-CM)
EQ(SSP)
Common-mode return loss
Receiver equalization
50 MHz – 2.5 GHz at 90 Ω
SSEQ[1:0] and EQ[1:0] at 2.5 GHz
11
USB Gen 1 Differential Transmitter (TX1P/N, TX2P/N, SSRXP/N)
VTX(DIFF-PP)
Transmitter dynamic differential voltage swing range
1500
1.75
mVPP
mV
VTX(RCV-DETECT)
Amount of voltage change allowed during receiver detection
600
600
Transmitter idle common-mode voltage change while in U2/U3 and not actively
transmitting LFPS
VTX(CM-IDLE-DELTA)
VTX(DC-CM)
–600
mV
V
Common-mode voltage bias in the transmitter (DC)
Max mismatch from Txp + Txn for both
Tx AC common-mode voltage active
VTX(CM-AC-PP-ACTIVE)
100
10
mVPP
time and amplitude
AC electrical idle differential peak-to-
At package pins
VTX(IDLE-DIFF-AC-PP)
VTX(IDLE-DIFF-DC)
0
0
mV
mV
mV
peak output voltage
DC electrical idle differential output
voltage
At package pins after low pass filter to
remove AC component
14
VTX(CM-DC-ACTIVE-IDLE- Absolute DC common-mode voltage
At package pin
200
between U1 and U0
DELTA)
RTX(DIFF)
Differential impedance of the driver
AC coupling capacitor
75
75
120
265
Ω
CAC(COUPLING)
nF
Measured with respect to AC ground
over
0–500 mV
Common-mode impedance of the
driver
RTX(CM)
18
30
Ω
ITX(SHORT)
TX short circuit current
TXP/N shorted to GND
At package pins, at 2.5GHz
50 MHz – 1.25 GHz at 90 Ω
2.5 GHz at 90 Ω
67
mA
pF
dB
dB
dB
CTX(PARASITIC)
TX input capacitance for return loss
1.25
-15
-12
-13
RLTX(DIFF)
Differential return loss
RLTX(CM)
Common-mode return loss
50 MHz – 2.5 GHz at 90 Ω
AC Characteristics
Differential crosstalk between TX and
RX signal pairs
Crosstalk
C(P1dB-LF)
C(P1dB-HF)
at 2.5 GHz
–30
1300
1300
dB
Low frequency 1-dB compression
point
at 100 MHz, 200 mVPP < VID
< 2000 mVPP
mVPP
mVPP
High frequency 1-dB compression
point
at 2.5 GHz, 200 mVPP < VID
< 2000 mVPP
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AC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fLF
Low frequency cutoff
200 mVPP< VID < 2000 mVPP
20
50
kHz
200 mVPP < VID < 2000 mVPP, PRBS7,
5 Gbps
0.05
0.08
UIpp
UIpp
UIpp
UIpp
TX output deterministic jitter
TX output total jitter
200 mVPP < VID < 2000 mVPP, PRBS7,
8.1 Gbps
200 mVPP < VID < 2000 mVPP, PRBS7,
5 Gbps
0.08
200 mVPP < VID < 2000 mVPP, PRBS7,
8.1 Gbps
0.135
DisplayPort Receiver (DP[3:0]p or DP[3:0]n)
VID(PP) Peak-to-peak input differential dynamic voltage range
VIC
2000
0
V
V
Input common mode voltage
AC coupling capacitance
Receiver equalization
Data rate
C(AC)
EQ(DP)
dR
75
80
200
14
nF
DPEQ[1:0] at 4.05 GHz
HBR3
dB
Gbps
Ω
8.1
120
R(ti)
Input termination resistance
100
DisplayPort Transmitter (TX1p or TX1n, TX2p or TX2n, RX1p or RX1n, RX2p or RX2n)
ITX(SHORT) TX short circuit current TX± shorted to GND
VTX(DC-CM) Common-mode voltage bias in the transmitter (DC)
AUXp or AUXn and SBU1 or SBU2
67
mA
V
1.75
5
VCC = 3.3V; VI = 0 to 0.4 V for AUXp;
VI = 2.7 V to 3.6 V for AUXn
RON
Output ON resistance
10
Ω
Ω
VCC = 3.3 V; VI = 0 to 0.4 V for AUXP;
VI = 2.7 V to 3.6 V for AUXN
ΔRON
ON resistance mismatch within pair
2.5
ON resistance flatness (RON max –
RON min) measured at identical VCC
and temperature
VCC = 3.3 V; VI = 0 to 0.4 V for AUXp;
VI = 2.7 V to 3.6 V for AUXn
RON(FLAT)
2
Ω
AUX Channel DC common mode
voltage for AUXp and SBU1.
V(AUXP_DC_CM)
V(AUXN_DC_CM)
C(AUX_ON)
VCC = 3.3 V
VCC = 3.3 V
0
0.4
3.6
7
V
V
AUX Channel DC common mode
voltage for AUXn and SBU2
2.7
VCC = 3.3 V; CTL1 = 1; VI = 0 V
or 3.3 V
ON-state capacitance
OFF-state capacitance
4
3
pF
pF
VCC = 3.3 V; CTL1 = 0; VI = 0 V
or 3.3 V
C(AUX_OFF)
6
6.8 DCI Specific Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.45
33
UNIT
DCI_CLK and DCI_DAT LVCMOS Outputs
VOL
Low-Level output voltage
High-Level output voltage
Output characteristic impedance
DCI Clock period
VCC = 3 V; IOL = 2 mA; CL = 10 pF
VCC = 3 V; IOL = –2 mA;
V
V
VOH
2.4
21
RDCI
tPERIOD
25
Ω
Measured at 50%
6.67
ns
Rising edge of DCI clock to DCI
data valid
tVALID
1
ns
tDCI_RISE
tDCI_FALL
DCI output rise time
DCI output fall time
Measured at 20% to 80%.
Measured at 80% to 20%
350
350
ps
ps
8
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6.9 Timing Requirements
MIN
NOM
MAX
UNIT
USB Gen 1
tIDLEEntry
Delay from U0 to electrical idle
See Figure 14
See Figure 14
10
6
ns
ns
U1 exist time: break in electrical idle to
the transmission of LFPS
tIDELExit_U1
tIDLEExit_U2U3
tRXDET_INTVL
tIDLEExit_DISC
tExit_SHTDN
tDIFF_DLY
U2/U3 exit time: break in electrical idle to transmission of LFPS
RX detect interval while in Disconnect
Disconnect Exit Time
10
µs
ms
µs
12
10
1
Shutdown Exit Time
ms
ps
Differential Propagation Delay
See Figure 13
300
20%-80% of differential
voltage measured 1 inch
from the output pin
tR, tF
Output Rise/Fall time (see Figure 15)
40
ps
ps
20%-80% of differential
voltage measured 1 inch
from the output pin
tRF_MM
Output Rise/Fall time mismatch
2.6
6.10 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUXp or AUXn and SBU1 or SBU2
tAUX_PD
Switch propagation delay
400
500
ps
ns
Switching time CTL1 to switch OFF. Not including
TCTL1_DEBOUNCE.
tAUX_SW_OFF
tAUX_SW_ON
tAUX_INTRA
Switching time CTL1 to switch ON
Intra-pair output skew
500
100
ns
ps
USB3.1 and DisplayPort mode transition requirement GPIO mode
Min overlap of CTL0 and CTL1 when transitioning from USB 3.1 only
mode to 4-Lane DisplayPort mode or vice versa.
tGP_USB_4DP
4
2
µs
CTL1 and HPDIN
tCTL1_DEBOUNCE CTL1 and HPDIN debounce time when transitioning from H to L.
I2C (Refer to Figure 11)
10
1
ms
fSCL
tBUF
I2C clock frequency
MHz
µs
Bus free time between START and STOP conditions
0.5
Hold time after repeated START condition. After this period, the first
clock pulse is generated
tHDSTA
0.26
µs
tLOW
Low period of the I2C clock
High period of the I2C clock
Setup time for a repeated START condition
Data hold time
0.5
0.26
0.26
0
µs
µs
µs
μs
ns
ns
tHIGH
tSUSTA
tHDDAT
tSUDAT
tR
Data setup time
50
Rise time of both SDA and SCL signals
120
120
20 × (V(I2C)/5.5
V)
tF
Fall time of both SDA and SCL signals
ns
tSUSTO
Cb
Setup time for STOP condition
Capacitive load for each bus line
0.26
μs
150
pF
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6.11 Typical Characteristics
15
10
5
15
10
5
0
0
-5
-5
EQ0
EQ1
EQ2
EQ3
EQ4
EQ5
EQ6
EQ7
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
EQ0
EQ1
EQ2
EQ3
EQ4
EQ5
EQ6
EQ7
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
-10
-10
-15
-15
0.01
0.1
1
Frequency (GHz)
10
0.01
0.1
1
Frequency (GHz)
10
D001
D002
Figure 1. DisplayPort EQ Settings Curves
Figure 2. USB RX EQ Settings Curves
15
10
5
1.6
1.4
1.2
1
0
0.8
0.6
0.4
0.2
0
-5
EQ0
EQ1
EQ2
EQ3
EQ4
EQ5
EQ6
EQ7
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
EQ0
EQ1
EQ2
EQ3
EQ4
EQ5
EQ6
EQ7
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
-10
-15
0.01
0.1
1
Frequency (GHz)
10
0
0.2 0.4 0.6 0.8
1
Differential Input Voltage (V)
1.2 1.4 1.6 1.8
2
D003
D004
Figure 3. USB TX EQ Settings Curves
Figure 4. DisplayPort Linearity Curves at 4.05 GHz
1.8
1.6
1.4
1.2
1
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
EQ0
EQ1
EQ2
EQ3
EQ4
EQ5
EQ6
EQ7
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
EQ0
EQ1
EQ2
EQ3
EQ4
EQ5
EQ6
EQ7
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
0
0.2 0.4 0.6 0.8
1
Differential Input Voltage (V)
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
Differential Input Voltage (V)
1.2 1.4 1.6 1.8
2
D005
D006
Figure 5. USB TX Linearity Curves at 2.5 GHz
Figure 6. USB RX Linearity Curves at 2.5 GHz
10
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Typical Characteristics (continued)
5
5
0
DP0
DP1
DP2
DP3
SSTX
RX1
RX2
RX1
RX2
TX1
TX2
SSRX
0
-5
-5
-10
-15
-20
-25
-30
-35
-40
-10
-15
-20
-25
-30
0.01
0.1
1
Frequency (GHz)
10
0.01
0.1
1
Frequency (GHz)
10
D007
D008
Figure 7. Input Return Loss Performance
Figure 8. Output Return Loss Performance
Time (20.57 ps/Div)
Time (33.33 ps/Div)
Figure 9. DisplayPort HBR3 Eye-Pattern Performance with
12-inch Input PCB Trace at 8.1 Gbps
Figure 10. USB 3.1 Gen1 Eye-Pattern Performance with
12-inch Input PCB Trace at 5 Gbps
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7 Parameter Measurement Information
70%
SDA
30%
t
t
t
F
HDSTA
R
tHIGH
t
t
LOW
BUF
70%
30%
SCL
S
P
P
S
t
t
SUSTO
t
t
SUDAT
HDDAT
HDSTA
t
SUSTA
Figure 11. I2C Timing Diagram Definitions
4us
(min)
CTL1 pin
CTL0 pin
Figure 12. USB3.1 to 4-Lane DisplayPort in GPIO Mode
IN
T
T
DIFF_DLY
DIFF_DLY
OUT
Figure 13. Propagation Delay
12
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Parameter Measurement Information (continued)
IN+
V
Vcm
RX-LFPS-DET-DIFF-PP
IN-
T
T
IDLEEntry
IDLEExit
OUT+
Vcm
OUT-
Figure 14. Electrical Idle Mode Exit and Entry Delay
80%
20%
t
r
t
f
Figure 15. Output Rise and Fall Times
50%
50%
CTL1
90%
10%
V
OUT
T
AUX_SW_ON
T
+ T
CTL1_DEBOUNCE
AUX_SW_OFF
Figure 16. AUX and SBU Switch ON and OFF Timing Diagram
TDCI_CLK_PD
TDCI_CLK_PD
VIH_MIN
RX1N
or
RX2N
VIH_MAX
VOH_MIN
DCI_CLK
VOL_MAX
Figure 17. DCI Clock Propagation Delay
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8 Detailed Description
8.1 Overview
The TUSB546A-DCI is a VESA USB Type-C Alt Mode redriving switch supporting data rates up to 8.1 Gbps for
downstream facing port. These devices utilize 5th generation USB redriver technology. The devices are utilized
for DFP configurations C, D, E, and F from the VESA DisplayPort Alt Mode on USB Type-C.
The TUSB546A-DCI provides several levels of receive equalization to compensate for cable and board trace loss
due to inter-symbol interference (ISI) when USB 3.1 Gen1 or DisplayPort 1.4 signals travel across a PCB or
cable. This device requires a 3.3-V power supply. It comes in a commercial temperature range and industrial
temperature range.
For a host application the TUSB546A-DCI enables the system to pass both transmitter compliance and receiver
jitter tolerance tests for USB 3.1 Gen 1 and DisplayPort version 1.4 HBR3. The re-driver recovers incoming data
by applying equalization that compensates for channel loss, and drives out signals with a high differential
voltage. Each channel has a receiver equalizer with selectable gain settings. The equalization should be set
based on the amount of insertion loss before the TUSB546A-DCI receivers. Independent equalization control for
each channel can be set using EQ[1:0], SSEQ[1:0], and DPEQ[1:0] pins.
The TUSB546A-DCI advanced state machine makes it transparent to hosts and devices. After power up, the
TUSB546A-DCI. periodically performs receiver detection on the TX pairs. If it detects a USB 3.1 Gen1 receiver,
the RX termination is enabled, and the TUSB546A-DCI is ready to re-drive.
The device ultra-low-power architecture operates at a 3.3-V power supply and achieves Enhanced performance.
The automatic LFPS De-Emphasis control further enables the system to be USB3.1 compliant.
14
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8.2 Functional Block Diagram
SSRXp
SSRXn
Driver
EQ_SEL
EQ
SSEQ_SEL
SSTXp
EQ
RX2p
RX2n
SSTXn
Driver
DPEQ_SEL
DP0p
DP0n
TX2p
TX2n
EQ
Driver
MUX
TX1n
TX1p
Driver
DP1p
EQ
EQ
DP1n
DPEQ_SEL
RX1n
RX1p
Driver
DP2p
DP2n
EQ
EQ_SEL
DP3p
EQ
DP3n
DPEQ_SEL
SSEQ_SEL
DPEQ_SEL
EQ_SEL
DPEQ[1:0]/A1
SSEQ[1:0]/A0
I2C_EN
EQ[1:0]
FSM, Control Logic and
Registers
FLIP/SCL
I2C
Slave
CTL0/SDA
HPDIN/DCI_CLK
CTL1/HPDIN
CAD_SNK/DCI_DAT
M
U
X
SBU1
SBU2
AUXp
AUXn
VREG
VCC
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8.3 Feature Description
8.3.1 USB 3.1
The TUSB546A-DCI supports USB 3.1 Gen1 datarates up to 5 Gbps. The TUSB546A-DCI supports all the USB
defined power states (U0, U1, U2, and U3). Because the TUSB546A-DCI is a linear redriver, it can’t decode
USB3.1 physical layer traffic. The TUSB546A-DCI monitors the actual physical layer conditions like receiver
termination, electrical idle, LFPS, and SuperSpeed signaling rate to determine the USB power state of the USB
3.1 interface.
The TUSB546A-DCI features an intelligent low frequency periodic signaling (LFPS) detector. The LFPS detector
automatically senses the low frequency signals and disables receiver equalization functionality. When not
receiving LFPS, the TUSB546A-DCI will enable receiver equalization based on the EQ[1:0] and SSEQ[1:0] pins
or values programmed into EQ1_SEL, EQ2_SEL, and SSEQ_SEL registers.
8.3.2 DisplayPort
The TUSB546A-DCI supports up to 4 DisplayPort lanes at datarates up to 8.1Gbps (HBR3). The TUSB546A-
DCI, when configured in DisplayPort mode, monitors the native AUX traffic as it traverses between DisplayPort
source and DisplayPort sink. For the purposes of reducing power, the TUSB546A-DCI manages the number of
active DisplayPort lanes based on the content of the AUX transactions. The TUSB546A-DCI snoops native AUX
writes to DisplayPort sink’s DPCD registers 0x00101 (LANE_COUNT_SET) and 0x00600
(SET_POWER_STATE). TUSB546A-DCI disables/enables lanes based on value written to LANE_COUNT_SET.
The TUSB546A-DCI disables all lanes when SET_POWER_STATE is in the D3. Otherwise active lanes will be
based on value of LANE_COUNT_SET.
DisplayPort AUX snooping is enabled by default but can be disabled by changing the AUX_SNOOP_DISABLE
register. Once AUX snoop is disabled, management of TUSB546A-DCI DisplayPort lanes are controlled through
various configuration registers. When TUSB546A-DCI is enabled for GPIO mode (I2C_EN = "0"), the CAD_SNK
pin can be used to disable AUX snooping. When CAD_SNK pin is high, the AUX snooping functionality is
disabled and all four DisplayPort lanes will be active.
8.3.3 4-level Inputs
The TUSB546A-DCI has (I2C_EN, EQ[1:0], DPEQ[1:0], and SSEQ[1:0]) 4-level inputs pins that are used to
control the equalization gain and place TUSB546A-DCI into different modes of operation. These 4-level inputs
utilize a resistor divider to help set the 4 valid levels and provide a wider range of control settings. There is an
internal 30 kΩ pull-up and a 94 kΩ pull-down. These resistors, together with the external resistor connection
combine to achieve the desired voltage level.
Table 1. 4-Level Control Pin Settings
LEVEL
SETTINGS
Option 1: Tie 1 KΩ 5% to GND.
Option 2: Tie directly to GND.
0
R
F
Tie 20 KΩ 5% to GND.
Float (leave pin open)
Option 1: Tie 1 KΩ 5%to VCC
.
1
Option 2: Tie directly to VCC
.
16
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NOTE
All four-level inputs are latched on rising edge of internal reset. After tcfg_hd, the internal
pull-up and pull-down resistors will be isolated in order to save power.
8.3.4 Receiver Linear Equalization
The purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference in
the system before the input of the TUSB546A-DCI. The receiver overcomes these losses by attenuating the low
frequency components of the signals with respect to the high frequency components. The proper gain setting
should be selected to match the channel insertion loss before the input of the TUSB546A-DCI receivers. Two 4-
level inputs pins enable up to 16 possible equalization settings. USB3.1 upstream path, USB3.1 downstream
path, and DisplayPort each have their own two 4-level inputs. The TUSB546A-DCI also provides the flexibility of
adjusting settings through I2C registers.
8.4 Device Functional Modes
8.4.1 Device Configuration in GPIO Mode
The TUSB546A-DCI is in GPIO configuration when I2C_EN = “0”. The TUSB546A-DCI supports the following
configurations: USB 3.1 only, 2 DisplayPort lanes + USB 3.1, or 4 DisplayPort lanes (no USB 3.1). The CTL1 pin
controls whether DisplayPort is enabled. The combination of CTL1 and CTL0 selects between USB 3.1 only, 2
lanes of DisplayPort, or 4-lanes of DisplayPort as detailed in Table 2. The AUXp or AUXn to SBU1 or SBU2
mapping is controlled based on Table 3.
After power-up (VCC from 0 V to 3.3 V), the TUSB546A-DCI defaults to USB3.1 mode. The USB PD controller
upon detecting no device attached to Type-C port or USB3.1 operation not required by attached device must
take TUSB546A-DCI out of USB3.1 mode by transitioning the CTL0 pin from L to H and back to L.
Table 2. GPIO Configuration Control
VESA DisplayPort ALT MODE
DFP_D CONFIGURATION
CTL1 PIN
CTL0 PIN
FLIP PIN
TUSB546A-DCI CONFIGURATION
L
L
L
L
L
H
L
Power Down
Power Down
—
—
L
H
H
L
One Port USB 3.1 - No Flip
One Port USB 3.1 – With Flip
4 Lane DP - No Flip
—
L
H
L
—
H
H
H
H
C and E
C and E
D and F
D and F
L
H
L
4 Lane DP – With Flip
H
H
One Port USB 3.1 + 2 Lane DP- No Flip
One Port USB 3.1 + 2 Lane DP– With Flip
H
Table 3. GPIO AUXp or AUXn to SBU1 or SBU2 Mapping
CTL1 PIN
FLIP PIN
MAPPING
AUXp → SBU1
AUXn → SBU2
H
L
AUXp → SBU2
AUXn → SBU1
H
H
X
L > 2 ms
Open
Table 4 Details the TUSB546A-DCI’s mux routing. This table is valid for both I2C and GPIO configuration modes.
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Table 4. INPUT to OUTPUT Mapping
FROM
TO
OUTPUT PIN
NA
CTL1 PIN
CTL0 PIN
FLIP PIN
INPUT PIN
NA
L
L
L
L
L
H
NA
NA
RX1P
RX1N
SSTXP
SSTXN
RX2P
RX2N
SSTXP
SSTXN
DP0P
DP0N
DP1P
DP1N
DP2P
DP2N
DP3P
DP3N
DP0P
DP0N
DP1P
DP1N
DP2P
DP2N
DP3P
DP3N
RX1P
RX1N
SSTXP
SSTXN
DP0P
DP0N
DP1P
DP1N
RX2P
RX2N
SSTXP
SSTXN
DP0P
DP0N
DP1P
DP1N
SSRXP
SSRXN
TX1P
L
L
H
H
L
TX1N
SSRXP
SSRXN
TX2P
H
TX2P
RX2P
RX2N
TX2P
TX2N
TX1P
H
H
H
H
L
L
H
L
TX1N
RX1P
RX1N
RX1P
RX1N
TX1P
TX1N
TX2P
L
TX2N
RX2P
RX2N
SSRXP
SSRXN
TX1P
TX1N
RX2P
RX2N
TX2P
H
TX2N
SSRXP
SSRXN
TX2P
TX2N
RX1P
RX1N
TX1P
H
H
TX1N
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8.4.2 Device Configuration In I2C Mode
The TUSB546A-DCI is in I2C mode when I2C_EN is not equal to “0”. The same configurations defined in GPIO
mode are also available in I2C mode. The TUSB546A-DCI USB3.1 and DisplayPort configuration is controlled
based on Table 5. The AUXp or AUXn to SBU1 or SBU2 mapping control is based on Table 6.
Table 5. I2C Configuration Control
REGISTERS
VESA DisplayPort ALT MODE
DFP_D CONFIGURATION
TUSB546A-DCI CONFIGURATION
CTLSEL1
CTLSEL0
FLIPSEL
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Power Down
Power Down
—
—
One Port USB 3.1 - No Flip
One Port USB 3.1 – With Flip
4 Lane DP - No Flip
—
—
C and E
C and E
D and F
D and F
4 Lane DP – With Flip
One Port USB 3.1 + 2 Lane DP- No Flip
One Port USB 3.1 + 2 Lane DP– With Flip
Table 6. I2C AUXp or AUXn to SBU1 or SBU2 Mapping
REGISTERS
MAPPING
AUX_SBU_OVR
CTLSEL1
FLIPSEL
AUXp → SBU1
AUXn → SBU2
00
1
0
AUXp → SBU2
AUXn → SBU1
00
00
01
1
1
X
1
X
X
Open
AUXp → SBU1
AUXn → SBU2
AUXp → SBU2
AUXn → SBU1
10
11
X
X
X
X
Open
8.4.3 DisplayPort Mode
The TUSB546A-DCI supports up to four DisplayPort lanes at datarates up to 8.1 Gbps. TUSB546A-DCI can be
enabled for DisplayPort through GPIO control or through I2C register control. When I2C_EN is ‘0’, DisplayPort is
controlled based on Table 2. When not in GPIO mode, enable of DisplayPort functionality is controlled through
I2C registers.
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8.4.4 Linear EQ Configuration
Each of the TUSB546A-DCI receiver lanes has individual controls for receiver equalization. The receiver
equalization gain value can be controlled either through I2C registers or through GPIOs. Table 7 details the gain
value for each available combination when TUSB546A-DCI is in GPIO mode. These same options are also
available in I2C mode by updating registers DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL, DP3EQ_SEL, EQ1_SEL,
EQ2_SEL, and SSEQ_SEL.
Table 7. TUSB546A-DCI Receiver Equalization GPIO Control
USB3.1 DOWNSTREAM FACING PORTS
USB 3.1 UPSTREAM FACING PORT
ALL DISPLAYPORT LANES
Equalization
Setting #
EQ GAIN at
2.5 GHz
(dB)
EQ1 PIN
LEVEL
SSEQ1 PIN
LEVEL
SSEQ0 PIN
LEVEL
EQ GAIN at 2.5
GHz (dB)
DPEQ1 PIN
LEVEL
DPEQ0 PIN
LEVEL
EQ GAIN at
4.05 GHz (dB)
EQ0 PIN LEVEL
0
1
0
0
0
R
F
1
0.2
1.2
2.2
3.3
4.2
5.1
5.9
6.7
7.4
8.1
8.7
9.3
9.7
10.2
10.6
11.1
0
0
0
R
F
1
-1.6
-0.5
0.5
1.6
2.4
3.4
4.1
4.9
5.7
6.4
6.9
7.5
8.0
8.5
8.9
9.4
0
0
0
R
F
1
1.0
3.3
2
0
0
0
4.9
3
0
0
0
6.5
4
R
R
R
R
F
F
F
F
1
0
R
R
R
R
F
F
F
F
1
0
R
R
R
R
F
F
F
F
1
0
7.5
5
R
F
1
R
F
1
R
F
1
8.6
6
9.5
7
10.4
11.1
11.7
12.3
12.8
13.2
13.6
14.0
14.4
8
0
0
0
9
R
F
1
R
F
1
R
F
1
10
11
12
13
14
15
0
0
0
1
R
F
1
1
R
F
1
1
R
F
1
1
1
1
1
1
1
8.4.5 USB3.1 Modes
The TUSB546A-DCI monitors the physical layer conditions like receiver termination, electrical idle, LFPS, and
SuperSpeed signaling rate to determine the state of the USB3.1 interface. Depending on the state of the USB
3.1 interface, the TUSB546A-DCI can be in one of four primary modes of operation when USB 3.1 is enabled
(CTL0 = H or CTLSEL0 = 1b1): Disconnect, U2/U3, U1, and U0.
The Disconnect mode is the state in which TUSB546A-DCI has not detected far-end termination on both
upstream facing port (UFP) or downstream facing port (DFP). The disconnect mode is the lowest power mode of
each of the four modes. The TUSB546A-DCI remains in this mode until far-end receiver termination has been
detected on both UFP and DFP. The TUSB546A-DCI immediately exits this mode and enter U0 once far-end
termination is detected.
Once in U0 mode, the TUSB546A-DCI will redrive all traffic received on UFP and DFP. U0 is the highest power
mode of all USB3.1 modes. The TUSB546A-DCI remains in U0 mode until electrical idle occurs on both UFP and
DFP. Upon detecting electrical idle, the TUSB546A-DCI immediately transitions to U1.
The U1 mode is the intermediate mode between U0 mode and U2/U3 mode. In U1 mode, the TUSB546A-DCI
UFP and DFP receiver termination remains enabled. The UFP and DFP transmitter DC common mode is
maintained. The power consumption in U1 is similar to power consumption of U0.
Next to the disconnect mode, the U2/U3 mode is next lowest power state. While in this mode, the TUSB546A-
DCI periodically performs far-end receiver detection. Anytime the far-end receiver termination is not detected on
either UFP or DFP, the TUSB546A-DCI leaves the U2/U3 mode and transitions to the Disconnect mode. It also
monitors for a valid LFPS. Upon detection of a valid LFPS, the TUSB546A-DCI immediately transitions to the U0
mode. In U2/U3 mode, the TUSB546A-DCI receiver terminations remain enabled but the TX DC common mode
voltage is not maintained.
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8.4.6 Operation Timing – Power Up
Tctl_db
Mode of operation
determined by value of
FLIPSEL bit and CTLSEL[1:0]
bits at offset0x0A. Default
is USB3.1- only no Flip.
USB3.1-only
FLIP = 0
TUSB546A-DCI
In I2C mode
DISABLED
If(( CTL[1:0 ] ==2'b 00 | CTL[1:0 ] ==2'b01 ) & FLIP == 0 ) {
USB3.1- only no FLIP;
} ELSEIF((CTL[1:0 ] ==2'b 00 | CTL[1:0 ] ==2'b01 ) & FLIP == 1 ){
USB3.1- only with FLIP;
} ELSEIF(CTL[1:0 ] ==2'b10 & FLIP ==0 ) {
4-Lane DP no FLIP;
} ELSEIF(CTL[1:0 ] ==2'b10 & FLIP ==1 ){
4-Lane DP with FLIP;
} ELSEIF(CTL[1:0 ] ==2'b11 & FLIP ==0 ) {
2-Lane DP USB3.1 no FLIP;
TUSB546A-DCI
In GPIO mode
USB3.1-only
FLIP = 0
DISABLED
} ELSE{
2-Lane DP USB3.1 with FLIP ;
};
CTL[1:0 pins
]
FLIP pin
VCC (min)
VCC
Td_pg
Internal
Power
Good
T Cfg_su
TCfg_hd
CFG pins
Figure 18. Power-Up Timing
Table 8. Power-Up Timing(1)(2)
PARAMETER
MIN
MAX
UNIT
µs
td_pg
VCC (minimum) to Internal Power Good asserted high
CFG(1) pins setup(2)
500
tcfg_su
50
10
µs
tcfg_hd
CFG(1) pins hold
µs
tCTL_DB
tVCC_RAMP
CTL[1:0] and FLIP pin debounce
VCC supply ramp requirement
16
ms
ms
100
(1) Following pins comprise CFG pins: I2C_EN, EQ[1:0], SSEQ[1:0], and DPEQ[1:0].
(2) Recommend CFG pins are stable when VCC is at min.
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8.5 Programming
For further programmability, the TUSB546A-DCI can be controlled using I2C. The SCL and SDA pins are used
for I2C clock and I2C data respectively.
Table 9. TUSB546A-DCI I2C Target Address
DPEQ0/A1
PIN LEVEL
SSEQ0/A0
PIN LEVEL
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (W/R)
0
0
0
R
F
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
R
R
R
R
F
F
F
F
1
0
R
F
1
0
R
F
1
0
1
R
F
1
1
1
The following procedure should be followed to write to TUSB546A-DCI I2C registers:
1. The master initiates a write operation by generating a start condition (S), followed by the TUSB546A-DCI 7-
bit address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB546A-DCI acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TUSB546A-DCI) to be written, consisting of one
byte of data, MSB-first.
4. The TUSB546A-DCI acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I2C register.
6. The TUSB546A-DCI acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the TUSB546A-DCI.
8. The master terminates the write operation by generating a stop condition (P).
The following procedure should be followed to read the TUSB546A-DCI I2C registers:
1. The master initiates a read operation by generating a start condition (S), followed by the TUSB546A-DCI 7-
bit address and a one-value “W/R” bit to indicate a read cycle.
2. The TUSB546A-DCI acknowledges the address cycle.
3. The TUSB546A-DCI transmit the contents of the memory registers MSB-first starting at register 00h or last
read sub-address+1. If a write to the T I2C register occurred prior to the read, then the TUSB546A-DCI shall
start at the sub-address specified in the write.
4. The TUSB546A-DCI shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the
master after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the TUSB546A-DCI transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).
The following procedure should be followed for setting a starting sub-address for I2C reads:
1. The master initiates a write operation by generating a start condition (S), followed by the TUSB546A-DCI 7-
bit address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB546A-DCI acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TUSB546A-DCI) to be written, consisting of one
byte of data, MSB-first.
22
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4. The TUSB546A-DCI acknowledges the sub-address cycle.
5. The master terminates the write operation by generating a stop condition (P).
NOTE
If no sub-addressing is included for the read procedure, and reads start at register offset
00h and continue byte by byte through the registers until the I2C master terminates the
read operation. If a I2C address write occurred prior to the read, then the reads start at the
sub-address specified by the address write.
Table 10. Register Legend
ACCESS TAG
NAME
Read
MEANING
R
W
S
The field may be read by software
The field may be written by software
Write
Set
The field may be set by a write of one. Writes of zeros to the field have no effect.
The field may be cleared by a write of one. Write of zero to the field have no effect.
Hardware may autonomously update this field.
C
Clear
U
Update
No Access
NA
Not accessible or not applicable
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8.6 Register Maps
8.6.1 General Register (address = 0x0A) [reset = 00000001]
Figure 19. General Registers
7
6
5
4
3
2
1
0
Reserved
R
SWAP_HPDIN EQ_OVERRID HPDIN_OVRRI
FLIPSEL
CTLSEL[1:0].
R/W
E
DE
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. General Registers
Bit
Field
Type
Reset
Description
7:6
Reserved.
R
00
Reserved.
0 – HPDIN is in default location (Default)
5
4
SWAP_HPDIN
EQ_OVERRIDE
R/W
R/W
0
0
1 – HPDIN location is swapped (PIN 23 to PIN 32, or PIN 32 to
PIN23).
Setting of this field will allow software to use EQ settings from
registers instead of value sample from pins.
0 – EQ settings based on sampled state of the EQ pins
(SSEQ[1:0], EQ[1:0], and DPEQ[1:0]).
1 – EQ settings based on programmed value of each of the EQ
registers
0 – HPD IN based on state of HPD_IN pin (Default)
1 – HPD_IN high.
3
2
HPDIN_OVRRIDE
FLIPSEL
R/W
R/W
0
0
FLIPSEL. Refer to Table 5 and Table 6 for this field functionality.
00 – Disabled. All RX and TX for USB3 and DisplayPort are
disabled.
1:0
CTLSEL[1:0].
R/W
01
01 – USB3.1 only enabled. (Default)
10 – Four DisplayPort lanes enabled.
11 – Two DisplayPort lanes and one USB3.1
8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
Figure 20. DisplayPort Control/Status Registers (0x10)
7
6
5
4
3
2
1
0
DP1EQ_SEL
R/W/U
DP0EQ_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. DisplayPort Control/Status Registers (0x10)
Bit
Field
Type
Reset
Description
Field selects between 0 to 14dB of EQ for DP lane 1. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for DP lane 1 based on value written to
this field.
7:4
DP1EQ_SEL
R/W/U
0000
Field selects between 0 to 14dB of EQ for DP lane 0. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for DP lane 0 based on value written to
this field.
3:0
DP0EQ_SEL
R/W/U
0000
24
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8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
Figure 21. DisplayPort Control/Status Registers (0x11)
7
6
5
4
3
2
1
0
DP3EQ_SEL
R/W/U
DP2EQ_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. DisplayPort Control/Status Registers (0x11)
Bit
Field
Type
Reset
Description
Field selects between 0 to 14dB of EQ for DP lane 3. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for DP lane 3 based on value written to
this field.
7:4
DP3EQ_SEL
R/W/U
0000
Field selects between 0 to 14dB of EQ for DP lane 2. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for DP lane 2 based on value written to
this field.
3:0
DP2EQ_SEL
R/W/U
0000
8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
Figure 22. DisplayPort Control/Status Registers (0x12)
7
Reserved
R
6
5
4
3
2
LANE_COUNT_SET
RU
1
0
SET_POWER_STATE
RU
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. DisplayPort Control/Status Registers (0x12)
Bit
Field
Type
Reset
Description
7
Reserved
R
0
Reserved
This field represents the snooped value of the AUX write to
DPCD address 0x00600. When AUX_SNOOP_DISABLE = 1’b0,
the TUSB546A-DCI will enable/disable DP lanes based on the
snooped value. When AUX_SNOOP_DISABLE = 1’b1, then DP
lane enable/disable are determined by state of DPx_DISABLE
registers, where x = 0, 1, 2, or 3. This field is reset to 2’b00 by
hardware when CTLSEL1 changes from a 1’b1 to a 1’b0.
6:5
4:0
SET_POWER_STATE
LANE_COUNT_SET
R/U
R/U
00
This field represents the snooped value of AUX write to DPCD
address 0x00101 register. When AUX_SNOOP_DISABLE =
1’b0, TUSB546A-DCI will enable DP lanes specified by the
snoop value. Unused DP lanes will be disabled to save power.
When AUX_SNOOP_DISABLE = 1’b1, then DP lanes
enable/disable are determined by DPx_DISABLE registers,
where x = 0, 1, 2, or 3. This field is reset to 0x0 by hardware
when CTLSEL1 changes from a 1’b1 to a 1’b0.
00000
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8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
Figure 23. DisplayPort Control/Status Registers (0x13)
7
6
5
4
3
2
1
0
AUX_SNOOP_
DISABLE
Reserved
AUX_SBU_OVR
DP3_DISABLE DP2_DISABLE DP1_DISABLE DP0_DISABLE
R/W
R
R/W
R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. DisplayPort Control/Status Registers (0x13)
Bit
7
Field
Type
R/W
R
Reset
Description
0 – AUX snoop enabled. (Default)
1 – AUX snoop disabled.
AUX_SNOOP_DISABLE
Reserved
0
0
6
Reserved
This field overrides the AUXp or AUXn to SBU1 or SBU2
connect and disconnect based on CTL1 and FLIP. Changing this
field to 1’b1 will allow traffic to pass through AUX to SBU
regardless of the state of CTLSEL1 and FLIPSEL register
00 – AUX to SBU connect/disconnect determined by CTLSEL1
and FLIPSEL (Default)
5:4
AUX_SBU_OVR
R/W
00
01 – AUXp -> SBU1 and AUXn -> SBU2 connection always
enabled.
10 – AUXp -> SBU2 and AUXn -> SBU1 connection always
enabled.
11 – AUX to SBU open.
When AUX_SNOOP_DISABLE = 1’b1, this field can be used to
enable or disable DP lane 3. When AUX_SNOOP_DISABLE =
1’b0, changes to this field will have no effect on lane 3
functionality.
0 – DP Lane 3 Enabled (default)
1 – DP Lane 3 Disabled.
3
2
1
0
DP3_DISABLE
DP2_DISABLE
DP1_DISABLE
DP0_DISABLE
R/W
R/W
R/W
R/W
0
0
0
0
When AUX_SNOOP_DISABLE = 1’b1, this field can be used to
enable or disable DP lane 2. When AUX_SNOOP_DISABLE =
1’b0, changes to this field will have no effect on lane 2
functionality.
0 – DP Lane 2 Enabled (default)
1 – DP Lane 2 Disabled.
When AUX_SNOOP_DISABLE = 1’b1, this field can be used to
enable or disable DP lane 1. When AUX_SNOOP_DISABLE =
1’b0, changes to this field will have no effect on lane 1
functionality.
0 – DP Lane 1 Enabled (default)
1 – DP Lane 1 Disabled.
DISABLE. When AUX_SNOOP_DISABLE = 1’b1, this field can
be used to enable or disable DP lane 0. When
AUX_SNOOP_DISABLE = 1’b0, changes to this field will have
no effect on lane 0 functionality.
0 – DP Lane 0 Enabled (default)
1 – DP Lane 0 Disabled.
26
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8.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
Figure 24. USB3.1 Control/Status Registers (0x20)
7
6
5
4
3
2
1
0
EQ2_SEL
R/W/U
EQ1_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. USB3.1 Control/Status Registers (0x20)
Bit
Field
Type
Reset
Description
Field selects between 0 to 9 dB of EQ for USB3.1 RX2 receiver.
When EQ_OVERRIDE = 1’b0, this field reflects the sampled
state of EQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software
can change the EQ setting for USB3.1 RX2 receiver based on
value written to this field.
7:4
EQ2_SEL
R/W/U
0000
Field selects between 0 to 9 dB of EQ for USB3.1 RX1 receiver.
When EQ_OVERRIDE = 1’b0, this field reflects the sampled
state of EQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software
can change the EQ setting for USB3.1 RX1 receiver based on
value written to this field.
3:0
EQ1_SEL
R/W/U
0000
8.6.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
Figure 25. USB3.1 Control/Status Registers (0x21)
7
6
5
4
3
2
1
0
Reserved
R
SSEQ_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. USB3.1 Control/Status Registers (0x21)
Bit
Field
Type
Reset
Description
7:4
Reserved
R
0000
Reserved
Field selects between 0 to 11 dB of EQ for USB3.1 SSTXP/N
receiver. When EQ_OVERRIDE = 1’b0, this field reflects the
sampled state of SSEQ[1:0] pins. When EQ_OVERRIDE = 1’b1,
software can change the EQ setting for USB3.1 SSTXP/N
receiver based on value written to this field.
3:0
SSEQ_SEL
R/W/U
0000
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8.6.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000100]
Figure 26. USB3.1 Control/Status Registers (0x22)
7
6
5
4
3
2
1
0
CM_ACTIVE
LFPS_EQ
U2U3_LFPS_D DISABLE_U2U
DFP_RXDET_INTERVAL
USB3_COMPLIANCE_CTRL
EBOUNCE
3_RXDET
R/U
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. USB3.1 Control/Status Registers (0x22)
Bit
Field
Type
Reset
Description
0 –device not in USB 3.1 compliance mode. (Default)
1 –device in USB 3.1 compliance mode
7
CM_ACTIVE
R/U
0
Controls whether settings of EQ based on EQ1_SEL, EQ2_SEL
and SSEQ_SEL applies to received LFPS signal.
0 – EQ set to zero when receiving LFPS (default)
1 – EQ set to EQ1_SEL, EQ2_SEL, and SSEQ_SEL when
receiving LFPS.
6
LFPS_EQ
R/W
0
0 – No debounce of LFPS before U2/U3 exit. (Default)
1 – 200 µs debounce of LFPS before U2/U3 exit.
5
4
U2U3_LFPS_DEBOUNCE
DISABLE_U2U3_RXDET
R/W
R/W
0
0
0 – Rx.Detect in U2/U3 enabled. (Default)
1 – Rx.Detect in U2/U3 disabled.
This field controls the Rx.Detect interval for the Downstream
facing port (TX1P/N and TX2P/N).
00 – 8 ms
01 – 12 ms (default)
10 – Reserved
3:2
1:0
DFP_RXDET_INTERVAL
R/W
R/W
01
00
11 – Reserved
00 – FSM determined compliance mode. (Default)
01 – Compliance Mode enabled in DFP direction (SSTX ->
TX1/TX2)
10 – Compliance Mode enabled in UFP direction (RX1/RX2 ->
SSRX)
USB3_COMPLIANCE_CTRL
11 – Compliance Mode Disabled.
28
Copyright © 2017–2019, Texas Instruments Incorporated
TUSB546A-DCI
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ZHCSGH4B –JUNE 2017–REVISED MAY 2019
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TUSB546A-DCI is a linear redriver designed specifically to compensation for intersymbol interference (ISI)
jitter caused by signal attenuation through a passive medium like PCB traces and cables. Because the
TUSB546A-DCI has four independent DisplayPort 1.4 inputs, one upstream facing USB 3.1 Gen1 input, and two
downstream facing USB 3.1 Gen1 inputs, it can be optimized to correct ISI on all those seven inputs through 16
different equalization choices. Placing the TUSB546A-DCI between a USB3.1 Host/DisplayPort 1.4 GPU and a
USB3.1 Type-C receptacle can correct signal integrity issues resulting in a more robust system.
9.2 Typical Application
A
B
F
E
PCB Trace of Length XAB
PCB Trace of Length XEF
SSRXP
SSRXN
SSTXP
USB3.1
Host
RX2P
RX2N
SSTXN
TX2P
TX2N
TUSB546A-DCI
DP0P
DP0N
DP1P
DP1N
TX1N
TX1P
DP 1.4
GPU
DP2P
RX1N
RX1P
DP2N
DP3P
DP3N
PCB Trace of Length XCD
PCB Trace of Length XGH
G
H
C
D
Copyright © 2017, Texas Instruments Incorporated
Figure 27. TUSB546A-DCI in a Host Application
Copyright © 2017–2019, Texas Instruments Incorporated
29
TUSB546A-DCI
ZHCSGH4B –JUNE 2017–REVISED MAY 2019
www.ti.com.cn
Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the parameters shown in Table 19.
Table 19. Design Parameters
PARAMETER
A to B PCB trace length, XAB
C to D PCB trace length, XCD
E to F PCB trace length, XEF
G to H PCB trace length, XGH
PCB trace width
VALUE
12 inches
12 inches
2 inches
2 inches
4 mils
AC-coupling capacitor (75 nF to 265 nF)
VCC supply (3 V to 3.6 V)
100 nF
3.3 V
I2C Mode or GPIO Mode
I2C Mode. (I2C_EN pin != "0")
3.3V I2C. Pull-up the I2C_EN pin to 3.3V with a 1K
ohm resistor.
1.8V or 3.3V I2C Interface
9.2.2 Detailed Design Procedure
A typical usage of the TUSB564-DCI device is shown in Figure 28. The device can be controlled either through
its GPIO pins or through its I2C interface. In the example shown below, a Type-C PD controller is used to
configure the device through the I2C interface. When configured for I2C mode, pins 29 and 32 can be left
unconnected if DCI is not used. In I2C mode, the equalization settings for each receiver can be independently
controlled through I2C registers. For this reason, all of the equalization pins (EQ[1:0], SSEQ[1:0], and
DPEQ[1:0]) can be left unconnected. If these pins are left unconnected, the TUSB546A-DCI 7-bit I2C slave
address will be 0x12 because both DPEQ/A1 and SSEQ0/A0 will be at pin level "F". If a different I2C slave
address is desired, DPEQ/A1 and SSEQ0/A0 pins should be set to a level which produces the desired I2C slave
address.
30
Copyright © 2017–2019, Texas Instruments Incorporated
TUSB546A-DCI
www.ti.com.cn
ZHCSGH4B –JUNE 2017–REVISED MAY 2019
3.3V
10mF
100nF
100nF
100nF
100nF
USB 3.1 Host
100nF
SSRXP
SSRXP
SSRXN
SSTXP
RX2P
RX2N
TX2P
TX2N
100nF
100nF
100nF
USB Type-C
Receptacle
SSRXN
100nF
SSTXP
SSTXN
A12
GND
RXP2
RXN2
VBUS
SBU1
DN1
100nF
SSTXN
B1
B2
GND
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
22O
To PCH DCI
TXP2
TXN2
DCI_CLK
DCI_DAT
»
»
Clock Input
100K
22O
To PCH DCI
DATA Input
100nF
100nF
DP1.4 AUXP
GPU
AUXP
AUXN
B3
AUXN
B4
VBUS
CC2
100K
SBU1
SBU2
DP_PWR (3.3V)
B5
100nF
100nF
B6
DP2
DN2
DP_ML0P
DP0P
2M
DP1
2M
DP_ML0N
DP_ML1P
DP_ML1N
DP_ML2P
DP_ML2N
DP_ML3P
DP_ML3N
DP0N
DP1P
B7
100nF
100nF
100nF
100nF
100nF
100nF
CC1
B8
SBU2
VBUS
DP1N
VBUS
100 nF
100 nF
DP2P
DP2N
TX1N
B9
TXN1
TXP1
TX1P
RX1N
B10
B11
B12
RXN1
RXP1
GND
DP3P
DP3N
RX1P
3.3V
GND
I2C_EN
3.3V
3.3V
SSEQ0/A0
SSEQ1
DPEQ0/A1
DPEQ1
EQ0
VI2C
R
R
FLIP/SCL
CTL0/SDA
3.3V
3.3V
3.3V
3.3V
Type-C
PD
Controller
CTL1/HPDIN
EQ1
Copyright © 2016, Texas Instruments Incorporated
Figure 28. Application Circuit
Copyright © 2017–2019, Texas Instruments Incorporated
31
TUSB546A-DCI
ZHCSGH4B –JUNE 2017–REVISED MAY 2019
www.ti.com.cn
9.2.3 Application Curve
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
Length=12in, Width=6mil
Length=16in, Width=6mil
Length=20in, Width=6mil
Length=24in, Width=6mil
Length=4in, Width=4mil
Length=8in, Width=10mil
Length=8in, Width=6mil
0
2
4
6
8
10
Frequency (GHz)
12
14
16
D009
Figure 29. Insertion Loss of FR4 PCB Traces
32
Copyright © 2017–2019, Texas Instruments Incorporated
TUSB546A-DCI
www.ti.com.cn
ZHCSGH4B –JUNE 2017–REVISED MAY 2019
9.3 System Examples
9.3.1 USB 3.1 Only
The TUSB546A-DCI is in USB3.1 only when the CTL1 pin is low and CTL0 pin is high.
D+/-
D+/-
1 Port USB
USB Host
USB Hub
TUSB546A-DCI
TUSB564
SSRX
SSTX
SSTX
SSRX
RX2
TX1
RX1
RX2
TX2
TX2
TX1
DP0
DP0
DP1
DP2
DP1
DP2
RX1
GPU
DP RX
DP3
DP3
SBU1
SBU2
SBU2
SBU1
AUXn
AUXp
AUXp
HPDIN
AUXn
HPDIN
FLIP 0 1 CTL
PD Controller
FLIP 0 1 CTL
PD Controller
CC1
CC2
HPD
Control
HPD
Control
CC1
CC2
CTL1/0/FLIP=L/H/L
CTL1/0/FLIP=L/H/L
Copyright © 2017, Texas Instruments Incorporated
Figure 30. USB3.1 Only – No Flip (CTL1 = L, CTL0 = H, FLIP = L)
Copyright © 2017–2019, Texas Instruments Incorporated
33
TUSB546A-DCI
ZHCSGH4B –JUNE 2017–REVISED MAY 2019
www.ti.com.cn
System Examples (continued)
D+/-
D+/-
1 Port USB
USB Host
USB Hub
TUSB564
TUSB546A-DCI
SSTX
SSRX
SSRX
SSTX
RX2
TX1
RX1
RX2
TX2
TX2
TX1
DP0
DP1
DP2
DP0
DP1
RX1
DP2
GPU
DP RX
DP3
DP3
AUXp
SBU1
SBU2
SBU2
SBU1
AUXn
AUXp
AUXn
HPDIN
HPDIN
FLIP 0 1 CTL
PD Controller
FLIP 0 1 CTL
PD Controller
CC1
CC2
HPD
Control
HPD
Control
CC1
CC2
CTL1/0/FLIP=L/H/H
CTL1/0/FLIP=L/H/H
Copyright © 2017, Texas Instruments Incorporated
Figure 31. USB3.1 Only – With Flip (CTL1 = L, CTL0 = H, FLIP = H)
34
Copyright © 2017–2019, Texas Instruments Incorporated
TUSB546A-DCI
www.ti.com.cn
ZHCSGH4B –JUNE 2017–REVISED MAY 2019
System Examples (continued)
9.3.2 USB 3.1 and 2 Lanes of DisplayPort
The TUSB546A-DCI operates in USB3.1 and 2 Lanes of DisplayPort mode when the CTL1 pin is high and CTL0
pin is high.
1 Port USB &
2 Lane DP
D+/-
D+/-
USB Host
USB Hub
SSRX
SSTX
SSTX
SSRX
TUSB546A-DCI
TUSB564
TX1
RX1
RX2
TX2
RX2
TX2
TX1
RX1
DP0
DP1
DP0
DP1
DP2
DP2
GPU
DP RX
DP3
DP3
AUXp
AUXn
SBU1
SBU2
SBU1
SBU2
AUXp
AUXn
HPDIN
HPDIN
FLIP 0 1 CTL
PD Controller
FLIP 0 1 CTL
PD Controller
HPD
Control
HPD
Control
CC1
CC2
CC1
CC2
CTL1/0/FLIP=H/H/L
CTL1/0/FLIP=H/H/L
Copyright © 2016, Texas Instruments Incorporated
Figure 32. USB3.1 + 2 Lane DP – No Flip (CTL1 = H, CTL0 = H, FLIP = L)
Copyright © 2017–2019, Texas Instruments Incorporated
35
TUSB546A-DCI
ZHCSGH4B –JUNE 2017–REVISED MAY 2019
www.ti.com.cn
System Examples (continued)
1 Port USB &
2 Lane DP
D+/-
D+/-
USB Host
USB Hub
TUSB546A-DCI
SSTX
TUSB564
SSRX
SSTX
SSRX
RX2
TX1
RX1
RX2
TX2
TX2
TX1
RX1
DP0
DP1
DP0
DP1
DP2
DP2
GPU
DP3
DP RX
DP3
SBU1
SBU2
AUXp
AUXn
SBU1
SBU2
AUXn
AUXp
HPDIN
HPDIN
FLIP 0 1 CTL
HPD
FLIP 0 1 CTL
PD Controller
HPD
Control
CC1
CC2
CC1
CC2
PD Controller
Control
CTL1/0/FLIP=H/H/H
CTL1/0/FLIP=H/H/H
Copyright © 2016, Texas Instruments Incorporated
Figure 33. USB 3.1 + 2 Lane DP – Flip (CTL1 = H, CTL0 = H, FLIP = H)
36
Copyright © 2017–2019, Texas Instruments Incorporated
TUSB546A-DCI
www.ti.com.cn
ZHCSGH4B –JUNE 2017–REVISED MAY 2019
System Examples (continued)
9.3.3 DisplayPort Only
The TUSB546A-DCI operates in 4 Lanes of DisplayPort only mode when the CTL1 pin is high and CTL0 pin is
low.
D+/-
D+/-
4 Lane DP
USB Host
USB Hub
TUSB564
TUSB546A-DCI
SSTX
SSRX
SSRX
SSTX
RX2
TX1
RX1
TX2
TX1
RX1
DP0
DP0
RX2
TX2
DP1
DP2
DP1
DP2
GPU
DP RX
DP3
DP3
AUXp
AUXn
SBU1
SBU2
SBU1
SBU2
AUXn
AUXp
HPDIN
HPDIN
FLIP 0 1 CTL
PD Controller
FLIP 0 1 CTL
PD Controller
HPD
Control
HPD
Control
CC1
CC2
CC1
CC2
CTL1/0/FLIP=H/L/L
CTL1/0/FLIP=H/L/L
Copyright © 2017, Texas Instruments Incorporated
Figure 34. Four Lane DP – No Flip (CTL1 = H, CTL0 = L, FLIP = L)
Copyright © 2017–2019, Texas Instruments Incorporated
37
TUSB546A-DCI
ZHCSGH4B –JUNE 2017–REVISED MAY 2019
www.ti.com.cn
System Examples (continued)
D+/-
D+/-
4 Lane DP
USB Host
USB Hub
SSRX
SSTX
SSTX
SSRX
TUSB546A-DCI
TUSB564
TX1
RX1
RX2
TX2
RX2
TX2
TX1
RX1
DP0
DP1
DP0
DP1
DP2
DP2
GPU
DP RX
DP3
DP3
SBU1
SBU2
AUXn
AUXp
SBU1
SBU2
AUXp
AUXn
HPDIN
HPDIN
CTL
FLIP 0 1
FLIP 0 1 CTL
PD Controller
HPD
Control
HPD
Control
CC1
CC2
CC1
CC2
PD Controller
CTL1/0/FLIP=H/L/H
CTL1/0/FLIP=H/L/H
Copyright © 2017, Texas Instruments Incorporated
Figure 35. Four Lane DP – With Flip (CTL1 = H, CTL0 = L, FLIP = H)
10 Power Supply Recommendations
The TUSB546A-DCI is designed to operate with a 3.3-V power supply. Levels above those listed in the Absolute
Maximum Ratings table should not be used. If using a higher voltage system power supply, a voltage regulator
can be used to step down to 3.3 V. Decoupling capacitors should be used to reduce noise and improve power
supply integrity. A 0.1-µF capacitor should be used on each power pin.
38
Copyright © 2017–2019, Texas Instruments Incorporated
TUSB546A-DCI
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ZHCSGH4B –JUNE 2017–REVISED MAY 2019
11 Layout
11.1 Layout Guidelines
1. RXP/N and TXP/N pairs should be routed with controlled 90-Ω differential impedance (±15%).
2. Keep away from other high speed signals.
3. Intra-pair routing should be kept to within 2 mils.
4. Length matching should be near the location of mismatch.
5. Each pair should be separated at least by 3 times the signal trace width.
6. The use of bends in differential traces should be kept to a minimum. When bends are used, the number of
left and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This
will minimize any length mismatch causes by the bends and therefore minimize the impact bends have on
EMI.
7. Route all differential pairs on the same of layer.
8. The number of VIAS should be kept to a minimum. It is recommended to keep the VIAS count to 2 or less.
9. Keep traces on layers adjacent to ground plane.
10. Do NOT route differential pairs over any plane split.
11. Adding Test points will cause impedance discontinuity, and therefore, negatively impact signal performance.
If test points are used, they should be placed in series and symmetrically. They must not be placed in a
manner that causes a stub on the differential pair.
11.2 Layout Example
To USB Host
AC Coupling
capacitors
RX2
TX2
DP0
DP1
DP2
DP3
TX1
RX1
Figure 36. Layout Example
版权 © 2017–2019, Texas Instruments Incorporated
39
TUSB546A-DCI
ZHCSGH4B –JUNE 2017–REVISED MAY 2019
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
12.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链
接。
表 20. 相关链接
器件
产品文件夹
单击此处
单击此处
样片与购买
单击此处
单击此处
技术文档
单击此处
单击此处
工具与软件
单击此处
单击此处
支持和社区
单击此处
单击此处
TUSB546A-DCI
TUSB546AI-DCI
12.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 商标
E2E is a trademark of Texas Instruments.
DisplayPort is a trademark of VESA.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
40
版权 © 2017–2019, Texas Instruments Incorporated
TUSB546A-DCI
www.ti.com.cn
ZHCSGH4B –JUNE 2017–REVISED MAY 2019
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2017–2019, Texas Instruments Incorporated
41
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TUSB546A-DCIRNQR
TUSB546A-DCIRNQT
TUSB546AI-DCIRNQR
TUSB546AI-DCIRNQT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
RNQ
RNQ
RNQ
RNQ
40
40
40
40
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
0 to 70
TUSB46
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
TUSB46
TUSB46
TUSB46
-40 to 85
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TUSB546A-DCIRNQR
TUSB546A-DCIRNQT
TUSB546AI-DCIRNQR
TUSB546AI-DCIRNQT
WQFN
WQFN
WQFN
WQFN
RNQ
RNQ
RNQ
RNQ
40
40
40
40
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
4.3
4.3
4.3
4.3
6.3
6.3
6.3
6.3
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TUSB546A-DCIRNQR
TUSB546A-DCIRNQT
TUSB546AI-DCIRNQR
TUSB546AI-DCIRNQT
WQFN
WQFN
WQFN
WQFN
RNQ
RNQ
RNQ
RNQ
40
40
40
40
3000
250
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
RNQ0040A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
4.1
3.9
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
4.7±0.1
2X 4.4
(0.2) TYP
9
20
EXPOSED
THERMAL PAD
36X 0.4
8
21
2X
2.8
2.7±0.1
1
28
0.25
40X
0.15
29
40
PIN 1 ID
0.1
C A
B
0.5
0.3
(OPTIONAL)
40X
0.05
4222125/B 01/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(4.7)
2X (2.1)
6X (0.75)
40
29
40X (0.6)
1
28
40X (0.2)
SYMM
4X
(1.1)
(3.8)
(2.7)
36X (0.4)
8
21
(R0.05) TYP
9
20
SYMM
(5.8)
(
0.2) TYP
VIA
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222125/B 01/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
4X (1.5)
40
29
40X (0.6)
1
28
40X (0.2)
SYMM
6X
(0.695)
(3.8)
6X
(1.19)
36X (0.4)
8
21
(R0.05) TYP
METAL
TYP
9
20
6X (1.3)
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
73% PRINTED SOLDER COVERAGE BY AREA
SCALE:18X
4222125/B 01/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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