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TUSB8041

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

TUSB8041 四端口 USB 3.0 集线器

1 特性

•

单时钟输入，24MHz 晶振或者振荡器

无特殊驱动程序要求；可与任一支持 USB 堆叠的

操作系统无缝工作

1

•

四端口 USB 3.0 集线器

USB 2.0 集线器特性

•

64 引脚四方扁平无引脚 (QFN) 封装 (RGC)

–

多事务转换器 (MTT) 集线器：四个事务转换器

每个事务转换器有四个异步端点缓冲器

2 应用

•

支持电池充电

•

计算机系统

–

充电下行端口 (CDP) 模式（上行端口已连接）

专用充电端口 (DCP) 模式（上行端口未连接）

扩展坞

监视器

机顶盒

DCP 模式符合中国电信行业标准 YD/T 1591-

2009

–

D+/D- 分压器模式

3 说明

•

支持作为一个 USB 3.0 或者 USB 2.0 复合器件运

行

TUSB8041 是一款四端口 USB 3.0 集线器。该器件在

上行端口上可提供同步超快速和高速/全速 USB 连接，

在下行端口上可提供超快速、高速、全速或者低速

USB 连接。当上行端口被连接到一个只支持高速或者

全速/低速连接的电气环境中时，下行端口上的超快速

USB 连接被禁用。当上行端口被连接到一个只支持全

速/低速连接的电气环境中时，下行端口上的超快速

USB 和高速连接被禁用。

•

支持每端口或成组电源开关以及过流告知输入

可使用一次性可编程 (OTP) ROM、串行 EEPROM

或 I²C/SMBus 受控接口进行自定义配置：

–

VID 和 PID

端口定制

生产商和产品字串（OTP ROM 不支持）

序列号（OTP ROM 不支持）

可使用引脚选择或 EEPROM/I²C/SMBus 受控接口

器件信息⁽¹⁾

•

选择应用特性

器件型号

TUSB8041

TUSB8041I

封装

封装尺寸（标称值）

•

提供 128 位通用唯一标识符 (UUID)

VQFN (64)

9.00mm x 9.00mm

支持通过 USB 2.0 上行端口进行板载和系统内

OTP/EEPROM 编程

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

图

USB 3.0

HDD

USB 2.0

Webcam

USB 2.0

Hub

USB 2.0

HDD

USB 1.1

Mouse

Personal

Computer

TUSB8041

USB 3.0

HDD

USB 2.0

USB 3.0

HDD

USB 3.0

Hub

USB 1.1

Keyboard

USB 2.0

Printer

USB 1.x Connection

USB 2.0 Connection

USB 3.0 Hub

USB 2.0 Device

USB 1.x Device

USB 3.0 Connection

USB 3.0 Device

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLLSEE4

TUSB8041

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

www.ti.com.cn

8.4 Device Functional Modes........................................ 15

8.5 Register Maps......................................................... 17

Applications and Implementation ...................... 29

9.1 Application Information............................................ 29

9.2 Typical Application .................................................. 29

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）.............................................................. 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 9

7.1 Absolute Maximum Ratings ..................................... 9

7.2 ESD Ratings.............................................................. 9

7.3 Recommended Operating Conditions....................... 9

7.4 Thermal Information................................................ 10

7.5 Electrical Characteristics, 3.3-V I/O ........................ 10

7.6 Timing Requirements, Power-Up............................ 11

7.7 Hub Input Supply Current ....................................... 11

Detailed Description ............................................ 12

8.1 Overview ................................................................. 12

8.2 Functional Block Diagram ....................................... 12

8.3 Feature Description................................................. 12

9

10 Power Supply Recommendations ..................... 37

10.1 TUSB8041 Power Supply ..................................... 37

10.2 Downstream Port Power ....................................... 37

10.3 Ground .................................................................. 37

11 Layout................................................................... 38

11.1 Layout Guidelines ................................................. 38

11.2 Layout Examples................................................... 39

12 器件和文档支持 ..................................................... 41

12.1 社区资源................................................................ 41

12.2 商标....................................................................... 41

12.3 静电放电警告......................................................... 41

12.4 Glossary................................................................ 41

13 机械、封装和可订购信息....................................... 42

8

4 修订历史记录

Changes from Revision D (January 2016) to Revision E

Page

•

Added SMBUS Programming current to the Hub Input Supply Current table ..................................................................... 11

Added Note to the SMBus Slave Operation section ............................................................................................................ 16

Changes from Revision C (July 2015) to Revision D

Page

•

Changed Active High. (PWRCTL_POL = 0) To: Active High. (PWRCTL_POL = 1) in 表 48 ............................................. 30

Changed text in the Clock, Reset, and Misc section From: "The PWRCTL_POL is pulled down which results in

active low" To: "The PWRCTL_POL is left unconnected which results in active high"........................................................ 34

•

Deleted R17 from pin 41 of 图 11 ........................................................................................................................................ 34

Changes from Revision A (July 2014) to Revision B

Page

•

Added Note ""Power switching must be supported for battery charging applications"" to pin FULLPWRMGMTz /

SMBA1/SS_UP in the Pin Functions table............................................................................................................................. 7

Added Note "Individual power control must be enabled for battery charging applications" to pin GANGED / SMBA2 /

HS_UP in the Pin Functions table.......................................................................................................................................... 8

•

Changed the Handling Ratings table to the ESD Ratings table............................................................................................. 9

Changed the Timing Requirements, Power-Up table: Deleted text from the t_d1description: "There is no timing

relationship between VDD33 and VDD": Added Note 2 to the MIN value ........................................................................... 11

•

Added Note: "An active reset is required.." To the Timing Requirements, Power-Up table................................................. 11

Changed text in the Clock, Reset, and Misc section From: "The PWRCTL_POL is pulled down which results in

active high power enable" To: "The PWRCTL_POL is pulled down which results in active low power enable" ................. 34

2

TUSB8041

www.ti.com.cn

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

Changes from Original (June 2014) to Revision A

Page

•

器件状态从：预览更改为：量产 ............................................................................................................................................. 1

特性从：支持 USB 电池充电规范版本 1.2 更改为：支持电池充电......................................................................................... 1

特性从：支持 D+/D- 分压器模式更改为：D+/D- 分压器模式.................................................................................................. 1

已更改描述段落：“TUSB8041 下行端口可 ...”...................................................................................................................... 3

Changed the Battery Charging Features section ................................................................................................................. 13

Changed Note 3 of 表 1 ....................................................................................................................................................... 13

Changed Note 1 of 表 1 ....................................................................................................................................................... 13

5 说明（续）

TUSB8041 支持每端口或成组电源开关和过流保护，而且支持电池充电应用。

按照 USB 主机的要求，一个端口电源单独控制集线器开关为每个下行端口加电或者断电。同样地，当一个端口电

源单独控制集线器感测到一个过流事件时，它只关闭到受影响的下行端口的电源。

当需要为任一端口供电时，一个成组集线器开关打开到其所有下行端口的电源。只有当所有端口处于电源可被移除

的状态时，到下行端口的电源才可被关闭。同样地，当一个成组集线器感测到一个过流事件时，到所有下行端口的

电源将被关闭。

TUSB8041 下行端口可提供电池充电连接下行端口 (CDP) 握手支持，以此为电池充电应用提供支持。未连接上行

端口时，该器件还支持专用充电端口 (DCP) 模式。DCP 模式支持 USB 电池充电并且符合中国电信行业标准 YD/T

1591-2009，能够为 USB 器件提供支持。此外，未连接上行端口时，自动模式能够为 BC 器件以及支持分压器模

式充电解决方案的器件提供透明支持。

TUSB8041 能够为包括电池充电支持在内的部分特性提供引脚搭接配置，还能够通过 OTP ROM、I²C EEPROM

或 I²C/SMBus 受控接口为 PID、VID、自定义端口和物理层配置提供定制支持。使用 I²C EEPROM 或 I²C/SMBus

受控接口时，还可以提供定制字串支持。

该器件采用 64 引脚 RGC 封装，商用版 (TUSB8041) 的工作温度范围为 0°C 到 70°C，工业版 (TUSB8041I) 的工

作温度范围为 -40°C 到 85°C。

3

TUSB8041

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

www.ti.com.cn

6 Pin Configuration and Functions

RGC Package

64 Pin

(Top View)

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

TEST 49

32 PWRCTL4/BATEN4

GRSTz 50

31 VDD

51

30 USB_SSRXM_DN4

29 USB_SSRXP_DN4

28 VDD

VDD

VDD33 52

USB_DP_UP 53

USB_DM_UP 54

27 USB_SSTXM_DN4

26 USB_SSTXP_DN4

25 USB_DM_DN4

24 USB_DP_DN4

23 USB_SSRXM_DN3

22 USB_SSRXP_DN3

21 VDD

USB_SSTXP_UP 55

USB_SSTXM_UP 56

VSS

57

VDD

USB_SSRXP_UP 58

USB_SSRXM_UP 59

NC 60

XO 61

20 USB_SSTXM_DN3

19 USB_SSTXP_DN3

18 USB_DM_DN3

17 USB_DP_DN3

XI 62

VDD33 63

USB_R1 64

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

4

TUSB8041

www.ti.com.cn

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

Pin Functions

NAME

I/O

DESCRIPTION

NO.

Clock and Reset Signals

I

Global power reset. This reset brings all of the TUSB8041 internal registers to their default

states. When GRSTz is asserted, the device is completely nonfunctional.

GRSTz

50

62

PU

Crystal input. This pin is the crystal input for the internal oscillator. The input may alternately

be driven by the output of an external oscillator. When using a crystal a 1-MΩ feedback

resistor is required between XI and XO.

XI

I

Crystal output. This pin is the crystal output for the internal oscillator. If XI is driven by an

external oscillator this pin may be left unconnected. When using a crystal a 1-MΩ feedback

resistor is required between XI and XO.

XO

61

O

USB Upstream Signals

USB_SSTXP_UP

USB_SSTXM_UP

USB_SSRXP_UP

USB_SSRXM_UP

USB_DP_UP

55

56

58

59

53

54

O

I

USB SuperSpeed transmitter differential pair (positive)

USB SuperSpeed transmitter differential pair (negative)

USB SuperSpeed receiver differential pair (positive)

USB SuperSpeed receiver differential pair (negative)

USB High-speed differential transceiver (positive)

USB High-speed differential transceiver (negative)

I

I/O

I

USB_DM_UP

Precision resistor reference. A 9.53-kΩ ±1% resistor should be connected between USB_R1

and GND.

USB_R1

64

I

USB upstream port power monitor. The VBUS detection requires a voltage divider. The signal

USB_VBUS must be connected to VBUS through a 90.9-KΩ ±1% resistor, and to ground

through a 10-kΩ ±1% resistor from the signal to ground.

USB_VBUS

48

USB Downstream Signals

USB_SSTXP_DN1

USB_SSTXM_DN1

USB_SSRXP_DN1

USB_SSRXM_DN1

USB_DP_DN1

3

4

6

7

1

2

O

I

USB SuperSpeed transmitter differential pair (positive)

USB SuperSpeed transmitter differential pair (negative)

USB SuperSpeed receiver differential pair (positive)

USB SuperSpeed receiver differential pair (negative)

USB High-speed differential transceiver (positive)

USB High-speed differential transceiver (negative)

I

I/O

USB_DM_DN1

USB Port 1 Power On Control for Downstream Power/Battery Charging Enable. The pin is

used for control of the downstream power switch for Port 1.

In addition, the value of the pin is sampled at the de-assertion of reset to determine the value

of the battery charging support for Port 1 as indicated in the Battery Charging Support

register:

PWRCTL1/BATEN1

36

46

I/O, PD

0 = Battery charging not supported

1 = Battery charging supported

USB Port 1 Over-Current Detection. This pin is used to connect the over current output of the

downstream port power switch for Port 1.

0 = An over current event has occurred

1 = An over current event has not occurred

OVERCUR1z

I, PU

This pin can be left unconnected if power management is not implemented. If power

management is enabled, the external circuitry needed should be determined by the power

switch.

USB_SSTXP_DN2

USB_SSTXM_DN2

USB_SSRXP_DN2

USB_SSRXM_DN2

USB_DP_DN2

11

12

14

15

9

O

I

USB SuperSpeed transmitter differential pair (positive)

USB SuperSpeed transmitter differential pair (negative)

USB SuperSpeed receiver differential pair (positive)

USB SuperSpeed receiver differential pair (negative)

USB High-speed differential transceiver (positive)

USB High-speed differential transceiver (negative)

I

I/O

USB_DM_DN2

10

5

TUSB8041

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

www.ti.com.cn

Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

USB Port 2 Power On Control for Downstream Power/Battery Charging Enable. The pin is

used for control of the downstream power switch for Port 2.

In addition, the value of the pin is sampled at the de-assertion of reset to determine the value

of the battery charging support for Port 2 as indicated in the Battery Charging Support

register:

PWRCTL2/BATEN2

35

I/O, PD

0 = Battery charging not supported

1 = Battery charging supported

USB Port 2 Over-Current Detection. This pin is used to connect the over current output of the

downstream port power switch for Port 2.

0 = An over current event has occurred

1 = An over current event has not occurred

OVERCUR2z

47

I, PU

This pin be left unconnected if power management is not implemented. If power management

is enabled, the external circuitry needed should be determined by the power switch.

USB_SSTXP_DN3

USB_SSTXM_DN3

USB_SSRXP_DN3

USB_SSRXM_DN3

USB_DP_DN3

19

20

22

23

17

18

O

I

USB SuperSpeed transmitter differential pair (positive)

USB SuperSpeed transmitter differential pair (negative)

USB SuperSpeed receiver differential pair (positive)

USB SuperSpeed receiver differential pair (negative)

USB High-speed differential transceiver (positive)

USB High-speed differential transceiver (negative)

I

I/O

USB_DM_DN3

USB Port 3 Power On Control for Downstream Power/Battery Charging Enable. The pin is

used for control of the downstream power switch for Port 3.

In addition, the value of the pin is sampled at the de-assertion of reset to determine the value

of the battery charging support for Port 3 as indicated in the Battery Charging Support

register:

PWRCTL3/BATEN3

33

44

I/O, PD

0 = Battery charging not supported

1 = Battery charging supported

USB Port 3 Over-Current Detection. This pin is used to connect the over current output of the

downstream port power switch for Port 3.

0 = An over current event has occurred

1 = An over current event has not occurred

OVERCUR3z

I, PU

This pin can be left unconnected if power management is not implemented. If power

management is enabled, the external circuitry needed should be determined by the power

switch.

USB_SSTXP_DN4

USB_SSTXM_DN4

USB_SSRXP_DN4

USB_SSRXM_DN4

USB_DP_DN4

26

27

29

30

24

25

O

I

USB SuperSpeed transmitter differential pair (positive)

USB SuperSpeed transmitter differential pair (negative)

USB SuperSpeed receiver differential pair (positive)

USB SuperSpeed receiver differential pair (negative)

USB High-speed differential transceiver (positive)

USB High-speed differential transceiver (negative)

I

I/O

USB_DM_DN4

USB Port 4 Power On Control for Downstream Power/Battery Charging Enable. The pin is

used for control of the downstream power switch for Port 4.

In addition, the value of the pin is sampled at the de-assertion of reset to determine the value

of the battery charging support for Port 4 as indicated in the Battery Charging Support

register:

PWRCTL4/BATEN4

32

I/O, PD

0 = Battery charging not supported

1 = Battery charging supported

6

TUSB8041

www.ti.com.cn

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

Pin Functions (continued)

NAME

I/O

DESCRIPTION

NO.

USB Port 4 Over-Current Detection. This pin is used to connect the over current output of the

downstream port power switch for Port 4.

0 = An over current event has occurred

1 = An over current event has not occurred

OVERCUR4z

43

I, PU

This pin can be left unconnected if power management is not implemented. If power

management is enabled, the external circuitry needed should be determined by the power

switch.

I²C/SMBUS Signals

I²C clock/SMBus clock. Function of pin depends on the setting of the SMBUSz input.

When SMBUSz = 1, this pin acts as the serial clock interface for an I²C EEPROM.

When SMBUSz = 0, this pin acts as the serial clock interface for an SMBus host.

Can be left unconnected if external interface not implemented.

I²C data/SMBus data. Function of pin depends on the setting of the SMBUSz input.

When SMBUSz = 1, this pin acts as the serial data interface for an I²C EEPROM.

When SMBUSz = 0, this pin acts as the serial data interface for an SMBus host.

Can be left unconnected if external interface not implemented.

SCL/SMBCLK

38

37

I/O, PD

SDA/SMBDAT

I²C/SMBus mode select/SuperSpeed USB Suspend Status. The value of the pin is sampled

at the de-assertion of reset set I²C or SMBus mode as follows:

1 = I²C Mode Selected

0 = SMBus Mode Selected

SMBUSz/SS_SUSPEND

39

I/O, PU

Can be left unconnected if external interface not implemented.

After reset, this signal indicates the SuperSpeed USB Suspend status of the upstream port if

enabled through the Additional Feature Configuration register. When enabled a value of 1

indicates the connection is suspended.

Test and Miscellaneous Signals

Full power management enable/SMBus address bit 1/SuperSpeed USB Connection Status

Upstream port.

The value of the pin is sampled at the de-assertion of reset to set the power switch control

follows:

0 = Power switching and over current inputs supported

1 = Power switching and over current inputs not supported

Full power management is the ability to control power to the downstream ports of the

I/O, PD TUSB8041 using PWRCTL[4:1]/BATEN[4:1].

FULLPWRMGMTz/

40

SMBA1/SS_UP

When SMBus mode is enabled using SMBUSz, this pin sets the value of the SMBus slave

address bit 1.

Can be left unconnected if full power management and SMBus are not implemented.

After reset, this signal indicates the SuperSpeed USB connection status of the upstream port

if enabled through the Additional Feature Configuration register. When enabled a value of 1

indicates the upstream port is connected to a SuperSpeed USB capable port.

Note: Power switching must be supported for battery charging applications.

Power Control Polarity.

The value of the pin is sampled at the de-assertion of reset to set the polarity of

PWRCTL[4:1].

PWRCTL_POL

41

I/O, PU

0 = PWRCTL polarity is active low

1 = PWRCTL polarity is active high

7

TUSB8041

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

www.ti.com.cn

Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

Ganged operation enable/SMBus Address bit 2/HS Connection Status Upstream Port.

The value of the pin is sampled at the de-assertion of reset to set the power switch and over

current detection mode as follows:

0 = Individual power control supported when power switching is enabled

1 = Power control gangs supported when power switching is enabled

GANGED/SMBA2/

HS_UP

42

I/O, PD

When SMBus mode is enabled using SMBUSz, this pin sets the value of the SMBus slave

address bit 2.

After reset, this signal indicates the High-speed USB connection status of the upstream port if

enabled through the Additional Feature Configuration register. When enabled a value of 1

indicates the upstream port is connected to a High-speed USB capable port.

Note: Individual power control must be enabled for battery charging applications.

Automatic Charge Mode Enable/HS Suspend Status.

The value of the pin is sampled at the de-assertion of reset to determine if automatic mode is

enabled as follows:

0 = Automatic Mode is enabled on ports that are enabled for battery charging when the

hub is unconnected. Please note that CDP is not supported on Port 1 when operating in

Automatic mode.

AUTOENz/

HS_SUSPEND

45

49

I/O, PU

1 = Automatic Mode is disabled

This value is also used to set the autoEnz bit in the Battery Charging Support Register.

After reset, this signal indicates the High-speed USB Suspend status of the upstream port if

enabled through the Additional Feature Configuration register. When enabled a value of 1

indicates the connection is suspended.

TEST

I, PD This pin is reserved for factory test.

Power and Ground Signals

5, 8,

13, 21,

28, 31,

51, 57

VDD

PWR 1.1-V power rail

16, 34,

52, 63

VDD33

PWR 3.3-V power rail

THERM

AL PAD

VSS

NC

PWR Ground. Thermal pad must be connected to ground.

60

—

No connect, leave floating

8

TUSB8041

www.ti.com.cn

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–0.3

MAX

1.4

UNIT

V

V_DDSteady-state supply voltage

Supply Voltage Range

V_DD33Steady-state supply voltage

3.8

V

USB_SSRXP_UP, USB_SSRXN_UP, USB_SSRXP_DN[4:1],

USB_SSRXN_DP[4:1] and USB_VBUS terminals

-0.3

1.4

V

Voltage Range

XI terminals

-0.3

–65

2.45

3.8

V

All other terminals

Storage temperature, T_stg

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

±2000

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

0.99

3

NOM

1.1

MAX

UNIT

V

VDD⁽¹⁾

1.1V supply voltage

1.26

3.6

VDD33

3.3V supply voltage

3.3

V

USB_VBUS

Voltage at USB_VBUS PAD

0

1.155

70

V

TUSB8041

TUSB8041I

0

°C

T_A

T_J

Operating free-air temperature

Operating junction temperature

–40

85

105

(1) A 1.05-V, 1.1-V, or 1.2-V supply may be used as long as minimum and maximum supply conditions are met.

9

TUSB8041

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

www.ti.com.cn

7.4 Thermal Information

TUSB8041

RGC

64 PINS

26

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

R_θJCtop

R_θJB

11.5

5.3

°C/W

ψ_JT

0.2

ψ_JB

5.2

R_θJCbot

1.0

(1) 有关传统和新热指标的更多信息，请参见应用报告《半导体和 IC 封装热指标》（文献编号：SPRA953）。

(2) 在 JESD51-2a 描述的环境中，按照 JESD51-7 的规定，在一个 JEDEC 标准高 K 电路板上进行仿真，从而获得自然对流条件下的结至环

境热阻抗。

(3) 通过在封装顶部进行冷板测试仿真来获得结至外壳（顶部）热阻。JEDEC 标准中没有相关测试的描述，但可在 ANSI SEMI 标准 G30 -

88 中找到相应的说明。

(4) 结至板热阻，可按照 JESD51-8 中的说明在使用环形冷板夹具来控制 PCB 温度的环境中进行仿真来获得。

(5) 结点至顶部特性参数 ψ_JT估算器件在实际系统中的结温，可通过 JESD51-2a（第 6 节和第 7 节）介绍的步骤从获得 R_θJA的仿真数据中获

取该温度。

(6) 结点至电路板特性参数 ψ_JB估算器件在实际系统中的结温，可通过 JESD51-2a（第 6 节和第 7 节）介绍的步骤从获得 R_θJA的仿真数据中

获取该温度。

(7) 通过在外露（电源）焊盘上进行冷板测试仿真来获得结至外壳（底部）热阻。JEDEC 标准中没有相关测试的描述，但可在 ANSI SEMI 标

准 G30 - 88 中找到相应的说明。

空白

7.5 Electrical Characteristics, 3.3-V I/O

over operating free-air temperature range (unless otherwise noted)

PARAMETER

High-level input voltage⁽¹⁾

OPERATION

TEST CONDITIONS

MIN

2

MAX

VDD33

0.8

UNIT

V_IH

V_IL

VDD33

V

0

Low-level input voltage⁽¹⁾

VDD33

V

JTAG pins only

0

0.55

V_I

Input voltage

Output voltage⁽²⁾

0

VDD33

25

V

V_O

t_t

0

Input transition time (t_riseand t_fall

Input hysteresis⁽³⁾

)

0

ns

V

V_hys

V_OH

V_OL

I_OZ

0.13 x VDD33

High-level output voltage

Low-level output voltage

High-impedance, output current⁽²⁾

VDD33

I_OH= -4 mA

I_OL= 4 mA

2.4

V

0.4

V

V_I= 0 to VDD33

±20

µA

High-impedance, output current with

internal pullup or pulldown

resistor⁽⁴⁾

Input current⁽⁵⁾

I_OZP

I_I

VDD33

V_I= 0 to VDD33

±250

±15

µA

(1) Applies to external inputs and bidirectional buffers.

(2) Applies to external outputs and bidirectional buffers.

(3) Applies to GRSTz.

(4) Applies to pins with internal pullups/pulldowns.

(5) Applies to external input buffers.

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7.6 Timing Requirements, Power-Up

PARAMETER

DESCRIPTION

VDD33 stable before VDD stable⁽¹⁾

MIN

TYP

MAX

UNIT

ms

µs

(2)

t_d1

See

t_d2

VDD and VDD33 stable before de-assertion of GRSTz

Setup for MISC inputs⁽³⁾sampled at the de-assertion of GRSTz

Hold for MISC inputs⁽³⁾sampled at the de-assertion of GRSTz

VDD33 supply ramp requirements

3

0.1

0.2

t_{su_io}

t_{hd_io}

µs

t_{VDD33_RAMP}

t_{VDD_RAMP}

100

ms

VDD supply ramp requirements

(1) An active reset is required if the VDD33 supply is stable before the VDD11 supply. This active Reset shall meet the 3ms power-up delay

counting from both power supplies being stable to the de-assertion of GRSTz.

(2) There is no power-on relationship between VDD33 and VDD unless GRSTz is only connected to a capacitor to GND. Then VDD must

be stable minimum of 10 μs before the VDD33.

(3) MISC pins sampled at de-assertion of GRSTz: FULLPWRMGMTz, GANGED, PWRCTL_POL, SMBUSz, BATEN[4:1], and AUTOENz.

t

d2

GRSTz

VDD33

t

d1

VDD

t

hd_io

su_io

MISC_IO

图 2. Power-Up Timing Requirements

7.7 Hub Input Supply Current

Typical values measured at T_A= 25°C

VDD33

3.3 V

VDD

PARAMETER

UNIT

1.1 V

LOW POWER MODES

Power On (after Reset)

2.3

2.5

28

33

mA

Upstream Disconnect

Suspend

ACTIVE MODES (US state / DS State)

3.0 host / 1 SS Device and Hub in U1 / U2

3.0 host / 1 SS Device and Hub in U0

3.0 host / 2 SS Devices and Hub in U1 / U2

3.0 host / 2 SS Devices and Hub in U0

3.0 host / 3 SS Devices and Hub in U1 / U2

3.0 host / 3 SS Devices and Hub in U0

3.0 host / 4 SS Devices and Hub in U1 / U2

3.0 host / 4 SS Devices and Hub in U0

49

85

99

45

76

79

225

366

305

508

380

661

455

778

395

554

63

mA

3.0 host / 1 SS Device in U0 and 1 HS Device

3.0 host / 2 SS Devices in U0 and 2 HS Devices

2.0 host / HS Device

2.0 host / 4 HS Devices

86

SMBUS Programming current

225

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8 Detailed Description

8.1 Overview

The TUSB8041 is a four-port USB 3.0 compliant hub. It provides simultaneous SuperSpeed USB and high-

speed/full-speed connections on the upstream port and provides SuperSpeed USB, high-speed, full-speed, or

low-speed connections on the downstream ports. When the upstream port is connected to an electrical

environment that only supports high-speed or full-speed/low-speed connections, SuperSpeed USB connectivity is

disabled on the downstream ports. When the upstream port is connected to an electrical environment that only

supports full-speed/low-speed connections, SuperSpeed USB and high-speed connectivity are disabled on the

downstream ports.

8.2 Functional Block Diagram

VDD33

Power

Distribution

VBUS

Detect

VDD

VSS

USB 2.0 Hub

SuperSpeed Hub

XI

Oscilator

XO

Clock

and

Reset

GRSTz

Distribution

TEST

GANGED/SMBA2/HS_UP

FULLPWRMGMTz/SMBA1/SS_UP

PWRCTL_POL

SMBUSz/SS_SUSPEND

AUTOENz/HS_SUSPEND

SCL/SMBCLK

OTP

ROM

Control

Registers

SDA/SMBDAT

GPIO

I²C

OVERCUR1z

PWRCTL1/BATEN1

SMBUS

OVERCUR2z

PWRCTL2/BATEN2

OVERCUR3z

PWRCTL3/BATEN3

OVERCUR4z

PWRCTL4/BATEN4

8.3 Feature Description

8.3.1 Battery Charging Features

The TUSB8041 provides support for USB Battery Charging. Battery charging support may be enabled on a per

port basis through the REG_6h(batEn[3:0]).

Battery charging support includes both Charging Downstream Port (CDP) and Dedicated Charging Port (DCP)

modes. The DCP mode is compliant with the Chinese Telecommunications Industry Standard YD/T 1591-2009.

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Feature Description (接下页)

In addition, to standard DCP mode, the TUSB8041 provides a mode (AUTOMODE) which automatically provides

support for DCP devices and devices that support custom charging indication. When in AUTOMODE, the port will

automatically switch between a divider mode and the DCP mode depending on the portable device connected.

The divided mode places a fixed DC voltage on the ports DP and DM signals which allows some devices to

identify the capabilities of the charger. The default divider mode indicates support for up to 5W. The divider mode

can be configured to report a high-current setting (up to 10 W) through REG_Ah (HiCurAcpModeEn).

The battery charging mode for each port is dependent on the state of Reg_6h(batEn[n]), the status of the VBUS

input, and the state of REG_Ah(autoModeEnz) upstream port as identified in 表 1.

表 1. TUSB8041 Battery Charging Modes

BC Mode Port x

batEn[n]

VBUS

autoModeEnz

(x = n + 1)

Don’t Care

Automode^{(1) (2)}

DCP^{(3) (4)}

0

Don’t Care

0

1

< 4 V

> 4 V

1

Don’t Care

CDP⁽³⁾

(1) Auto-mode automatically selects divider-mode or DCP mode.

(2) Divider mode can be configured for high-current mode through register or OTP settings.

(3) USB Device is USB Battery Charging Specification Revision 1.2 Compliant

(4) USB Device is Chinese Telecommunications Industry Standard YD/T 1591-2009

8.3.2 USB Power Management

The TUSB8041 can be configured for power switched applications using either per-port or ganged power-enable

controls and over-current status inputs.

Power switch support is enabled by REG_5h (fullPwrMgmtz) and the per-port or ganged mode is configured by

REG_5h(ganged).

The TUSB8041 supports both active high and active low power-enable controls. The PWRCTL[4:1] polarity is

configured by REG_Ah(pwrctlPol).

8.3.3 One Time Programmable (OTP) Configuration

The TUSB8041 allows device configuration through one time programmable non-volatile memory (OTP). The

programming of the OTP is supported using vendor-defined USB device requests. For details using the OTP

features please contact your TI representative.

The table below provides a list features which may be configured using the OTP.

表 2. OTP Configurable Features

CONFIGURATION REGISTER

BIT FIELD

DESCRIPTION

OFFSET

REG_01h

REG_02h

REG_03h

REG_04h

[7:0]

Vendor ID LSB

Vendor ID MSB

Product ID LSB

Product ID MSB

Port removable configuration for downstream ports 1. OTP

configuration is inverse of rmbl[3:0], i.e. 1 = not removable, 0 =

removable.

REG_07h

[0]

[1]

[2]

Port removable configuration for downstream ports 2. OTP

configuration is inverse of rmbl[3:0], i.e. 1 = not removable, 0 =

removable.

Port removable configuration for downstream ports 3. OTP

configuration is inverse of rmbl[3:0], i.e. 1 = not removable, 0 =

removable.

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表 2. OTP Configurable Features (接下页)

CONFIGURATION REGISTER

OFFSET

BIT FIELD

DESCRIPTION

Port removable configuration for downstream ports 4. OTP

configuration is inverse of rmbl[3:0], i.e. 1 = not removable, 0 =

removable.

REG_07h

[3]

REG_0Ah

REG_0Bh

REG_F0h

[3]

[4]

Enable Device Attach Detection..

High-current divider mode enable.

[0]

USB 2.0 port polarity configuration for downstream ports 1.

USB 2.0 port polarity configuration for downstream ports 2.

USB 2.0 port polarity configuration for downstream ports 3.

USB 2.0 port polarity configuration for downstream ports 4.

USB power switch power-on delay.

[1]

[2]

[3]

[3:1]

8.3.4 Clock Generation

The TUSB8041 accepts a crystal input to drive an internal oscillator or an external clock source. If a clock is

provided to XI instead of a crystal, XO is left open. Otherwise, if a crystal is used, the connection needs to follow

the guidelines below. Since XI and XO are coupled to other leads and supplies on the PCB, it is important to

keep them as short as possible and away from any switching leads. It is also recommended to minimize the

capacitance between XI and XO. This can be accomplished by shielding C1 and C2 with the clean ground lines.

R1

1M

Y1

XI

24 MHz

TUSB8041

CLOCK

XO

CL1

CL2

图 3. TUSB8041 Clock

8.3.5 Crystal Requirements

The crystal must be fundamental mode with load capacitance of 12 pF - 24 pF and frequency stability rating of

±100 PPM or better. To ensure proper startup oscillation condition, a maximum crystal equivalent series

resistance (ESR) of 50 Ω is recommended. A parallel load capacitor should be used if a crystal source is used.

The exact load capacitance value used depends on the crystal vendor. Refer to application note Selection and

Specification for Crystals for Texas Instruments USB2.0 devices (SLLA122) for details on how to determine the

load capacitance value.

8.3.6 Input Clock Requirements

When using an external clock source such as an oscillator, the reference clock should have a ±100 PPM or

better frequency stability and have less than 50-ps absolute peak to peak jitter or less than 25-ps peak to peak

jitter after applying the USB 3.0 jitter transfer function. XI should be tied to the 1.8-V clock source and XO should

be left floating.

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8.3.7 Power-Up and Reset

The TUSB8041 does not have specific power sequencing requirements with respect to the core power (VDD) or

I/O and analog power (VDD33). The core power (VDD) or I/O power (VDD33) may be powered up for an

indefinite period of time while the other is not powered up if all of these constraints are met:

•

All maximum ratings and recommended operating conditions are observed.

All warnings about exposure to maximum rated and recommended conditions are observed, particularly

junction temperature. These apply to power transitions as well as normal operation.

•

Bus contention while VDD33 is powered up must be limited to 100 hours over the projected life-time of the

device.

•

Bus contention while VDD33 is powered down may violate the absolute maximum ratings.

A supply bus is powered up when the voltage is within the recommended operating range. It is powered down

when it is below that range, either stable or in transition.

A minimum reset duration of 3 ms is required. This is defined as the time when the power supplies are in the

recommended operating range to the de-assertion of GRSTz. This can be generated using programmable-delay

supervisory device or using an RC circuit.

8.4 Device Functional Modes

8.4.1 External Configuration Interface

The TUSB8041 supports a serial interface for configuration register access. The device may be configured by an

attached I²C EEPROM or accessed as a slave by an SMBus capable host controller. The external interface is

enabled when both the SCL/SMBCLK and SDA/SMBDAT pins are pulled up to 3.3 V at the de-assertion of reset.

The mode, I²C master or SMBus slave, is determined by the state of SMBUSz/SS_SUSPEND pin at reset.

8.4.2 I²C EEPROM Operation

The TUSB8041 supports a single-master, standard mode (100 kbit/s) connection to a dedicated I²C EEPROM

when the I²C interface mode is enabled. In I²C mode, the TUSB8041 reads the contents of the EEPROM at bus

address 1010000b using 7-bit addressing starting at address 0.

If the value of the EEPROM contents at byte 00h equals 55h, the TUSB8041 loads the configuration registers

according to the EEPROM map. If the first byte is not 55h, the TUSB8041 exits the I²C mode and continues

execution with the default values in the configuration registers. The hub will not connect on the upstream port

until the configuration is completed. If the hub detected an un-programmed EEPROM (value other than 55h), the

hub will enter Programming Mode and a Programming Endpoint within the hub will be enabled.

Note, the bytes located above offset Ah are optional. The requirement for data in those addresses is dependent

on the options configured in the Device Configuration, and Device Configuration 2 registers.

For details on I²C operation refer to the UM10204 I²C-bus Specification and User Manual.

8.4.3 SMBus Slave Operation

When the SMBus interface mode is enabled, the TUSB8041 supports read block and write block protocols as a

slave-only SMBus device.

The TUSB8041 slave address is 1000 1xyz, where:

•

x is the state of GANGED/SMBA2/HS_UP pin at reset,

y is the state of FULLPWRMGMTz/SMBA1/SS_UP pin at reset, and

z is the read/write bit; 1 = read access, 0 = write access.

If the TUSB8041 is addressed by a host using an unsupported protocol it will not respond. The TUSB8041 will

wait indefinitely for configuration by the SMBus host and will not connect on the upstream port until the SMBus

host indicates configuration is complete by clearing the CFG_ACTIVE bit.

For details on SMBus requirements refer to the System Management Bus Specification.

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Device Functional Modes (接下页)

注

During the SMBUS configuration the hub may draw an extra current, this extra current

consumption will end as soon as the CFG_ACTIVE bit is cleared. For more information,

see Hub Input Supply Current Section in this datasheet.

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8.5 Register Maps

8.5.1 Configuration Registers

The internal configuration registers are accessed on byte boundaries. The configuration register values are

loaded with defaults but can be over-written when the TUSB8041 is in I²C or SMBus mode.

表 3. TUSB8041 Register Map

BYTE

ADDRESS

CONTENTS

EEPROM CONFIGURABLE

00h

ROM Signature Register

Vendor ID LSB

No

01h

Yes

02h

Vendor ID MSB

Yes

03h

Product ID LSB

Yes

04h

Product ID MSB

Yes

05h

Device Configuration Register

Battery Charging Support Register

Device Removable Configuration Register

Port Used Configuration Register

Reserved

Yes

06h

Yes

07h

Yes

08h

Yes

09h

Yes, program to 00h

0Ah

Device Configuration Register 2

USB 2.0 Port Polarity Control Register

Reserved

Yes

0Bh

Yes

0Ch-0Fh

10h-1Fh

20h-21h

22h

No

UUID Byte [15:0]

No

LangID Byte [1:0]

Yes, if customStrings is set

Serial Number String Length

Manufacturer String Length

Product String Length

Reserved

Yes, if customSerNum is set

23h

Yes, if customStrings is set

24h

Yes, if customStrings is set

25h-2Fh

30h-4Fh

50h-8Fh

90h-CFh

D0-DFh

F0h

No

Serial Number String Byte [31:0]

Manufacturer String Byte [63:0]

Product String Byte [63:0]

Reserved

Yes, if customSerNum is set

Yes, if customStrings is set

No

Yes

No

Additional Feature Configuration Register

Reserved

F1-F7h

F8h

Device Status and Command Register

Reserved

No

F9-FFh

No

8.5.2 ROM Signature Register

表 4. Register Offset 0h

Bit No.

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset State

表 5. Bit Descriptions – ROM Signature Register

Bit

Field Name

Access

Description

ROM Signature Register. This register is used by the TUSB8041 in I²C

mode to validate the attached EEPROM has been programmed. The first

byte of the EEPROM is compared to the mask 55h and if not a match,

the TUSB8041 aborts the EEPROM load and executes with the register

defaults.

7:0

romSignature

RW

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8.5.3 Vendor ID LSB Register

表 6. Register Offset 1h

Bit No.

7

0

6

1

5

0

4

1

3

0

2

0

1

0

1

Reset State

表 7. Bit Descriptions – Vendor ID LSB Register

Bit

Field Name

Access

Description

Vendor ID LSB. Least significant byte of the unique vendor ID assigned

by the USB-IF; the default value of this register is 51h representing the

LSB of the TI Vendor ID 0451h. The value may be over-written to

indicate a customer Vendor ID.

7:0

vendorIdLsb

RO/RW

This field is read/write unless the OTP ROM VID and OTP ROM PID

values are non-zero. If both values are non-zero the value when reading

this register shall reflect the OTP ROM value.

8.5.4 Vendor ID MSB Register

表 8. Register Offset 2h

Bit No.

7

0

6

0

5

0

4

0

3

0

2

1

0

Reset State

表 9. Bit Descriptions – Vendor ID MSB Register

Bit

Field Name

Access

Description

Vendor ID MSB. Most significant byte of the unique vendor ID assigned

by the USB-IF; the default value of this register is 04h representing the

MSB of the TI Vendor ID 0451h. The value may be over-written to

indicate a customer Vendor ID.

7:0

vendorIdMsb

RO/RW

This field is read/write unless the OTP ROM VID and OTP ROM PID

values are non-zero. If both values are non-zero the value when reading

this register shall reflect the OTP ROM value.

8.5.5 Product ID LSB Register

表 10. Register Offset 3h

Bit No.

7

0

6

1

5

0

4

0

3

0

2

0

1

0

Reset State

表 11. Bit Descriptions – Product ID LSB Register

Bit

Field Name

Access

Description

Product ID LSB. Least significant byte of the product ID assigned by

Texas Instruments and reported in the SuperSpeed Device descriptor.

the default value of this register is 40h representing the LSB of the

SuperSpeed product ID assigned by Texas Instruments The value

reported in the USB 2.0 Device descriptor is the value of this register bit

wise XORed with 00000010b. The value may be over-written to indicate

a customer product ID.

7:0

productIdLsb

RO/RW

This field is read/write unless the OTP ROM VID and OTP ROM PID

values are non-zero. If both values are non-zero the value when reading

this register will reflect the OTP ROM value.

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8.5.6 Product ID MSB Register

表 12. Register Offset 4h

Bit No.

7

1

6

0

5

0

4

0

3

0

2

0

1

0

1

Reset State

表 13. Bit Descriptions – Product ID MSB Register

Bit

Field Name

Access

Description

Product ID MSB. Most significant byte of the product ID assigned by

Texas Instruments; the default value of this register is 81h representing

the MSB of the product ID assigned by Texas Instruments. The value

may be over-written to indicate a customer product ID.

7:0

productIdMsb

RO/RW

This field is read/write unless the OTP ROM VID and OTP ROM PID

values are non-zero. If both values are non-zero, the value when reading

this register will reflect the OTP ROM value.

8.5.7 Device Configuration Register

表 14. Register Offset 5h

Bit No.

7

0

6

0

5

0

4

1

3

2

1

0

Reset State

X

表 15. Bit Descriptions – Device Configuration Register

Bit

Field Name

Access

Description

Custom strings enable. This bit controls the ability to write to the

Manufacturer String Length, Manufacturer String, Product String Length,

Product String, and Language ID registers

0 = The Manufacturer String Length, Manufacturer String, Product

String Length, Product String, and Language ID registers are read

only

7

customStrings

RW

1 = The Manufacturer String Length, Manufacturer String, Product

String Length, Product String, and Language ID registers may be

loaded by EEPROM or written by SMBus

The default value of this bit is 0.

Custom serial number enable. This bit controls the ability to write to the

serial number registers.

0 = The Serial Number String Length and Serial Number String

registers are read only

6

customSernum

RW

1 = Serial Number String Length and Serial Number String registers

may be loaded by EEPROM or written by SMBus

The default value of this bit is 0.

U1 U2 Disable. This bit controls the U1/U2 support.

0 = U1/U2 support is enabled

1 = U1/U2 support is disabled, the TUSB8041 will not initiate or

accept any U1 or U2 requests on any port, upstream or downstream,

unless it receives or sends a Force_LinkPM_Accept LMP. After

receiving or sending an FLPMA LMP, it will continue to enable U1

and U2 according to USB 3.0 protocol until it gets a power-on reset

or is disconnected on its upstream port.

5

4

u1u2Disable

RW

RO

When the TUSB8041 is in I²C mode, the TUSB8041 loads this bit from

the contents of the EEPROM.

When the TUSB8041 is in SMBUS mode, the value may be over-written

by an SMBus host.

RSVD

Reserved. This bit is reserved and returns 1 when read.

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表 15. Bit Descriptions – Device Configuration Register (接下页)

Ganged. This bit is loaded at the de-assertion of reset with the value of

the GANGED/SMBA2/HS_UP pin.

0 = When fullPwrMgmtz = 0, each port is individually power switched

and enabled by the PWRCTL[4:1]/BATEN[4:1] pins

1 = When fullPwrMgmtz = 0, the power switch control for all ports is

ganged and enabled by the PWRCTL[4:1]/BATEN1 pin

3

ganged

RW

When the TUSB8041 is in I²C mode, the TUSB8041 loads this bit from

the contents of the EEPROM.

When the TUSB8041 is in SMBUS mode, the value may be over-written

by an SMBus host.

Full Power Management. This bit is loaded at the de-assertion of reset

with the value of the FULLPWRMGMTz/SMBA1/SS_UP pin.

0 = Port power switching status reporting is enabled

1 = Port power switching status reporting is disabled

When the TUSB8041 is in I²C mode, the TUSB8041 loads this bit from

the contents of the EEPROM.

2

fullPwrMgmtz

RW

When the TUSB8041 is in SMBUS mode, the value may be over-written

by an SMBus host.

Reserved. This field is reserved and should not be altered from the

default.

1

0

RSVD

RW

RO

Reserved. This field is reserved and returns 0 when read.

8.5.8 Battery Charging Support Register

表 16. Register Offset 6h

Bit No.

7

0

6

0

5

4

3

2

1

0

Reset State

0

X

表 17. Bit Descriptions – Battery Charging Support Register

Bit

Field Name

Access

Description

7:4

RSVD

RO

Reserved. Read only, returns 0 when read.

Battery Charger Support. The bits in this field indicate whether the

downstream port implements the charging port features.

0 = The port is not enabled for battery charging support features

1 = The port is enabled for battery charging support features

Each bit corresponds directly to a downstream port, i.e. batEn0

corresponds to downstream port 1, and batEN1 corresponds to

downstream port 2.

3:0

batEn[3:0]

RW

The default value for these bits are loaded at the de-assertion of reset

with the value of PWRCTL/BATEN[3:0].

When in I2C/SMBus mode the bits in this field may be over-written by

EEPROM contents or by an SMBus host.

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8.5.9 Device Removable Configuration Register

表 18. Register Offset 7h

Bit No.

7

0

6

0

5

0

4

0

3

2

1

0

Reset State

X

表 19. Bit Descriptions – Device Removable Configuration Register

Bit

7

Field Name

customRmbl

RSVD

Access

Description

Custom Removable. This bit controls the ability to write to the port

removable bits.

0 = rmbl[3:0] are read only and the values are loaded from the OTP

ROM

RW

1 = rmbl[3:0] are read/write and can be loaded by EEPROM or

written by SMBus

This bit may be written simultaneously with rmbl[3:0].

Reserved. Read only, returns 0 when read.

6:4

RO

Removable. The bits in this field indicate whether a device attached to

downstream ports 4 through 1 are removable or permanently attached.

0 = The device attached to the port is not removable

1 = The device attached to the port is removable

Each bit corresponds directly to a downstream port n + 1, i.e. rmbl0

corresponds to downstream port 1, rmbl1 corresponds to downstream

port 2, etc.

3:0

rmbl[3:0]

RW

This field is read only unless the customRmbl bit is set to 1. Otherwise

the value of this filed reflects the inverted values of the OTP ROM

non_rmb[3:0] field.

8.5.10 Port Used Configuration Register

表 20. Register Offset 8h

Bit No.

7

0

6

0

5

4

3

2

1

0

1

Reset State

0

1

表 21. Bit Descriptions – Port Used Configuration Register

Bit

Field Name

Access

Description

7:4

RSVD

RO

Reserved. Read only.

Used. The bits in this field indicate whether a port is enabled.

0 = The port is disabled

1 = The port is enabled

3:0

used[3:0]

RW

Each bit corresponds directly to a downstream port, i.e. used0

corresponds to downstream port 1, used1 corresponds to downstream

port 2, etc. All combinations are supported with the exception of both

ports 1 and 3 marked as disabled.

21

TUSB8041

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8.5.11 Device Configuration Register 2

表 22. Register Offset Ah

Bit No.

7

0

6

0

5

4

0

3

0

2

0

1

0

Reset State

X

表 23. Bit Descriptions – Device Configuration Register 2

Bit

Field Name

Access

Description

Reserved. Read-only, returns 0 when read.

7

Reserved

RO

Custom Battery Charging Feature Enable. This bit controls the ability to

write to the battery charging feature configuration controls.

0 = The HiCurAcpModeEn and cpdEN bits are read only and the

values are loaded from the OTP ROM.

6

customBCfeatures

RW

1 = The HiCurAcpModeEn and cpdEN, bits are read/write and can

be loaded by EEPROM or written by SMBus. from this register.

This bit may be written simultaneously with HiCurAcpModeEn and

cpdEN.

Power enable polarity. This bit is loaded at the de-assertion of reset with

the value of the PWRCTL_POL pin.

0 = PWRCTL polarity is active low

1 = PWRCTL polarity is active high

When the TUSB8041 is in I²C mode, the TUSB8041 loads this bit from

the contents of the EEPROM.

5

pwrctlPol

RW

When the TUSB8041 is in SMBUS mode, the value may be over-written

by an SMBus host.

High-current ACP mode enable. This bit enables the high-current tablet

charging mode when the automatic battery charging mode is enabled for

downstream ports.

0 = High current divider mode disabled

1 = High current divider mode enabled

4

3

2

HiCurAcpModeEn

RO/RW

RORW

RW

This bit is read only unless the customBCfeatures bit is set to 1. If

customBCfeatures is 0, the value of this bit reflects the value of the OTP

ROM HiCurAcpModeEn bit.

Enable Device Attach Detection. This bit enables device attach detection

(aka, cell phone detect) when autoMode is enabled.

0 = Device Attach detect is disabled in automode.

1 = Device Attach detect is enabled in automode..

cpdEN

This bit is read only unless the customBCfeatures bit is set to 1. If

customBCfeatures is 0 the value of this bit reflects the value of the OTP

ROM cpdEN bit.

DSPORT ECR Enable. This bit enables full implementation of the

DSPORT ECR (April 2013).

0 = The DSPORT ECR (April 2013) is enabled with exception of the

following: Changes related to when CCS bit is set upon entering U0,

and Changes related to avoiding or reporting compliance mode entry

dsportEcr_en

1 = The full DSPORT ECR (April 2013) is enabled.

The default value of this bit is 0. The value returned from this register will

be the OR of this bit and the OTP ROM dsport_ecr_en bit.

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表 23. Bit Descriptions – Device Configuration Register 2 (接下页)

Automatic Mode Enable. This bit is loaded at the de-assertion of reset

with the value of the AUTOENz/HS_SUSPEND pin.

The automatic mode only applies to downstream ports with battery

charging enabled when the upstream port is not connected. Under these

conditions:

0 = Automatic mode battery charging features are enabled.

1

0

autoModeEnz

RW

RO

1 = Automatic mode is disabled; only Battery Charging DCP and

CDP mode is supported.

NOTE: When the upstream port is connected, Battery Charging CDP

mode will be supported on all ports that enabled for battery charging

support regardless of the value of this bit with the exception of Port 1.

CDP on Port 1 is not supported when Automatic Mode is enabled.

RSVD

Reserved. Read only, returns 0 when read.

8.5.12 USB 2.0 Port Polarity Control Register

表 24. Register Offset Bh

Bit No.

7

0

6

0

5

4

3

2

0

1

0

Reset State

0

表 25. Bit Descriptions – USB 2.0 Port Polarity Control Register

Bit

7

Field Name

customPolarity

RSVD

Access

Description

Custom USB 2.0 Polarity. This bit controls the ability to write the

p[4:0]_usb2pol bits.

0 = The p[4:0]_usb2pol bits are read only and the values are loaded

from the OTP ROM.

RW

1 = The p[4:0]_usb2pol bits are read/write and can be loaded by

EEPROM or written by SMBus. from this register

This bit may be written simultaneously with the p[4:0]_usb2pol bits

Reserved. Read only, returns 0 when read.

6:5

4

RO

Downstream Port 4 DM/DP Polarity. This controls the polarity of the port.

0 = USB 2.0 port polarity is as documented by the pin out

1 = USB 2.0 port polarity is swapped from that documented in the

pin out, i.e. DM becomes DP, and DP becomes DM.

p4_usb2pol

RO/RW

This bit is read only unless the customPolarity bit is set to 1. If

customPolarity is 0 the value of this bit reflects the value of the OTP

ROM p4_usb2pol bit.

Downstream Port 3 DM/DP Polarity. This controls the polarity of the port.

0 = USB 2.0 port polarity is as documented by the pin out

1 = USB 2.0 port polarity is swapped from that documented in the

pin out, i.e. DM becomes DP, and DP becomes DM.

3

2

p3_usb2pol

p2_usb2pol

RO/RW

This bit is read only unless the customPolarity bit is set to 1. If

customPolarity is 0 the value of this bit reflects the value of the OTP

ROM p3_usb2pol bit.

Downstream Port 2 DM/DP Polarity. This controls the polarity of the port.

0 = USB 2.0 port polarity is as documented by the pin out

1 = USB 2.0 port polarity is swapped from that documented in the

pin out, i.e. DM becomes DP, and DP becomes DM.

This bit is read only unless the customPolarity bit is set to 1. If

customPolarity is 0 the value of this bit reflects the value of the OTP

ROM p2_usb2pol bit.

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表 25. Bit Descriptions – USB 2.0 Port Polarity Control Register (接下页)

Downstream Port 1 DM/DP Polarity. This controls the polarity of the port.

0 = USB 2.0 port polarity is as documented by the pin out

1 = USB 2.0 port polarity is swapped from that documented in the

pin out, i.e. DM becomes DP, and DP becomes DM.

1

0

p1_usb2pol

p0_usb2pol

RORW

This bit is read only unless the customPolarity bit is set to 1. If

customPolarity is 0 the value of this bit reflects the value of the OTP

ROM p1_usb2pol bit.

Upstream Port DM/DP Polarity. This controls the polarity of the port.

0 = USB 2.0 port polarity is as documented by the pin out

1 = USB 2.0 port polarity is swapped from that documented in the

pin out, i.e. DM becomes DP, and DP becomes DM.

RO/RW

This bit is read only unless the customPolarity bit is set to 1. If

customPolarity is 0 the value of this bit reflects the value of the OTP

ROM p0_usb2pol bit.

8.5.13 UUID Registers

表 26. Register Offset 10h-1Fh

Bit No.

7

6

5

4

3

2

1

0

Reset State

X

表 27. Bit Descriptions – UUID Byte N Register

Bit

Field Name

Access

Description

UUID byte N. The UUID returned in the Container ID descriptor. The

value of this register is provided by the device and is meets the UUID

requirements of Internet Engineering Task Force (IETF) RFC 4122 A

UUID URN Namespace.

7:0

uuidByte[n]

RO

8.5.14 Language ID LSB Register

表 28. Register Offset 20h

Bit No.

7

0

6

0

5

0

4

0

3

1

2

0

1

0

1

Reset State

表 29. Bit Descriptions – Language ID LSB Register

Bit

Field Name

Access

Description

Language ID least significant byte. This register contains the value

returned in the LSB of the LANGID code in string index 0. The

TUSB8041 only supports one language ID. The default value of this

register is 09h representing the LSB of the LangID 0409h indicating

English United States.

7:0

langIdLsb

RO/RW

When customStrings is 1, this field may be over-written by the contents

of an attached EEPROM or by an SMBus host.

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ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

8.5.15 Language ID MSB Register

表 30. Register Offset 21h

Bit No.

7

0

6

0

5

0

4

0

3

0

2

1

0

Reset State

表 31. Bit Descriptions – Language ID MSB Register

Bit

Field Name

Access

Description

Language ID most significant byte. This register contains the value

returned in the MSB of the LANGID code in string index 0. The

TUSB8041 only supports one language ID. The default value of this

register is 04h representing the MSB of the LangID 0409h indicating

English United States.

7:0

langIdMsb

RO/RW

When customStrings is 1, this field may be over-written by the contents

of an attached EEPROM or by an SMBus host.

8.5.16 Serial Number String Length Register

表 32. Register Offset 22h

Bit No.

7

0

6

0

5

4

3

2

0

1

0

Reset State

0

1

表 33. Bit Descriptions – Serial Number String Length Register

Bit

Field Name

Access

Description

7:6

RSVD

RO

Reserved. Read only, returns 0 when read.

Serial number string length. The string length in bytes for the serial

number string. The default value is 18h indicating that a 24 byte serial

number string is supported. The maximum string length is 32 bytes.

When customSernum is 1, this field may be over-written by the contents

of an attached EEPROM or by an SMBus host.

5:0

serNumStringLen

RO/RW

When the field is non-zero, a serial number string of serNumbStringLen

bytes is returned at string index 1 from the data contained in the Serial

Number String registers.

8.5.17 Manufacturer String Length Register

表 34. Register Offset 23h

Bit No.

7

0

6

0

5

4

3

2

0

1

0

Reset State

0

表 35. Bit Descriptions – Manufacturer String Length Register

Bit

Field Name

Access

Description

7

RSVD

RO

Reserved. Read only, returns 0 when read.

Manufacturer string length. The string length in bytes for the

manufacturer string. The default value is 0, indicating that a manufacturer

string is not provided. The maximum string length is 64 bytes.

When customStrings is 1, this field may be over-written by the contents

of an attached EEPROM or by an SMBus host.

6:0

mfgStringLen

RO/RW

When the field is non-zero, a manufacturer string of mfgStringLen bytes

is returned at string index 3 from the data contained in the Manufacturer

String registers.

25

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8.5.18 Product String Length Register

表 36. Register Offset 24h

Bit No.

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset State

表 37. Bit Descriptions – Product String Length Register

Bit

Field Name

Access

Description

7

RSVD

RO

Reserved. Read only, returns 0 when read.

Product string length. The string length in bytes for the product string.

The default value is 0, indicating that a product string is not provided.

The maximum string length is 64 bytes.

When customStrings is 1, this field may be over-written by the contents

of an attached EEPROM or by an SMBus host.

6:0

prodStringLen

RO/RW

When the field is non-zero, a product string of prodStringLen bytes is

returned at string index 3 from the data contained in the Product String

registers.

8.5.19 Serial Number String Registers

表 38. Register Offset 30h-4Fh

Bit No.

7

6

5

x

4

x

3

x

2

x

1

x

0

x

Reset State

X

表 39. Bit Descriptions – Serial Number Registers

Bit

Field Name

Access

Description

Serial Number byte N. The serial number returned in the Serial Number

string descriptor at string index 1. The default value of these registers is

assigned by TI. When customSernum is 1, these registers may be over-

written by EEPROM contents or by an SMBus host.

7:0

serialNumber[n]

RO/RW

8.5.20 Manufacturer String Registers

表 40. Register Offset 50h-8Fh

Bit No.

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset State

表 41. Bit Descriptions – Manufacturer String Registers

Bit

Field Name

Access

Description

Manufacturer string byte N. These registers provide the string values

returned for string index 3 when mfgStringLen is greater than 0. The

number of bytes returned in the string is equal to mfgStringLen.

The programmed data should be in UNICODE UTF-16LE encodings as

defined by The Unicode Standard, Worldwide Character Encoding,

Version 5.0.

7:0

mfgStringByte[n]

RW

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8.5.21 Product String Registers

表 42. Register Offset 90h-CFh

Bit No.

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset State

表 43. Bit Descriptions – Product String Byte N Register

Bit

Field Name

Access

Description

Product string byte N. These registers provide the string values returned

for string index 2 when prodStringLen is greater than 0. The number of

bytes returned in the string is equal to prodStringLen.

The programmed data should be in UNICODE UTF-16LE encodings as

defined by The Unicode Standard, Worldwide Character Encoding,

Version 5.0.

7:0

prodStringByte[n]

RO/RW

8.5.22 Additional Feature Configuration Register

表 44. Register Offset F0h

Bit No.

7

0

6

0

5

4

3

2

0

1

0

Reset State

0

表 45. Bit Descriptions – Additional Feature Configuration Register

Bit

7:5

4

Field Name

RSVD

Access

RO

Description

Reserved. Read only, returns 0 when read.

stsOutputEn

RO/RW

Status output enable. This bit enables the HS, HS_SUSPEND, SS, and

SS_SUSPEND outputs..

0 = HS, HS_SUSPEND, SS, and SS_SUSPEND outputs are

disabled and tri-stated.

1 = HS, HS_SUSPEND, SS, and SS_SUSPEND outputs are

enabled.

This field may be over-written by EEPROM contents or by an SMBus

Host.

3:1

pwronTime

RW

Power On Delay Time. When OTP ROM pwronTime field is all zero , this

field sets the delay time from the removal disable of PWRCTL to the

enable of PWRCTL when transitioning battery charging modes. For

example, when disabling the power on a transition from a custom

charging mode to Dedicated Charging Port Mode. The nominal timing is

defined as follows:

TPWRON_EN = (pwronTime + 1) x 200 ms

(1)

This field may be over-written by EEPROM contents or by an SMBus

host.

USB3 Spread Spectrum Disable. This bit allows firmware to disable the

spread spectrum function of the USB3 phy PLL.

0

usb3spreadDis

RW

0 = Spread spectrum function is enabled

1= Spread spectrum function is disabled

27

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8.5.23 Device Status and Command Register

表 46. Register Offset F8h

Bit No.

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset State

表 47. Bit Descriptions – Device Status and Command Register

Bit

Field Name

Access

Description

7:2

RSVD

RO

Reserved. Read only, returns 0 when read.

SMBus interface reset. This bit loads the registers back to their GRSTz

values.

This bit is set by writing a 1 and is cleared by hardware on completion of

the reset. A write of 0 has no effect.

1

smbusRst

cfgActive

RSU

RCU

Configuration active. This bit indicates that configuration of the

TUSB8041 is currently active. The bit is set by hardware when the

device enters the I²C or SMBus mode. The TUSB8041 shall not connect

on the upstream port while this bit is 1.

When in the SMBus mode, this bit must be cleared by the SMBus host in

order to exit the configuration mode and allow the upstream port to

connect.

0

The bit is cleared by a writing 1. A write of 0 has no effect.

28

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ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

9 Applications and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TUSB8041 is a four-port USB 3.0 compliant hub. It provides simultaneous SuperSpeed USB and high-

speed/full-speed connections on the upstream port and provides SuperSpeed USB, high-speed, full-speed, or

low speed connections on the downstream port. The TUSB8041 can be used in any application that needs

additional USB compliant ports. For example, a specific notebook may only have two downstream USB ports. By

using the TUSB8041, the notebook can increase the downstream port count to five.

9.2 Typical Application

9.2.1 Discrete USB Hub Product

A common application for the TUSB8041 is as a self powered standalone USB hub product. The product is

powered by an external 5V DC Power adapter. In this application, using a USB cable TUSB8041’s upstream port

is plugged into a USB Host controller. The downstream ports of the TUSB8041 are exposed to users for

connecting USB hard drives, cameras, flash drives, and so forth.

USB

Type B

DC

PWR

Connector

US Port

TUSB8041

USB

PWR

USB

PWR

SWITCH

DS Port 1

DS Port 2 DS Port 3 DS Port 4

USB Type A

Connector

USB Type A

Connector

USB Type A

Connector

USB Type A

Connector

图 4. Discrete USB Hub Product

29

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Typical Application (接下页)

9.2.1.1 Design Requirements

表 48. Design Parameters

DESIGN PARAMETER

VDD Supply

EXAMPLE VALUE

1.1V

VDD33 Supply

3.3V

Upstream Port USB Support (SS, HS, FS)

SS, HS, FS

Downstream Port 1 USB Support (SS, HS, FS, LS)

Downstream Port 2 USB Support (SS, HS, FS, LS)

Downstream Port 3 USB Support (SS, HS, FS, LS)

Downstream Port 4 USB Support (SS, HS, FS, LS)

Number of Removable Downstream Ports

Number of Non-Removable Downstream Ports

Full Power Management of Downstream Ports

Individual Control of Downstream Port Power Switch

Power Switch Enable Polarity

SS, HS, FS, LS

4

0

Yes. (FULLPWRMGMTZ = 0)

Yes. (GANGED = 0)

Active High. (PWRCTL_POL = 1)

Battery Charge Support for Downstream Port 1

Battery Charge Support for Downstream Port 2

Battery Charge Support for Downstream Port 3

Battery Charge Support for Downstream Port 4

I2C EEPROM Support

Yes

No.

24MHz Clock Source

Crystal

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Upstream Port Implementation

The upstream of the TUSB8041 is connected to a USB3 Type B connector. This particular example has

GANGED pin and FULLPWRMGMTZ pin pulled low which results in individual power support each downstream

port. The VBUS signal from the USB3 Type B connector is feed through a voltage divider. The purpose of the

voltage divider is to make sure the level meets USB_VBUS input requirements

R1

90.9K

0402

1%

R2

C1

10uF

10K 1%

0402

1%

U1A

J1

48

42

40

USB_VBUS

GANGED/SMBA2/HS_UP

1

2

3

4

5

6

7

8

VBUS

DM

DP

USB_DM_UP

USB_DP_UP

54

53

USB_DM_UP

USB_DP_UP

FULLPWRMGMTZ/SMBA1/SS_UP

GND

CAP_UP_TXM

CAP_UP_TXP

USB_SSTXM_UP

56

55

C2

C3

0.1uF 0201

SSTXN

SSTXP

GND

SSRXN

SSRXP

SHIELD0

SHIELD1

USB_SSTXM_UP

USB_SSTXP_UP

R3

R4

USB_SSTXP_UP

USB_SSRXM_UP

USB_SSRXP_UP

4.7K

0402

5%

4.7K

0402

5%

59

58

USB_SSRXM_UP

USB_SSRXP_UP

9

10

11

TUSB8041

USB3_TYPEB_CONNECTOR

C4

0.1uF

C5

0.001uF

R5

1M

0402

5%

图 5. Upstream Port Implementation

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TUSB8041

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ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

9.2.1.2.2 Downstream Port 1 Implementation

The downstream port 1 of the TUSB8041 is connected to a USB3 Type A connector. With BATEN1 pin pulled

up, Battery Charge support is enabled for Port 1. If Battery Charge support is not needed, then pull-up resistor on

BATEN1 should be uninstalled.

BOARD_3P3V

FB1

R6

POPULATE

DN1_VBUS

VBUS_DS1

4.7K

0402

5%

DN1_VBUS

FOR BC SUPPORT

220 @ 100MHZ C6

0.1uF

J2

1

2

3

4

5

6

7

8

9

U1B

VBUS

DM

DP

2

1

USB_DM_DN1

USB_DP_DN1

USB_DM_DN1

USB_DP_DN1

GND

7

6

USB_SSRXM_DN1

USB_SSRXP_DN1

USB_SSRXM_DN1

USB_SSRXP_DN1

SSRXN

SSRXP

GND

SSTXN

SSTXP

0.1uF 0201

C7

C8

4

3

USB_SSTXM_DN1

USB_SSTXP_DN1

CAP_DN_TXM1

CAP_DN_TXP1

USB_SSTXM_DN1

USB_SSTXP_DN1

10

11

SHIELD0

SHIELD1

36

46

PWRCTRL1_BATEN1

OVERCUR1Z

PWRCTL1/BATEN1

OVERCUR1

USB3_TYPEA_CONNECTOR

R7

1M

C9

0.001uF

C10

0.1uF

TUSB8041

0402

5%

图 6. Downstream Port 1 Implementation

9.2.1.2.3 Downstream Port 2 Implementation

The downstream port 2 of the TUSB8041 is connected to a USB3 Type A connector. With BATEN2 pin pulled

up, Battery Charge support is enabled for Port 2. If Battery Charge support is not needed, then pull-up resistor on

BATEN2 should be uninstalled.

BOARD_3P3V

FB2

DN2_VBUS

VBUS_DS2

R8

DN2_VBUS

POPULATE

4.7K

0402

5%

FOR BC SUPPORT

220 @ 100MHZ

C11

0.1uF

J3

1

2

3

4

5

6

7

8

9

U1C

VBUS

DM

DP

10

USB_DM_DN2

USB_DP_DN2

USB_DM_DN2

9

USB_DP_DN2

GND

15

14

USB_SSRXM_DN2

USB_SSRXP_DN2

USB_SSRXM_DN2

USB_SSRXP_DN2

SSRXN

SSRXP

GND

SSTXN

SSTXP

12

11

USB_SSTXM_DN2

USB_SSTXP_DN2

CAP_DN2_TXM

CAP_DN2_TXP

C12

0.1uF 0201

USB_SSTXM_DN2

USB_SSTXP_DN2

C13

10

11

SHIELD0

SHIELD1

35

47

PWRCTRL2_BATEN2

OVERCUR2Z

PWRCTL2/BATEN2

OVERCUR2

R9

1M

C15

0.001uF

USB3_TYPEA_CONNECTOR

C14

0.1uF

0402

5%

TUSB8041

图 7. Downstream Port 2 Implementation

31

TUSB8041

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

www.ti.com.cn

9.2.1.2.4 Downstream Port 3 Implementation

The downstream port3 of the TUSB8041 is connected to a USB3 Type A connector. With BATEN3 pin pulled up,

Battery Charge support is enabled for Port 3. If Battery Charge support is not needed, then pull-up resistor on

BATEN3 should be uninstalled.

BOARD_3P3V

FB3

VBUS_DS3

R10

4.7K

0402

5%

DN3_VBUS

POPULATE

FOR BC SUPPORT

220 @ 100MHZ

C16

0.1uF

J4

1

2

3

4

5

6

7

8

9

U1D

VBUS

DM

DP

18

USB_DM_DN3

USB_DP_DN3

USB_DM_DN3

17

USB_DP_DN3

GND

23

22

USB_SSRXM_DN3

USB_SSRXP_DN3

USB_SSRXM_DN3

USB_SSRXP_DN3

SSRXN

SSRXP

GND

SSTXN

SSTXP

20

19

USB_SSTXM_DN3

USB_SSTXP_DN3

CAP_DN3_TXM

CAP_DN3_TXP

C17

0.1uF 0201

USB_SSTXM_DN3

USB_SSTXP_DN3

C18

10

11

SHIELD0

SHIELD1

33

44

PWRCTRL3_BATEN3

OVERCUR3Z

PWRCTL3/BATEN3

OVERCUR3

R11

C19

0.001uF

USB3_TYPEA_CONNECTOR

C20

0.1uF

1M

0402

5%

TUSB8041

图 8. Downstream Port 3 Implementation

9.2.1.2.5 Downstream Port 4 Implementation

The downstream port 4 of the TUSB8041 is connected to a USB3 Type A connector. With BATEN4 pin pulled

up, Battery Charge support is enabled for Port 4. If Battery Charge support is not needed, then pull-up resistor on

BATEN4 should be uninstalled.

BOARD_3P3V

FB4

VBUS_DS4

R12

4.7K

0402

5%

DN4_VBUS

POPULATE

FOR BC SUPPORT

220 @ 100MHZ

C21

0.1uF

J5

1

2

3

4

5

6

7

8

9

U1E

VBUS

DM

DP

25

USB_DM_DN4

USB_DP_DN4

USB_DM_DN4

24

USB_DP_DN4

GND

30

29

USB_SSRXM_DN4

USB_SSRXP_DN4

USB_SSRXM_DN4

USB_SSRXP_DN4

SSRXN

SSRXP

GND

SSTXN

SSTXP

27

26

USB_SSTXM_DN4

USB_SSTXP_DN4

CAP_DN4_TXM

CAP_DN4_TXP

C22

0.1uF 0201

USB_SSTXM_DN4

USB_SSTXP_DN4

C23

10

11

SHIELD0

SHIELD1

32

43

PWRCTRL4_BATEN4

OVERCUR4Z

PWRCTL4/BATEN4

OVERCUR4

R13

C25

0.001uF

USB3_TYPEA_CONNECTOR

C24

0.1uF

1M

0402

5%

TUSB8041

图 9. Downstream Port 4 Implementation

32

TUSB8041

www.ti.com.cn

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

9.2.1.2.6 VBUS Power Switch Implementation

This particular example uses the Texas Instruments TPS2561 Dual Channel Precision Adjustable Current-

Limited power switch. For details on this power switch or other power switches available from Texas Instruments,

refer to the Texas Instruments website.

BOARD_3P3V

BOARD_5V

R19

10K

0402

5%

R20

10K

0402

5%

C42

0.1uF

U2

2

3

9

DN1_VBUS

DN2_VBUS

ILIM1

DN1_VBUS

OVERCUR1Z

DN2_VBUS

OVERCUR2Z

IN

OUT1

FAULT1Z

OUT2

10

8

PWRCTRL1_BATEN1

PWRCTRL2_BATEN2

4

5

PWRCTRL1_BATEN1

PWRCTRL2_BATEN2

EN1

EN2

6

FAULT2Z

ILIM

1

11

GND

PAD

7

C43

C45

0.1uF

+

C44

150uF

0.1uF

+

C46

150uF

TPS2561

R21

25.5K

0402

5%

Limiting DS Port VBUS current to 2.2A per port.

BOARD_3P3V

BOARD_5V

R22

10K

0402

5%

R23

10K

0402

5%

C47

0.1uF

U3

2

9

DN3_VBUS

DN4_VBUS

ILIM2

DN3_VBUS

IN

OUT1

FAULT1Z

OUT2

3

4

5

10

8

OVERCUR3Z

DN4_VBUS

PWRCTRL3_BATEN3

PWRCTRL4_BATEN4

EN1

EN2

6

OVERCUR4Z

FAULT2Z

ILIM

1

11

GND

PAD

7

C48

0.1uF

C50

+

C49

150uF

0.1uF

+

C51

150uF

TPS2561

R24

25.5K

0402

5%

Limiting DS Port VBUS current to 2.2A per port.

图 10. VBUS Power Switch Implementation

33

TUSB8041

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

www.ti.com.cn

9.2.1.2.7 Clock, Reset, and Misc

The PWRCTL_POL is left unconnected which results in active high power enable (PWRCTL1, PWRCTL2,

PWRCTL3, and PWRCTL4) for a USB VBUS power switch. The 1 µF capacitor on the GRSTN pin can only be

used if the VDD11 supply is stable before the VDD33 supply. The depending on the supply ramp of the two

supplies the capacitor may have to be adjusted.

U1F

C39

50

38

37

GRSTN

SCL/SMBCLK

SDA/SMBDAT

1uF

39

45

SMBUSZ/SS_SUSPEND

AUTOENZ/HS_SUSPEND

PWRCTL_POL

TEST

62

61

XI

41

49

64

R14

1M

XO

Y1

USB_R1

R15

TUSB8041

R16

4.7K

R18

4.7K

0402

5%

9.53K

0402

1%

24MHz

C40

C41

18pF

图 11. Clock, Reset, and Misc

9.2.1.2.8 TUSB8041 Power Implementation

BOARD_1P1V

VDD11

FB5

C26

0.1uF

C27

C28

C29

C30

C31

C32

C33

10uF

220 @ 100MHZ

0.1uF

U1G

16

VDD33

34

VDD33

60

52

63

VDD33

BOARD_3P3V

NC

FB6

C34

C35

0.1uF

C36

0.1uF

C37

0.1uF

C38

10uF

220 @ 100MHZ

0.1uF

TUSB8041

图 12. TUSB8041 Power Implementation

34

TUSB8041

www.ti.com.cn

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

9.2.1.3 Application Curves

图 13. Upstream Port

图 14. Downstream Port 1

图 15. Downstream Port 2

图 16. Downstream Port 3

图 17. Downstream Port 4

图 18. High-Speed Upstream Port

35

TUSB8041

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

www.ti.com.cn

图 19. High-Speed Downstream Port 1

图 20. High-Speed Downstream Port 2

图 21. High-Speed Downstream Port 3

图 22. High-Speed Downstream Port 4

36

TUSB8041

www.ti.com.cn

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

10 Power Supply Recommendations

10.1 TUSB8041 Power Supply

V_DDshould be implemented as a single power plane, as should V_DD33

.

•

The V_DDpins of the TUSB8041 supply 1.1 V (nominal) power to the core of the TUSB8041. This power rail

can be isolated from all other power rails by a ferrite bead to reduce noise.

•

The DC resistance of the ferrite bead on the core power rail can affect the voltage provided to the device due

to the high current draw on the power rail. The output of the core voltage regulator may need to be adjusted

to account for this or a ferrite bead with low DC resistance (less than 0.05 Ω) can be selected.

•

The V_DD33pins of the TUSB8041 supply 3.3 V power rail to the I/O of the TUSB8041. This power rail can be

isolated from all other power rails by a ferrite bead to reduce noise.

All power rails require a 10 µF capacitor or 1 µF capacitors for stability and noise immunity. These bulk

capacitors can be placed anywhere on the power rail. The smaller decoupling capacitors should be placed as

close to the TUSB8041 power pins as possible with an optimal grouping of two of differing values per pin.

10.2 Downstream Port Power

•

The downstream port power, VBUS, must be supplied by a source capable of supplying 5V and up to 900 mA

per port. Downstream port power switches can be controlled by the TUSB8041 signals. It is also possible to

leave the downstream port power always enabled.

•

A large bulk low-ESR capacitor of 22 µF or larger is required on each downstream port’s VBUS to limit in-rush

current.

The ferrite beads on the VBUS pins of the downstream USB port connections are recommended for both

ESD and EMI reasons. A 0.1µF capacitor on the USB connector side of the ferrite provides a low impedance

path to ground for fast rise time ESD current that might have coupled onto the VBUS trace from the cable.

10.3 Ground

It is recommended that only one board ground plane be used in the design. This provides the best image plane

for signal traces running above the plane. The thermal pad of the TUSB8041 and any of the voltage regulators

should be connected to this plane with vias. An earth or chassis ground is implemented only near the USB port

connectors on a different plane for EMI and ESD purposes.

37

TUSB8041

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

11.1.1 Placement

1. 9.53K ±1% resistor connected to pin USB_R1 should be placed as close as possible to the TUSB8041.

2. A 0.1 µF capacitor should be placed as close as possible on each VDD and VDD33 power pin.

3. The 100 nF capacitors on the SSTXP and SSTXM nets should be placed close to the USB connector (Type

A, Type B, and so forth).

4. The ESD and EMI protection devices (if used) should also be placed as possible to the USB connector.

5. If a crystal is used, it must be placed as close as possible to the TUSB8041’s XI and XO pins.

6. Place voltage regulators as far away as possible from the TUSB8041, the crystal, and the differential pairs.

7. In general, the large bulk capacitors associated with each power rail should be placed as close as possible to

the voltage regulators.

11.1.2 Package Specific

1. The TUSB8041 package has a 0.5-mm pin pitch.

2. The TUSB8041 package has a 6.0-mm x 6.0-mm thermal pad. This thermal pad must be connected to

ground through a system of vias.

3. All vias under device, except for those connected to thermal pad, should be solder masked to avoid any

potential issues with thermal pad layouts.

11.1.3 Differential Pairs

This section describes the layout recommendations for all the TUSB8041 differential pairs: USB_DP_XX,

USB_DM_XX, USB_SSTXP_XX, USB_SSTXM_XX, USB_SSRXP_XX, and USB_SSRXM_XX.

1. Must be designed with a differential impedance of 90 Ω ±10%.

2. In order to minimize cross talk, it is recommended to keep high speed signals away from each other. Each

pair should be separated by at least 5 times the signal trace width. Separating with ground as depicted in the

layout example will also help minimize cross talk.

3. Route all differential pairs on the same layer adjacent to a solid ground plane.

4. Do not route differential pairs over any plane split.

5. Adding test points will cause impedance discontinuity and will therefore negative impact signal performance.

If test points are used, they should be placed in series and symmetrically. They must not be placed in a

manner that causes stub on the differential pair.

6. Avoid 90 degree turns in trace. The use of bends in differential traces should be kept to a minimum. When

bends are used, the number of left and right bends should be as equal as possible and the angle of the bend

should be ≥ 135 degrees. This will minimize any length mismatch causes by the bends and therefore

minimize the impact bends have on EMI.

7. Minimize the trace lengths of the differential pair traces. The maximum recommended trace length for SS

differential pair signals and USB 2.0 differential pair signals is eight inches. Longer trace lengths require very

careful routing to assure proper signal integrity.

8. Match the etch lengths of the differential pair traces (i.e. DP and DM or SSRXP and SSRXM or SSTXP and

SSTXM). There should be less than 5 mils difference between a SS differential pair signal and its

complement. The USB 2.0 differential pairs should not exceed 50 mils relative trace length difference.

9. The etch lengths of the differential pair groups do not need to match (i.e. the length of the SSRX pair to that

of the SSTX pair), but all trace lengths should be minimized.

10. Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure

that the same via type and placement are used for both signals in a pair. Any vias used should be placed as

close as possible to the TUSB8041 device.

11. To ease routing, the polarity of the SS differential pairs can be swapped. This means that SSTXP can be

routed to SSTXM or SSRXM can be routed to SSRXP.

12. To ease routing of the USB2 DP and DM pair, the polarity of these pins can be swapped. If this is done, the

38

TUSB8041

www.ti.com.cn

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

Layout Guidelines (接下页)

appropriate Px_usb2pol register, where x = 0, 1, 2, 3, or 4, must be set.

13. Do not place power fuses across the differential pair traces.

11.2 Layout Examples

11.2.1 Upstream Port

图 23. Example Routing of Upstream Port

39

TUSB8041

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

www.ti.com.cn

Layout Examples (接下页)

11.2.2 Downstream Port

图 24. Example Routing of Downstream Port

The remaining three downstream ports routing can be similar to the example provided.

40

TUSB8041

www.ti.com.cn

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

12 器件和文档支持

12.1 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.2 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.3 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

41

TUSB8041

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

www.ti.com.cn

13 机械、封装和可订购信息

以下页中包括机械封装、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据发生变化时，

我们可能不会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。

42

TUSB8041

www.ti.com.cn

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

PACKAGE OUTLINE

RGC0064G

VQFN - 1 mm max height

S

C

A

L

E

1

.

5

0

PLASTIC QUAD FLATPACK - NO LEAD

9.1

8.9

B

A

PIN 1 INDEX AREA

9.1

8.9

(0.1) TYP

LEADFRAME PROFILE

OPTION

S

C

A

L

E

8

.

0

1 MAX

C

SEATING PLANE

0.08

0.05

0.00

2X 7.5

(0.2) TYP

6

0.05

17

32

60X 0.5

16

33

SEE DETAIL

2X

EXPOSED

THERMAL PAD

7.5

1

48

0.30

64X

64

49

PIN 1 ID

(OPTIONAL)

0.18

0.5

0.3

0.1

C A

B

64X

0.05

4222053/B 06/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

43

TUSB8041

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

www.ti.com.cn

EXAMPLE BOARD LAYOUT

RGC0064G

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

6)

SYMM

64

49

64X (0.6)

1

48

64X (0.24)

8X (1.01)

60X (0.5)

SYMM

18X (1.16)

(8.8)

(0.58)

TYP

(

0.2) TYP

VIA

(0.58) TYP

33

16

17

32

18X (1.16)

(8.8)

8X (1.01)

(R0.05)

ALL PAD CORNERS

LAND PATTERN EXAMPLE

SCALE:10X

0.07 MIN

ALL SIDES

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222053/B 06/2015

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

44

TUSB8041

www.ti.com.cn

ZHCSCN9E –JUNE 2014–REVISED JUNE 2016

EXAMPLE STENCIL DESIGN

RGC0064G

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

25X ( 0.96)

64

(1.16) TYP

(R0.05) TYP

49

64X (0.6)

1

48

64X (0.24)

60X (0.5)

(1.16)

TYP

SYMM

(8.8)

(R0.05) TYP

33

16

METAL

TYP

17

32

SYMM

(8.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

64% PRINTED SOLDER COVERAGE BY AREA

SCALE:12X

4222053/B 06/2015

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

45

PACKAGE MATERIALS INFORMATION

www.ti.com

31-May-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TUSB8041IRGCR

TUSB8041IRGCT

TUSB8041RGCR

TUSB8041RGCT

VQFN

RGC

64

2000

250

330.0

180.0

330.0

180.0

16.4

9.3

1.1

12.0

16.0

Q2

2500

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

31-May-2019

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TUSB8041IRGCR

TUSB8041IRGCT

TUSB8041RGCR

TUSB8041RGCT

VQFN

RGC

64

2000

250

367.0

210.0

367.0

210.0

367.0

185.0

367.0

185.0

38.0

35.0

38.0

35.0

2500

250

Pack Materials-Page 2

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

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所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

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邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122


型号：	TUSB8041IRGCR
厂家：	TEXAS INSTRUMENTS
描述：	4 端口 5Gbps SuperSpeed USB 3.0 集线器 \| RGC \| 64 \| -40 to 85 外围集成电路
文件：	总50页 (文件大小：2470K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TUSB8041IRGCR [TI]

相关型号：

TUSB8041IRGCT

TUSB8041RGCR

TUSB8041RGCT

TUSB8042

TUSB8042A

TUSB8042AIRGCR

TUSB8042AIRGCT

TUSB8042ARGCR

TUSB8042ARGCT

TUSB8042RGCR

TUSB8042RGCT

TUSB8043