TVP7002_16 [TI]
TRIPLE 8-/10-BIT 165-/110-MSPS VIDEO AND GRAPHICS DIGITIZER WITH HORIZONTAL PLL;
| 型号： | TVP7002_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TRIPLE 8-/10-BIT 165-/110-MSPS VIDEO AND GRAPHICS DIGITIZER WITH HORIZONTAL PLL |
| 文件： | 总52页 (文件大小：619K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TVP7002
www.ti.com
SLES206–MAY 2007
TRIPLE 8-/10-BIT 165-/110-MSPS,
VIDEO AND GRAPHICS DIGITIZER WITH HORIZONTAL PLL
FEATURES
•
Analog Channels
•
Horizontal PLL
–
–
–
–
–6-dB to 6-dB Analog Gain
Analog Input Multiplexers (MUXs)
Automatic Video Clamp
–
–
–
–
Fully Integrated Horizontal PLL for Pixel
Clock Generation
12-MHz to 165-MHz Pixel Clock Generation
From HSYNC Input
Three Digitizing Channels, Each With
Independently Controllable Clamp, Gain,
Offset, and Analog-to-Digital Converter
(ADC)
Adjustable Horizontal PLL Loop Bandwidth
for Minimum Jitter
5-Bit Programmable Subpixel Accurate
Positioning of Sampling Phase
–
–
Clamping: Selectable Clamping Between
Bottom Level and Mid-Level
•
Output Formatter
Offset: 1024-Step Programmable RGB or
YPbPr Offset Control
–
Supports 20-bit 4:2:2 Outputs With
Embedded Syncs
–
–
–
–
Gain: 8-Bit Programmable Gain Control
ADC: 8-/10-Bit 165-/110-MSPS ADC
Automatic Level Control (ALC) Circuit
–
Support for RGB/YCbCr 4:4:4 and YCbCr
4:2:2 Output Modes to Reduce Board
Traces
–
Dedicated DATACLK Output With
Programmable Output Polarity for Easy
Latching of Output Data
Composite Sync: Integrated
Sync-on-Green Extraction From
Green/Luminance Channel
•
System
–
–
Support for DC- and AC-Coupled Input
Signals
–
Industry-Standard Normal/Fast I2C
Interface With Register Readback
Capability
Supports Component Video Standards
480i, 576i, 480p, 576p, 720p, 1080i, and
1080p
–
–
Space-Saving 100-Pin TQFP Package
Thermally-Enhanced PowerPAD™ Package
for Better Heat Dissipation
–
Supports PC Graphics Inputs up to UXGA
–
Programmable RGB-to-YCbCr Color
Space Conversion
–
Glueless Interface to TVP9000/9001 Video
Processor Back-End Devices
<br/>
APPLICATIONS
•
•
•
•
•
LCD TV/Monitors/Projectors
DLP TV/Projectors
PDP TV/Monitors
LCOS TV/Monitors
PCTV Set-Top Boxes
•
•
•
•
•
Digital Image Processing
Video Capture/Video Editing
Scan Rate/Image Resolution Converters
Video Conferencing
Video/Graphics Digitizing Equipment
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TVP7002
www.ti.com
SLES206–MAY 2007
DESCRIPTION
TVP7002 is a complete solution for digitizing video and graphic signals in RGB or YPbPr color spaces. The
device supports pixel rates up to 165 MHz. Therefore, it can be used for PC graphics digitizing up to the VESA
standard of UXGA (1600 × 1200) resolution at 60-Hz screen refresh rate, and in video environments for the
digitizing of digital TV formats, including HDTV up to 1080p.
The TVP7002 is powered from 3.3-V and 1.9-V supply and integrates a triple high-performance analog-to-digital
(A/D) converter with clamping functions and variable gain, independently programmable for each channel. The
clamp timing window is provided by an external pulse or can be generated internally. The TVP7002 includes
analog slicing circuitry on the SOG inputs to support sync-on-luminance or sync-on-green extraction. In addition,
TVP7002 can extract discrete HSYNC and VSYNC from composite sync using a sync slicer.
TVP7002 also contains a complete horizontal PLL block to generate a pixel clock from the HSYNC input. Pixel
clock output frequencies range from 12 MHz to 165 MHz.
All programming of the part is done via an industry-standard I2C interface, which supports both reading and
writing of register settings. The TVP7002 is available in a space-saving 100-pin TQFP PowerPAD package.
ORDERING INFORMATION
PACKAGED DEVICES
TA
PACKAGE OPTION
100-PIN PLASTIC FLATPACK PowerPAD™
TVP7002PZP
Tray
Reel
0°C to 70°C
TVP7002PZPR
2
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TVP7002
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SLES206–MAY 2007
FUNCTIONAL BLOCK DIAGRAM
Clamp
Clamp
Clamp
RIN_1
Gain and
Offset
10-bit
ADC
RIN_2
RIN_3
ROUT[9:0]
GOUT[9:0]
BOUT[9:0]
Color Space
Conversion
and
GIN_1
GIN_2
GIN_3
GIN_4
Output
Gain and
Offset
10-bit
ADC
Formatter
4:4:4 to 4:2:2
Conversion
BIN_1
BIN_2
BIN_3
Gain and
Offset
10-bit
ADC
SOGIN_1
SOGIN_2
SOGIN_3
DATACLK
SOGOUT
HSOUT
HSYNC_A
HSYNC_B
VSOUT
FIDOUT
VSYNC_A
VSYNC_B
COAST
Timing Processor
and
Clock Generation
CLAMP
EXT_CLK
FILT1
FILT2
PWDN
RESETB
SCL
SDA
I2CA
Host
Interface
3
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SLES206–MAY 2007
TERMINAL ASSIGNMENTS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SOGIN_1
GIN_1
1
SDA
2
SCL
3
I2CA
TMS
AGND
4
AVDD
5
RESETB
PWDN
DVDD
GND
IOGND
IOVDD
R_0
AGND
6
AVDD
7
AVDD
8
AGND
RIN_3
9
RIN_2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
RIN_1
R_1
A33GND
A33VDD
A33VDD
A33GND
BIN_3
TVP7002
100-Pin TQFP Package
(Top View)
R_2
R_3
R_4
IOGND
R_5
BIN_2
R_6
BIN_1
R_7
AVDD
R_8
AGND
R_9
NSUB
IOGND
IOVDD
G_0
FIDOUT
VSOUT
HSOUT
SOGOUT
G_1
4
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SLES206–MAY 2007
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
ANALOG VIDEO
RIN_1
RIN_2
RIN_3
GIN_1
GIN_2
GIN_3
GIN_4
BIN_1
BIN_2
BIN_3
11
10
9
I
I
I
I
I
I
I
I
I
I
Analog video input for R/Pr 1
Analog video input for R/Pr 2
Analog video input for R/Pr 3
Analog video input for G/Y 1
Analog video input for G/Y 2
Analog video input for G/Y 3
Analog video input for G/Y 4
Analog video input for B/Pb 1
Analog video input for B/Pb 2
Analog video input for B/Pb 3
2
100
98
96
18
17
16
The inputs must be AC coupled. The recommended coupling capacitor is 0.1 µF. Unused analog
inputs should be connected to ground using a 10-nF capacitor.
CLOCK SIGNALS
DATACLK
28
80
O
I
Data clock output
EXT_CLK
External clock input. May be used as a timing reference for the mode detection block instead of
the internal clock reference. May also be used as the ADC sample clock instead of the H-PLL
generated clock.
DIGITAL VIDEO
ROUT[9:0]
GOUT[9:0]
BOUT[9:0]
55–59, 61–65
43-52
O
O
O
Digital video output of R/Cr, ROUT[9] is the most-significant bit (MSB).
Digital video output of G/Y, GOUT[9] is the MSB.
Digital video output of B/Cb, BOUT[9] is the MSB.
For 4:2:2 mode, multiplexed CbCr data is output on BOUT[9:0].
Unused outputs can be left unconnected.
29-38
MISCELLANEOUS SIGNALS
PWDN
70
I
Power down input
0 = Normal mode
1 = Power down
RESETB
TMS
71
72
87
88
89
I
I
Reset input, active low. Outputs are placed in a high-impedance mode during reset (see
Table 8).
Test mode select input, active high. Used to enable scan test mode. For normal operation,
connect to ground.
FILT1
FILT2
O
O
I
External filter connection for the horizontal PLL. A 0.1-µF capacitor in series with a 1.5-kΩ
resistor should be connected from this pin to pin 89 (see Figure 4).
External filter connection for the horizontal PLL. A 4.7-nF capacitor should be connected from
this pin to pin 89 (see Figure 4).
PLL_F
Horizontal PLL filter internal supply connection
HOST INTERFACE
I2CA
73
I
I2C slave address input. Has internal pulldown resistor (see Table 7).
0 = Slave address = B8h
1 = Slave address = BAh
SCL
SDA
74
75
I
I2C clock input
I/O I2C data bus
5
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SLES206–MAY 2007
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
POWER SUPPLIES
NSUB
21, 91
I
I
I
I
I
I
I
I
I
I
Substrate ground. Connect to analog ground.
Analog power. Connect to 3.3 V.
A33VDD
A33GND
AGND
13, 14, 93, 94
12, 15, 92, 95
3, 5, 8, 20
4, 6, 7, 19
84, 85
Analog 3.3-V return. Connect to ground.
Analog 1.9-V return. Connect to ground.
Analog power. Connect to 1.9 V.
AVDD
PLL_AVDD
PLL_AGND
DGND
PLL analog power. Connect to 1.9 V.
PLL analog power return. Connect to ground.
Digital return. Connect to ground.
83, 86, 90
40, 68
DVDD
39, 69
Digital power. Connect to 1.9 V.
IOGND
27, 42, 54, 60,
67
Digital power return. Connect to ground.
IOVDD
26, 41, 53, 66
I
Digital power. Connect to 3.3 V or less for reduced noise.
SYNC SIGNALS
CLAMP
76
77
I
I
External Clamp input. Unused inputs can be connected to ground.
COAST
External PLL COAST signal input. Unused inputs can be connected to ground.
VSYNC_A
VSYNC_B
78
79
I
I
Vertical sync input A
Vertical sync input B
Unused inputs can be connected to ground.
HSYNC_A
HSYNC_B
81
82
I
I
Horizontal sync input A
Horizontal sync input B
Unused inputs can be connected to ground.
SOGIN1
SOGIN2
SOGIN3
1
99
97
I
I
I
Sync-on-green input 1
Sync-on-green input 2
Sync-on-green input 3
Unused inputs should be connected to ground using a 1-nF capacitor.
FIDOUT
22
O
Field ID output. Using bits 2 and 3 of register 16h, this pin may also be programmed to be the
internal sync processing clock output, coast output, clamp pulse output, or data enable.
VSOUT
HSOUT
SOGOUT
23
24
25
O
O
O
Vertical sync output
Horizontal sync output
Sync-on-green slicer output
6
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SLES206–MAY 2007
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
IOVDD to IOGND
–0.5 V to 4.5 V
DVDD to DGND
–0.5 V to 2.3 V
–0.5 V to 2.3 V
– 0.5 V to 4.5 V
–0.5 V to 4.5 V
–0.2 V to 2.3 V
–0.5 V to 4.5 V
0°C to 70°C
Supply voltage range
PLL_AVDD to PLL_AGND and AVDD to AGND
A33VDD to A33GND
VI to DGND
Digital input voltage range
Analog input voltage range
Digital output voltage range
AI to A33GND
VO to DGND
TA
Operating free-air temperature range
Storage temperature range
Tstg
–65°C to 150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
3.3
MAX
3.6
2
UNIT
V
IOVDD
DVDD
PLL_AVDD
AVDD
A33VDD
VI(P-P)
Digital I/O supply voltage
3
Digital supply voltage
1.8
1.9
V
Analog supply voltage for horizontal PLL
Analog supply voltage
1.8
1.9
2
V
1.8
1.9
2
V
Analog supply voltage
3
0.5
3.3
3.6
2
V
Analog input voltage (ac-coupling necessary)
Digital input voltage high
V
VIH
0.7 IOVDD
V
VIL
Digital input voltage low
0.3 IOVDD
V
IOH
High-level output current
2
–2
4
mA
mA
mA
mA
MHz
°C
IOL
Low-level output current
IOH_DATACLK
IOL_DATACLK
DATACLK high-level output current
DATACLK low-level output current
ADC conversion rate
–4
162
70
12
0
TA
Operating free-air temperature
7
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ELECTRICAL CHARACTERISTICS
IOVDD = 3.3 V, DVDD = 1.9 V, PLL_AVDD = 1.9 V, AVDD = 1.9 V, A33VDD = 3.3 V, TA = 25°C
PARAMETER
TEST CONDITIONS(1)
TYP(2)
TYP(3)
UNIT
POWER SUPPLY
IA33VDD
IIOVDD
IAVDD
3.3-V supply current
3.3-V supply current
78.75 MHz, BC = 5
78.75 MHz, BC = 5
78.75 MHz, BC = 5
78.75 MHz, BC = 5
78.75 MHz, BC = 5
78.75 MHz, BC = 5
162 MHz, BC = 8
162 MHz, BC = 8
162 MHz, BC = 8
162 MHz, BC = 8
162 MHz, BC = 8
162 MHz, BC = 8
67
21
67
mA
56
209
16
mA
mA
mA
mA
mW
mA
mA
mA
mA
mA
mW
mW
1.9-V supply current
206
16
IPLL_VDD
IDVDD
1.9-V supply current
1.9-V supply current
30
46
PTOT
Total power dissipation, normal mode
3.3-V supply current
743
110
35
893
110
102
279
23
IA33VDD
IIOVDD
IAVDD
3.3-V supply current
1.9-V supply current
275
22
IPLL_VDD
IDVDD
1.9-V supply current
1.9-V supply current
56
89
PTOT
Total power dissipation, normal mode
Total power dissipation, power-down mode
1112
15
1403
15
PDOWN
(1) BC = ADC bias control setting in I2C register, 2Ch.
(2) SMPTE color bar RGB input pattern used.
(3) Worst-case vertical line RGB input pattern used.
8
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ELECTRICAL CHARACTERISTICS
IOVDD = 3.3 V, DVDD = 1.9 V, PLL_AVDD = 1.9 V, AVDD = 1.9 V, A33VDD = 3.3 V, TA = 0°C to 70°C (unless otherwise
noted)
PARAMETER
ANALOG INTERFACE
Input voltage range
Input impedance, analog video inputs
DIGITAL LOGIC INTERFACE
TEST CONDITIONS(1)
MIN
TYP
MAX UNIT
By design
0.5
1
2
Vpp
ZI
By design
500
kΩ
CI
Input capacitance
Input impedance
Output voltage high
Output voltage low
By design
By design
IOH = 2 mA
IOL = –2 mA
IOH = 4 mA
IOH = –4 mA
By design
By design
10
pF
kΩ
V
ZI
500
VOH
VOL
0.8 IOVDD
0.8 IOVDD
0.7 IOVDD
0.2 IOVDD
0.2 IOVDD
0.3 IOVDD
V
VOH_SCLK DATACLK output voltage high
V
VOL_SCLK
VIH
DATACLK output voltage low
High-level input voltage
Low-level input voltage
V
V
VIL
V
ADCs
ADC full scale input range
ADC resolution
Clamp disabled
0.95
1
1.05
10
Vpp
bits
10-bit range
10 bit, 110 MHz, BC = 5
8 bit, 162 MHz, BC = 8
10 bit, 110 MHz, BC = 5
8 bit, 162 MHz, BC = 8
10 bit, 110 MHz, BC = 5
8 bit, 162 MHz, BC = 8
10 MHz, 1 VP-P at 110 MSPS
By design
–1
–1
–4
–4
±0.5
±0.5
±1
+1
DNL
INL
DC differential nonlinearity
DC integral nonlinearity
Missing code
LSB
LSB
+1
+4
±1
+4
none
none
55
SNR
Signal-to-noise ratio
dB
Analog 3-dB bandwidth
350
12
500
MHz
HORIZONTAL PLL
Clock jitter
500
ps
Phase adjustment
11.6
degree
MHz
VCO frequency range
By design
162
ANALOG ADC CHANNEL
Coarse gain full-scale control range
Coarse offset full-scale control range
Coarse offset step size
Gain control value NG = 15
Referred to 10-bit ADC output
Referred to 10-bit ADC output
±6
±124
4
dB
counts
counts
SYNC PROCESSING
Internal clock reference frequency
By design
6.3
MHz
(1) BC = ADC bias control setting in I2C register, 2Ch.
9
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TIMING REQUIREMENTS
PARAMETER
CLOCKS, VIDEO DATA, SYNC TIMING
Duty cycle DATACLK (CLK POL=0)
Duty cycle DATACLK (CLK POL=1)
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
51
44
1
%
%
t1
t2
t3
DATACLK rise time
DATACLK fall time
Output delay time
10% to 90%
90% to 10%
ns
ns
ns
1
0
2.5
(1) Measured at 162 MHz with 22-Ω series termination resistor and 10-pF load. Specified by characterization only.
t1
DATACLK
t2
VOH
ROUT, GOUT,
BOUT, HSOUT
Valid Data
Valid Data
VOL
t3
Figure 1. Clock, Video Data, and Sync Timing
10
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TIMING REQUIREMENTS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I2C HOST PORT TIMING
t1
Bus free time between STOP and START
Specified by design
Specified by design
Specified by design
Specified by design
Specified by design
Specified by design
Specified by design
Specified by design
Specified by design
Specified by design
1.3
0.6
0.6
0.6
100
0
µs
µs
µs
ns
t2
Setup time for a (repeated) START condition
Hold time (repeated) START condition
Setup time for a STOP condition
Data setup time
t3
t4
t5
ns
t6
Data hold time
0.9
250
250
400
400
µs
ns
t7
Rise time SDA and SCL signal
Fall time SDA and SCL signal
Capacitive load for each bus line
I2C clock frequency
t8
ns
Cb
fI2C
pF
kHz
Stop Start
Stop
SDA
SCL
Data
t7
t1
t6
t3
t6
t2
t5
t4
t8
Figure 2. I2C Host Port Timing
11
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FUNCTIONAL DESCRIPTION
Analog Channel
The TVP7002 contains three identical analog channels that are independently programmable. Each channel
consists of a clamping circuit, programmable gain control, programmable offset control, and an ADC.
Analog Input Switch Control
TVP7002 has three analog channels that accept up to ten video inputs. The user can configure the internal
analog video switches via the I2C interface. The ten analog video inputs can be used for different input
configurations, some of which are:
•
•
Up to three SDTV, EDTV, or HDTV component video inputs (limited by number of SOG inputs)
Up to two 5-wire PC graphics inputs (limited by number of HSYNC and VSYNC inputs)
The input selection is performed by the input select register at I2C subaddress 19h a 1Ah (see Input Mux Select
1 and Input Mux Select 2).
Video Formats Supported
The TVP7002 supports A/D conversion of SDTV (480i, 576i), EDTV (480p, 765p), and HDTV (720p, 1080i,
1080p) YPbPr component video inputs. The TVP7002 also supports A/D conversion and color space conversion
of all standard PC graphics formats (RGB) from VGA up to UXGA.
A summary of the analog video standards supported by the TVP7002 module is show in Table 1.
Table 1. Analog Video Standards
VIDEO FORMAT
VIDEO STANDARDS
480i, 576i
SDTV (YPbPr Component)
EDTV (YPbPr Component)
HDTV (YPbPr Component)
PC Graphics (RGB Component)
SCART (RGB Component)
480p, 576p
720p, 1080i, 1080p
VGA to UXGA
576i
Analog Input Clamping
The TVP7002 provides dc restoration for all analog video inputs including the SOG slicer inputs. The dc
restoration circuit (a.k.a. clamp circuit) restores the ac-coupled video signal to a fixed dc level. One dc
restoration circuit is implemented prior to each of the three ADC, and a fourth one is located prior to the SOG
slicer. The dc restoration circuit can be programmed to operate as either a sync-tip clamp (a.k.a. coarse clamp)
or a back-porch clamp (a.k.a. fine clamp). The sync-tip clamp always clamps the video sync-tip level near the
bottom of the ADC range. The back-porch type clamp supports two clamping levels (bottom-level and mid-level)
that are selectable using bits 0, 1, and 2 of register 10h. When using the fine bottom-level clamp, an optional
300-mV common-mode offset may be selected using bit 7 of register 2Ah.
In general, the analog video input being used for horizontal synchronization purposes should always use the
sync-tip clamp; all other analog video inputs should use the back-porch clamp. The advantage of the back-porch
clamp is that it has negligible video droop or tilt across a video line.
12
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The selection between bottom- and mid-level clamping is performed by I2C subaddress 10h (see
Sync-On-Green Threshold). The fine clamps must also be enabled via I2C register 2Ah for proper operation. The
internal clamping time can be adjusted using the I2C clamp start and width registers at subaddress 05h and 06h,
respectively (see Clamp Start and Clamp Width).
Table 2. Recommended Clamp Setting by Video Mode
SOG Input
(Y/G)
Green ADC Ch
(Y/G)
Red ADC Ch
(Pr/R)
Blue ADC Ch
(Pb/B)
Video Mode
YPbPr Component
PC Graphics
Coarse
Coarse
Coarse
Fine Bottom-Level
Fine Bottom-Level
Fine Bottom-Level
Fine Mid-Level
Fine Bottom-Level
Fine Bottom-Level
Fine Mid-Level
Fine Bottom-Level
Fine Bottom-Level
SCART-RGB
A single-pole low-pass filter with three selectable cutoff frequencies (0.5, 1.7, and 4.8 MHz) is implemented in
the feedback loop of the sync-tip clamp circuit.
Programmable Gain Control
The TVP7002 provides a 4-bit coarse analog gain control (before A/D conversion) and an 8-bit fine digital gain
control (after A/D conversion). The coarse analog gain and the fine digital gain are both independently
programmable for each ADC channel.
Coarse Gain Control
The 4-bit coarse analog gain control has a 4:1 linear gain control range defined by the following equation.
Coarse Gain = 0.5 + NCG/10, where 0 ≤ NCG ≤ 15
0.5 ≤ Coarse_Gain ≤ 2.0
Default: NCG = 7 (Coarse_Gain = 1.2)
The 4-bit coarse gain control can scale a signal with a voltage-input compliance of 0.5-Vpp to 2-Vpp to a
full-scale 10-bit A/D output code range. The minimum gain corresponds to a code 0h (2-Vpp full-scale input,
–6-dB gain) while the maximum gain corresponds to code Fh (0.5-Vpp full-scale, +6 dB gain). The 4-bit coarse
gain control is independently controllable for each ADC channel (Red Coarse Gain, Green Coarse Gain, and
Blue Coarse Gain).
Fine Gain Control
The 8-bit fine digital gain control has a 2:1 linear gain control range defined by the following equation.
Fine Gain = 1.0 + NFG/256 where 0 ≤ NFG ≤ 255
1.0 ≤ Fine Gain < 2.0
Default: NFG = 0 (Fine Gain = 1.0)
The 8-bit fine gain control is independently controllable for each ADC channel (Red Fine Gain, Green Fine Gain,
and Blue Fine Gain). For a normal PC graphics input, the fine gain is used mostly.
Programmable Offset Control
The TVP7002 provides a 6-bit coarse analog offset control (before A/D conversion) and a 10-bit fine digital offset
control (after A/D conversion). The coarse analog offset and the fine digital offset are both independently
programmable for each ADC channel.
Coarse Offset Control
A 6-bit code sets the coarse offset (Red Coarse Offset, Green Coarse Offset, Blue Coarse Offset) with individual
adjustment per channel. The coarse offset ranges from –32 counts to +31 counts. The coarse offset registers
apply before the ADC.
Fine Offset Control
A 10-bit fine offset registers (Red Fine Offset, Green Fine Offset, Blue Fine Offset) apply after the ADC. The fine
offset ranges from –512 counts to +511 counts.
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Automatic Level Control (ALC)
The ALC circuit maintains the level of the signal to be set at a value which is programmed at fine offset I2C
register. It consists of pixel averaging filter and feedback loop. This ALC function can be enabled or disabled by
the I2C register at subaddress 26h.
The ALC circuit needs a timing pulse generated internally but the user should program the position properly. The
ALC pulse must be positioning after the clamp pulse. The position of ALC pulse is controlled by ALC placement
I2C register at address 31h. This is available only for internal ALC pulse timing. When using an external clamp
pulse, the fine clamp and the ALC both start on the leading edge of the external clamp pulse. Therefore, it is
recommended to keep the external clamp pulse as long as possible.
Analog-to-Digital Converters (ADCs)
All ADCs have a resolution of 10 bits and can operate up to 165 MSPS. All A/D channels receive an identical
clock from the on-chip phase-locked loop (PLL) at a frequency between 12 MHz and 165 MHz. All ADC
reference voltages are generated internally. Also the external sampling clock can be used.
Horizontal PLL
The horizontal PLL generates a high-frequency internal clock used by the ADC sampling and data clocking out
to derive the pixel output frequency with programmable phase. The reference signal for this PLL is the horizontal
sync signal supplied on the HSYNC input or from extracted horizontal sync of the sync slicer block for
embedded sync signals. The horizontal PLL consisted of phase detector, charge pump, loop filter, voltage
controlled oscillator (VCO), phase select, feedback divider, and post divider. The horizontal PLL block diagram is
shown in Figure 3.
PLL Control
Register 03h
Bit [5:3]
PLL Control
Register 03h
Bit [7:6]
Phase Select
Register 04h
Bit [7:3]
Post Divider
Register 04h
Bit [0]
COAST
HSYNC
Post
Divider
÷N
Phase
Detector
Charge
Pump
Loop
Filter
Phase
Select
VCO
ADC
Sampling
CLK
N = 1 or 2
Divider
External
Clock
PLL Divide
Register 01h and 02h
Bit [11:0]
Figure 3. Horizontal PLL Block Diagram
The COAST signal is used to allow the PLL to keep running at the same frequency, in the absence of the
incoming HSYNC signal or disordered HSYNC period. This is useful during the vertical sync period, or any other
time that the HSYNC is not available.
There are several PLL controls to produce the correct sampling clock. The 12-bit feedback divider register is
programmable to select exact multiplication number to generate the pixel clock in the range of 12 MHz to
165 MHz. The 3-bit loop filter current control register is to control the charge pump current that drives the
low-pass loop filter. The applicable current values are listed in the Table 3.
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The purpose of the 2-bit VCO range control is to improve the noise performance of the TVP7002. The frequency
ranges for the VCO are shown in Table 3. The phase of the ADC sample clock generated by the horizontal PLL
can be accurately controlled in 32 uniform steps over a single clock period (360/32 = 11.25 degrees phase
resolution) using the phase select register located at subaddress 04h.
The horizontal PLL characteristics are determined by the loop filter design, the PLL charge pump current, and
the VCO range setting. The loop filter design is shown in Figure 4. Supported settings of VCO range and charge
pump current for VESA standard display modes are listed in Table 3.
89
PLL_F
4.7 nF
88
87
1.5 kW
FILT2
FILT1
0.1 µF
TVP7002
Figure 4. Horizontal PLL Loop Filter
In addition to sourcing the ADC sample clock from the horizontal PLL, an external pixel clock can be used (from
pin 80).
Table 3. Recommended VCO Range and Charge Pump Current Settings for Supporting Standard Display
Formats
PLL
OUTPUT
DIVIDER
REG 04h
[0]
VCO
RANGE
REG 03h
[7:6]
CP
FRAME
RATE
(Hz)
PIXEL
RATE
(MHz)
PLLDIV
[11:4] REG
01h [7:0]
PLLDIV
[3:0] REG
02h [7:4]
LINE RATE
(kHz)
DIVIDER
TOTAL
PIX/LINE
CURRENT
REG 03h
[5:3]
STANDARD
RESOLUTION
REG 03h
640 × 480
640 × 480
59.94
72.809
75
31.469
37.861
37.5
25.175
31.5
31.5
36
800
32h
34h
34h
34h
40h
42h
41h
42h
41h
54h
53h
52h
56h
5Ah
68h
6Ah
6Bh
69h
69h
6Ch
61h
74h
76h
64h
77h
79h
7Ah
87h
00h
00h
80h
00h
00h
00h
00h
00h
80h
00h
00h
00h
00h
00h
00h
00h
00h
80h
80h
00h
80h
80h
80h
00h
00h
00h
00h
00h
20h
20h
20h
60h
58h
58h
58h
58h
58h
58h
A8h
A8h
A0h
50h
A0h
A0h
A0h
A0h
E8h
E8h
A0h
98h
E0h
A0h
98h
E0h
E0h
E0h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ULow (00b)
ULow (00b)
ULow (00b)
Low (01b)
Low (01b)
Low (01b)
Low (01b)
Low (01b)
Low (01b)
Low (01b)
Med (10b)
Med (10b)
Med (10b)
Low (01b)
Med (10b)
Med (10b)
Med (10b)
Med (10b)
High (11b)
High (11b)
Med (10b)
Med (10b)
High (11b)
Med (10b)
Med (10b)
High (11b)
High (11b)
High (11b)
100b
100b
100b
100b
011b
011b
011b
011b
011b
011b
101b
101b
100b
010b
100b
100b
100b
100b
101b
101b
100b
011b
100b
100b
011b
100b
100b
100b
832
VGA
640 × 480
840
640 × 480
85.008
56.25
43.269
35.156
37.879
48.077
46.875
53.674
48.363
56.476
60.023
68.677
47.396
47.776
60.289
68.633
63.981
79.976
91.146
64.744
65.317
82.278
55.469
55.935
70.635
80.43
832
800 × 600
36
1024
1056
1040
1056
1048
1344
1328
1312
1376
1440
1664
1696
1712
1688
1688
1728
1560
1864
1896
1600
1904
1936
1952
2160
800 × 600
60.317
72.188
75
40
SVGA
800 × 600
50
800 × 600
49.5
56.25
65
800 × 600
85.061
60.004
70.069
75.029
84.997
59.995
59.87
1024 × 768
1024 ×768
1024 × 768
1024 × 768
1280 × 768
1280 × 768
1280 × 768
1280 × 768
1280 × 1024
1280 × 1024
1280 × 1024
1400 × 1050
1400 × 1050
1400 × 1050
1440 × 900
1440 × 900
1440 × 900
1440 × 900
1600 × 1200
75
XGA
78.75
94.5
68.25
79.5
102.25
117.5
108
WXGA (I)
74.893
84.837
60.02
SXGA
75.025
85.024
59.948
59.978
74.867
59.901
59.887
74.984
84.842
60
135
157.5
101
SXGA+
121.75
156
88.75
106.5
136.75
157
WXGA (II)
UXGA
75
162
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Table 3. Recommended VCO Range and Charge Pump Current Settings for Supporting Standard Display
Formats (continued)
PLL
OUTPUT
DIVIDER
REG 04h
[0]
VCO
RANGE
REG 03h
[7:6]
CP
FRAME
RATE
(Hz)
PIXEL
RATE
(MHz)
PLLDIV
[11:4] REG
01h [7:0]
PLLDIV
[3:0] REG
02h [7:4]
LINE RATE
(kHz)
DIVIDER
TOTAL
PIX/LINE
CURRENT
REG 03h
[5:3]
STANDARD
RESOLUTION
REG 03h
720 × 480i
720 × 576i
29.97
25
15.374
15.625
31.469
31.25
45
13.5
13.5
858
864
35h
36h
35h
36h
67h
7Bh
89h
A5h
89h
A5h
A0h
00h
A0h
00h
20h
C0h
80h
00h
80h
00h
18h
18h
18h
18h
A0h
98h
98h
90h
E0h
D8h
0
0
0
0
0
0
0
0
0
0
ULow (00b)
ULow (00b)
ULow (00b)
ULow (00b)
Med (10b)
Med (10b)
Med (10b)
Med (10b)
High (11b)
High (11b)
011b
011b
011b
011b
100b
011b
011b
010b
100b
011b
720 × 480p
720 × 576p
1280 × 720p
1280 × 720p
1920 × 1080i
1920 × 1080i
1920 × 1080p
1920 × 1080p
59.94
50
27
858
27
864
60
74.25
74.25
74.25
74.25
148.5
148.5
1650
1980
2200
2640
2200
2640
Video
50
37.5
60
33.75
28.125
67.5
50
60
50
56.25
RGB-to-YCbCr Color Space Conversion
The TVP7002 supports RGB-to-YCbCr color space conversion (CSC) with I2C programmable coefficients. The
TVP7002 should default to the CSC coefficients required for HDTV component video inputs. The TVP7002
supports the ability to bypass the CSC block and defaults to the bypass mode (bit 4 of subaddress 18h).
RGB-to-YCbCr CSC coefficients for HDTV component video (see CEA-770.3-C, ITU-R BT.709)
(default coefficients):
G'
B'
R'
Y
00000016E3
FFFFFFF3AB
FFFFFFF178
000000024F
0000001000
FFFFFFFE88
00000006CE
FFFFFFFC55
0000001000
Pb
Pr
RGB-to-YCbCr CSC coefficients for SDTV component video (see CEA-770.2-C, ITU-R BT.601)
(informative only):
G'
B'
R'
Y
00000012C9
FFFFFFF566
FFFFFFF29A
00000003A6
0000001000
FFFFFFFD66
0000000991
FFFFFFFA9A
0000001000
Pb
Pr
4:4:4 to 4:2:2 Conversion
For 4:4:4 YPbPr component video inputs, the TVP7002 can downsample the chroma samples (CbCr) from 1x to
0.5x using a 27-tap half-band filter.
NOTE:
•
Selection between the 30-bit 4:4:4 output format and the 20-bit 4:2:2 output format is made
using bit 1 of register 15h.
•
•
Multiplexed CbCr data is output on BOUT [9:0] in the 20-bit 4:2:2 output format.
4:4:4 to 4:2:2 conversion is implemented after RGB to YCbCr color space conversion.
Sync Processing
Horizontal Sync Selection
The TVP7002 provides two HSYNC inputs and three analog SOG inputs for HDTV and PC graphics inputs. The
sync input used by the horizontal PLL is automatically selected based on activity detection.
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Sync Slicer
TVP7002 includes a circuit that compares the input signal on Green channel to a level 150 mV (typical value)
above the clamped level (sync tip). The slicing level is programmable by I2C register subaddress at 10h. The
digital output of the composite sync slicer is available on the SOGOUT pin.
Noise Immunity
In general, noise on a slowly varying input signal (i.e., sync falling edge) may cause a voltage comparator to
false trigger as the input passes through the linear range of the comparator. To improve the overall performance
of the TVP7002 sync slicer in the presence of noise on the SOG input, the voltage comparator includes
hysteresis. Maintaining a 50% slice level using the I2C programmable slice level control can further improve the
noise immunity of the Sync slicer. The slice level is programmable in 11.2-mV increments over a 350-mV range
as follows.
slice_level = (350 mV) × (NTH/31)
where 0 ≤ NTH ≤ 31, default: 11
0 ≤ slice_level ≤ 350 mV
Glitch Immunity
During white to black transitions, the input video waveform may undershoot below the sync slicer threshold. To
help attenuate the amplitude of such glitches, a single-pole low-pass filter with three selectable cutoff
frequencies (2.5, 10, and 33 MHz) is provided at the input of the SOG voltage comparator circuit. This filter is
bypassed in the default mode.
NOTE:
Although the low-pass filter may attenuate the amplitude of glitches present on the
SOG input, it also makes the sync falling edge less sharp.
Sync Separator
The sync separator automatically extracts VSYNC and HSYNC from the sliced composite sync input supplied at
the SOG input. The G or Y input containing the composite sync must be ac coupled to the SOG input pin using
a 1-nF capacitor. Support for PC graphics, SDTV, EDTV, and HDTV up to 1080p is provided.
Sync Activity Detection (Informative)
The TVP7002 provides activity detection on the sync inputs (VSYNC, HSYNC) to enable the host processor to
determine whether the PC graphics source is configured as a 3-wire, 4-wire, or 5-wire interface as defined here:
•
•
•
5 wire (G, B, R, HSYNC, VSYNC)
4 wire (G, B, R, CSYNC)
3 wire (G, B, R with SOG)
If activity is detected on the VSYNC input, the host processor should assume that the PC graphics input is
configured as a standard 5-wire interface. In this case, the HSYNC input of the TVP7002 should be configured
as an HSYNC input.
If activity is detected on the HSYNC input but not on the VSYNC input, the host processor should assume that
the PC graphics input is configured as a standard 4-wire interface. In this case, the HSYNC input of the
TVP7002 should be configured as a CSYNC input. The TVP7002 supports the following two types of CSYNC
inputs.
CSYNC = VSYNC XOR HSYNC (default)
CSYNC = VSYNC OR HSYNC
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If activity is not detected on either the HSYNC input or the VSYNC input, the host processor should assume that
the PC graphics input is configured as a standard 3-wire interface. In this case, the TVP7002 is automatically
configured for a SOG input.
VSYNC Input
Activity Detect
HSYNC Input
Activity Detect
PC Graphics
Input Type
1
1
0
0
1
0
1
0
5 wire (default)
Undefined (assume 5 wire)
4 wire
3 wire
The activity detection status for the VSYNC and HSYNC inputs is written to the I2C status register at subaddress
14h.
NOTE:
Pin 13 of a standard 15-pin VGA video connect can be either a horizontal sync
(HSYNC) or a composite sync (CSYNC).
NOTE:
For component video inputs, the active HSYNC and VSYNC should always be
derived from the selected SOG input. This can most easily be ensured by setting the
AHSO, AVSO, AHSS and AVSS bit fields in register 0Eh to logic 1.
NOTE:
For proper operation when separate HSYNC and VSYNC inputs are used, the
leading edge of VSYNC must not be presicely aligned with the leading edged of
HSYNC. A simple RC delay circuit will provide adequate delay in most applications.
Figure 5. Sync Processing
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Output Formatter
The output formatter sets how the data is formatted for output on the TVP7002 output buses. Table 4 shows the
available component video output modes.
Table 4. YCbCr Component Video Output Formats(1)
TERMINAL NAME
G_9
G_8
G_7
G_6
G_5
G_4
G_3
G_2
G_1
G_0
B_9
TERMINAL NUMBER
30-BIT 4:2:2 YCbCr
20-BIT 4:2:2 YCbCr
43
44
45
46
47
48
49
50
51
52
29
30
31
32
33
34
35
36
37
38
29
30
31
32
33
34
35
36
37
38
Y9
Y8
Y9
Y8
Y7
Y7
Y6
Y6
Y5
Y5
Y4
Y4
Y3
Y3
Y2
Y2
Y1
Y1
Y0
Y0
Cb9
Cb8
Cb7
Cb6
Cb5
Cb4
Cb3
Cb2
Cb1
Cb0
Cr9
Cr8
Cr7
Cr6
Cr5
Cr4
Cr3
Cr2
Cr1
Cr0
Cb9, Cr9
Cb8, Cr8
Cb7, Cr7
Cb6, Cr6
Cb5, Cr5
Cb4, Cr4
Cb3, Cr3
Cb2, Cr2
Cb1, Cr1
Cb0, Cr0
B_8
B_7
B_6
B_5
B_4
B_3
B_2
B_1
B_0
R_9
R_8
R_7
R_6
R_5
R_4
R_3
R_2
R_1
R_0
(1) 10-bit 4:2:2 YCbCr output format (i.e., ITU-R BT.656) is not supported by the TVP7002.
<br/>
NOTE:
In the 20-bit 4:2:2 YCbCr output mode, the unused red outputs (Cr[9:0]) are placed in
a high-impedance state.
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Embedded Syncs
Standard with embedded syncs insert SAV and EAV codes into the data stream on the rising and falling edges
of AVID. These codes contain the V and F bits which also define vertical timing. Table 5 gives the format of the
SAV and EAV codes.
H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line and
field counter varies depending on the standard. The P bits are protection bits:
P3 = V xor H
P2 = F xor H
P1 = F xor V
P0 = F xor V xor H
Table 5. EAV and SAV Sequence
Y9 (MSB)
Y8
1
Y7
1
Y6
1
Y5
1
Y4
1
Y3
1
Y2
1
Y1
1
Y0
1
Preamble
Preamble
Preamble
Status
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
V
H
P3
P2
P1
P0
0
0
The insertion location of the SAV/EAV codes on a video line is programmable using the AVID start/stop pixel
values located at subaddresses 40h through 43h.
NOTE:
When enabled (bit 0 of subaddress 15h), embedded syncs are present in both the Y
and C outputs.
Output Range Limits
The TVP7002 provides selectable output range limits in I2C subaddress 15h:
00 = RGB coding range (Y, Cb, and Cr range from 0 to 1023) (default)
01 = Extended coding range (Y, Cb, and Cr range from 4 to 1019)
10 = ITU-R BT.601 coding range (Y ranges from 64 to 940, Cb and Cr range from 64 to 960)
11 = Reserved
NOTE:
RGB coding range not allowed with embedded syncs.
Power Management
The TVP7002 supports both automatic and manual power-down modes. The automatic power-down mode can
be selected by setting bit 2 of subaddress 0Fh to logic 0.
In the automatic power-down mode, the TVP7002 powers down the ADCs, the ADC reference, and horizontal
PLL when activity is not detected on both the selected HSYNC input and the selected SOG input (VSYNC is no
longer used). The TVP7002 restores power whenever activity is detected on either the selected HSYNC input or
the selected SOG input.
The TVP7002 can also be placed in power down mode via the active high PWDN input (pin 70). When the
PWDN input is driven high, the TVP7002 powers down everything including the I2C interface and the digital
outputs are not placed in a high-impedance mode.
The TVP7002 can also be placed in a power down mode using bit 1 of register 0Fh.
Individual blocks of the TVP7002 can be independently powered down using register 2Bh.
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Timing
The TVP7002 supports RGB/YCbCr 4:4:4 and YCbCr 4:2:2 modes. Output timing is shown in Figure 6. All
timing diagrams are shown for operation with internal PLL clock at phase 0 and HSOUT Output Start = 0. For
the 4:2:2 mode, CbCr data output is on the BOUT[9:0] output port.
P12
P10
P11
RGBin
...
P0
P1
P3
HSYNC
DATACLK
NPD clocks latency
D0
D1
D3
D4
D5
RGBout
HSOUT
HSOUT Programmable Start
Programmable Width
4:4:4 RGB/YCbCr Output Timing. Npd = 18 clock cycles. HSOUT start is programmable in register 21h.
P12
P10
P11
RGBin
...
P0
P1
P3
HSYNC
DATACLK
NPD clocks latency
Y0
Y1
Y3
Y4
Y5
Gout
Bout
U0
V1
U2
V3
U4
HSOUT Programmable Start
Programmable Width
HSOUT
4:2:2YCbCr Output Timing. Npd = 39 clock cycles. HSOUT start is programmable in register 21h.
Figure 6. Output Timing Diagram
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I2C Host Interface
Communication with the TVP7002 device is via an I2C host interface. The I2C standard consists of two signals,
serial input/output data (SDA) line and input clock line (SCL), which carry information between the devices
connected to the bus. A third signal (I2CA) is used for slave address selection. Although an I2C system can be
multi-mastered, the TVP7002 can function as a slave device only.
Since SDA and SCL are kept open-drain at logic high output level or when the bus is not driven, the user should
connect SDA and SCL to a positive supply voltage via a pullup resistor on the board. SDA is implemented
bidirectional. The slave addresses select, terminal 73 (I2CA), enables the use of two TVP7002 devices tied to
the same I2C bus, as it controls the least-significant bit of the I2C device address
Table 6. I2C Host Interface Terminal Description
SIGNAL
I2CA
TYPE
DESCRIPTION
Slave address selection
Input clock line
I
I
SCL
SDA
I/O
Input/output data line
Reset and I2C Bus Address Selection
TVP7002 can respond to two possible chip addresses. The address selection is made at reset by an externally
supplied level on the I2CA pin. The TVP7002 device samples the level of terminal 73 at power up or at the
trailing edge of RESETB and configures the I2C bus address bit A0. The I2CA terminal has an internal pulldown
resistor to pull the terminal low to set a zero.
Table 7. I2C Host Interface Device Addresses
A6
1
A5
0
A4
1
A3
1
A2
1
A1
0
A0 (I2C A)
0 (default)
1(1)
R/W
1/0
HEX
B9h/B8h
BBh/BAh
1
0
1
1
1
0
1/0
(1) If terminal 73 is strapped to DVDD via a 2.2-kΩ resistor, I2C device address A0 is set to 1.
I2C Operation
Data transfers occur utilizing the following illustrated formats.
S
10111000
ACK
Subaddress
ACK
Send data
ACK
P
Read from I2C control registers
S
10111000
ACK
Subaddress
ACK
S
10111001
ACK
Receive data
NAK
P
S = I2C bus Start condition
P = I2C bus Stop condition
ACK = Acknowledge generated by the slave
NAK = Acknowledge generated by the master, for multiple byte read master with ACK each byte except last byte
Subaddress = Subaddress byte
Data = Data byte, if more than one byte of DATA is transmitted (read and write), the subaddress pointer is
automatically incremented
I2C bus address = Example shown that I2CA is in default mode; write (B8h), read (B9h).
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Power Up, Reset, and Initialization
No specific power-up sequence is required, but all power supplies should be active and stable within 500 ms of
each other. Reset may be low during power up, but must remain low for at least 1 µs after the power supplies
become stable. Alternatively, reset may be asserted any time with minimum 5-ms delay after power-up and must
remain asserted for at least 1 µs. Reset timing is shown in Figure 7. It is also recommended that any I2C
operation starts 1 µs after reset ended. Table 8 describes the status of the TVP7002 terminals during and
immediately after reset.
Table 8. Output Mode Per Reset Sequence State
OUTPUT MODE
SIGNAL NAME
DURING RESET
RESET COMPLETED
Default Condition
(see bit 0 of subaddress
17h)
ROUT[9:0], BOUT[9:0], GOUT[9:0]
HSOUT, VSOUT, FIDOUT, DATACLK
SOGOUT
High impedance
Default Condition
(see bit 0 of subaddress
17h)
High impedance
High impedance
Default Condition
(see bit 1 of subaddress
17h)
5 ms
1 µs
1 µs
Power
Reset
I2C
Figure 7. Reset Timing
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CONTROL REGISTERS
The TVP7002 is initialized and controlled by a set of internal registers that define the operating parameters of
the entire device. Communication between the external controller and the TVP7002 is through a standard I2C
host port interface, as previously described.
Table 9 shows the summary of these registers. Detailed programming information for each register is described
in the following sections.
Table 9. Control Registers Summary(1)(2)
REGISTER NAME
I2C SUBADDRESS
DEFAULT
02h
67h
20h
A8h
80h
32h
20h
20h
00h
00h
00h
80h
80h
80h
5Bh
2Eh
5Dh
20h
00h
00h
R/W(3)
R
Chip Revision
00h
H-PLL Feedback Divider MSBs
H-PLL Feedback Divider LSBs
H-PLL Control
01h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
02h
03h
H-PLL Phase Select
Clamp Start
04h
05h
Clamp Width
06h
HSYNC Output Width
Blue Fine Gain
07h
08h
Green Fine Gain
09h
Red Fine Gain
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
Blue Fine Offset MSBs
Green Fine Offset MSBs
Red Fine Offset MSBs
Sync Control 1
H-PLL and Clamp Control
Sync On Green Threshold
Sync Separator Threshold
H-PLL Pre-Coast
11h
12h
H-PLL Post-Coast
13h
Sync Detect Status
Output Formatter
14h
15h
04h
11h
03h
00h
00h
C2h
77h
07h
00h
10h
10h
10h
0Dh
08h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
MISC Control 1
16h
MISC Control 2
17h
MISC Control 3
18h
Input Mux Select 1
Input Mux Select 2
Blue and Green Coarse Gain
Red Coarse Gain
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
Fine Offset LSBs
Blue Coarse Offset
Green Coarse Offset
Red Coarse Offset
HSOUT Output Start
MISC Control 4
21h
22h
Blue Digital ALC Output LSBs
Green Digital ALC Output LSBs
23h
24h
R
(1) For proper operation of the TVP7002 device, the default settings for all register locations designated as "Reserved" in the register map
summary should never be changed from the values provided.
(2) For registers with reserved bits, a 0b must be written to reserved bit locations, unless otherwise stated.
(3) R = Read only, W = Write only, R/W = Read Write
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CONTROL REGISTERS (continued)
Table 9. Control Registers Summary (continued)
REGISTER NAME
I2C SUBADDRESS
DEFAULT
R/W(3)
R
Red Digital ALC Output LSBs
Automatic Level Control Enable
Digital ALC Output MSBs
Automatic Level Control Filter
Reserved
25h
26h
80h
R/W
R
27h
28h
53h
08h
07h
00h
50h
00h
80h
8Ch
04h
5Ah
18h
60h
03h
10h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
29h
Fine Clamp Control
Power Control
2Ah
2Bh
ADC Setup
2Ch
Coarse Clamp Control
SOG Clamp
2Dh
2Eh
RGB Coarse Clamp Control
SOG Coarse Clamp Control
ALC Placement
2Fh
30h
31h
Reserved
32h
Reserved
33h
Reserved
34h
VSYNC Alignment
Sync Bypass
35h
36h
Lines Per Frame Status
Clocks Per Line Status
HSYNC Width
37h–38h
39h–3Ah
3Bh
R
R
VSYNC Width
3Ch
R
Line Length Tolerance
Reserved
3Dh
03h
04h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
3Eh
Video Bandwidth Control
AVID Start Pixel
3Fh
00h
40h–41h
42h–43h
44h
012Ch
062Ch
05h
AVID Stop Pixel
VBLK Field 0 Start Line Offset
VBLK Field 1 Start Line Offset
VBLK Field 0 Duration
VBLK Field 1 Duration
F-bit Field 0 Start Line Offset
F-bit Field 1 Start Line Offset
1st CSC Coefficient
2nd CSC Coefficient
3rd CSC Coefficient
4th CSC Coefficient
5th CSC Coefficient
6th CSC Coefficient
7th CSC Coefficient
8th CSC Coefficient
9th CSC Coefficient
Reserved
45h
05h
46h
1Eh
47h
1Eh
48h
00h
49h
00h
4Ah–4Bh
4Ch–4Dh
4Eh–4Fh
50h–51h
52h–53h
54h–55h
56h–57h
58h–59h
5Ah–5Bh
5Ch–5Dh
5Eh–FFh
16E3h
024Fh
06CEh
F3ABh
1000h
FC55h
F178h
FE88h
1000h
0000h
0000h
Reserved
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Register Definitions
Chip Revision
Subaddress
00h
Read Only
7
6
5
5
4
3
3
2
2
1
1
0
Chip revision [7:0]
Chip revision [7:0]: Chip revision number
H-PLL Feedback Divider MSBs
Subaddress
01h
Default (67h)
0
7
6
4
PLL divide [11:4]
PLL divide [11:0]: Controls the 12-bit horizontal PLL feedback divider value which determines the number of pixels per line. PLL divide
[11:4] bits should be loaded first whenever a change is required.
H-PLL Feedback Divider LSBs
Subaddress
02h
Default (20h)
0
7
6
5
4
3
2
1
PLL divide [3:0]
Reserved
PLL divide [11:0]: Controls the 12-bit horizontal PLL feedback divider value which determines the number of pixels per line. PLL divide
[11:4] bits should be loaded first whenever a change is required.
H-PLL Control
Subaddress
03h
Default (A8h)
0
7
6
5
4
3
2
1
VCO[1:0]
Charge Pump Current [2:0]
Reserved
VCO [1:0]: Selects VCO frequency range
VCO Gain
VCO Range
Pixel Clock Frequency (PCLK)
(KVCO
)
00 =
01 =
10 =
11 =
75
85
150
200
Ultra low
Low
Medium (default)
High
PCLK < 36 MHz
36 MHz ≤ PCLK < 70 MHz
70 MHz ≤ PCLK < 135 MHz
135 MHz ≤ PCLK ≤ 165 MHz
Charge Pump Current [2:0]: Selects PLL charge pump current setting. The recommended charge pump current setting (ICP) can be
determined using the following equation.
ICP = 40 × KVCO/(pixels per line)
000 = 0: Small
101 = 5 (default)
111 = 7: Large
Note: Also see the "PLL and CLAMP Control" register at subaddress 0Fh.
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H-PLL Phase Select
Subaddress
04h
Default (80h)
7
6
5
4
3
2
1
0
Phase Select [4:0]
Reserved
DIV2
Phase Select [4:0]: ADC sampling clock phase select. (1 LSB = 360/32 = 11.25°). A host-based automatic phase control algorithm can be
used to control this setting to optimize graphics sampling phase.
00h = 0 degrees
10h = 180 degrees (default)
1Fh = 348.75 degrees
DIV2: DATACLK Divide-by-2. H-PLL post divider (internal use only)
0 = DATACLK/1 (default)
1 = DATACLK/2
Note: Phase wrap-around and phase instability can occur with phase settings of 00h or 01h. These settings are therfore not recommended
for use. Not all 32 phase settings are available when using the DATACLK/2 setting. This setting is therefore not recommended for PC
graphics inputs.
Clamp Start
Subaddress
05h
Default (32h)
0
7
6
5
4
3
2
1
Clamp Start [7:0]
Clamp Start [7:0]: Positions the clamp signal an integer number of clock periods after the HSYNC signal. If external clamping is selected
this value has no meaning. Clamp Start must be correctly positioned for proper operation. See Table 10 for the recommended settings.
Clamp Width
Subaddress
06h
Default (20h)
0
7
6
5
4
3
2
1
Clamp Width [7:0]
Clamp Width [7:0]: Sets the width in pixels for the fine clamp. See also register Clamp Start (subaddress 05h).
Table 10. Recommended Fine Clamp Settings
VIDEO STANDARD
HDTV (tri-level)
SDTV (bi-level)
PC Graphics
CLAMP START
50 (32h)
CLAMP WIDTH
32 (20h)
6 (06h)
16 (10h)
6 (06h)
16 (10h)
HSYNC Output Width
Subaddress
07h
Default (20h)
0
7
6
5
4
3
2
1
1
HSOUT Width [7:0]
HSOUT Width [7:0]: Sets the width in pixels for HSYNC output.
Blue Fine Gain
Subaddress
08h
Default (00h)
0
7
6
5
4
3
2
Blue Fine Gain [7:0]
Blue Fine Gain [7:0]: 8-bit fine digital gain (contrast) for Blue channel (applied after the ADC). Offset binary value.
Blue Fine Gain = 1 + Blue Fine Gain [7:0]/256
Blue Fine Gain [7:0]
Blue Fine Gain
00h
80h
FFh
1.0 (default)
1.5
2.0
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Green Fine Gain
Subaddress
09h
Default (00h)
0
7
6
5
4
3
2
1
Green Fine Gain [7:0]
Green Fine Gain [7:0]: 8-bit fine digital gain (contrast) for Green channel (applied after the ADC). Offset binary value.
Green Fine Gain = 1 + Green Fine Gain [7:0]/256
Green Fine Gain [7:0]
Green Fine Gain
00h
80h
FFh
1.0 (default)
1.5
2.0
Red Fine Gain
Subaddress
0Ah
Default (00h)
0
7
6
5
4
3
2
1
Red Fine Gain [7:0]
Red Fine Gain [7:0]: 8-bit fine digital gain (contrast) for Red channel (applied after the ADC). Offset binary value.
Red Fine Gain = 1 + Red Fine Gain [7:0]/256
Red Fine Gain [7:0]
Red Fine Gain
1.0 (default)
1.5
00h
80h
FFh
2.0
Blue Fine Offset MSBs
Subaddress
0Bh
Default (80h)
0
7
6
5
4
3
2
1
Blue Fine Offset [9:2]
Blue Fine Offset [9:2]: Eight MSBs of 10-bit fine digital offset (brightness) for Blue channel (applied after ADC). Corresponding two LSBs
located at register 1Dh. Offset binary value.
The default setting of 80h places the bottom-level (RGB) clamped output blank levels at 0 and mid-level clamped (PbPr) output blank levels
at 512.
FFh = Maximum fine offset
81h = 1 LSB
80h = 0 (default)
7Fh = –1 LSB
00h = Minimum fine offset
Green Fine Offset MSBs
Subaddress
0Ch
Default (80h)
0
7
6
5
4
3
2
1
Green Fine Offset [9:2]
Green Fine Offset [9:2]: Eight MSBs of 10-bit fine digital offset (brightness) for Green channel (applied after ADC). Corresponding two LSBs
located at register 1Dh. Offset binary value.
The default setting of 80h places the bottom-level (RGB) clamped output blank levels at 0 and mid-level clamped (PbPr) output blank levels
at 512.
FFh = Maximum fine offset
81h = 1 LSB
80h = 0 (default)
7Fh = –1 LSB
00h = Minimum fine offset
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Red Fine Offset MSBs
Subaddress
0Dh
Default (80h)
0
7
6
5
4
3
2
1
Red Fine Offset [9:2]
Red Fine Offset [9:2]: 8 MSBs of 10-bit fine digital offset (brightness) for Red channel (applied after ADC). Corresponding two LSBs located
at register 1Dh. Offset binary value.
The default setting of 80h places the bottom-level (RGB) clamped output blank levels at 0 and mid-level clamped (PbPr) output blank levels
at 512.
FFh = Maximum fine offset
81h = 1 LSB
80h = 0 (default)
7Fh = –1 LSB
00h = Minimum fine offset
Sync Control 1
Subaddress
0Eh
Default (5Bh)
7
6
5
4
3
2
1
0
HSPO
HSIP
HSOP
AHSO
AHSS
VSOP
AVSO
AVSS
HSPO: HSYNC polarity override
0 = Polarity determined by chip (default)
1 = Polarity set by bit 6 in register 0Eh (not recommended)
HSIP: HSYNC input polarity
0 = Indicates input HSYNC polarity active low
1 = Indicates input HSYNC polarity active high (default)
HSOP: HSYNC output polarity
0 = Active low HSYNC output (default)
1 = Active high HSYNC output
Note: HSOP has no effect in raw sync bypass mode. See register 36h.
AHSO: Active HSYNC override
0 = Active HSYNC is automatically selected by TVP7002. If selected SOG and HSYNC inputs both have active inputs,
HSYNC is selected as the active sync source. The selected active HSYNC is provided via the AHS status bit (bit 6 of
register 14h).
1 = Active HSYNC is manually selected via the AHSS control bit (bit 3 of register 0Eh). (default)
Note: Automatic sync selection should be enabled only for 5-wire PC graphics inputs.
AHSS: Active HSYNC select. The indicated HSYNC is used only if the AHSO control bit (bit 4) is set to 1 or if activity is detected on both
the selected HSYNC input and the selected SOG input (bits 1, 7 = 1 in register 14h).
0 = Active HSYNC is derived from the selected HSYNC input
1 = Active HSYNC is derived from the selected SOG input (default)
VSOP: VSYNC output polarity
0 = Active low VSYNC output (default)
1 = Active high VSYNC output
AVSO: Active VSYNC override
0 = Active VSYNC is automatically selected by TVP7002. If selected SOG and VSYNC inputs both have active inputs, VSYNC
is selected as the active sync source. The selected active VSYNC is provided via the AVS status bit (bit 3 of register 14h).
1 = Active VSYNC is manually selected via the AVSS control bit (bit 0 of register 0Eh). (default)
Note: Automatic sync selection should be enabled only for 5-wire PC graphics inputs.
AVSS: Active VSYNC select. This bit is effective when the AVSO control bit (bit 1) is set to 1.
0 = Active VSYNC is derived from the selected VSYNC input
1 = Active VSYNC is derived from the Sync separated VSYNC (default)
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H-PLL and Clamp Control
Subaddress
0Fh
Default (2Eh)
7
6
5
4
3
2
1
0
CF
CP
Coast Sel
CPO
CPC
SMO
FCPD
ADC Test
Clamp Function: Clamp pulse select. This control bit determines whether the timing for both the fine clamp and the ALC circuit are
generated internally or externally.
0 = Internal fine clamp and ALC timing (default)
1 = External fine clamp and ALC timing (pin 76)
Clamp Polarity: External clamp polarity select
0 = Active high clamp pulse (default)
1 = Active low clamp pulse
Coast Select: Coast signal select. This control bit determines whether the timing for H-PLL coast signal is generated internally or externally.
0 = External H-PLL coast timing (pin 77)
1 = Internal H-PLL coast timing (default)
Coast Polarity Override:
0 = Polarity determined by chip (default)
1 = Polarity set be Bit 3 in register 0Fh
Coast Polarity Change: External coast polarity select
0 = Active low coast signal
1 = Active high coast signal (default)
Seek Mode Override: Places the TVP7002 in a low power mode whenever no activity is detected on the selected sync inputs.
0 = Enable automatic power management mode
1 = Disable automatic power management mode (default)
Note: Digital outputs are not high impedance and may be in a random state during low power mode. Outputs can be put in
high impedance state by I2C register 17h.
Full Chip Power-Down: Active low power down. FCPD powers down all blocks except I2C. The I2C register values are retained.
0 = Power-down mode
1 = Normal operation (default)
Note: Digital outputs are not high impedance and may be in random state during FCPD. Outputs can be put in high
impedance state by I2C register 17h.
ADC Test: Active high ADC test mode select. When placed in the ADC test mode, the TVP7002 disables the fine clamp, enables the coarse
clamp, and selects the external clock input (pin 80) for each ADC channel.
0 = ADC test mode disabled (default)
1 = ADC test mode enabled
Note: Also see the Horizontal PLL Control register at subaddress 03h.
Sync-On-Green Threshold
Subaddress
10h
Default (5Dh)
7
6
5
4
3
2
1
0
SOG Threshold [4:0]
Blue CS
Green CS
Red CS
SOG Threshold [4:0]: Sets the voltage level of the SOG slicer comparator according to the following equation.
slice_level = (350 mV) × (NTH/31)
00h = 0 mV
0Bh = 124 mV (default)
1Fh = 350 mV
Blue Clamp Select: This bit has no effect when the Blue channel fine clamp is disabled (bit 2 of subaddress 2Ah).
0 = Bottom-level fine clamp
1 = Mid-level fine clamp (default)
Green Clamp Select: This bit has no effect when the Green channel fine clamp is disabled (bit 1 of subaddress 2Ah).
0 = Bottom-level fine clamp (default)
1 = Mid level fine clamp
Red Clamp Select: This bit has no effect when the Red channel fine clamp is disabled (bit 0 of subaddress 2Ah).
0 = Bottom-level fine clamp
1 = Mid-level fine clamp (default)
Note: Bottom-level clamping is required for Y and RGB inputs, while mid-level clamping is required for Pb and Pr inputs. The internal clamp
pulse must also be correctly positioned for proper clamp operation. See register 05h.
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Sync Separator Threshold
Subaddress
11h
Default (20h)
0
7
6
5
4
3
2
1
Sync Separator Threshold [7:0]
Sync Separator Threshold [7:0]: Sets how many internal clock reference periods the sync separator counts to before toggling high or low.
Sync Separator Threshold [7:0] × (minimum clock period) must be greater than the width of the negative sync pulse. This setting can also
affect the position of the VSOUT. See register 22h.
Note: The internal clock reference is typically 6.3 MHz, but a minimum clock period of 133 ns is recommended to allow for clock variation.
H-PLL Pre-Coast
Subaddress
12h
Default (00h)
0
7
6
5
4
3
2
1
1
Pre-Coast [7:0]
Pre-Coast [7:0]: Sets the number of HSYNC periods that coast becomes active prior to VSYNC leading edge.
H-PLL Post-Coast
Subaddress
13h
Default (00h)
0
7
6
5
4
3
2
Post-Coast [7:0]
Post-Coast [7:0]: Sets the number of HSYNC periods that coast stays active following VSYNC trailing edge. Post-Coast settings must be
extended to include Macrovision pseudo syncs when Macrovision is present.
Table 11. Recommended H-PLL Pre-Coast and H-PLL Post-Coast Settings
STANDARD
480i/p with Macrovision
H-PLL PRE_COAST
H-PLL POST-COAST
3
3
0
0
0
0Ch
0Ch
0
576i/p with Macrovision
1080i
1080p
720p
0
0
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Sync Detect Status
Subaddress
14h
Read Only
7
6
5
4
3
2
1
0
HSD
AHS
IHSPD
VSD
AVS
VSPD
SOGD
ICPD
HSYNC Detect: HSYNC activity detection for selected HSYNC input (pin 81 or 82).
0 = No HSYNC activity detected
1 = HSYNC activity detected
Active HSYNC: Indicates whether the active HSYNC is derived from the selected HSYNC input or the selected SOG input.
0 = HSYNC from selected HSYNC input (pin 81 or 82)
1 = HSYNC from selected SOG input (pin 1, 99, or 97)
Input HSYNC Polarity Detect: HSYNC polarity detection for selected HSYNC input (pin 81 or 82).
0 = Active low HSYNC
1 = Active high HSYNC
VSYNC Detect: VSYNC activity detection for selected VSYNC input (pin 78 or 79).
0 = No VSYNC activity detected
1 = VSYNC activity detected
Active VSYNC: Indicates whether the active VSYNC is derived from the selected VSYNC input or the sync separator.
0 = VSYNC from selected VSYNC input (pin 78 or 79)
1 = VSYNC from sync separator
Input VSYNC Polarity Detect: VSYNC polarity detection for selected VSYNC input (pin 78 or 79).
0 = Active low VSYNC
1 = Active high VSYNC
SOG Detect: SOG activity detection for selected SOG input (pin 1, 99, or 97).
0 = No SOG activity detected
1 = SOG activity detected
Input Coast Polarity Detect: Coast signal polarity detection.
0 = Active low coast signal
1 = Active high coast signal
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Output Formatter
Subaddress
15h
Default (04h)
7
6
5
4
3
2
1
0
Reserved
Output code range [1:0]
Reserved
Clamp REF
CbCr order
422/444
Sync En
Reserved [7]:
0 = Required (default)
Output code range [1:0]:
00 = RGB coding range (Y, Cb, and Cr range from 0 to 1023) (default)
01 = Extended coding range (Y, Cb, and Cr range from 4 to 1019.)
10 = ITU-R BT.601 coding range (Y ranges from 64 to 940, Cb and Cr range from 64 to 960)
11 = Reserved
Reserved [4]:
0 = Required (default)
Clamp REF: Selects which edge of HSYNC is used as the timing reference for the fine clamp pulse placement and also the ALC placement.
0 = Clamp pulse placement referred to the trailing edge of HSYNC (default)
1 = Clamp pulse placement referred to the leading edge of HSYNC
CbCr order: This bit is only effective in the 4:2:2 output mode (i.e., bit 1 is set to 1).
0 = CbCr order
1 = CrCb order (default)
422/444: Active high 4:4:4 to 4:2:2 decimation filter enable
0 = 30-bit 4:4:4 output format (default)
1 = 20-bit 4:2:2 output format
Notes:
1. Multiplexed CbCr data is output on BOUT [9:0] in the 20-bit 4:2:2 output format.
2. 10-bit 4:2:2 output format is not supported.
Sync En: Active high embedded sync enable
0 = Embedded sync disabled (default)
1 = Embedded sync enabled
Notes:
1. Embedded syncs are not supported when the RGB coding range (0 to 1023) is selected.
2. Embedded syncs are not supported when the 30-bit 4:4:4 output format is selected.
3. Discrete syncs are always enabled except when outputs are placed in the high-impedance mode.
4. When enabled, embedded syncs are present in both the Y and C outputs.
MISC Control 1
Subaddress
16h
Default (11h)
7
6
5
4
3
2
1
0
Reserved
CbCr Align: CbCr alignment
0 = Alternative operation
CbCr Align
Reserved
PLL PD
STRTB
1 = Normal operation (default)
PLL PD: Active high H-PLL power down
0 = Normal operation (default)
1 = H-PLL powered down
STRTB: Active high H-PLL start-up circuit enable
0 = H-PLL start-up circuit disabled
1 = H-PLL start-up circuit enabled (default)
33
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MISC Control 2
Subaddress
17h
Default (03h)
7
6
5
4
3
2
1
0
Reserved
Test output control [2:0]
Reserved
SOG En
Output En
Test output control [2:0]: Selects which signal is output on pin 22. Output polarity control is also provided using bit 2 of subaddress 18h.
000 = Field ID output (default)
001 = Data Enable output
010 = Reserved
011 = Reserved
100 = Internal clock reference output (~6.3 MHz typical)
101 = Coast output
110 = Clamp pulse output
111 = High-impedance mode
SOG En: Active low output enable for SOGOUT output.
0 = SOG output enabled
1 = SOG output placed in high-impedance mode (default)
Output En: Active low output enable for RGB, DATACLK, HSOUT, VSOUT, and FIDOUT outputs. This control bit allows selecting a
high-impedance output mode for multiplexing the output of the TVP7002 with another device.
0 = Outputs enabled
1 = Outputs placed in high-impedance mode (default)
Note: Data Enable output is equivalent to the internal active video signal that is controlled by the AVID start/stop pixel
values and the VBLK offset/duration line values.
MISC Control 3
Subaddress
18h
Default (00h)
7
6
5
4
3
2
1
0
Reserved
Reserved
Blank En
CSC En
Reserved
FID POL
SOG POL
CLK POL
Reserved [7]:
0 = Required (default)
Blank En: Active high blank level enable. Forces the video blank level to a standard value when using embedded syncs.
0 = Normal operation (default)
1 = Force standard blank levels
CSC En: Active high CSC enable. When disabled, the CSC block is bypassed.
0 = CSC disabled (default)
1 = CSC enabled
FID POL: Active high Field ID output polarity control. Under normal operation, the field ID output is set to logic 1 for an odd field (field 1) and
set to logic 0 for an even field (field 0).
0 = Normal operation (default)
1 = FID output polarity inverted
Note: This control bit also affects the polarity of the data enable output when selected (see Test output control [2:0] at
subaddress 17h).
SOG POL: Active high SOG output polarity control
0 = Normal operation (default)
1 = SOG output polarity inverted
CLK POL: Allows selecting the polarity of the output data clock.
0 = Data is clocked out on rising edge of DATACLK (default)
1 = Data is clocked out on falling edge of DATACLK
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Input Mux Select 1
Subaddress
19h
Default (00h)
0
7
6
5
4
3
2
1
SOG Select [1:0]
Red Select [1:0]
Green Select [1:0]
Blue Select [1:0]
SOG Select [1:0]: Selects one of three SOG inputs.
00 = SOGIN_1 input selected (default)
01 = SOGIN_2 input selected
10 = SOGIN_3 input selected
11 = Reserved
Red Select [1:0]: Selects one of three R/Pr inputs.
00 = RIN_1 input selected (default)
01 = RIN_2 input selected
10 = RIN_3 input selected
11 = Reserved
Green Select [1:0]: Selects one of four G/Y inputs.
00 = GIN_1 input selected (default)
01 = GIN_2 input selected
10 = GIN_3 input selected
11 = GIN_4 input selected
Blue Select [1:0]: Selects one of three B/Pb inputs.
00 = BIN_1 input selected (default)
01 = BIN_2 input selected
10 = BIN_3 input selected
11 = Reserved
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Input Mux Select 2
Subaddress
1Ah
Default (C2h)
7
6
5
4
3
2
1
0
SOG LPF SEL [1:0]
CLP LPF SEL [1:0]
CLK SEL
VS SEL
PCLK SEL
HS SEL
SOG LPF SEL [1:0]: SOG low-pass filter selection. The SOG low-pass filter is used to attenuate any glitches present on
the SOG input.
00 = 2.5-MHz low-pass filter
01 = 10-MHz low-pass filter
10 = 33-MHz low-pass filter
11 = Low-pass filter bypass (default)
CLP LPF SEL [1:0]: Coarse clamp low-pass filter selection. This filter effects the operation of all enabled coarse clamps which is generally
the SOG coarse clamp only.
00 = 4.8-MHz low-pass filter (default)
01 = 0.5-MHz low-pass filter
10 = 1.7-MHz low-pass filter
11 = Reserved
CLK SEL: Clock reference select for Sync Processing block. The internal reference clock is typically 6.3 MHz, but it should not be
considered a precise clock. An external 27-MHz reference clock is therefore recommended for accurate mode detection. Note: The I2C
interface, Sync Separator, and activity detection circuitry always uses the internal clock reference.
0 = Internal clock reference (default)
1 = External clock reference (EXT_CLK)
Note: The external clock input can also be selected as the sample clock for the ADCs (see bit 1).
VS SEL: VSYNC input select
0 = VSYNC_A input selected (default)
1 = VSYNC_B input selected
PCLK SEL: Pixel clock selection. When the external clock input (pin 80) is selected as the ADC sample clock, the external clamp pulse (pin
76) should also be selected (Bit 7 of subaddress 0Fh).
0 = ADC samples data using external clock input (pin 80)
1 = ADC samples data using H-PLL generated clock (default)
Note: The external clock input can also be selected as the reference clock for the Sync Processing block (see bit 3).
HS SEL: HSYNC input select
0 = HSYNC_A input selected (default)
1 = HSYNC_B input selected
Note: See the Sync Control register at subaddress 0Eh.
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Blue and Green Coarse Gain
Subaddress
1Bh
Default (77h)
0
7
6
5
4
3
2
1
Green Coarse Gain [3:0]
Blue Coarse Gain [3:0]
Green Coarse Gain [3:0]: 4-bit coarse analog gain for Green channel (applied before the ADC). To avoid clipping at the ADC, VP-P in X Gain
must be less than 1 VP-P
.
Gain [3:0]
0000 = 0.5
0001 = 0.6
0010 = 0.7
0011 = 0.8
0100 = 0.9
0101 = 1.0
0110 = 1.1
0111 = 1.2
1000 =1.3
1001 =1.4
1010 = 1.5
1011 =1.6
1100 = 1.7
1101 =1.8
1110 =1.9
1111 = 2.0
Description
Default
Maximum recommended gain for 700 mVP-P input
Blue Coarse Gain [3:0]: 4-bit coarse analog gain for Blue channel (applied before the ADC).
Red Coarse Gain
Subaddress
1Ch
Default (07h)
0
7
6
5
4
3
2
1
Reserved
Red Coarse Gain [3:0]
Red Coarse Gain [3:0]: 4-bit coarse analog gain for Red channel (applied before ADC).
Fine Offset LSBs
Subaddress
1Dh
Default (00h)
0
7
6
5
4
3
2
1
Reserved
Red Fine Offset [1:0]
Green Fine Offset [1:0]
Blue Fine Offset [1:0]
Red Fine Offset [1:0]: Two LSBs of 10-bit fine digital offset for Red channel (applied after ADC). Corresponding eight MSBs located at
register 0Dh. Offset binary value
Green Fine Offset [1:0]: Two LSBs of 10-bit fine digital offset for Green channel (applied after ADC). Corresponding eight MSBs located at
register 0Ch. Offset binary value.
Blue Fine Offset [1:0]: Two LSBs of 10-bit fine digital offset for Blue channel (applied after ADC). Corresponding eight MSBs located at
register 0Bh. Offset binary value.
Blue Coarse Offset
Subaddress
1Eh
Default (10h)
0
7
6
5
4
3
2
1
Reserved
Blue Coarse Offset [5:0]
Blue Coarse Offset [5:0]: 6-bit coarse analog offset for blue channel (applied before ADC). 6-bit sign magnitude value.
1Fh = +124 counts
10h = +64 counts referred to ADC output (default)
01h = +4 counts
00h = +0 counts
20h = –0 counts
21h = –4 counts
3Fh = –124 LSB
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Green Coarse Offset
Subaddress
1Fh
Default (10h)
0
7
6
5
4
3
2
1
Reserved
Green Coarse Offset [5:0]
Green Coarse Offset [5:0]: 6-bit coarse analog offset for Green channel (applied before ADC). 6-bit sign magnitude value.
Red Coarse Offset
Subaddress
20h
Default (10h)
0
7
6
5
4
3
2
1
Reserved
Red Coarse Offset [5:0]
Red Coarse Offset [5:0]: 6-bit coarse analog offset for Red channel (applied before ADC). 6-bit sign magnitude value.
HSOUT Output Start
Subaddress
21h
Default (0Dh)
0
7
6
5
4
3
2
1
HSOUT Start [7:0]
HSOUT Start [7:0]: Adjusts the leading edge of the HSYNC output relative to the leading edge of the HSYNC input in pixel or clock cycles.
MISC Control 4
Subaddress
22h
Default (08h)
7
6
5
4
3
2
1
0
SP Reset
Yadj_delay [2:0]
MAC_EN
Coast Dis
VS Select
VS Bypass
SP Reset: Active high reset for Sync Processing block. This bit may be used to manually reset the sync separator, sync accumulator,
activity and polarity detectors, and line and pixels counters.
0 = Normal operation (default)
1 = Sync processing reset
Yadj_delay [2:0]: Adjusts the phase delay of the luma output relative to the chroma output. Used to compensate for the chroma delay
associated with the 4:4:4 to 4:2:2 chroma sample conversion.
0h = Minimum delay (default)
7h = Maximum delay
MAC_EN: Toggling of the MAC_EN bit was required for TVP7000 and TVP7001 Macrovision support. This is no longer required with the
TVP7002.
0 = Macrovision stripper disabled (recommended)
1 = Macrovision stripper enabled (default)
Note: For correct ALC and fine clamp pulse placement, the MAC_EN bit must be set to 0 in the TVP7002.
Coast Dis: Active high internal coast signal disable for 5-wire PC graphics inputs. Has no effect when the external coast signal is selected.
See bit 5 of register 0Fh.
0 = Internal coast signal enabled (default)
1 = Internal coast signal disabled
VS Select: VSYNC select
0 = VSOUT is generated by the sync separator.
1 = VSOUT is generated by the half line accumulator (default).
VS Bypass: VSYNC timing bypass
0 = Normal operation (default). VS is derived from the sync separator or half line accumulator based on VS select, and the
internal pixel/line counters. Register 35h can be used to adjust VSOUT alignment relative to HSOUT.
1 = Bypass VSYNC processing. VSOUT is derived directly from the sync separator. VSOUT delay varies with sync separator
threshold (register 11h). Register 35h has no effect.
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Blue Digital ALC Output LSBs
Subaddress
23h
Read only
0
7
6
5
4
3
2
1
Blue ALC Out [7:0]
Blue ALC Out [7:0]: Eight LSBs of 10-bit filtered digital ALC output for Blue channel. The corresponding two MSBs are located at
subaddress 27h. With the internal ALC loop enabled, the ADC dynamic range can be maximized by adjusting the coarse offset settings
based on the ALC read back values. See registers 1Eh–20h for analog coarse offset control. Twos-complement value.
ALC Out[9:0] = ADC output – 512
For bottom-level clamped inputs (YRGB):
•
Target ADC output blank level = 16 to avoid bottom level clipping at ADC
ALC Out[9:0] = 16 – 512 = –496 = 210h
•
Starting from positive offset, decrement YRGB coarse offset until ALC Out [9:0] ≤ –496
For mid-level clamped inputs (PbPr):
•
Target ADC output blank level = 512
ALC Out[9:0] = 512 – 512 = 0
•
Starting from positive offset, decrement PbPr coarse offset until ALC Out [9:0] ≤ 0.
Green Digital ALC Output LSBs
Subaddress
24h
Read only
0
7
6
5
4
3
2
1
Green ALC Out [7:0]
Green ALC Out [7:0]: Eight LSBs of 10-bit filtered digital ALC output for Green channel. The corresponding two MSBs are located at
subaddress 27h. Twos-complement value. Also see register 23h.
Red Digital ALC Output LSBs
Subaddress
25h
Read only
0
7
6
5
4
3
2
1
Red ALC Out [7:0]
Red ALC Out [7:0]: Eight LSBs of 10-bit filtered digital ALC output for Red channel. The corresponding two MSBs are located at subaddress
27h. Twos-complement value. Also see register 23h.
Automatic Level Control Enable
Subaddress
26h
Default (80h)
0
7
6
5
4
3
2
1
ALC enable
Reserved
ALC enable: Active high automatic level control (ALC) enable
0 = ALC disabled
1 = ALC enabled (default)
See the ALC Placement register located at subaddress 31h.
Digital ALC Output MSBs
Subaddress
27h
Read only
0
7
6
5
4
3
2
1
Reserved
Red ALC Out [9:8]
Green ALC Out [9:8]
Blue ALC Out [9:8]
Red ALC Out [9:8]: Two MSBs of 10-bit filtered digital ALC output for Red channel. The corresponding eight LSBs are located at
subaddress 25h. Twos-complement value.
Green ALC Out [9:8]: Two MSBs of 10-bit filtered digital ALC output for Green channel. The corresponding eight LSBs are located at
subaddress 24h. Twos-complement value.
Blue ALC Out [9:8]: Two MSBs of 10-bit filtered digital ALC output for Blue channel. The corresponding eight LSBs are located at
subaddress 23h. Twos-complement value.
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Automatic Level Control Filter
Subaddress
28h
Default (53h)
0
7
6
5
4
3
2
1
Reserved
NSV [3:0]
NSH [2:0]
NSV [3:0]: ALC vertical filter coefficient. First-order recursive filter coefficient. ALC updates once per video line.
NSV [3:0]
0000 = 1
Description
Fastest setting. ALC converges in one iteration (i.e., one video line)
0001 = 1/2
0010 = 1/4
0011 = 1/8
0100 = 1/16
0101 = 1/32
0110 = 1/64
0111 = 1/128
1000 = 1/256
1001 = 1/512
1010 = 1/1024 (default)
1011 = 1/1024
1100 = 1/1024
1101 = 1/1024
1110 = 1/1024
1111 = 1/1024
Slowest setting. Provides the most filtering.
NSH [2:0]: ALC horizontal sample filter coefficient. Multi-tap running average filter coefficient.
NSH [2:0]
000 = 1/2
Description
2-tap running average filter
001 = 1/4
010 = 1/8
011 = 1/16 (default)
100 = 1/32
101 = 1/64
110 = 1/128
111 = 1/256
256-tap running average filter
Reserved
Subaddress
29h
Default (08h)
0
7
6
5
4
3
2
1
Reserved[7:0]
Reserved [7:0]:
08h = Required (default)
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Fine Clamp Control
Subaddress
2Ah
Default (07h)
7
6
5
4
3
2
1
0
CM Offset
Reserved
Fine swsel [1:0]
Reserved
Fine GB
Fine R
CM Offset: Fine bottom-level clamp common mode offset enable. The common mode offset is approximately 300 mV when enabled. Has no
effect when the coarse clamp or fine mid-level clamp is selected. See registers 10h and 2Dh.
0 = Common mode offset disabled (default)
1 = Common mode offset enabled
Note: The 300-mV common-mode offset can be enabled to improve isolation and channel crosstalk, when inputs with sync
tips larger than nominal (>300 mV) must be supported.
Reserved [6:5]:
0 = Normal operation (default)
Fine swsel: Fine clamp time constant adjustment
00 = Longest time constant (default)
11 = Shortest time constant
Reserved [2]:
1 = Normal operation (default)
Fine GB: Active high fine clamp enable for Green and Blue channel
0 = Green channel fine clamp disabled
1 = Green and Blue channel fine clamps enabled (default)
Fine R: Active high fine clamp enable for Red channel
0 = Red channel fine clamp disabled
1 = Red channel fine clamp enabled (default)
Note: Leave Fine GB and Fine R bits turned on for proper clamp operation. See register 10h for mid and bottom level clamping control.
Power Control
Subaddress
2Bh
(Default 00h)
7
6
5
4
3
2
1
0
Reserved
SOG
SLICER
REF
CURRENT
PW ADC B
PW ADC G
PW ADC R
SOG:
0 = Normal operation (default)
1 = SOG power-down
Slicer:
0 = Normal operation (default)
1 = Slicer power-down
Reference:
0 = Normal operation (default)
1 = Reference block power-down
Current control:
0 = Normal operation (default)
1 = Current control block power-down
PW ADC B: Active high power-down for ADC blue channel
0 = ADC blue channel power-down disabled (default)
1 = ADC blue channel power-down enabled
PW ADC G: Active high power-down for ADC green channel
0 = ADC green channel power-down disabled (default)
1 = ADC green channel power-down enabled
PW ADC R: Active high power-down for ADC red channel
0 = ADC red channel power-down disabled (default)
1 = ADC red channel power-down enabled
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ADC Setup
Subaddress
2Ch
(Default 50h)
0
7
6
5
4
3
2
1
ADC bias control [3:0]
Trim clamp [3:0]
ADC bias control [3:0]: Allows adjusting the internal ADC bias current for optimum performance.
0h = Minimum setting
5h = Recommended setting for sample rates ≤ 110 MSPS (default)
8h = Recommended setting for sample rates > 110 MSPS
Fh = Maximum setting
Trim clamp [3:0]: SOG coarse clamp bias current control.
0h = 2 µA (default)
3h = 8 µA
Fh = 32 µA
IBIAS = 2 + 2 × NBIAS, where 0 ≤ NBIAS ≤ 15
The SOG coarse clamp leakage current (subaddress 30h) is derived from the SOG coarse clamp bias current.
Coarse Clamp Control
Subaddress
2Dh
Default (00h)
7
6
5
4
3
2
1
0
CCCLP_cur_CH1 [1:0]
Reserved [5:3]
Coarse B
Coarse G
Coarse R
CCCLP_cur_CH1 [1:0]: Coarse clamp charge current switch selection.
00 = Highest charge current setting (default)
11 = Lowest charge current setting
Reserved [5:3]:
000 = Normal operation (default)
Coarse B: Active high coarse clamp enable for Blue channel
0 = Blue channel coarse clamp disabled (default)
1 = Blue channel coarse clamp enabled
Coarse G: Active high coarse clamp enable for Green channel
0 = Green channel coarse clamp disabled (default)
1 = Green channel coarse clamp enabled
Coarse R: Active high coarse clamp enable for Red channel
0 = Red channel coarse clamp disabled (default)
1 = Red channel coarse clamp enabled
Note: Enabling Coarse clamps will disable Fine clamps and override Fine clamp enable setttings in subaddress 2Ah.
SOG Clamp
Subaddress
2Eh
(Default 80h)
0
7
6
5
4
3
2
1
SOG_CE
CCCLP_cur_SOG [1:0]
upi_sog
dwni_sog
upi_ch123 [2:0]
SOG_CE: Active high SOG clamp enable.
0 = SOG clamp disabled
1 = SOG clamp enabled (default)
CCCLP_cur_SOG [1:0]: SOG coarse clamp charge current switch selection.
00 = Lowest charge current setting (default)
11 = Highest charge current setting
Reserved [4:0]:
0 = Normal operation (default)
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RGB Coarse Clamp Control
Subaddress
2Fh
(Default 8Ch)
0
7
6
5
4
3
2
1
Reserved
RGB leakage [5:0]
RGB leakage [5:0]: RGB channel coarse clamp leakage current switch. Increasing the coarse clamp leakage current increases horizontal
droop but improves hum rejection.
00h = 0.5 µA
0Ch = 6.5 µA when IBIAS = 2 µA (default)
3Fh = 32.0 µA when IBIAS = 2 µA
Droop_Current = 0.5 + (IBIAS/4) × NDC, where 0 ≤ NDC ≤ 63
SOG Coarse Clamp Control
Subaddress
30h
(Default 04h)
0
7
6
5
4
3
2
1
Reserved
SOG leakage [5:0]
SOG leakage [5:0]: SOG coarse clamp leakage current switch. The SOG coarse clamp leakage current is derived from the bias current.
Increasing the coarse clamp leakage current increases horizontal droop but improves hum rejection.
00h = 0.01 µA
04h = 0.21 µA when IBIAS = 2 µA (default)
3Fh = 3.16 µA when IBIAS = 2 µA
Droop_Current = (0.01 + (IBIAS/40) × NDC, where 0 ≤ NDC ≤ 63
Note: IBIAS is controlled using Trim clamp [3:0] at subaddress 2Ch.
ALC Placement
Subaddress
31h
(Default 5Ah)
0
7
6
5
4
3
2
1
ALC placement [7:0]
ALC placement [7:0]: Positions the ALC signal an integer number of clock periods after either the leading edge or the trailing edge (default)
of the HSYNC signal. Bit 3 of subaddress 15h allows selecting which edge of HSYNC is used as the timing reference for ALC placement.
The ALC must be applied after the end of the fine clamp interval.
0 = Minimum setting
18h = PC graphics and SDTV with bi-level syncs
5Ah = HDTV with tri-level syncs (default)
Reserved
Subaddress
32h
33h
34h
Default (18h)
0
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
Reserved[7:0]
Reserved[7:0]
Reserved[7:0]
Reserved
Subaddress
Default (60h)
0
7
Reserved
Subaddress
Default (03h)
0
7
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VSYNC Alignment
Subaddress
35h
Default (10h)
0
7
6
5
4
3
2
1
VS-HS Align [7:0]
VS-HS Align [7:0]: Specifies the number of pixels that the leading edge of the VSYNC output should be delayed or advanced relative to the
leading edge of the HSYNC output. The Field ID output is delayed by the same amount. Twos-complement number. This register has no
effect when either Sync bypass mode is enabled (see subaddresses 22h and 36h).
00h–7Fh = VSYNC leading edge delayed relative to the HSYNC leading edge
FFh–80h = VSYNC leading edge advanced relative to the HSYNC leading edge
Sync Bypass
Subaddress
36h
Default (00h)
7
6
5
4
3
2
1
0
Reserved
VS INV
HS INV
VS BP
HS BP
VS INV: VSYNC output polarity control. This bit only has an effect if the VSYNC bypass is asserted (bit 1 = 1).
0 = HSYNC output polarity matches input polarity (default)
1 = HSYNC output polarity inverted
HS INV: HSYNC output polarity control. This bit only has an effect if the HSYNC bypass is asserted (bit 0 = 1).
0 = HSYNC output polarity matches input polarity (default)
1 = HSYNC output polarity inverted
VS BP: VSYNC bypass. This bit enables bypassing the Sync processing block in order to output a raw unprocessed VSYNC.
0 = Normal operation (default)
1 = VSYNC bypass mode
HS BP: HSYNC bypass. This bit enables bypassing the Sync processing block in order to output a raw unprocessed HSYNC.
0 = Normal operation (default)
1 = HSYNC bypass mode
Note: See register 14h for input sync polarity detect.
Lines Per Frame Status
Subaddress
37h–38h
Read only
0
Subaddress
37h
7
6
5
4
3
2
1
Lines per Frame [7:0]
Reserved
38h
Reserved
mac detect
P/I detect
Lines per Frame [11:8]
mac detect: Macrovision pseudo-sync detection status
0 = Macrovision not detected
1 = Macrovision detected
P/I detect: Progressive/interlaced video detection status. Not dependent on the H-PLL being locked.
0 = Interlaced video detected
1 = Progressive video detected
Lines per Frame [11:0]: Number of lines per frame.
The lines per frame value may be used along with the clocks per line value (subaddresses 39h–3Ah) to determine the vertical frequency (fV)
of the video input.
fV = clock reference frequency / clocks per line / lines per frame
Note: The Lines per Frame counter is not dependent on the H-PLL being locked.
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Clocks Per Line Status
Subaddress
39h–3Ah
Read only
0
Subaddress
39h
7
6
5
4
3
2
1
Clocks per Line [7:0]
3Ah
Reserved
Clocks per Line [11:8]
Clocks per Line [11:0]: Number of clock cycles per line. The value written to this register represents the length of the longest line per frame.
A known timing reference based on either the internal clock reference (~6.3 MHz) or an external clock reference input (EXT_CLK) of up to
27 MHz may be selected using subaddress 1Ah.
The clocks per line value may be used to determine the horizontal frequency (fH) of the video input.
fH = clock reference frequency / clocks per line
Note: The Clocks per Line counter is not dependent on the H-PLL being locked.
HSYNC Width
Subaddress
3Bh
Read only
0
7
6
5
4
3
2
1
HSYNC width [7:0]
HSYNC width [7:0]: Number of clock cycles between the leading and trailing edges of the HSYNC input. A known timing reference based on
either the internal clock reference (~6.3 MHz) or an external clock reference input (EXT_CLK) of up to 27 MHz may be selected using
subaddress 1Ah.
Note: The HSYNC width counter is not dependent on the H-PLL being locked.
VSYNC Width
Subaddress
3Ch
Read only
0
7
6
5
4
3
2
1
Reserved
VSYNC width [4:0]
VSYNC width [4:0]: Number of lines between the leading and trailing edges of the VSYNC input. The VSYNC width along with the HSYNC
and VSYNC polarities can be used to determine whether the input graphics format is using VESA-CVT generated timings.
Note: The VSYNC width counter is not dependent on the H-PLL being locked.
Line Length Tolerance
Subaddress
3Dh
Default (03h)
0
7
6
5
4
3
2
1
Reserved
Line length tolerance [6:0]
Line length tolerance [6:0]: Controls sensitivity to HSYNC input stability when using either the internal or external clock reference. Increasing
the line length tolerance may be required for input signals having horizontal instability. Effects the clock cycles per line counter (see
subaddresses 39h–3Ah)
00h = No tolerance (minimum)
03h = 3 line length tolerance (default)
7Fh = 127 line length tolerance (maximum)
Reserved
Subaddress
3Eh
Default (04h)
0
7
6
5
4
3
2
1
Reserved [7:0]
Reserved [7:0]:
04h = Required setting (default)
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Video Bandwidth Control
Subaddress
3Fh
Default (00h)
0
7
6
5
4
3
2
1
Reserved
BW select [3:0]
BW select [3:0]: Selectable low-pass filter settings for controlling the analog video bandwidth. This control affects the analog video
bandwidth of all three ADC channels.
0h = Highest video bandwidth (default)
Fh = Lowest video bandwidth (~95 MHz analog video bandwidth )
Note: This register can be used to filter high frequency noise but lacks the precision for maximum filtering of various video formats. The
lowest bandwidth setting provides a video bandwidth of at least 50 MHz.
AVID Start Pixel
Subaddress
40h–41h
Default (012Ch)
0
Subaddress
40h
7
6
5
4
3
2
1
AVID start [7:0]
41h
Reserved
AVID active
AVID start [12:8]
AVID active
0 = AVID out active during VBLK (default)
1 = AVID out inactive during VBLK
AVID start [12:0]: AVID start pixel number, this is an absolute pixel location from the leading edge of HSYNC (start pixel 0). The TVP7002
updates the AVID start only when the AVID start MSB byte is written to.
AVID start pixel register also controls the position of SAV code. The TVP7002 inserts the SAV code four pixels before the pixel number
specified in the AVID start pixel register.
AVID Stop Pixel
Subaddress
42h–43h
Default (062Ch)
0
Subaddress
42h
7
6
5
4
3
2
1
AVID stop [7:0]
43h
Reserved
AVID stop [12:8]
AVID stop [12:0]: AVID stop pixel number. The number of pixels of active video must be an even number. This is an absolute pixel location
from the leading edge of HSYNC (start pixel 0).
The TVP7002 updates the AVID Stop only when the AVID Stop MSB byte is written to.
AVID stop pixel register also controls the position of EAV code.
VBLK Field 0 Start Line Offset
Subaddress
44h
Default (05h)
0
7
6
5
4
3
2
1
VBLK start 0 [7:0]
VBLK start 0 [7:0]: VBLK start line offset for field 0 relative to the leading edge of VSYNC. The VBLK start line offset value affects the
location of transitions on the embedded sync V-bit and VBLK of the Data Enable output, but not the VSYNC output (VSOUT). Unsigned
integer.
VBLK Field 1 Start Line Offset
Subaddress
45h
Default (05h)
0
7
6
5
4
3
2
1
VBLK start 1 [7:0]
VBLK start 1 [7:0]: VBLK start line offset for field 1 relative to the leading edge of VSYNC. The VBLK start line offset value affects the
location of transitions on the embedded sync V-bit and VBLK of the Data Enable output, but not the VSYNC output (VSOUT). Unsigned
integer.
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VBLK Field 0 Duration
Subaddress
46h
Default (1Eh)
0
7
6
5
4
3
2
2
2
1
1
1
VBLK duration 0 [7:0]
VBLK duration 0 [7:0]: VBLK duration in lines for field 0.
VBLK Field 1 Duration
Subaddress
47h
Default (1Eh)
0
7
6
5
4
3
VBLK duration 1 [7:0]
VBLK duration 1 [7:0]: VBLK duration in lines for field 1.
F-bit Field 0 Start Line Offset
Subaddress
48h
Default (00h)
0
7
6
5
4
3
F-bit start 0 [7:0]
F-bit start 0 [7:0]: F-bit Field 0 start line offset relative to the leading edge of VSYNC, signed integer, set F-bit to 0 until field 1 start line, it
only applies in interlaced mode. For a non-interlace mode, F-bit is always set to 0.
Note: The field ID output (FIDOUT) is always aligned with the leading edge of the VSYNC output (VSOUT).
F-bit Field 1 Start Line Offset
Subaddress
49h
Default (00h)
0
7
6
5
4
3
2
1
F-bit start 1 [7:0]
F-bit start 1 [7:0]: F-bit Field 1 start line offset relative to the leading edge of VSYNC, signed integer, set F-bit to 1 until field 0 start line, it
only applies in interlaced mode. For a non-interlace mode, F-Bit is always set to 0.
Note: The field ID output (FIDOUT) is always aligned with the leading edge of the VSYNC output (VSOUT).
1st CSC Coefficient
Subaddress
4Ah–4Bh
Default (16E3h)
0
Subaddress
4Ah
7
6
5
5
5
4
3
2
2
2
1
1
1
1st Coefficient [7:0]
1st Coefficient [15:8]
4Bh
1st Coefficient [15:0]: 16-bit G’ coefficient MSB for Y
2nd CSC Coefficient
Subaddress
4Ch–4Dh
Default (024Fh)
0
Subaddress
4Ch
7
6
4
3
2nd Coefficient [7:0]
2nd Coefficient [15:8]
4Dh
2nd Coefficient [15:0]: 16-bit B’ coefficient MSB for Y
3rd CSC Coefficient
Subaddress
4Eh–4Fh
Default (06CEh)
0
Subaddress
4Eh
7
6
4
3
3rd Coefficient [7:0]
3rd Coefficient [15:8]
4Fh
3rd Coefficient [15:0]: 16-bit R’ coefficient MSB for Y
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4th CSC Coefficient
Subaddress
50h–51h
Default (F3ABh)
0
Subaddress
50h
7
6
5
5
5
5
5
5
4
3
2
2
2
2
2
2
1
1
1
1
1
1
4th Coefficient [7:0]
4th Coefficient [15:8]
51h
4th Coefficient [15:0]: 16-bit G’ coefficient MSB for U
5th CSC Coefficient
Subaddress
52h–53h
Default (1000h)
0
Subaddress
52h
7
6
4
3
5th Coefficient [7:0]
5th Coefficient [15:8]
53h
5th Coefficient [15:0]: 16-bit B’ coefficient MSB for U
6th CSC Coefficient
Subaddress
54h–55h
Default (FC55h)
0
Subaddress
54h
7
6
4
3
6th Coefficient [7:0]
6th Coefficient [15:8]
55h
6th Coefficient [15:0]: 16-bit R’ coefficient MSB for U
7th CSC Coefficient
Subaddress
56h–57h
Default (F178h)
0
Subaddress
56h
7
6
4
3
7th Coefficient [7:0]
7th Coefficient [15:8]
57h
7th Coefficient [15:0]: 16-bit G’ coefficient MSB for V
8th CSC Coefficient
Subaddress
58h–59h
Default (FE88h)
0
Subaddress
58h
7
6
4
3
8th Coefficient [7:0]
8th Coefficient [15:8]
59h
8th Coefficient [15:0]: 16-bit B’ coefficient MSB for V
9th CSC Coefficient
Subaddress
5Ah–5Bh
Default (1000h)
0
Subaddress
5Ah
7
6
4
3
9th Coefficient [7:0]
9th Coefficient [15:8]
5Bh
9th Coefficient [15:0]: 16-bit R’ coefficient MSB for V
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APPLICATION INFORMATION
PLL Loop Filter
0.1 µF
4.7 nF
1 nF
1.5 kW
0.1 µF
0.1 µF
0.1 µF
G/Y
B/Pb
R/Pr
GIN
75 W
G[9:0]
B[9:0]
BIN1
RIN1
75 W
75 W
R[9:0]
DATACLK
TVP7002
FIDOUT
SOGOUT
VSOUT
HSYNC
VSYNC
HSYNC_A
VSYNC_A
RESETB
5 V/3.3 V
330 W
1 nF
HSOUT
3.3 V
2.2 kW × 2
2.2 kW × 3
Figure 8. TVP7002 Application Example
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PACKAGE OPTION ADDENDUM
www.ti.com
18-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TVP7002PZP
PREVIEW
PREVIEW
HTQFP
HTQFP
PZP
100
100
TBD
TBD
Call TI
Call TI
Call TI
Call TI
TVP7002PZPR
PZP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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