TWL6040 [TI]
8-CHANNEL HIGH_QUALITY LOW-POWER AUDIO CODEC FOR PORTABLE APPLICATIONS; 8通道HIGH_QUALITY低功耗音频编解码器,用于便携式应用型号: | TWL6040 |
厂家: | TEXAS INSTRUMENTS |
描述: | 8-CHANNEL HIGH_QUALITY LOW-POWER AUDIO CODEC FOR PORTABLE APPLICATIONS |
文件: | 总37页 (文件大小:532K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TWL6040
www.ti.com
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
8-CHANNEL HIGH_QUALITY LOW-POWER AUDIO CODEC
FOR PORTABLE APPLICATIONS
Check for Samples: TWL6040
1
FEATURES
–
12-/19.2-/26-/38.4-MHz system clock input
•
•
Accessory plug/unplug detection, accessory
button press detection
2
•
Four audio digital-to-analog (DAC) channels
Stereo capless headphone drivers:
•
Integrated power supplies:
–
–
Up to 104-dB DR
–
Negative charge pump for capless
headphone driver
Power tune for performance/power
consumption tradeoff
–
Two low dropout voltage regulators (LDOs)
for high power supply rejection ratio
(PSRR)
•
•
•
•
Stereo 8 Ω, 1.5 W per channel speaker drivers
Differential earpiece driver
Stereo line-out
•
•
I2C control
Two audio analog-to-digital (ADC) channels:
Thermal protection:
–
96-dBA SNR
–
Host interrupt
•
Four audio inputs:
•
Power supplies:
–
–
Three differential microphone inputs
Stereo line-in/FM input
–
–
–
Analog: 2.1 V
Digital I/O: 1.8 V
Battery 2.3 to 5.5 V
•
•
Two vibrator/haptics feedback channels:
Differential H-bridge drivers
–
•
Package 6-mm × 6-mm 120-pin PBGA
Two low-noise analog microphone bias
outputs
APPLICATIONS
•
•
Two digital microphone bias outputs
•
•
•
Mobile and smart phones
MP3 players
Analog low-power loop from line-in to
headphone/speaker outputs
Handheld devices
•
Dual phase-locked loops (PLLs) for flexible
clock support:
–
32-kHz sleep clock input for system
low-power playback mode
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
OMAP4 is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2011, Texas Instruments Incorporated
TWL6040
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
www.ti.com
DESCRIPTION
The TWL6040 device is an audio coder/decoder (codec) with a high level of integration providing analog audio
codec functions for portable applications, as shown in Figure 1. It contains multiple audio analog inputs and
outputs, as well as microphone biases and accessory detection. It is connected to the OMAP4™ host processor
through a proprietary PDM interface for audio data communication enabling partitioning with optimized power
consumption and performance. Multichannel audio data is multiplexed to a single wire for downlink (PDML) and
uplink (PDMUL).
The OMAP4 device provides the TWL6040 device with five PDM audio-input channels (DL0–DL4). Channels
DL0–DL3 are connected to four parallel DAC channels multiplexed to stereo headphone (HSL, HSR), stereo
speaker (HFL, HFR), and earpiece (EAR) or stereo line outputs (AUXL, AUXR).
The stereo headphone path has a low-power (LP) mode operating from a 32-kHz sleep clock to enable more
than 100 hours of MP3 playback time. Very-high dynamic range of 104 dBA is achieved when using the system
clock input and DAC path high-performance (HP) mode. Class-AB headphone drivers provide a 1-Vrms output
and are ground centered for capless connection to headphone, thus enabling system size and cost reduction.
The earpiece driver is a differential class-AB driver with 2 Vrms capability to a typical 32-Ω load or 1.4 Vrms to a
typical 16-Ω load.
Stereo speaker path has filterless class-D outputs with 1.5-W capability per channel. For output power
maximization supply connection to an external boost is supported. Speaker drivers also support also hearing aid
coil loads. For vibrator and haptic feedback support, the TWL6040 has two PWM channels with independent
input signals from DL4 or inter-integrated circuit (I2C™).
Vibrator drivers are differential H-bridge outputs, enabling fast acceleration and deceleration of vibrator motor. An
external driver for a hearing aid coil or a piezo speaker requiring high voltage can be connected to line outputs.
The TWL6040 supports three differential microphone inputs (MMIC, HMIC, SMIC) and a stereo line-input (AFML,
AFMR) multiplexed to two parallel ADCs. The PDM output from the ADCs is transmitted to the OMAP4 processor
through UL0 and UL1. AFML, AFMR inputs can also be looped to analog outputs (LB0, LB1).
Two LDOs provide a voltage of 2.1 V to bias analog microphones (MBIAS and HBIAS). The maximum output
current is 2 mA for each analog bias, allowing up to two microphones on one bias. Two LDOs provide a voltage
of 1.8 V/1.85 V to bias digital microphones (DBIAS1 and DBIAS2). One bias generator can bias up several digital
microphones at the same time, with a total maximum output current of 10 mA.
The TWL6040 has an integrated negative charge pump (NCP) and two LDOs (HS LDO and LS LDO) for high
PSRR. The only external supply needed is 2.1 V, which is available from the 2.1-V DC-DC of the TWL6030
power management IC (PMIC) in the OMAP4 system. By powering audio from low-noise 2.1-V DC-DC of low
power consumption, high dynamic range and high output swing at headset output are achieved. All other supply
inputs can be directly connected to battery or system 1.8-V I/O.
Two integrated PLLs enable operatation from a 12/19.2/26/38.4-MHz system clock (MCLK) or, in LP playback
mode, from a 32-kHz sleep clock (CLK32K). The frequency plan is based on a 48-kS/s audio data rate for all
channels, and host processor uses sample-rate converters to interface with different sample rates (for example,
44.1 kHz). In the specific case of low-power audio playback, the 44.1-kS/s and 48-kS/s rates are supported by
the TWL6040. Transitions between sample rates or input clocks are seamless.
Accessory plug and unplug detections are supported (PLUGDET). Some headsets have a manual switch for
submitting send/end signal to the terminal through the microphone input pin. This feature is supported by a
periodic accessory button press detection to minimize current consumption in sleep mode. Detection cycle
properties can be programmed according to system requirements.
Figure 1 shows a simplified block diagram of the device.
Table 1. ORDERING INFORMATION
PART NUMBER
PACKAGE
ORDERING
MEDIUM
TWL6040
6-mm × 6-mm PBGA
TWL6040A2ZQZ/R
Reel
2
Copyright © 2009–2011, Texas Instruments Incorporated
TWL6040
www.ti.com
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
MMICP
MicAmpL
VDDAMBIAS
HBIAS
AAFL
AAFR
MMICN
HMICP
HMICN
HMBIAS
MMBIAS
DMBIAS1
DMBIAS2
ADCL
1
GNDAMIC
0:30 dB
MBIAS
VDDUL
VSSUL
Uplink
VDDDMBIAS
MicAmpR
DBIAS1
SMICP
SMICN
ADCR
GNDDMIC
1
DBIAS2
0:30 dB
LineInAmpR
UL0
UL1
DL0
DL1
DL2
DL3
DL4
PDMDN
PDMUP
LB1
AFMR
LineInAmpL
PDM
interface
PDMCLK
PDMCLKLB
PDMFRAME
GPO1(2,3)
LB0
AFML
GNDVCM
–18:24 dB
EarDrv
VDDEAR
EARP
Interface
EARN
VSSEAR
–24:6 dB
HSLDrv
2
SDA
SCL
I C
registers
HSL
HSDACL
HSDACR
PBKG
1
VDDHS
VSSHS
GNDHS
–30:0 dB
HSRDrv
VDDV2V1
VDDLDO
HS LDO
LS LDO
HSR
VSSLDOIN
VSSLDO
VDDDL
VSSDL
AUXLP
AUXLN
AUXRP
AUXRN
1
–30:0 dB
GNDLDO
VDDREGNCP
CFLYP
Negative
charge
pump
GNDNCP
CFLYN
Downlink
NCPOUT
NCPFB
PGAL
VDDHFL
HFLP
HFLDrv
Power
HFLN
HFDACL
1
REF
REFP
GNDHFL
Reference
temp
sense
–52:6 dB
PGAR
REFN
VDDHFR
HFRP
HFRDrv
VIBLDrv
GNDREF
PLUGDET
ACCONN
HFRN
Accessory
connector
detection
HFDACR
1
GNDHFR
–52:6 dB
PCM
VDDVIO
PDM
to
PCM
VDDVIBL
VIBLP
VDDPLL
MCLK
1
8
1
to
PWM
VIBLN
8
HP PLL
LP PLL
1
8
GNDVIBL
CLK32K
VSSPLL
VDDVIBR
VIBRP
VIBRDrv
PCM
to
PWM
Clock system
8
8
1
1
VIBRN
8
Osc
GNDVIBR
SWCS044-001
Figure 1. Simplified Block Diagram
Copyright © 2009–2011, Texas Instruments Incorporated
3
TWL6040
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
www.ti.com
Table 2. Terminal Functions
NAME
BALL
TYPE
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
I/O(1)
DESCRIPTION
MCLK
K7
H7
D8
J9
I
I
System clock
CLK32K
AUDPWRON
NRESPWRON
NAUDINT
SDA
Real-time clock (RTC)
Power-up signal
I
I
Power-up reset
E8
H6
G6
K8
L10
H8
K9
L8
O
I/O
I
Interrupt
I2C serial interface data
I2C serial interface clock
PDM loopback clock
PDM reference clock
PDM frame
SCL
PDMCLKLB
PDMCLK
PDMFRAME
PDMDN
PDMUP
Uplink Channel
HBIAS
I
O
I/O
I
PDM downlink audio data
PDM uplink audio data
O
J3
K3
J5
Power
Power
Power
Power
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
O
O
O
O
I
Headset microphone bias supply
Main analog microphone bias supply
Digital microphone 1st bias supply
Digital microphone 2nd bias supply
Main microphone (+)
MBIAS
DBIAS1
DBIAS2
MMICP
MMICN
SMICP
L4
K1
J2
I
Main microphone (–)
J4
I
Submicrophone (+)
SMICN
H4
H1
H2
F1
F2
I
Submicrophone (–)
HMICP
I
Headset microphone (+)
HMICN
AFML
I
Headset microphone (–)
I
Auxiliary or FM radio left input
Auxiliary or FM radio right input
AFMR
I
Downlink Channel
EARP
B10
C11
J11
K11
G3
F3
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Earphone output (+)
EARN
Earphone output (–)
HSL
Headset left output
HSR
Headset right output
AUXLP
AUXLN
AUXRP
AUXRN
HFLP1
Auxiliary predriver left output (+)
Auxiliary predriver left output (–)
Auxiliary predriver right output (+)
Auxiliary predriver right output (–)
Hands-free left output (+)
Hands-free left output (+)
Hands-free left output (–)
Hands-free left output (–)
Hands-free right output (+)
Hands-free right output (+)
Hands-free right output (–)
Hands-free right output (–)
Vibrator left output (+)
G4
F4
A4
B4
A5
B5
B9
A9
B8
A8
C1
D3
A2
B1
HFLP2
HFLN1
HFLN2
HFRP1
HFRP2
HFRN1
HFRN2
VIBLP
VIBLN
Vibrator left output (–)
VIBRP
Vibrator right output (+)
Vibrator right output (–)
VIBRN
(1) I = Input; O = Output
4
Copyright © 2009–2011, Texas Instruments Incorporated
TWL6040
www.ti.com
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
Table 2. Terminal Functions (continued)
NAME
BALL
TYPE
I/O(1)
DESCRIPTION
Positive Supplies
VDDVREF
VDDLDO
H5
D1
B11
J10
G2
E9
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
I
O
I
Reference system supply
High-side LDO output
VDDEAR
Earphone positive supply
Headset positive supply
VDDHS
I
VDDUL
I
Uplink codec positive supply
Downlink codec positive supply
PLL positive supply
VDDDL
I
VDDPLL
J7
I
VDDHFL1
VDDHFL2
VDDHFR1
VDDHFR2
VDDVIBL
VDDVIBR
VDDAMBIAS
VDDDMBIAS
VDDREGNCP
A3
I
Hands-free left positive supply
Hands-free left positive supply
Hands-free right positive supply
Hands-free right positive supply
Vibrator positive supply
A6
I
A7
I
A10
C2
B2
I
I
I
Vibrator positive supply
L2
I
Analog microphone bias supply
Digital microphone bias supply
K4
I
H11
I
Negative charge pump positive
supply
VDDV2V1
VDDVIO
E2
L9
Power
Power
I
I
Preregulated main positive supply
Interface I/O supply
Negative Supplies
CFLYN
F11
G11
E10
E11
G9
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
O
O
O
O
I
Flying capacitor negative terminal
Flying capacitor positive terminal
Negative charge pump output
Negative charge pump output
Negative SMPS feedback
Low-side LDO input supply
Low-side LDO output
CFLYP
NCPOUT1
NCPOUT2
NCPFB
VSSLDOIN
VSSLDO
VSSEAR
VSSHS
D11
D10
C10
H10
G1
I
O
I
Earphone negative supply
Headset negative supply
Uplink negative supply
I
VSSUL
I
VSSDL
F9
I
Downlink negative supply
PLL negative supply
VSSPLL
L7
I
Ground
GN DREF
GNDHS
K5
H9
H3
L3
Ground
Ground
Ground
Ground
I
I
I
I
Bandgap reference ground
Headset sense input
GNDAMIC
GNDDMIC
Analog microphone ground
Digital microphone and accessory
ground
GNDLDO1
GNDLDO2
GNDVCM
GNDNCP1
GNDNCP2
GNDHFL1
GNDHFL2
GNDHFL3
GNDHFR1
E3
D9
J1
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
I
I
I
I
I
I
I
I
I
HS and LS LDO ground
HS and LS LDO ground
Codec ground
F10
G10
C5
C4
C6
C7
Negative charge pump ground
Negative charge pump ground
Hands-free left driver ground
Hands-free left driver ground
Hands-free left driver ground
Hands-free right driver ground
Copyright © 2009–2011, Texas Instruments Incorporated
5
TWL6040
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
www.ti.com
Table 2. Terminal Functions (continued)
NAME
BALL
C8
C9
J6
TYPE
I/O(1)
DESCRIPTION
GNDHFR2
GNDHFR3
GNDDIG
GNDVIBR
GNDVIBL
GNDIO
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
I
I
I
I
I
I
I
I
I
I
I
Hands-free right driver ground
Hands-free right driver ground
Digital ground
B3
Vibrator driver ground
D2
J8
Vibrator driver ground
General-purpose I/O ground
Substrate package ground
Substrate package ground
Substrate package ground
Substrate package ground
Substrate package ground
PBKG1
PBKG2
PBKG3
PBKG4
PBKG5
Miscallaneous
REF
F5
F6
F7
E4
K10
L5
K6
L6
Analog
Analog
Analog
Analog
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Analog
Analog
I/O
I/O
I/O
O
O
O
O
I
Bandgap reference
REFP
Positive converter reference
Negative converter reference
Analog test pin
REFN
ATEST
K2
D4
B6
B7
A1
L1
GPO1
General-purpose output 1
General-purpose output 2
General-purpose output 3
Digital test pin 1
GPO2
GPO3
DTEST1
DTEST2
DTEST3
PROG
I
Digital test pin 2
A11
L11
E1
G5
I
Digital test pin 3
I
EEPROM programming pin
Accessory connector pin
Accessory plug detection pin
ACCONN
PLUGDET
I/O
I
6
Copyright © 2009–2011, Texas Instruments Incorporated
TWL6040
www.ti.com
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
1
2
3
4
9
10
11
5
6
7
8
VIB
RP
VDD
HFL
VDD
HFL
VDD
HFR
VDD
HFR
A
B
C
DTEST1
HFLP
HFLN
HFRN HFRP
DTEST3
VIB
RN
GND
VIBR
VDD
EAR
VDD
HFLP
HFLN GPO2 GPO3
HFRN HFRP EARP
VIBR
GND
HFL
VDD
VIBL
GND
HFL
GND
HFR
GND
HFR
GND
HFR
VSS
EAR
VIB
LP
GND
HFL
EARN
GND
VIB
LN
AUDP
GND
VIBL
VDD
LDO
VSS
LDO
VSS
GPO1
PBKG
D
E
F
LDO2
WRON
LDOIN
VDD
DL
ACC
ONN
GND
NAUD
INT
NCP
OUT
NCP
OUT
VDD
LDO1
V2V1
AUX
LN
AUX
RN
VSS
DL
GND
NCP
AFML AFMR
PBKG PBKG PBKG
CFLYN
CFLYP
VSS
UL
VDD
UL
AUX
LP
AUX
RP
PLUG
NCP
FB
GND
NCP
G
SCL
DET
VDD
REG
NCP
GND
VDD
VREF
CLK
32K
PDM
GND
HS
VSS
HS
H
J
HMICP
SMICN
SDA
HMICN
AMIC
FRAME
NRES
PWR
ON
GND
VCM
GND
DIG
VDD
PLL
GND
IO
VDD
HS
MMICN HBIAS SMICP DBIAS1
HSL
HSR
VDD
GND
DM
PDM
PDM
DN
K
L
MMICP ATEST MBIAS
PBKG
REFP MCLK
REF
CLKLB
BIAS
VDDA
GND
VSS
PDM
UP
VDD
VIO
PDM
CLK
DTEST2
DBIAS2 REF
REFN
PROG
MBIAS DMIC
PLL
SWCS044-002
Figure 2. Pin Assignment (Top View)
Copyright © 2009–2011, Texas Instruments Incorporated
7
TWL6040
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted)
Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated below are not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC
–0.3
5.5
V
AC, 1000 spikes of
10 ms
Supply voltage
–0.3
6
V
duration over 7 years
Ambient operating temperature
Storage temperature
–30
–55
2
85
°C
°C
kV
V
150
Electrostatic discharge protection (HBM)
Electrostatic discharge protection (CDM)
500
THERMAL CHARACTERISTICS(1)
Over operating free-air temperature range (unless otherwise noted)
PACKAGE
POWER (W)
RΘJA (°C/W)
RΘJB (°C/W)
RΘJC (°C/W)
BOARD TYPE
PBGA, 6mm x 6mm
0.4
34
22
8
2S2P
(1) NOTE: The maximum power, 0.4 W, is at 85°C ambient temperature.
(a) RθJA (Theta-JA) = Thermal Resistance Junction-to-Ambient, °C/W
(b) RθJB (Theta-JB) = Thermal Resistance Junction-to-Board, °C/W
(c) RθJC (Theta-JC) = Thermal Resistance Junction-to-Case, °C/W
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
Supply voltage
VBAT
2.3
2.039
1.747
–30
3.7
2.127
1.823
5.5
2.205
1.89
125
V
V2V1
VIO
Operating junction temperature range
Operating ambient temperature range
°C
–30
85
CURRENT CONSUMPTION
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
Power-off mode: only battery supply present, other supplies pulled down. From VBAT
(2.3–5.5 V)
0.54
4.4
15.3
17.6
40.5
Deep-sleep mode: 1.8 V I/O present, other regulated supplies pulled down, plug
detection enabled, other modules disabled. From VBAT (3.8 V)
1.4
2.4
µA
Sleep mode: all supplies present. No accessory connected, plug detection enabled,
other modules disabled. From VBAT (3.6 V)
Sleep mode: all supplies present. Accessory connected, accessory unplug and button
press detections enabled, other modules disabled. From VBAT (3.6 V)
15.2
8
Copyright © 2009–2011, Texas Instruments Incorporated
TWL6040
www.ti.com
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
UPLINK MICROPHONE CHANNEL
Over operating free-air temperature range (unless otherwise noted)
UPLINK MICROPHONE CHANNEL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2
UNIT
Vpp
V/µs
dB
Single-ended or differential input swing 0 dBFs (THD > 40 dB)
Single-ended or differential input slew rate
Programmable preattenuation
1
–6
0
Programmable preamplifier gain
6
30
dB
Programmable preamplifier gain step size
6
dB
Absolute gain accuracy
Relative gain accuracy
Gain step size accuracy
Gain = Min
–0.5
–0.5
0.5
0.5
dB
Gain = Min to Max referenced to
gain = Min
dB
dB
Referenced to step = Typ
–0.25
0.25
f = 20–20 kHz,
Gain variation with frequency
Single-ended input resistance
relative to f = 1 kHz
without external capacitor
–0.5
0.5
dB
160
200
–42
–72
–67
–47
–27
10.9
2.5
13.6
6.7
4.1
3
240
–40
–70
–65
–45
–25
14.8
3.3
kΩ
0 dBFs
–10 dBFs
Total harmonic distortion in 20–20 kHz bandwidth
Gain = Min, f = 1 kHz
–20 dBFs
dB(A)
–40 dBFs
–60 dBFs
20 Hz to 8 kHz, gain = 6 dB
Input referred idle channel noise (including
microphone bias and typical microphone biasing 20 Hz to 8 kHz, gain = 24 dB
circuitry)
20 Hz to 20 kHz, gain = 6 dB
18.6
9.6
µVrms(A)
20 Hz to 20 kHz, gain = 12 dB
20 Hz to 20 kHz, gain = 18 dB
20 Hz to 20 kHz, gain = 24 or 30 dB
5.6
4
Signal-to-noise ratio
20 Hz to 8 kHz, gain = 6 dB
20 Hz to 8 kHz, gain = 24 dB
20 Hz to 20 kHz, gain = 6 dB
20 Hz to 20 kHz, gain = 24 or 30 dB
Gain = Min
92
86
90
84
98
92
dB(A)
96
90
Power supply rejection from VBAT
VBAT > 2.3 V, f < 1 kHz
VBAT > 2.3 V, f < 8 kHz
VBAT > 2.3 V, f < 20 kHz
VBAT > 2.5 V, f < 1 kHz
VBAT > 2.5 V, f < 8 kHz
VBAT > 2.5 V, f < 20 kHz
6-dB gain
74
56
48
80
62
54
15
30
dB(A)
Antialias attenuation at Fs
22
40
dB
dB
24-dB gain
Interchannel crosstalk and separation
Input at 1 kHz and –20 dBFs
Preamplifier Gain = 18 dB
Input at 1 kHz and 0 dBFs
20 Hz to 20 kHz
60
Input-to-output leakage
Common mode rejection
Delay
–80
–74
45
4
dB
dB
µs
60
MicAmp input to McPDM output
Mono
Total uplink current from VBAT = 3.6 V
(with analog microphone load)
3
4.6
7.8
mA
Stereo
5.9
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ANALOG MICROPHONE BIAS
Over operating free-air temperature range (unless otherwise noted)
ANALOG MICROPHONE BIAS
PARAMETER
TEST CONDITIONS
At the pad
MIN
TYP
3.6
0
MAX
UNIT
V
Positive supply voltage (VDDAMBIAS)
Negative supply voltage (GNDAMIC)
2.3
5
At the pad
V
Output voltage (VOUT
Output current (IL)
Integrated noise
)
Normal mode
2.06
2.06
0
2.1
2.1
0.6
2.14
2.2
2
V
Sleep mode
Normal mode
mA
mA
Sleep mode
0
0.2
f = 20 Hz to 8 kHz
1.65
3
2.3 µVrms (P)
f = 20 Hz to 8 kHz
4
5
µVrms (A)
µVrms (A)
f = 20 Hz to 20 kHz
3.5
Power supply rejection from VDDAMBIAS
IL = 0 to Max, Cf = Min to Max
VDDAMBIAS > 2.3 V, f < 1 kHz
VDDAMBIAS > 2.3 V, f < 8 kHz
VDDAMBIAS > 2.3 V, f < 20 kHz
VDDAMBIAS > 2.5 V, f < 1 kHz
VDDAMBIAS > 2.5 V, f < 8 kHz
VDDAMBIAS > 2.5 V, f < 20 kHz
80% IL Max in 1 µs
74
56
48
80
62
54
dB(A)
100
80
Load transient
30
200
10
mV
µs
Startup time
VOUT at 90%
Short-circuit current limit
Output impedance in power-down mode
Output shorted to ground
dc, with respect to GND
VOUT from 0 to 2.1 V
V2V1 enabled
3
3
6
mA
MΩ
Pulldown
DC, with respect to GND
Normal mode, IL = 0–Max
Sleep mode, IL = 0–Max/10
200
300
20
Ω
Quiescent current
200
10
µA
Parasitic board capacitor Cp
External filter resistor value Rf
External filter capacitor value Cf
External capacitor ESR
200
215
250
6
pF
Ω
185
0
200
220
Ceramic capacitor
f = 100 kHz
nF
Ω
Biasing resistance Rb
2.09
1
2.2
3
2.31
6
kΩ
kΩ
Microphone equivalent resistance Rm
10
Copyright © 2009–2011, Texas Instruments Incorporated
TWL6040
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SWCS044H –NOVEMBER 2009–REVISED JULY 2011
DIGITAL MICROPHONE BIAS
Over operating free-air temperature range (unless otherwise noted)
DIGITAL MICROPHONE BIAS
PARAMETER
TEST CONDITIONS
At the pad
MIN
TYP
3.6
0
MAX
UNIT
V
Positive supply voltage (VDDDMBIAS)
Negative supply voltage (GNDDMIC)
2.3
5
At the pad
V
Output dc voltage (VOUT
)
Normal mode, IL = 0 to Max
Sleep mode, IL = 0 to Max/10
1.75
1.8
0
1.8
1.85
1.85
1.9
10
V
Output current (IL)
mA
Power supply rejection from VDDDMBIAS
IL = 200 µA to Max, normal mode
VOUT = 1.8 V, f < 20 kHz
80% IL Max in 1 µs
dB(A)
40
1
Load transient
30
mV
MΩ
µs
Output impedance in power-down mode
Startup time
DC, with respect to GND
600
40
Short-circuit current limit
Quiescent current
Output shorted to ground
Normal mode
20
30
20
7
mA
30
µA
Sleep mode
10
External capacitor value
External capacitor ESR
0.9
2.2
3.3
0.6
0.02
µF
Ω
f < 100 kHz
1 MHz < f < 10 MHz
Ω
ANALOG LOOP, LINE-IN TO HEADPHONE OUTPUT
Over operating free-air temperature range (unless otherwise noted)
ANALOG LOOP, LINE-IN TO HEADPHONE OUTPUT
PARAMETER
TEST CONDITIONS
MIN
–18
40
TYP
MAX
UNIT
dB
Programmable gain range in line-in amplifier
Programmable gain in line-in amplifier
Programmable gain step size
Single-ended input resistance
Maximum input voltage (0 dBFs)
Total analog loop SNR output
42
24
dB
6
dB
50
60
2
kΩ
For single-ended input
Vpp
dB(A)
Gain = 0 dB, 0.5 Vrms signal
90
LineG = 6 dB, HSDrvG = 0 dB,
output = 1 Vrms
Total analog loop THDN at FS
–66
dB
Total stereo analog loop path quiescent current
85% DC 3.8-V Vbat
From VBAT = 3.8 V
2.5
3.5
mA
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DOWNLINK (DAC) CHANNEL TO HEADPHONE OUTPUT
Over operating free-air temperature range (unless otherwise noted)
DOWNLINK (DAC) CHANNEL TO HEADPHONE OUTPUT
PARAMETER
TEST CONDITIONS
MIN
16
1
TYP
MAX
UNIT
Speaker load resistance (RL)
32
Ω
Single-ended output swing 0 dBFs (THD > 40
dB, –4 dB analog gain in HP mode and –2-dB
gain in LP mode)
at the ball RL + Rf = 32 + 15 = 47 Ω
at the load RL + Rf = 32 + 15 = 47 Ω
Vrms
0.7
Programmable gain range
Programmable gain step size
Absolute gain accuracy
Relative gain accuracy
–30
0
dB
dB
dB
dB
dB
2
Gain = Max
–0.5
–0.5
0.5
0.5
Relative to gain = Max
Gain step size accuracy
–0.25
0.25
f = 20 Hz to 20 kHz, gain = Min to
Max
Gain variation with frequency
–1.1
–0.85
–0.6
dB
relative to 1 kHz at the ball
LP mode, at the ball
HP mode, at the ball
HP mode
Idle channel noise
10
6
14
9
µVrms(A)
Gain = Max
Dynamic range
104
dB(A)
–60-dBFs output with –4-dB analog gain
Dynamic range
LP mode
100
105
94
103
108
97
dB(A)
dB(A)
–60-dBFs output with –30-dB analog gain
Signal-to-noise ratio
HP mode
–1-dBFs output, LP mode
–1-dBFs output, HP mode
–10-dBFs output, LP mode
–10-dBFs output, HP mode
0 dBFs
98
101
89
86
90
93
.
–40
–70
–56
–36
–16
Total harmonic distortion in 20 Hz–20 kHz
bandwidth
–10 dBFs
(sine-wave @1 kHz, gain = Max)
–20 dBFs
dB(A)
–40 dBFs
–60 dBFs
RL = 32 Ω, Pload = 20 mW (–2.5
dBFS)
THD+N
0.012
100
0.1
%
Gain = Max, 217 Hz TDMA pulse
noise
Power supply rejection from VBAT
80
40
dB(A)
HS reference GNDHS noise rejection
f = 1 kHz, 10 mVrms amplitude
Group delay
Offset
7.1
16
2
µs
mV
dB
From stand-alone IC
After system compensation
at 0 dBFs, 1 kHz
at 0 dBFs, 1 kHz
at 0 dBFs, 1 kHz
Driver and pulldown disabled
LP mode
–16
–2
L/R gain mismatch
–0.5
–10
0.5
L/R phase mismatch
L/R cross-talk
10 degrees
–60
dB
Output impedance
1
MΩ
Average playback current from VBAT
5.3
7.4
7
mA
HP mode
9.23
12
Copyright © 2009–2011, Texas Instruments Incorporated
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SWCS044H –NOVEMBER 2009–REVISED JULY 2011
EARPHONE PATH SPECIFICATION
Over operating free-air temperature range (unless otherwise noted)
EARPHONE PATH SPECIFICATION
PARAMETER
TEST CONDITIONS
MIN
16
TYP
MAX
UNIT
Ω
Speaker load resistance (RL)
32
100
RL = Typ
RL = Min
2
Vrms
Vrms
dB
Output differential swing 0 dBFs (THD > 40 dB)
at 6-dB analog gain
1.42
–24
Programmable gain range
Programmable gain step size
Absolute gain accuracy
Relative gain accuracy
6
2
dB
Gain = Max
–0.5
–0.5
0.5
0.5
dB
dB
Gain step size accuracy
–0.25
0.25
dB
f = 20 Hz to 20 kHz, relative to 1
kHz
Gain variation with frequency
Idle channel noise
–0.8
–0.55
32
0.3
dB
f = 20 Hz to 20 kHz
45 µVrms(A)
dB(A)
Dynamic range, –60-dBFs output with –24-dB
analog gain
87
87
97
SNR, 0-dBFs output
f = 20 Hz to 20 kHz
0 dBFs
97
–60
dB(A)
Total harmonic distortion
(sine wave @1 kHz, gain = Max)
–40
–10 dBFs
–70
–60
–60
–40
–20
0.1
0.1
25
–20 dBFs
–70
dB(A)
–40 dBFs
–50
–60 dBFs
–30
THD+N
RL = TYP, 0 dBFS output
RL = TYP, –6 dBFS output
0.02
0.015
%
THD+N
Differential offset
–25
mV
dB(A)
µs
Power supply rejection from VBAT
Gain = Max
SINC filter
FIR filter
80
100
3.7
4.125
1
Group delay
µs
Average current from VBAT
4.8
mA
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AUX-OUTPUT PATH SPECIFICATION
Over operating free-air temperature range (unless otherwise noted)
AUX-OUTPUT PATH SPECIFICATION
PARAMETER
TEST CONDITIONS
MIN
10
TYP
MAX
UNITS
kΩ
Load resistance (RL)
150
Output differential swing 0 dBFs (THD > 40 dB)
Programmable gain range
Programmable gain step size
Absolute gain accuracy
RL = Typ
1.7
Vrms
dB
58
2
dB
Gain = 0 dB
–1.0
–0.25
–0.5
–0.5
–1.0
–0.5
1.0
0.25
0.5
dB
Gain step size accuracy
Gain = 6 to –40 dB
Gain = –40 to –50 dB
Gain = 6 to –40 dB
Gain = –40 to –50 dB
f= 20 Hz to 20 kHz relative to 1 kHz
Gain = 0 dB
dB
dB
Relative gain accuracy
0.5
dB
1.0
dB
Gain variation with frequency
0.5
dB
Dynamic range, –60-dBFs output with –24-dB
analog gain
87
80
90
90
dB(A)
dB(A)
SNR, 0-dBFs output
10-kΩ load, HFPGA = 0 dB, 1-kHz
signal
1-Vpp single-ended output
2-Vpp single-ended output
1-Vpp differential output
2-Vpp differential output
0.07
0.4
%
THD+N
0.07
0.4
Idle channel noise
40
50 µVrms(A)
14
Copyright © 2009–2011, Texas Instruments Incorporated
TWL6040
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SWCS044H –NOVEMBER 2009–REVISED JULY 2011
HANDS-FREE PATH SPECIFICATION
Over operating free-air temperature range (unless otherwise noted)
HANDS-FREE PATH SPECIFICATION
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5
UNIT
Input supply
Battery
2.3
V
SMPS boost
5.5
Maximum output power (PGA = 0 dB)
RL = 8 Ω
VDDHF = 5.5 V (THD > 40 dB)
VDDHF = 4.5 V (THD > 40 dB)
VDDHF = 3.6 V (THD > 40 dB)
VDDHF = 2.8 V (THD > 40 dB)
VDDHF = 2.3 V (THD > 30 dB)
1.3
0.9
1.5
1
W
0.55
0.24
0.15
–52
0.6
0.28
0.2
Programmable gain range (PGA)
Programmable gain step size (PGA)
Absolute gain accuracy
6
dB
dB
dB
2
Gain = 0 dB
–1
–0.5
–1
1
0.5
Relative gain accuracy
Gain = 6 to –40 dB
Gain = –40 to –50 dB
Gain = 6 to –40 dB
Gain = –40 to –50 dB
f = 20 kHz relative to 1 kHz
dB
dB
1
Gain step size accuracy
–0.25
–0.5
–1.25
0.25
0.5
Gain variation with frequency
–1
93
65
–0.75
dB
Dynamic range, –60-dBFs output with –24-dB
HFPGA gain
85
dB(A)
Idle channel noise
Gain = –24 dB
170 µVrms(A)
Total harmonic distortion in f = 20 Hz to 20 kHz
(sine wave @ 1 kHz, 0-dB PGA gain setting)
RL = 8 Ω, VDDHF > 3.6 V
25 mW < POUT < 0.5 W
1 mW < POUT < 25 mW
Gain = 0 dB
–55
–45
–50
–40
dB(A)
Power supply rejection from VBAT
dB(A)
Idle channel
55
70
65
80
Intermodulation
dBc
kHz
kHz
mA
19.6 MHz PDM clock
17.64 MHz PDM clock
Mono
384
353
2
Carrier frequencey
Average quiescent current from VBAT
3
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TWL6040
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
www.ti.com
VIBRA DRIVER PATHS
Over operating free-air temperature range (unless otherwise noted)
VIBRA DRIVER PATHS
PARAMETER
TEST CONDITIONS
Battery or SMPS boost
Left channel, RL = 16 Ω
VDDVIB = 4.8 V
MIN
TYP
MAX
UNIT
Input supply VDD
DC output voltage
2.3
5.5
V
3.3
2.6
1.6
3.6
2.9
1.7
V
V
VDDVIB = 3.8 V
VDDVIB = 2.5 V
Right channel, RL = 8 Ω
VDDVIB = 4.8 V
3.6
2.7
3.9
3
VDDVIB = 3.8 V
VDDVIB = 2.3 V
1.6
1.8
Absolute gain accuracy
Voltage step
–0.5
0.5
dB
mV
50
0
Gain variation with frequency
Total harmonic distortion in f = 20 Hz to 8 kHz
Latency
f = 250 Hz to 8 kHz relative to 1 kHz
RL = 8 Ω, VDD > 3.6 V, –1 dBVrms
PDM input
–0.5
0.5
–30
dB
–35
dB(A)
20.8
10.4
µs
PCM input
Load resistance RL
8
16
1
Ω
Average quiescent current from VBAT
Mono
1.5
mA
INPUT CLOCK PARAMETERS
Over operating free-air temperature range (unless otherwise noted)
SYSTEM CLOCK
PARAMETER
TEST CONDITIONS
MIN
–100
1.65
TYP
MAX
100
UNIT
ppm
V
Input frequency accuracy
Square wave
1.89
Input swing
Sine wave, input common mode 0.5
to 0.7 V
0.4
1
Vpp
12 MHz
–89
–86
–83
–80
–86
–83
–80
–77
19.2 MHz
26 MHz
Input SSB phase noise @ 1 kHz
dBc/Hz
38.4 MHz
SLEEP CLOCK
Over operating free-air temperature range (unless otherwise noted)
SLEEP CLOCK
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Hz
Input frequency
32,768
Input frequency accuracy
Input duty cycle
–1000
1000
60
ppm
%
40
@ 100Hz
–108
–128
0.61
0.31
–105
–125
0.86
0.43
Input SSB phase noise
Input integrated jitter
dBc/Hz
nsrms
@ 1 kHz
20 Hz to 20 kHz flat
80 Hz to 20 kHz flat
16
Copyright © 2009–2011, Texas Instruments Incorporated
TWL6040
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SWCS044H –NOVEMBER 2009–REVISED JULY 2011
APPLICATION INFORMATION
UPLINK PATH DESCRIPTION
The voice uplink path includes two low-noise input amplifier stages (MicAmpL and MicAmpR) and two ADCs
dedicated to the three microphone inputs and stereo auxiliary/FM inputs. Two low-power input amplifiers
(LineInAmpL and LineInAmpR) enable stereo analog loops (LB0, LB1) to the downlink section, independent and
concurrent with stereo microphone uplink to OMAP4. The auxiliary/FM radio left and right channels can be
connected to the microphone preamplifiers for recording, or to a line-in amplifier for direct analog loop to
downlink drivers, or simultaneously to both.
Analog microphone bias outputs, MBIAS and HBIAS, have a dedicated supply pin (VDDABIAS), which can be
connected to the battery or to an external boost. If full PSR performance is required in a system with minimum
battery level below 2.5 V, the latter connection is recommended.
Microphone bias blocks can be set to sleep mode for low quiescent current consumption. In sleep mode, only the
output voltage specification is ensured with the specified sleep mode load current.
Mapping of analog inputs to uplink data channels UL0 and UL1 connected to the OMAP4 is indicated in the
following table:
UL0
UL1
LB0
LB1
Main microphone, MMIC
SubMicrophone, SMIC
Headset microphone, HSMIC
Left auxiliary/FM radio
X
X
X
X
X
X
Right auxiliary/FM radio
X
X
For microphone bias connection, if the negative terminal of the microphone is available, which is usually the case
for device internal microphones, the board schematic for a fully differential input shown in Figure 3 is proposed.
This approach minimizes differential coupling but provides almost no rejection from bias noise voltage (MBIAS).
200 W
MBIAS
220 nF
1 kW
100 nF
50 W
MMICP
SMICP
1 nF
50 W
MMICN
SMICN
100 nF
1 kW
1 nF
GNDAMIC
Reference
point
SWCS044-004
Figure 3. Board With Available Negative Terminal
If the negative terminal of the microphone is not available (that is, it is directly connected to ground), which is
usually the case for accessory microphones, the board schematic for a pseudodifferential input shown in Figure 4
is suggested. This approach can suffer from differential coupling, but provides good rejection from bias noise
voltage (HBIAS).
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www.ti.com
200 W
HBIAS
HMICP
100 nF
220 nF
2.2 kW
50 W
HMICN
100 nF
1 nF
GNDAMIC
Reference
point
SWCS044-005
Figure 4. Board With Unavailable Negative Terminal
In all board layouts, the star connection of all the ground lines to a single via to the ground plane (reference
point) is highly recommended to minimize degradation from unequal potential grounds.
The schematics and component values in Figure 3 and Figure 4 are general proposals and may not be the
optimal choice for specific user applications.
Two LDOs provide an external voltage of 1.8/1.85 V to bias digital microphones (DBIAS1 and DBIAS2). One bias
generator can bias several digital microphones at the same time, with a total maximum output current of 10 mA.
Digital microphone inputs and clocks are supported by OMAP.
DOWNLINK PATH DESCRIPTION
Mapping of audio data inputs from the OMAP4 to audio driver outputs is shown in the following table.
DL0
X(2)
X
DL1
DL2
DL3
DL4
I2C or Frame(1)
LB0
X
LB1
Earphone
Left headset
Right headset
Left hands-free
Right hands-free
Left auxiliary
Right auxiliary
Right vibrator
Left vibrator
X
X
X
X
X
X
X
X
X
X(3)
X(3)
X
X(3)
X
X
X
X
(1) The frame line can be used for register write (for example, vibrator data registers) in command mode.
(2) This path cannot be concurrent with L/R headset paths.
(3) These paths can be concurrent, but not independent of L/R hands-free paths.
Headphone/Headset Paths
For music playback, the analog headset path can be configured in two different modes:
•
•
Low-power mode (LP)
High-performance mode (HP)
The LP mode system is designed to maximize playback time while maintaining better audio performance than
provided by current compression algorithms. The only input clock required in this mode is the RTC at 32,768 Hz.
The HP mode improves the dynamic range (DR) performance by 5 dB with tradeoff of increased current
consumption compared to LP mode. A high-quality clock (that is, generated by VTCXO) is required in this mode.
The headset path modules (DAC and HS driver) can be individually set in LP and HP modes.
18
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SWCS044H –NOVEMBER 2009–REVISED JULY 2011
The DAC is followed by a class AB single-ended HS driver, to provide a signal up to 1 Vrms at the ball.
Programmable analog attenuation is available in the HS driver. The overall gain of the system is segmented
between this analog gain and the digital gain of the application processor, with a minimum step of 0.1 dB. The
HS path can drive headphone or line-out loads. Optional EMC or ESD protection circuitry can be inserted
between the stereo HS driver and the load connector, without performance degradation at the ball. A single
ground feedback is brought star connected from the connector ground to the stereo HS driver feedback.
Hands-Free/Speaker Paths
Hands-free/speaker drivers can be connected to a battery or to an external boost. To reach 1-W output power
from a mono speaker, a boosted supply equal to or greater than 4.5 V is recommended.
The board can be designed without an output filter if the traces from the TWL6040 to hands-free (HF) speakers
are short. A ferrite bead filter can be used if the board design is failing radiated emission. In both cases, the
audio performance is maintained.
There is a short-circuit protection for HF amplifiers to limit power dissipation. A short circuit can exist between
output terminals, output and ground, or output and battery.
Short circuit detection in at least one of the two drivers automatically disables both HF drivers and generates an
interrupt.
Vibra Paths
Two high-efficiency differential drivers, capable of driving rotational, linear multifunction vibrator devices, are
provided. Each vibrator can be independently supplied by an external power source. The left vibrator driver
RDSON is optimized for a 16-Ω equivalent load, whereas the right vibrator driver RDSON is optimized for an 8-Ω
equivalent load (higher current). Loads with higher equivalent resistance value than stated above are also
supported.
Each of the vibrators can be driven through PDM or PCM data. The PDM data comes from the 5th downlink
channel. The PCM data can be sent through the PDM interface command mode at a maximum rate of 48 kS/s,
or through the I2C interface for near DC signal. Better than 8-bit resolution on lower bandwidth can be achieved
through the PCM signal by averaging the data.
There is no analog or digital gain in the TWL6040 vibrator paths; that is, the signal amplitude is entirely set in the
digital companion IC.
Similar to the hands-free drivers, there is a short-circuit protection for vibrator drivers to limit power dissipation if
the current exceeds 500 mA in any of the output transistors. Short-circuit detection in at least one of the two
drivers automatically disables both vibrator drivers and generates an interrupt.
External Boost
An external boost can be used to supply the following functions:
•
•
•
Hands-free stereo drivers
Left and right vibrator drivers
Main and headset microphone biasing LDOs
Any of the corresponding modules in the TWL6040 device can be independently powered by the battery or by
the output of this external boost.
The external boost should provide a minimum output voltage of 4.5 V to allow each HF driver to deliver a typical
2-W peak power into an 8-Ω load. Larger output voltage values enable more output power in the HF loads, but it
must not exceed 5.5 V dc for reliability reasons.
By default, the two HF drivers work in phase quadrature (90-degree phase shift) to reduce the rms load current.
Figure 5 shows the stereo HF load current waveforms for worst-case (close to 100% modulation or 4-W stereo
output power) and typical (less than 50% modulation or 1-W stereo output). Figure 5 also indicates the driver
sinking the current (left or right).
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I(A)
1.0
A)
0.5
L/R
L/R
L/R
L/R
L/R
2.6 ms
0.0
T(s)
I(A)
2.6 ms
0.2
0.0
B)
L
R
L
R
L
R
T(s)
SWCS044-006
Figure 5. Current Load Waveforms, Worst-Case A) and Typical B)
The following table shows the external boost SMPS recommendations.
Parameter
Test Conditions
Min
Typ
Max
5.0
Units
V
Input voltage
at the ball
2.3
Output voltage
Output current
Output peak power
4.5
5
V
0.003
1.25
4.5
A
Stereo HF
W
W
W
W
%
Strereo HF + mono Vibra
Stereo HF
5.625
0.31
0.4
Output average power(1)
Strereo HF + mono Vibra
IL=3 mA to 1.3 A
Efficiency
80
20
90
30
Start-up time
4
ms
dB
A
Power supply rejection from VBAT
Output current limit for short-circuit detection
f = 217 Hz
1.6
(1) The Max/Typ ratio is based on 12-dB crest factor audio signal.
20
Copyright © 2009–2011, Texas Instruments Incorporated
TWL6040
www.ti.com
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
ACCESSORY DETECTIONS
The standard connector is shown in Figure 6, and has the following terminals:
1. Left headset speaker input
2. Right headset speaker input
3. Microphone input
4. Ground return for speakers and microphone
5. Open/ground switch input
4
2
1
3
5
SWCS044-007
Figure 6. Standard Connector
The TWL6040 is compatible with a system supporting the standard 2.5-mm and 3.5-mm audio-jack connector
shown in Figure 7:
Jack
No Mic
With Mic
L
R
G
L R M G
Stereo
SWCS044-008
Figure 7. Standard 2.5-mm and 3.5-mm Audio-Jack
With proper board wiring TWL6040 is compatible also with L-R-G-M -jack.
The TWL6040 is not compatible with the 2.5-mm and 3.5-mm audio-jack connectors shown in Figure 8. If this
type of connector is inserted, the system performances and/or functionality are not assured, but the TWL6040 is
not damaged.
¼-Inch Jack
Mono
No Mic
G
With Mic
L
L M
G
SWCS044-009
Figure 8. Incompatible 2.5-mm and 3.5-mm Connectors
Plug Detection
The TWL6040 supports plug detection through a mechanical switch closing to ground when a connector is
inserted. The plug detection is implemented as a simple comparator with a pullup resistance. The comparator
output is debounced to avoid false detection due to perturbation, such as ESD events. When a plug or unplug
event is detected, interrupt signal PLUGINT is generated. The maximum value of the plug resistance Rp is 10 Ω.
Figure 9 shows the plug-detection circuit.
Copyright © 2009–2011, Texas Instruments Incorporated
21
TWL6040
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
www.ti.com
VDDVIO
5
Ru
Rp
PLUGDET
SWCS044-010
Figure 9. Plug Detection Circuit
Send/End Button Detection
Some headsets have a manual switch for submitting send/end signals to the terminal through the microphone
input pin. The two possible configurations are:
•
•
The button switch is parallel to the microphone (most common).
The button switch is in series with the microphone.
The two configurations are shown in Figure 10.
Case
Case
Rm
Rs
Rs
Rm
Button
Button
1-parallel configuration
2-serial configuration
SWCS044-011
Figure 10. Manual Switch Configuration
In both configurations, the detection is based on an impedance detection involving the microphone. The
detection is assured for a maximum Rs of 100 Ω and a microphone having a current-to-voltage transfer function
within the mask described in Figure 11.
I
600 mA
100 mA
0.6 V
V
SWCS044-012
Figure 11. Microphone Current-to-Voltage Transfer Function
22
Copyright © 2009–2011, Texas Instruments Incorporated
TWL6040
www.ti.com
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
Two detection mechanisms are implemented on the TWL6040 to address the parallel and serial hook
configurations. By default, these detections are concurrent, but they can be independently disabled by the
HKPARADIS bit in register HKCTL1 and the HKSERDIS bit defined in register HKCTL2.
In the parallel configuration for send-event detection, the VDDV2V1 supply pulls up the bias resistance Rb to 2.1
V, while the microphone bias amplifier is in high-impedance output mode. It also provides a threshold Vth1 for the
hook comparator COMP1 through a resistor divider. This comparator is used to detect the short of the
microphone bias. The detection analog block diagram is described in Figure 12, and the entire system is
powered from the VDDV2V1 supply. During settling and comparison, switch Ri is closed and as much as 600 µA
can flow from VDDV2V1 to the microphone, and up to 1.1 mA if the button is pressed.
The same mechanism is used for end-event detection, except that the LDO HBIAS is already biasing the
microphone, and VDDV2V1 is used only as a supply for the comparator.
VDDV2V1
Cf
HBIAS
Rf
Ri
HKUPEN
HBIAS
HMICP
HKSEREN
Vth2
–
EN
Rb
+
COMPOUT
HKPARAEN
3
HKCOMP2
HKCOMP1
HMICN
Vth1
+
EN
–
ACCONN
GNDAMIC
SWCS044-013
Figure 12. Parallel/Serial Configuration Detection
The detection is performed with a duty cycle compatible with system quiescent-current requirements and timing
of the mechanical short. The sequence is programmed by setting three parameters based on the RTC clock:
•
•
•
Interval period between detection trials
Settling time (dependent on external RC filter)
Debounce time for comparison
The minimum recommended duration consists of eight clock cycles for settling and eight clock cycles to
debounce the output of the comparator. With one detection every 100 ms, this on-duration allows a duty cycle
smaller than 1/500 and a minimum sleep current. Figure 13 shows the timing diagram.
Copyright © 2009–2011, Texas Instruments Incorporated
23
TWL6040
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
www.ti.com
HKRATE
periods
HKSET
periods
HKDBNC
periods
HKSET
periods
HKDBNC
periods
CLK
HKEN
ACONN
COMPOUT
COMPINT
1
1
1
0
1 1 1 1 1
1 1 1
1
HOOKINT
SWCS044-016
Figure 13. Detection Timing
In end event mode detection, when the HMBIAS module is enabled, the duty cycle is disabled and the analog
module detection is always on to avoid transient perturbations coupling to the uplink channel. The duty cycle in
this mode can be restored by setting HKSWEN high.
The same detection scheme can be used for serial configuration. The comparator HKCOMP2 can work
synchronously with HKCOMP1 and their output can be combined before the debounce function.
When a send event is detected, an interrupt signal is generated and the switch between VDDV2V1 and
PAD_MBIAS is disabled. For end event detection, an interrupt signal is generated.
CLOCK SYSTEM
The frequency plan is based on a 48 kS/s audio data rate for all channels. The data converters use a fixed
oversampling ratio (OSR) equal to 80 (3.84 MHz). The audio data PDM interface runs at five times the OSR rate,
using a clock equal to 19.2 MHz. The application companion uses sample rate converters to interface with other
sample rates (for example, 44.1 kHz).
In the specific case of low-power audio playback (LP mode), where only the headphone path is active, the
TWL6040 supports the 44.1 kS/s and 48 kS/s rates. The ratio between audio sample rate, data converter clock,
and PDM clock remains the same.
The high-quality input clock MCLK from the system can have the following values: 12, 19.2, 26, or 38.4 MHz.
The input waveform can be a sine wave or a square wave. If the clock frequency is equal to 19.2 or 38.4 MHz,
the clock can be directly divided and level-shifted. If MCLK is 12 MHz or 26 MHz, the high frequency input PLL
(HF PLL) generates a 19.2 MHz signal from the MCLK, compatible with the requirement for HS quality in high
performance (HP) mode. A clock slicer is inserted between the MCLK input pad and the HF PLL.
The low frequency input PLL (LF PLL) generates a 17.64 MHz or 19.2 MHz signal from the RTC at 32,768 Hz
(CLK32K), compatible with the requirement for MP3 playback in low power (LP) mode. In all cases, the input
reference clock must meet the phase-noise performance described in INPUT CLOCK PARAMETERS.
Figure 14 shows the clock-system block diagram.
24
Copyright © 2009–2011, Texas Instruments Incorporated
TWL6040
www.ti.com
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
Digital
ADC
A
RC
HPLLSEL
osc
LP PLL
PAD_CLK32K_1P8V
0
1
HPLLSQR
0
1
0
1
Clock
slicer
HP PLL
PAD_MCLK_1P8V
HPLLENA
McPDM
PAD_PDMCLK_1P8V
NCP
DAC
SWCS044-017
Figure 14. Clock System
POWER MANAGEMENT
The TWL6030 PMIC provides a +2.1-V preregulated supply VDDV2V1 to the TWL6040. The digital I/O buffers
and other digital functions are directly powered by the VDDVIO supply for a maximum 5-mA average load
current. The TWL6040 has an internal reference system powered from VBAT.
A high-side LDO postregulates VDDV2V1 to VDDLDO supply of +1.6 V for a maximum load of 150 mA. The
preamplifiers, PGA, ADCs, DAC, PLL, headset drivers, earpiece driver, auxiliary drivers, and other analog
functions use the VDDLDO supply.
An integrated negative charge pump generates a –1.9-V preregulated supply NCPOUT. A low-side LDO
postregulates NCPOUT to a VSSLDO supply of –1.6 V for a maximum load of 150 mA, providing the negative
supply for the analog functions powered by VDDLDO formerly described.
Figure 15 shows the power-management diagram.
Copyright © 2009–2011, Texas Instruments Incorporated
25
TWL6040
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
www.ti.com
VBAT
TWL6030
SMPS
VIO_V1V8
SMPS
VR_V2V1
Band gap
Boost
Optional
I/O
digital,
5 mA
HS-LDO
150 mA
VDDLDO
Band gap
VDDVREF
VDDABIAS
GNDLDO1
VDDEAR, VDDHS,
VDDUL, VDDDL,
VDDPLL
PreAmp, ADC, DAC, PGA, PLL,
Earpiece, HS, AUX drivers
110 mA
IHF drivers
vibrator
1 A
Analog bias
2 x 2 mA
VSSEAR, VSSHS,
VSSUL, VSSDL,
VSSPLL
GNDAMIC
VDDBIAS
GNDLDO2
VSSLDO
LS-LDO
150 mA
Digital bias
2 x 10 mA
VSSLDOIN
NCPFB
GNDDMIC
NCPOUT
CFLYN
NCP
150 mA
Audio
ref
TWL6040
CFLYP
SWCS044-018
Figure 15. Power-Management Diagram
26
Copyright © 2009–2011, Texas Instruments Incorporated
TWL6040
www.ti.com
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
THERMAL PROTECTION
If the temperature in the TWL6040 increases above a thermal threshold at which damage can occur, a thermal
interrupt THINT is generated. Also, immediate action is automatically taken to reduce the amount of power drawn
from the device.
Figure 16 shows a timing sequence showing a thermal event.
TWL6040
Application
processor
AUDPWRON_SYS
VIO
AUDPWRON
V1V8_FDBK
V1V8_SW
TWL6030
VDDVIO
V2V1_FDBK
V2V1_SW
VDDV2V1
NRESPWRON
NRESPWRON
SWCS044-019
Figure 16. Thermal-Event Timing
PARAMETER
Thermal interrupt threshold
TEST CONDITIONS
Positive
MIN
142
132
TYP
152
142
MAX
162
UNITS
°C
Negative
152
°C
The TWL6040 initiates a power-down sequence (except for the reference system and temperature sensor) when
the junction temperature goes above the positive threshold (TSHUTCOMP equals 1). The must to pull the
AUDPWRON line down when the thermal-interrupt information is received. In this particular case, pulling
AUDPWRON down does not disable the reference system and temperature sensor. The host should only bring
the TWL6040 to POWER-ON state (by pulling the AUDPWRON high) when another thermal interrupt is received.
Copyright © 2009–2011, Texas Instruments Incorporated
27
TWL6040
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
www.ti.com
INTERFACES
The TWL6040 has three digital interfaces:
1. I2C interface for information with noncritical latency
2. PDM interface for the audio signal and the register associated with audio path (gain, control)
3. GPO for audio IC interacting with TWL6040 (drivers, power provider)
Some dual-access registers (addresses 0x0A to 0x1B) can be accessed by the I2C and PDM interfaces. The
concurrent access is disabled by default, and only the PDM interface can write to these registers. The R/W
access can be switched to I2C-only by setting the I2CSEL bit. A concurrent access by the I2C and PDM
interfaces is also possible by setting the PDMI2CSEL bit. In this case, the TWL6040 does not provide arbitration
of simultaneous accesses and the functionality of the system cannot be assured. In this mode, software must
ensure that access by one interface is complete before using the other one, to avoid collisions.
I2C
The TWL6040 device provides one I2C interface. This allows read/write access to the configuration registers of
all resources of the system. Table 3 describes the I2C interface.
Table 3. I2C Interface
SUPPORTED
NOT SUPPORTED
General call, bus clear, device ID, CBUS compatibility, SMBus,
time-out feature, PMBus, IPMI, ATCA
Compliant to Philips I2C spec Rev 3.0
Slave only (receiver and transmitter)
Standard mode (up to 100 kbits/s)
Fast mode (up to 400 kbit/s)
Master mode (bus arbitration and clock generation)
Fast-mode plus (up to 1 Mbit/s)
High-speed mode (up to 3.4 Mbit/s)
Four I2C slave address decoding features
7-bit device addressing mode
10-bit device-addressing mode
Clock stretching
The TWL6040 I2C embeds a single slave address hard coded to 0x4B to address a single register address
space of 256 bytes.
PDM Interface
The PDM interface is the oversampled serial interface used for communication between TWL6040 audio and the
application processor companion chip. PDM_CLK is 19.2 or 17.64 MHz, and the data rate represented by
PDM_FRAME is 1.92 or 1.764 MHz. Words of data can be transmitted from OMAP to the TWL6040 chip using
the PDM_DN line (downlink path), but words of data can also be transmitted from the TWL6040 chip to OMAP
using the PDM_UP line (uplink path). Both chips are synchronized through the PDM_FRAME line. The OMAP
device owns PDM_FRAME by default.
The PDM interface has three modes: normal, command, and test. The normal and command modes are
intended for use with OMAP McPDM. The test mode is designed for evaluation and production test.
Figure 17 shows the PDM interface.
28
Copyright © 2009–2011, Texas Instruments Incorporated
TWL6040
www.ti.com
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
TWL6040
OMAP
PDM_FRAME
PDMFRAME
PDM_UP
PDM_DN
PDMUL
PDMDL
PDM_CLK
PDMCLK
PDMCLKLB
PDM_CLK_LB
SWCS044-020
Figure 17. PDM Interface
PDM_CLK is used to generate all internal clocks in the OMAP McPDM interface. The clock-tree architecture in
the OMAP may produce multiclock cycle delays under the worst-case conditions. To assure the uplink/downlink
data handshake between the TWL6040 and OMAP, the TWL6040 PDM interface uses PDM_CLK_LB, which is
the clock reproduced in OMAP. This prevents any critical timing issues.
In normal mode, the ratio between PDM_FRAME and PDM_CLOCK_LB is 10. This ratio is static and the
PDM_FRAME low-pulse width is one clock period long. In this mode, the PDM_FRAME signal is driven by
OMAP (through its McPDM module) to TWL6040. The OMAP drives the PDM_FRAME line low during one clock
cycle, and then drives it high during one clock cycle before releasing the PDM_FRAME driver in Hi-Z state.
TWl6040 connects PDM_FRAME to the I/O supply with a pullup resistor to keep it high.
In normal mode, a maximum of 2 × 5 downlink samples can be received during a frame period. As data samples
are generated at 3.84 MHz, this mean that two words of five samples can be transmitted during one frame cycle.
The receive channels can be enabled through I2C register bits. A maximum of 2 × 2 uplink samples can be
transmitted during a frame. The transmit channels can be enabled by I2C register bits.
Figure 18 shows the timing in normal mode with two downlink and two uplink channels enabled.
PDM_FRAME_OUT
PDM_CLK_LB
U
U
Rx0 Rx1
Rx0 Rx1
Rx0
Tx0
Rx1
Tx1
Rx0
Tx0
Rx1
Tx1
PDM_DN
PDM_UP
Tx0
Tx1
Tx0 Tx1
SWCS044-021
Figure 18. Normal Mode With Two Downlink and Two Uplink Channels Enabled
OMAP starts to send downlink packet on the first rising edge of PDM_CLK_LB, after PDM_CLK_LB goes from
high to low while PDM_FRAM_OUT is low. This is the start downlink condition. The uplink path has the same
timing as its downlink path.
Figure 19 shows the timing in normal mode with five downlink and two uplink channels enabled.
Copyright © 2009–2011, Texas Instruments Incorporated
29
TWL6040
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
www.ti.com
PDM_FRAME_OUT
PDM_CLK_LB
U
U
Rx0 Rx1 Rx2 Rx3 Rx4 Rx0
Rx0
Rx1 Rx2 Rx3 Rx4
Rx1 Rx2 Rx3 Rx4
Rx0
PDM_DN
PDM_UP
Rx1 Rx2 Rx3 Rx4
Tx0 Tx1
Tx0 Tx1
Tx0 Tx1
Tx0 Tx1
SWCS044-022
Figure 19. Normal Mode With Five Downlink and Two Uplink Channels Enabled
In command mode, register data can be sent from the OMAP to the TWL6040 using the PDM_FRAME line. This
can be the case when OMAP attempts to change the audio gain value on the fly without using the I2C interfaces,
which may be busy, and add a timing mismatch between signal and gain correction. The command mode is
available by default, but can be disabled by register.
General-Purpose Interface
The TWL6040 audio provides three general-purpose digital output buffers accessible through the I2C interface.
The goal is to make provisions for the interface of external audio devices or power providers, such as HAC
drivers, high-voltage drivers for piezo-electric loads, or external boost supplies for internal HF drivers. The default
value of these buffers is low and they have pulldown resistors.
POWER-UP AND POWER-DOWN SEQUENCES
Figure 20 shows the schematic diagram for the power-up and power-down sequences.
TWL6040
Application
processor
AUDPWRON_SYS
VIO
AUDPWRON
V1V8_FDBK
V1V8_SW
TWL6030
VDDVIO
V2V1_FDBK
V2V1_SW
VDDV2V1
NRESPWRON
NRESPWRON
SWCS044-024
Figure 20. Power-Up and Power-Down Sequences
The NRESPWRON input signal is an active-low reset signal (NRESPWRON) delivered by the TWL6030 at the
30
Copyright © 2009–2011, Texas Instruments Incorporated
TWL6040
www.ti.com
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
end of its own power-on sequence, it is released when all the supply voltage (core and I/Os) are correctly set up.
TWL6030 has a VRTC domain powered pulldown on the NRESPWRON signal, ensuring a low-impedance path
to ground, even when the VIO supply is off. The TWL6040 uses this signal to reset the register and
state-machine running from the I/O supplies, as well as disable the modules directly powered by the VBAT
supply.
AUDPWRON is an active-high input signal generated by a GPIO on the application processor side. It triggers the
internal power-on and power-off sequences of the TWL6040. The AUDPWRON signal is internally debounced.
Power-Up Sequence
The VIO domain logic and registers are in reset when VIO is high and NRESPWRON is low.
After NRESPWRON goes high, I2C on the VIO domain, plug detect, and GPO functions are available
(deep-sleep mode).
After V2V1 goes high, the hook-detect function is available by I2C programming (sleep mode).
The power-up sequence is initiated by a low-to-high transition on the AUDPWRON signal. VBAT, VIO, and V2V1
must be within their specified limits when the AUDPWRON transition occurs. The power-up sequence is
internally generated by the TWL6040 state-machine and completion of sequence is signaled by the READYINT
active-high output-interrupt signal. READYINT signals the application processor that the TWL6040 has
completed its power-up sequence and is ready to communicate with the application processor through the I2C or
PDM interface.
Power-Down Sequence
The power-down sequence is initiated by a high-to-low transition of the AUDPWRON signal. The power-down
sequence is internally generated by the TWL6040 state-machine.
INTERRUPTS
The TWL6040 drives the NAUDINT line low when an interrupt is internally detected and the host must be
notified.
The possible events are:
•
•
•
•
•
•
•
THINT: Die temperature overlimit detection
PLUGINT: Plug insertion detection
UNPLUGINT: Plug removal detection
HOOKINT: Hook send/end detection
HFINT: Left or right hands-free driver overcurrent detection
VIBINT: Left or right vibrator driver overcurrent detection
READYINT: Completion of power-up sequence
For each interrupt, an optional mask bit can be set.
Copyright © 2009–2011, Texas Instruments Incorporated
31
TWL6040
SWCS044H –NOVEMBER 2009–REVISED JULY 2011
www.ti.com
PACKAGE CHARACTERISTICS
The package is a ZQZ lead-free 6 × 6 mm2 MicroStar Junior plastic ball grid array (PBGA) 120ZQZ
(PTWL6040A2ZQZ/R) 0.5 mm with 120 physical balls, of which 119 are routable. The mechanical data is shown
below.
SWCS044-026
Figure 21. TWL6040 Mechanical Package
32
Copyright © 2009–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
9-Aug-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TWL6040A2ZQZ
TWL6040A2ZQZR
ACTIVE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQZ
120
250
Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
BGA
MICROSTAR
JUNIOR
ZQZ
120
2500
Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TWL6040A2ZQZR
BGA MI
CROSTA
R JUNI
OR
ZQZ
120
2500
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
333.2 345.9 31.8
TWL6040A2ZQZR
BGA MICROSTAR
JUNIOR
ZQZ
120
2500
Pack Materials-Page 2
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