UC1707-SP [TI]

DUAL CHANNEL POWER DRIVER; 双通道电源驱动器
UC1707-SP
型号: UC1707-SP
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

DUAL CHANNEL POWER DRIVER
双通道电源驱动器

驱动器
文件: 总15页 (文件大小:578K)
中文:  中文翻译
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UC1707-SP  
www.ti.com  
SLUSAG0 MARCH 2011  
DUAL CHANNEL POWER DRIVER  
Check for Samples: UC1707-SP  
1
FEATURES  
J OR W PACKAGE  
(TOP VIEW)  
Rad-Tolerant: 50 kRad (Si) for  
5962-8761903VEA, 5962-8761903VFA  
(1)  
INPUT B INV.  
INPUT B N.I.  
LATCH DISABLE  
GROUND  
1
2
3
4
5
6
7
8
16 INPUT A INV.  
QML-V Qualified, SMD  
(5962-8761901VEA, 5962-8761903VEA,  
5962-8761903VFA, 5962-8761901V2A)  
15  
14  
13  
12  
11  
10  
9
INPUT A N.I.  
+VIN  
GROUND  
GROUND  
GROUND  
Two Independent Drivers  
OUTPUT A  
SHUTDOWN  
+VC  
OUTPUT B  
ANALOG STOP NON-INV.  
ANALOG STOP INV.  
1.5-A Totem Pole Outputs  
Inverting and Non-Inverting Inputs  
40-ns Rise and Fall Into 1000 pF  
High-Speed, Power MOSFET Compatible  
Low Cross-Conduction Current Spike  
Analog Shutdown With Optional Latch  
Low Quiescent Current  
NOTE: All four ground pins must be connected to a  
common ground.  
FK PACKAGE  
(TOP VIEW)  
NC  
INPUT A INV.  
INPUT B INV.  
INPUT B I.N.  
INPUT A NON INV.  
5-V to 40-V Operation  
3
2
1
20 19  
18  
17  
16  
15  
14  
Thermal Shutdown Protection  
16-Pin Dual-In-Line Package  
4
5
LATCH DISABLE  
GROUND  
VIN  
GROUND  
NC  
6
NC  
GROUND  
OUTPUT B  
GROUND  
7
8
OUTPUT A  
9
10 11 12 13  
SHUTDOWN  
VC  
(1) Radiation tolerance is a typical value based upon initial device  
qualification with dose rate = 10 mrad/sec. Radiation Lot  
Acceptance Testing is available - contact factory for details.  
ANALOG STOP INV.  
ANALOG STOP NON INV.  
NC  
DESCRIPTION  
The UC1707 power driver is made with a high-speed Schottky process to interface between low-level control  
functions and high-power switching devicesparticularly power MOSFETs. The UC1707 contains two  
independent channels, each of which can be activated by either a high or low input logic level signal. Each output  
can source or sink up to 1.5 A as long as power dissipation limits are not exceeded.  
Although each output can be activated independently with its own inputs, it can be forced low in common through  
the action either of a digital high signal at the Shutdown terminal or a differential low-level analog signal. The  
Shutdown command from either source can either be latching or not, depending on the status of the Latch  
Disable pin.  
Supply voltage for both VIN and VC can independently range from 5 V to 40 V.  
TRUTH TABLE  
(Each Channel)(1)  
INV.  
H
N.I.  
OUT  
H
L
H
L
L
H
H
L
L
L
L
(1) OUT = INV and N.I.  
OUT = INV or N.I.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
© 2011, Texas Instruments Incorporated  
UC1707-SP  
SLUSAG0 MARCH 2011  
www.ti.com  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
BLOCK DIAGRAM  
ORDERING INFORMATION(1)  
ORDERABLE PART NUMBER  
5962-8761901VEA  
TA  
PACKAGE(2)  
TOP-SIDE MARKING  
5962-8761901VEA  
5962-8761903VEA  
5962-8761903VFA  
5962-8761901V2A  
(J) CDIP  
5962-8761903VEA  
55°C to 125°C  
(W) CFP  
5962-8761903VFA  
(FK) LCCC  
5962-8761901V2A  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
2
Submit Documentation Feedback  
© 2011, Texas Instruments Incorporated  
Product Folder Link(s): UC1707-SP  
UC1707-SP  
www.ti.com  
SLUSAG0 MARCH 2011  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range (unless otherwise noted)  
MIN  
MAX UNIT  
VIN  
VC  
Supply voltage  
40  
40  
V
V
Collector supply voltage  
Output current (each output, source or sink) steady-state  
Peak transient  
±500  
±1  
mA  
A
Capacitive discharge energy  
Digital inputs(1)  
15  
mJ  
V
5.5  
VIN  
150  
9.6  
Analog stop inputs  
TJ  
Operating virtual-junction temperature  
°C  
J package  
W package  
FK package  
J package  
W package  
FK package  
θJC  
Package thermal impedance, junction to case(2)(3)  
8.3 °C/W  
9.5  
13  
Power dissipation at Tcase = 25°C(1)  
15  
13  
W
Operating temperature range  
55  
65  
125  
150  
300  
°C  
°C  
°C  
Storage temperature range  
Lead temperature (soldering, 10 seconds)  
(1) All voltages are with respect to the four ground pins which must be connected together. All currents are positive into, negative out of the  
specified terminal. Digital drive can exceed 5.5 V if input current is limited to 10 mA. Consult packaging section of databook for thermal  
limitations and considerations of package.  
(2) Maximum power dissipation is a function of TJ (max), θJC, and TC. The maximum allowable power dissipation at any allowable case  
temperature is PD = (TJ (max) TC)/θJC. Operating at the absolute maximum TJ of 150°C can affect reliability.  
(3) The package thermal impedance is calculated in accordance with MIL-STD-883.  
ELECTRICAL CHARACTERISTICS  
Unless otherwise stated, these specifications apply for TA = 55°C to 125°C; VIN = VC = 20 V. TA = TJ.  
PARAMETER  
Supply current  
TEST CONDITIONS  
MIN  
TYP  
12  
MAX UNIT  
15 mA  
VIN  
VC  
VC  
VIN = 40 V  
Supply current  
VC = 40 V, outputs low  
5.2  
7.5 mA  
0.1 mA  
Leakage current  
Digital input low level  
Digital input high level  
Input current  
VIN = 0, VC - 30 V, no load  
0.05  
0.8  
V
V
2.2  
VI = 0  
0.06  
1.0 mA  
Input leakage  
VI = 5 V  
0.05  
0.1 mA  
IO = 50 mA  
IO = 500 mA  
IO = 50 mA  
IO = 500 mA  
2.0  
V
V
C VO Output high sat.  
2.5  
0.4  
V
VO  
Output low sat.  
2.5  
8761901  
8761903  
100  
90  
130  
130  
10  
155  
1.0  
150  
mV  
150  
Analog threshold  
VCM = 0 to 15 V  
VCM = 0  
Input bias current  
20  
μA  
°C  
V
Thermal shutdown  
Shutdown threshold  
Latch disable threshold  
Pin 7 input  
Pin 3 input  
0.4  
0.8  
2.2  
2.2  
1.2  
V
© 2011, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Link(s): UC1707-SP  
UC1707-SP  
SLUSAG0 MARCH 2011  
www.ti.com  
TYPICAL SWITCHING CHARACTERISTICS  
VIN = VC = 20 V, TA = 25°C. Delays measured to 10% output change.  
PARAMETER  
From Inv. Input to Output  
TEST CONDITIONS  
OUTPUT CL =  
UNIT  
nF  
open  
1.0  
50  
40  
40  
40  
2.2  
60  
50  
50  
50  
Rise time delay  
10% to 90% rise  
Fall time delay  
40  
25  
30  
25  
ns  
ns  
ns  
90% to 10% fall  
ns  
From N.I. Input to Output  
Rise time delay  
30  
25  
40  
40  
55  
40  
50  
50  
65  
50  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
10% to 90% rise  
Fall time delay  
45  
90% to 10% fall  
25  
VC cross-conduction current spike duration Output rise  
25  
Output fall  
0
Analog shutdown delay  
Digital shutdown delay  
Stop non-Inv. = 0 V  
Stop Inv. = 0 to 0.5 V  
2 V input on Pin 7  
180  
180  
50  
4
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© 2011, Texas Instruments Incorporated  
Product Folder Link(s): UC1707-SP  
UC1707-SP  
www.ti.com  
SLUSAG0 MARCH 2011  
SIMPLIFIED INTERNAL CIRCUITRY  
Figure 1. Typical Digital Input Gate  
Figure 2. Typical Digital Input Gate  
Figure 3. Latch Disable  
© 2011, Texas Instruments Incorporated  
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5
Product Folder Link(s): UC1707-SP  
UC1707-SP  
SLUSAG0 MARCH 2011  
www.ti.com  
SIMPLIFIED INTERNAL CIRCUITRY (continued)  
Figure 4. Use of the Shutdown Pin  
SHUTDOWN CIRCUIT DESCRIPTION  
The function of the circuitry is to be able to provide a shutdown of the device. This is defined as functionality that  
will drive both outputs to the low state. There are three different inputs that govern this shutdown capability.  
Analog Stop Pins The differential inputs to this comparator provide a way to execute a shutdown.  
Latch Disable Pin Assuming that the Shutdown pin is left open, a high on this pin disables the latching  
functionality of the Analog Stop shutdown. A low on this pin enables the latching functionality of the Analog  
Stop shutdown. If a shutdown occurs through the Analog Stop circuit while Latch Disable is high, then the  
outputs will go low, but will return to normal operation as soon as the Analog Stop circuit allows it. If a  
shutdown occurs through the Analog Stop circuit while Latch Disable is low, then the outputs will go low and  
remain low even if the Analog Stop circuit no longer drives the shutdown. The outputs will remain "latched"  
low (in shutdown) until the Latch Disable goes high and the Analog Stop circuit allows it to return from  
shutdown or the VIN voltage is cycled to 0V and then returned above 5V.  
Shutdown Pin This pin serves two purposes.  
1. It can be used as an output of the Analog Stop circuit.  
2. It can be used as an input to force a shutdown or to force the device out of shutdown. This pin can  
override both the Analog Stop circuit as well as the Latch Disable Pin. When driving hard logic levels into  
the Shutdown pin, the Latch Disable functionality will be overridden and the Latch Disable will not function  
as it does when used in conjunction with the Analog Stop circuit. When the Shutdown pin is high, the  
outputs will be in the low state (shutdown). When the Shutdown pin is low (hard logic low) the outputs will  
operate normally, regardless of the state of the Latch Disable pin or the Analog Stop pins.  
In order to use the Shutdown Pin with the Latch Disable functional it is necessary to use either a diode in series  
with the Shutdown signal or to use an open collector pull-up so that the Shutdown pin is not pulled low. This  
configuration will allow the Latch Disable function to work with the Shutdown pin.  
6
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© 2011, Texas Instruments Incorporated  
Product Folder Link(s): UC1707-SP  
UC1707-SP  
www.ti.com  
SLUSAG0 MARCH 2011  
SIMPLIFIED INTERNAL CIRCUITRY (continued)  
Table 1. UG1707 SHUTDOWN TRUTH TABLE  
ANALOG STOP  
PREVIOUS STATE OF  
SHUTDOWN  
LATCH DISABLE  
OUTPUT  
LOGIC  
OUTPUT  
X
X
1
0
0
0
0
X
X
X
0
0
1
X
Follows Input Logic  
Low (Shutdown)  
1
X
X
Open  
Open  
Open  
Open  
Low (Shutdown)  
Shutdown  
Normal  
X
(1)Latched Shutdown  
Follows Input Logic  
Follows Input Logic  
(1) If the output was previously in Shutdown and Latch Disable was low and stays low, then even if the Analog Stop Logic is changed or the  
Shutdown pin is open, the outputs will remain in Shutdown.  
Figure 5. Transformer Coupled Push-Pull MOSFET Drive Circuit  
Figure 6. Current Limiting  
© 2011, Texas Instruments Incorporated  
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7
Product Folder Link(s): UC1707-SP  
UC1707-SP  
SLUSAG0 MARCH 2011  
www.ti.com  
Figure 7. Over-Voltage Protection  
Figure 8. Power MOSFET Drive Circuit  
Figure 9. Charge Pump Circuits  
8
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© 2011, Texas Instruments Incorporated  
Product Folder Link(s): UC1707-SP  
UC1707-SP  
www.ti.com  
SLUSAG0 MARCH 2011  
Figure 10. Power Bipolar Drive Circuit  
Figure 11. Transformer Coupled MOSFET Drive Circuit  
Figure 12. Power MOSFET Drive Circuit Using Negative Bias Voltage  
and Level Shifting to Ground Reference PWM  
© 2011, Texas Instruments Incorporated  
Submit Documentation Feedback  
9
Product Folder Link(s): UC1707-SP  
PACKAGE OPTION ADDENDUM  
www.ti.com  
28-Aug-2012  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
5962-8761901V2A  
5962-8761901VEA  
5962-8761903VEA  
5962-8761903VFA  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
LCCC  
CDIP  
CDIP  
CFP  
FK  
J
20  
16  
16  
16  
1
1
1
1
TBD  
TBD  
TBD  
TBD  
POST-PLATE N / A for Pkg Type  
A42  
A42  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
N / A for Pkg Type  
J
W
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF UC1707-SP :  
Catalog: UC1707  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
28-Aug-2012  
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
Addendum-Page 2  
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