UC1707_16 [TI]
DUAL CHANNEL POWER DRIVER;
| 型号： | UC1707_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL CHANNEL POWER DRIVER 驱动 |
| 文件： | 总16页 (文件大小：981K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1707, UC2707, UC3707
www.ti.com ............................................................................................................................................. SLUS177B–MARCH 1999–REVISED SEPTEMBER 2008
DUAL CHANNEL POWER DRIVER
1
FEATURES
•
•
•
•
•
•
Analog Shutdown With Optional Latch
Low Quiescent Current
•
•
•
•
•
•
Two Independent Drivers
1.5 A Totem Pole Outputs
5 V to 40 V Operation
Inverting and Non-Inverting Inputs
40 ns Rise and Fall Into 1000 pF
High-Speed, Power MOSFET Compatible
Low Cross-Conduction Current Spike
Thermal Shutdown Protection
16-Pin Dual-In-Line Package
20-Pin PLCC and CLCC Package
DESCRIPTION
The UC1707 family of power drivers is made with a high-speed Schottky process to interface between low-level
control functions and high-power switching devices–particularly power MOSFETs. These devices contain two
independent channels, each of which can be activated by either a high or low input logic level signal. Each output
can source or sink up to 1.5 A as long as power dissipation limits are not exceeded.
Although each output can be activated independently with its own inputs, it can be forced low in common through
the action either of a digital high signal at the Shutdown terminal or a differential low-level analog signal. The
Shutdown command from either source can either be latching or not, depending on the status of the Latch
Disable pin.
Supply voltage for both VIN and VC can independently range from 5 V to 40 V.
These devices are available in two-watt plastic "bat-wing" DIP for operation over a 0°C to 70°C temperature
range and, with reduced power, in a hermetically sealed cerdip for –55°C to +125°C operation. Also available in
surface mount DW, Q, L packages.
TRUTH TABLE
(Each Channel)(1)
INV.
H
N.I.
H
OUT
L
H
L
L
H
H
L
L
L
L
(1) OUT = INV and N.I.
OUT = INV or N.I.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2008, Texas Instruments Incorporated
UC1707, UC2707, UC3707
SLUS177B–MARCH 1999–REVISED SEPTEMBER 2008............................................................................................................................................. www.ti.com
BLOCK DIAGRAM
CONNECTION DIAGRAMS
2
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Copyright © 1999–2008, Texas Instruments Incorporated
Product Folder Link(s): UC1707 UC2707 UC3707
UC1707, UC2707, UC3707
www.ti.com ............................................................................................................................................. SLUS177B–MARCH 1999–REVISED SEPTEMBER 2008
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
VIN
VC
Supply voltage
N/J package
N/J package
N/J package
N package
J package
N package
J package
N/J-package
N/J package
N package
J package
N package
J package
40
40
V
V
Collector supply voltage
Output current (each output, source or sink) steady-state
±500
±1.5
±1.0
20
mA
Peak transient
A
Capacitive discharge energy
mJ
V
15
Digital inputs(1)
5.5
VIN
2
Analog stop inputs
Power dissipation at TA = 25°C
W
W
1
5
Power dissipation at T (leads/case) = 25°C(1)
2
Operating temperature range
–55
–65
+125
+150
300
°C
°C
°C
Storage temperature range
Lead temperature (soldering, 10 seconds)
(1) All voltages are with respect to the four ground pins which must be connected together. All currents are positive into, negative out of the
specified terminal. Digital drive can exceed 5.5 V if input current is limited to 10 mA. Consult packaging section of databook for thermal
limitations and considerations of package.
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply for TA = –55°C to +125°C for the UC1707, –25°C to +85°C for the
UC2707, and 0°C to +70°C for the UC3707; VIN = VC = 20 V. TA = TJ.
PARAMETER
Supply current
TEST CONDITIONS
MIN
TYP
12
MAX UNIT
VIN
VC
VC
VIN = 40 V
15
7.5
0.1
0.8
mA
mA
mA
V
Supply current
VC = 40 V, outputs low
5.2
Leakage current
Digital input low level
Digital input high level
Input current
VIN = 0, VC - 30 V, no load
0.05
2.2
V
VI = 0
–0.06
0.05
–1.0
0.1
2.0
2.5
0.4
2.5
160
–20
mA
mA
Input leakage
VI = 5 V
IO = –50 mA
IO = –500 mA
IO = –50 mA
IO = –500 mA
VCM = 0 to 15 V
VCM = 0
VC – VO Output high sat.
V
V
VO
Output low sat.
Analog threshold
100
130
–10
155
1.0
mV
µA
°C
V
Input bias current
Thermal shutdown
Shutdown threshold
Latch disable threshold
Pin 7 input
Pin 3 input
0.4
0.8
2.2
2.2
1.2
V
Copyright © 1999–2008, Texas Instruments Incorporated
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3
Product Folder Link(s): UC1707 UC2707 UC3707
UC1707, UC2707, UC3707
SLUS177B–MARCH 1999–REVISED SEPTEMBER 2008............................................................................................................................................. www.ti.com
TYPICAL SWITCHING CHARACTERISTICS
VIN = VC = 20 V, TA = 25°C. Delays measured to 10% output change.
PARAMETER
From Inv. Input to Output
TEST CONDITIONS
OUTPUT CL =
UNIT
nF
open
1.0
50
40
40
40
2.2
60
50
50
50
Rise time delay
10% to 90% rise
Fall time delay
40
25
30
25
ns
ns
ns
90% to 10% fall
ns
From N.I. Input to Output
Rise time delay
30
25
40
40
55
40
50
50
65
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
10% to 90% rise
Fall time delay
45
90% to 10% fall
25
VC cross-conduction current spike duration Output rise
Output fall
25
0
Analog shutdown delay
Stop non-Inv. = 0 V
Stop Inv. = 0 to 0.5 V
2 V input on Pin 7
180
180
50
Digital shutdown delay
4
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Copyright © 1999–2008, Texas Instruments Incorporated
Product Folder Link(s): UC1707 UC2707 UC3707
UC1707, UC2707, UC3707
www.ti.com ............................................................................................................................................. SLUS177B–MARCH 1999–REVISED SEPTEMBER 2008
SIMPLIFIED INTERNAL CIRCUITRY
Figure 1. Typical Digital Input Gate
Figure 2. Typical Digital Input Gate
Figure 3. Latch Disable
Copyright © 1999–2008, Texas Instruments Incorporated
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Product Folder Link(s): UC1707 UC2707 UC3707
UC1707, UC2707, UC3707
SLUS177B–MARCH 1999–REVISED SEPTEMBER 2008............................................................................................................................................. www.ti.com
SIMPLIFIED INTERNAL CIRCUITRY (continued)
Figure 4. Use of the Shutdown Pin
SHUTDOWN CIRCUIT DESCRIPTION
The function of the circuitry is to be able to provide a shutdown of the device. This is defined as functionality that
will drive both outputs to the low state. There are three different inputs that govern this shutdown capability.
•
•
Analog Stop Pins — The differential inputs to this comparator provide a way to execute a shutdown.
Latch Disable Pin — Assuming that the Shutdown pin is left open, a high on this pin disables the latching
functionality of the Analog Stop shutdown. A low on this pin enables the latching functionality of the Analog
Stop shutdown. If a shutdown occurs through the Analog Stop circuit while Latch Disable is high, then the
outputs will go low, but will return to normal operation as soon as the Analog Stop circuit allows it. If a
shutdown occurs through the Analog Stop circuit while Latch Disable is low, then the outputs will go low and
remain low even if the Analog Stop circuit no longer drives the shutdown. The outputs will remain "latched"
low (in shutdown) until the Latch Disable goes high and the Analog Stop circuit allows it to return from
shutdown or the VIN voltage is cycled to 0V and then returned above 5V.
•
Shutdown Pin — This pin serves two purposes.
1. It can be used as an output of the Analog Stop circuit.
2. It can be used as an input to force a shutdown or to force the device out of shutdown. This pin can
override both the Analog Stop circuit as well as the Latch Disable Pin. When driving hard logic levels into
the Shutdown pin, the Latch Disable functionality will be overridden and the Latch Disable will not function
as it does when used in conjunction with the Analog Stop circuit. When the Shutdown pin is high, the
outputs will be in the low state (shutdown). When the Shutdown pin is low (hard logic low) the outputs will
operate normally, regardless of the state of the Latch Disable pin or the Analog Stop pins.
In order to use the Shutdown Pin with the Latch Disable functional it is necessary to use either a diode in series
with the Shutdown signal or to use an open collector pull-up so that the Shutdown pin is not pulled low. This
configuration will allow the Latch Disable function to work with the Shutdown pin.
6
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Copyright © 1999–2008, Texas Instruments Incorporated
Product Folder Link(s): UC1707 UC2707 UC3707
UC1707, UC2707, UC3707
www.ti.com ............................................................................................................................................. SLUS177B–MARCH 1999–REVISED SEPTEMBER 2008
SIMPLIFIED INTERNAL CIRCUITRY (continued)
UG1707 SHUTDOWN TRUTH TABLE
ANALOG STOP
LOGIC
PREVIOUS STATE OF
OUTPUT
SHUTDOWN
LATCH DISABLE
OUTPUT
X
X
1
0
0
0
0
X
X
X
0
0
1
X
Follows Input Logic
Low (Shutdown)
1
X
X
Open
Open
Open
Open
Low (Shutdown)
Shutdown
Normal
X
(1)Latched Shutdown
Follows Input Logic
Follows Input Logic
(1) If the output was previously in Shutdown and Latch Disable was low and stays low, then even if the Analog Stop Logic is changed or the
Shutdown pin is open, the outputs will remain in Shutdown.
Figure 5. Transformer Coupled Push-Pull MOSFET Drive Circuit
Figure 6. Current Limiting
Copyright © 1999–2008, Texas Instruments Incorporated
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Product Folder Link(s): UC1707 UC2707 UC3707
UC1707, UC2707, UC3707
SLUS177B–MARCH 1999–REVISED SEPTEMBER 2008............................................................................................................................................. www.ti.com
Figure 7. Over-Voltage Protection
Figure 8. Power MOSFET Drive Circuit
Figure 9. Charge Pump Circuits
8
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Copyright © 1999–2008, Texas Instruments Incorporated
Product Folder Link(s): UC1707 UC2707 UC3707
UC1707, UC2707, UC3707
www.ti.com ............................................................................................................................................. SLUS177B–MARCH 1999–REVISED SEPTEMBER 2008
Figure 10. Power Bipolar Drive Circuit
Figure 11. Transformer Coupled MOSFET Drive Circuit
Copyright © 1999–2008, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Link(s): UC1707 UC2707 UC3707
UC1707, UC2707, UC3707
SLUS177B–MARCH 1999–REVISED SEPTEMBER 2008............................................................................................................................................. www.ti.com
Figure 12. Power MOSFET Drive Circuit Using Negative Bias Voltage
and Level Shifting to Ground Reference PWM
10
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Copyright © 1999–2008, Texas Instruments Incorporated
Product Folder Link(s): UC1707 UC2707 UC3707
PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-87619012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
87619012A
UC1707L/
81032
5962-8761901EA
5962-8761901V2A
ACTIVE
ACTIVE
CDIP
J
16
20
1
1
TBD
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-8761901EA
UC1707J/80900
LCCC
FK
POST-PLATE
5962-
8761901V2A
UC1707L
QMLV
5962-8761901VEA
5962-8761903VEA
5962-8761903VFA
UC1707J
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
CDIP
CFP
J
J
16
16
16
16
1
1
1
1
TBD
TBD
TBD
TBD
A42
A42
A42
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
-55 to 125
5962-8761901VE
A
UC1707JQMLV
5962-8761903VE
A
UC1707J-SP
W
J
5962-8761903VF
A
UC1707W-SP
CDIP
UC1707J
UC1707J/80313
UC1707J883B
OBSOLETE
ACTIVE
CDIP
CDIP
J
J
16
16
TBD
TBD
Call TI
A42
Call TI
-55 to 125
-55 to 125
1
1
1
N / A for Pkg Type
UC1707J/883B
UC1707L
UC1707L
ACTIVE
ACTIVE
LCCC
LCCC
FK
FK
20
20
TBD
TBD
POST-PLATE
POST-PLATE
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
UC1707L883B
UC1707L/
883B
UC2707DW
UC2707DWG4
UC2707DWTR
UC2707DWTRG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
16
16
16
16
40
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
UC2707DW
UC2707DW
UC2707DW
UC2707DW
Green (RoHS
& no Sb/Br)
2000
2000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
UC2707N
UC2707NG4
UC2707Q
ACTIVE
PDIP
PDIP
PLCC
PLCC
SOIC
SOIC
SOIC
SOIC
N
16
16
20
20
16
16
16
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU SN
N / A for Pkg Type
UC2707N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
N
25
46
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
UC2707N
FN
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
UC2707Q
UC2707QG3
UC3707DW
FN
46
Green (RoHS
& no Sb/Br)
CU SN
UC2707Q
DW
DW
DW
DW
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
UC3707DW
UC3707DW
UC3707DW
UC3707DW
UC3707DWG4
UC3707DWTR
UC3707DWTRG4
40
Green (RoHS
& no Sb/Br)
0 to 70
2000
2000
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
UC3707J
UC3707N
ACTIVE
ACTIVE
CDIP
PDIP
J
16
16
1
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
0 to 70
0 to 70
UC3707J
UC3707N
N
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
UC3707NG4
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
UC3707N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2013
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1707, UC1707-SP, UC3707, UC3707M :
Catalog: UC3707, UC1707, UC3707M, UC3707
•
Military: UC1707
•
Space: UC1707-SP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UC2707DWTR
UC3707DWTR
SOIC
SOIC
DW
DW
16
16
2000
2000
330.0
330.0
16.4
16.4
10.75 10.7
10.75 10.7
2.7
2.7
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UC2707DWTR
UC3707DWTR
SOIC
SOIC
DW
DW
16
16
2000
2000
367.0
367.0
367.0
367.0
38.0
38.0
Pack Materials-Page 2
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