UC1714DP [TI]
2A BUF OR INV BASED MOSFET DRIVER, PDSO16, POWER, PLASTIC, SOIC-16;
| 型号： | UC1714DP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2A BUF OR INV BASED MOSFET DRIVER, PDSO16, POWER, PLASTIC, SOIC-16 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总8页 (文件大小：297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
application
INFO
UC1714/5
UC2714/5
UC3714/5
available
Complementary Switch FET Drivers
FEATURES
DESCRIPTION
• Single Input (PWM and TTL
These two families of high speed drivers are designed to provide drive
waveforms for complementary switches. Complementary switch configura-
tions are commonly used in synchronous rectification circuits and active
clamp/reset circuits, which can provide zero voltage switching. In order to
facilitate the soft switching transitions, independently programmable delays
between the two output waveforms are provided on these drivers. The de-
lay pins also have true zero voltage sensing capability which allows imme-
diate activation of the corresponding switch when zero voltage is applied.
These devices require a PWM-type input to operate and can be interfaced
with commonly available PWM controllers.
Compatible)
• High Current Power FET Driver, 1.0A
Source/2A Sink
• Auxiliary Output FET Driver, 0.5A
Source/1A Sink
• Time Delays Between Power and
Auxiliary Outputs Independently
Programmable from 50ns to 500ns
In the UC1714 series, the AUX output is inverted to allow driving a
p-channel MOSFET. In the UC1715 series, the two outputs are configured
in a true complementary fashion.
• Time Delay or True Zero-Voltage
Operation Independently Configurable
for Each Output
• Switching Frequency to 1MHz
• Typical 50ns Propagation Delays
• ENBL Pin Activates 220µA Sleep
Mode
• Power Output is Active Low in Sleep
Mode
• Synchronous Rectifier Driver
BLOCK DIAGRAM
2
PWR
50ns –500ns
TIMER
INPUT
T1
6
7
S
Q
R
UC1714
ONLY
V
REF
4
1
AUX
VCC
50ns –500ns
TIMER
S
Q
V
5V
BIAS
ENBL
LOGIC
GATES
CC
T2
5
R
V
REF
TIMER
REF
3V
GND
3
GND
1.4V
ENBL
8
ENABLE
Note: Pin numbers refer to J, N and D packages.
UDG-99028
SLUS170A - FEBRUARY 1999 - REVISED JANUARY 2002
UC1714/5
UC2714/5
UC3714/5
ABSOLUTE MAXIMUM RATINGS
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
Power Driver IOH
continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −200mA
peak. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1A
Power Driver IOL
Input Voltage Range (INPUT, ENBL) . . . . . . . . . . −0.3V to 20V
Storage Temperature Range . . . . . . . . . . . . . . −65°C to 150°C
Operating Junction Temperature (Note 1) . . . . . . . . . . . . 150°C
Lead Temperature (Soldering 10 seconds) . . . . . . . . . . . 300°C
continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400mA
peak. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2A
Auxiliary Driver IOH
continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −100mA
peak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −500mA
Auxiliary Driver IOL
Note 1: Unless otherwise indicated, voltages are referenced to
ground and currents are positive into, negative out of, the speci-
fied terminals.
Note 2: Consult Packaging Section of databook for thermal limi-
tations and specifications of packages.
continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA
peak. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A
CONNECTION DIAGRAMS
DIL-8, SOIC-8 (Top View)
J or N, D Packages
SOIC-16 (Top View)
DP Package
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, VCC = 15V, ENBL ≥ 2V, RT1 = 100kΩ from T1 to GND,
RT2 = 100kΩ from T2 to GND, and −55°C < TA < 125°C for the UC1714/5, −40°C < TA < 85°C for the UC2714/5, and 0°C < TA <
70°C for the UC3714/5, TA = TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Overall
VCC
7
20
24
V
ICC, nominal
ENBL = 2.0V
ENBL = 0.8V
18
mA
µA
ICC, sleep mode
200
300
Power Driver (PWR)
Pre Turn-on PWR Output, Low
PWR Output Low, Sat. (VPWR
VCC = 0V, IOUT = 10mA, ENBL 0.8V
INPUT = 0.8V, IOUT = 40mA
INPUT = 0.8V, IOUT = 400mA
INPUT = 2.0V, IOUT = −20mA
INPUT = 2.0V, IOUT = −200mA
CL = 2200pF
0.3
0.3
2.1
2.1
2.3
30
1.6
0.8
2.8
3
V
V
)
V
PWR Output High, Sat. (VCC − VPWR
)
V
3
V
Rise Time
60
60
80
700
100
ns
ns
ns
ns
ns
Fall Time
CL = 2200pF
25
T1 Delay, AUX to PWR
T1 Delay, AUX to PWR
PWR Prop Delay
INPUT rising edge, RT1 = 10kΩ (Note 4)
INPUT rising edge, RT1 = 100kΩ (Note 4)
INPUT falling edge, 50% (Note 3)
20
35
350
500
35
2
UC1714/5
UC2714/5
UC3714/5
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, VCC = 15V, ENBL ≥ 2V, RT1 = 100kΩ from T1 to GND,
RT2 = 100kΩ from T2 to GND, and −55°C < TA < 125°C for the UC1714/5, −40°C < TA < 85°C for the UC2714/5, and 0°C < TA <
70°C for the UC3714/5, TA = TJ.
PARAMETER
Auxiliary Driver (AUX)
AUX Output Low, Sat (VAUX
TEST CONDITIONS
MIN
TYP
MAX UNITS
)
VIN = 2.0V, IOUT = 20mA
0.3
1.8
2.1
2.3
45
0.8
2.6
3.0
3.0
60
V
V
VIN = 2.0V, IOUT = 200mA
VIN = 0.8V, IOUT = -10mA
VIN = 0.8V, IOUT = -100mA
CL = 1000pF
AUX Output High, Sat (VCC – VAUX
)
V
V
Rise Time
ns
ns
ns
ns
ns
Fall Time
CL = 1000pF
30
60
T2 Delay, PWR to AUX
T2 Delay, PWR to AUX
AUX Prop Delay
Enable (ENBL)
Input Threshold
Input Current, IIH
Input Current, IIL
T1
INPUT falling edge, RT2 = 10kΩ (Note 4)
INPUT falling edge, RT2 = 100kΩ (Note 4)
INPUT rising edge, 50% (Note 3)
20
50
80
250
350
35
550
80
0.8
2.7
1.2
1
2.0
10
V
ENBL = 15V
ENBL = 0V
µA
µA
−1
−10
Current Limit
T1 = 0V
−1.6
3
−2
3.3
70
mA
V
Nominal Voltage at T1
Minimum T1 Delay
T2
T1 = 2.5V, (Note 4)
T2 = 0V
40
ns
Current Limit
−1.2
3
−2
3.3
100
mA
V
Nominal Voltage at T2
Minumum T2 Delay
Input (INPUT)
Input Threshold
Input Current, IIH
Input Current, IIL
2.7
0.8
T2 = 2.5V, (Note 4)
50
ns
1.4
1
2.0
10
V
INPUT = 15V
INPUT = 0V
µA
µA
−5
−20
Note 3: Propagation delay times are measured from the 50% point of the input signal to the 10% point of the output signal’s transi-
tion with no load on outputs.
Note 4: T1 delay is defined from the 50% point of the transition edge of AUX to the 10% of the rising edge of PWR. T2 delay is de-
fined from the 90% of the falling edge of PWR to the 50% point of the transition edge of AUX.
PIN DESCRIPTIONS
The ENBL input will place the device into sleep mode
when it is a logical low. The current into VCC during the
sleep mode is typically 220µA.
AUX: The AUX switches immediately at INPUT’s rising
edge but waits through the T2 delay after INPUT’s falling
edge before switching. AUX is capable of sourcing 0.5A
and sinking 1.0A of drive current. See the Time Relation-
ships diagram below for the difference between the
UC1714 and UC1715 for INPUT, MAIN, and AUX. During
sleep mode, AUX is inactive with a high impedance.
GND: This is the reference pin for all input voltages and
the return point for all device currents. It carries the full
peak sinking current from the outputs. Any tendency for
the outputs to ring below GND voltage must be damped
or clamped such that GND remains the most negative
potential.
ENBL: The ENBL input switches at TTL logic levels (ap-
proximately 1.2V), and its input range is from 0V to 20V.
3
UC1714/5
UC2714/5
UC3714/5
PIN DESCRIPTIONS (cont.)
INPUT: The input switches at TTL logic levels (approxi- T2: This pin functions in the same way as T1 but controls
mately 1.4V) but the allowable range is from 0V to 20V, the time delay between PWR turn-off and activation of
allowing direct connection to most common IC PWM con- the AUX switch.
troller outputs. The rising edge immediately switches the
T1, T2: The resistor on each of these pins sets the
AUX output, and initiates a timing delay, T1, before
charging current on internal timing capacitors to provide
switching on the PWR output. Similarly, the INPUT falling
independent time control. The nominal voltage level at
edge immediately turns off the PWR output and initiates
each pin is 3V and the current is internally limited to
1mA. The total delay from INPUT to each output includes
a timing delay, T2, before switching the AUX output.
It should be noted that if the input signal comes from a
controller with FET drive capability, this signal provides
another option. INPUT and PWR provide a delay only at
the leading edge while INPUT and AUX provide the delay
at the trailing edge.
a propagation delay in addition to the programmable
timer but since the propagation delays are approximately
equal, the relative time delay between the two outputs
can be assumed to be solely a function of the pro-
grammed delays. The relationship of the time delay vs.
RT is shown in the Typical Characteristics curves.
PWR: The PWR output waits for the T1 delay after the
INPUT’s rising edge before switching on, but switches off Either or both pins can alternatively be used for voltage
immediately at INPUT’s falling edge (neglecting propaga- sensing in lieu of delay programming. This is done by
tion delays). This output is capable of sourcing 1A and pulling the timer pins below their nominal voltage level
sinking 2A of peak gate drive current. PWR output in- which immediately activates the timer output.
cludes a passive, self-biased circuit which holds this pin
active low, when ENBL ≥ 0.8V regardless of VCC’s volt-
age.
VCC: The VCC input range is from 7V to 20V. This pin
should be bypassed with a capacitor to GND consistent
with peak load current demands.
T1: A resistor to ground programs the time delay be-
tween AUX switch turn-off and PWR turn-on.
TYPICAL CHARACTERISTICS
INPUT
PROPAGATION
DELAYS
PWR OUTPUT
T1 vs RT1
T2 vs RT2
500
400
300
200
100
0
T1 DELAY
T2 DELAY
UC1714 AUX OUTPUT
UC1715 AUX OUTPUT
0
10
20
30
40
50
60
70
80
90 100
RT (kW)
UDG-99027
Time relationships. (Notes 3, 4)
T1 Delay, T2 Delay vs. RT
4
UC1714/5
UC2714/5
UC3714/5
TYPICAL CHARACTERISTICS (cont.)
21
18
17
16
15
20
19
18
17
16
0
100 200 300 400 500 600 700 800 9001000
Switching Frequency (kHz)
0
10 20 30 40 50 60 70 80 90 100
RT (kΩ)
ICC vs Switching Frequency with No Load and 50%
Duty Cycle RT1 = RT2 = 50k
ICC vs RT with Opposite RT = 50k
600
600
500
RT1 = 100k
500
400
400
RT2 = 100k
300
300
RT1 = 50k
RT2 = 50k
200
200
100
100
RT2 = 10k
RT1 = 10k
RT2 < 6k
RT1 < 6k
25
Temperature (°C)
0
-75
0
-75
-50
-25
0
25
50
75
100
125
-50
-25
0
50
75
100
125
Temperature (°C)
T1 Deadband vs. Temperature AUX to PWR
TYPICAL APPLICATIONS
T2 Deadband vs. Temperature PWR to AUX
UDG-94011
UDG-94012
Figure 1. Typical application with timed delays.
Figure 2. Using the timer input for
zero-voltage sensing.
5
UC1714/5
UC2714/5
UC3714/5
TYPICAL APPLICATIONS (cont.)
UDG-94013
Figure 3. Self-actuated sleep mode with the absence of an input PWM signal. Wake up occurs with the first
pulse while turn-off is determined by the (RTO CTO) time constant.
UDG-94015-2
Figure 4. Using the UC1715 as a complementary synchronous rectifier switch driver with n-channel FETs
UDG-94014-1
Figure 5. Synchronous rectifier application with a charge pump to drive the high-side n-channel buck switch.
VIN is limited to 10V as VCC will rise to approximately 2VIN.
6
UC1714/5
UC2714/5
UC3714/5
TYPICAL APPLICATIONS (cont.)
UDG-94016-1
Figure 6. Typical forward converter topology with active reset provided by the UC1714 driving an N-channel
switch (Q1) and a P-channel auxilliary switch (Q2).
UDG-94017-1
Figure 7. Using an N-channel active reset switch with a floating drive command.
7
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