UC1827J-2 [TI]
Buck Current/Voltage Fed Push-Pull PWM Controllers; 降电流/电压馈送推挽PWM控制器
| 型号： | UC1827J-2 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Buck Current/Voltage Fed Push-Pull PWM Controllers |
| 文件： | 总15页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2
www.ti.com
SLUS365A–APRIL 1999–REVISED AUGUST 2005
BUCK CURRENT/VOLTAGE FED PUSH-PULL
PWM CONTROLLERS
FEATURES
DESCRIPTION
•
Ideal for Multiple Output and/or High
Voltage Output Voltage Converters
The UC3827 family of controller devices provides an
integrated control solution for cascaded buck and
push-pull converters. These converters are known as
current fed or voltage fed push-pull converters and
are ideally suited for multiple output and/or high
voltage output applications. In both current fed and
voltage fed modes, the push-pull switches are driven
at 50% nominal duty cycles and at one half the
switching frequency of the buck stage. In the current
fed mode, the two switches are driven with a speci-
fied over-lap period to prevent ringing and voltage
stress on the devices. In the voltage fed mode, the
two switches are driven with a specified gap time
between the switches to prevent shorting the trans-
former across the energy storage capacitor and to
prohibit excessive currents flowing through the de-
vices.
•
•
Up to 500 kHz Operation
High Voltage, High Current Floating
Driver for Buck Converter Stage
•
•
•
UC3827-1 Current Fed Controller has
Push-Pull Drivers with Overlapping
Conduction Periods
UC3827-2 Voltage Fed Controller has
Push-Pull Drivers with Nonoverlapping
Conduction Periods
Average Current Mode, Peak Current
Mode or Voltage Mode with Input
Voltage Feedforward Control for Buck
Power Stage
•
•
Wide Bandwidth, Low Offset,
Differential Current Sense Amplifier
The converter's output voltage is regulated by pulse
width modulation of the buck switch. The UC3827
contains complete protection and PWM control func-
tions for the buck converter. Easy control of the
floating switch is accomplished by the floating drive
circuitry. The gate drive waveform is level shifted to
Precise Short Circuit Current Control
support an input voltage up to 72 VDC
.
BLOCK DIAGRAM
VEAOCEA+ CEAO RAMP
10
12
6
5
Voltage Error
Amplifier
14
16
13
7
VEA+
VEA−
CEA−
CSAO
CSA+
CSA−
SS
0.7 V PWM Comparator
Current Error
Amplifier
R
D
Flying
Driver
1
2
3
V+
+3 V
ILIM Comparator
8
S
Q
BUCK
SRC
9
Current Sense
Amplifier
SS
INHBT
UV
4
OSC
19
18
17
15
23
21 PGND
SYNC
CT
OSC
Q
DELAY
T
500 kHz
MAX
Push/Pull
Drivers
RT
Q
REF
24 PUSH
22 PULL
VCC
REF
&
UVLO
UVLO
DELAY
11
GND
20
DELAY
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2005, Texas Instruments Incorporated
UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2
www.ti.com
SLUS365A–APRIL 1999–REVISED AUGUST 2005
DESCRIPTION (CONTINUED)
The UC3827 can be set up in traditional voltage mode control using input voltage feedforward technique or in
current mode control. Using current mode control prevents potential core saturation of the push-pull transformer
due to mismatches in timing and in component tolerances. With average current mode control, precise control of
the inductor current feeding the push-pull stage is possible without the noise sensitivity associated with peak
current mode control. The UC3827 average current mode loop can also be connected in parallel with the voltage
regulation loop to assist only in fault conditions.
Other valuable features of the UC3827 include bidirectional synchronization capability, user programmable
overlap time (UC3827-1), user programmable gap time (UC3827-2), a high bandwidth differential current sense
amplifier, and soft start circuitry.
ORDERING INFORMATION(1)
PACKAGES
TA = TJ
PUSH-PULL TOPOLOGY
SOIC-24
PDIP-24
PLCC-28
Current Fed
Voltage Fed
Current Fed
Voltage Fed
Current Fed
Voltage Fed
UC1827J-1
UC1827J-1
UC1827J-2
UC2827N-1
UC2827N-2
UC3827N-1
UC3827N-2
-55°C to 125°C
-40°C to 85°C
0°C to 70°C
UC1827J-2
UC2827DW-1
UC2827DW-2
UC3827DW-1
UC3827DW-2
-
-
UC3827Q-1
-
(1) The DW and Q packages are also available taped and reeled. Add a TR suffix to the device type (i.e., UC2827DWTR-1).
DISSIPATION RATINGS
PACKAGE
(θJA) JUNCTION-TO-AMBIENT
(θJC) JUNCTION-TO-WHAT?
TEMPERATURE (°C/W)
TEMPERATURE (°C/W)
24-pin (N)
24-pin (J)
60(1)
30
28(2)
24(3)
30
70 to 90
71 to 83(3)
40-65(1)
28-pin (DW)
28-pin (QLCC)
(1) Specified θJA (junction-to-ambient) refers to devices mounted to 5-in2 FR4 PC board with 1 oz. copper where noted. When a resistance
range is given, the lower values refer to a 5-in2 aluminum PC board. The test PWB is 0.062 inches thick and typically used 0.635 mm
trace widths for power packages and 1.3 mm trace widths for non-power packages with a 100 × 100 mil probe land area at the end of
each trace.
(2) Specified θJC (junction-to-what?) data values stated were derived from MIL-STD-1835B which states "The baseline values shown are
worst case (mean + 2s) for a 60 x 60 mil microcircuit device silicon die and applicable for devices with die sizes up to 14400 mils2. For
device sizes greater than 14400 mils2 use the following values; dual-in-line, 11 °C/W; flat pack, 10 °C/W; pin grid array, 10 °C/W pin grid
array, 10 °C/W."
(3) Modeled data. If there is a value range given for θJA, the lower value refers to a 3 x 3 in., 1-oz, internal copper ground plane. The higher
value refers to a 1 x 1 in. ground plane. All model data assumes only one trace for each non-fused lead.
2
UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2
www.ti.com
SLUS365A–APRIL 1999–REVISED AUGUST 2005
ABSOLUTE MAXIMUM RATINGS(1)
UC2827-1
UC2827-2
UC3827-1
UNITS
UC3827-2
Supply voltage, VCC
20
CEAO, CEA+, CEA-, CSAO, CSA+, CSA-, CT, DELAY, PUSH, PULL,
RAMP, RT, SS, SYNC, VEA+, VEAO,
–0.3 to 5
V
Input voltage range
V+ and BUCK
SRC
90
90-VCC
I/O continuous
I/O peak
±250
±1
mA
A
BUCK driver
I/O continuous
I/O peak
±200
mA
A
PUSH/PULL driver
±0.8
Storage temperature
Junction temperature
–65 to 150
–55 to 150
300
°C
Lead temperature (soldering, 10 sec)
(1) Voltages are referenced to ground. Currents are positive into, negative out of the specified terminal. Consult Packaging section of
databook for thermal limitations and considerations of packages.
PLCC-28 (Q PACKAGE)
CONNECTION DIAGRAMS
(TOP VIEW)
DIL-24 (N or J, DW PACKAGES)
(TOP VIEW)
Q PACKAGE
(TOP VIEW)
N, J OR DW PACKAGES
(TOP VIEW)
1
24
23
22
21
20
19
18
17
16
15
14
13
V+
BUCK
SRC
PUSH
VCC
4
3
2 1 28 27 26
2
SS
RAMP
CEAO
CSAO
CSA+
CSA−
VEAO
5
6
7
8
9
PGND
25
3
PULL
PGND
DELAY
SYNC
CT
RT
VEA−
REF
24 NC
23 NC
4
SS
5
RAMP
CEAO
CSAO
CSA+
CSA−
VEAO
GND
22
21
20
19
DELAY
SYNC
CT
6
7
10
8
11
RT
9
12 13 14 15 16 17 18
10
11
12
VEA+
CEA−
CEA+
NC − No internal connection
3
UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2
www.ti.com
SLUS365A–APRIL 1999–REVISED AUGUST 2005
Terminal Functions
TERMINAL
I/O
DESCRIPTION
N or
DW
NAME
Q
Output of the buck PWM controller. The BUCK output is a floating driver, optimized for controlling the
gate of an N-channel MOSFET. The peak sink and source currents are 1 A. VCC undervoltage faults
disables BUCK to an off condition (low).
BUCK
2
3
O
CEA+
CEA-
12
13
13
14
I
I
Non-inverting input of the current error amplifier.
Inverting input of the current error amplifier
Output of the current error amplifier and the inverting input of the PWM comparator of the buck
converter.
CEAO
6
7
O
CSA+
CSA–
8
9
9
I
I
Noninverting input of the current sense amplifier.
Inverting input of the current sense amplifier.
10
Output of the current sense amplifier and the noninverting input of the current limit comparator. When
the signal level on this pin exceeds the 3V threshold of the current limit comparator, the buck gate drive
pulse is terminated. This feature is useful to implement cycle-by-cycle current limiting for the buck
converter.
CSAO
CT
7
8
O
I
Provides for the timing capacitor which is connected between CT and GND. The oscillator frequency is
set by CT and a resistor RT, connected between pin RT and GND. The CT discharge current is
approximately 40 x the bias current through the resistor connected to RT. A practical maximum value for
the discharge current is 20 mA. The frequency of the oscillator is given by equation(1)
18
20
A resistor to GND programs the overlap time of the PUSH and PULL outputs of the UC3827-1 and the
DELAY
GND
20
11
21
22
12
25
I
-
-
dead time of the PUSH and PULL outputs of the UC3827-2. The minimum value of the resistor, RDELAY,
is 18 kΩ. The delay or overlap time is given by equation(2)
Ground reference for all sensitive setup components not related to driving the outputs. They include all
timing, voltage sense, current sense, and bypass components.
Ground connection for the PUSH and PULL outputs. PGND must be connected to GND at a single point
on the printed circuit board. This is imperative to prevent large, high frequency switching currents
flowing through the ground metalization inside the device.
PGND
Ground referenced output to drive an N-channel MOSFET. The PULL and the PUSH outputs are driving
the two switches of the push-pull converter with complementary signals at close to a 50% duty cycle.
Any undervoltage faults will disable PULL to an off condition (low).
PULL
22
24
26
28
O
O
Ground referenced output to drive an N-channel MOSFET. The PULL and the PUSH outputs are driving
the two switches of the push-pull converter with complementary signals at close to a 50% duty cycle.
Any undervoltage faults disables PUSH to an off condition (low).
PUSH
The RAMP voltage, after a 700 mV internal level shift, is fed to the noninverting input of the buck PWM
comparator. A resistor to VIN and a capacitor to GND provide an input voltage feedforward signal for the
buck controller in voltage mode control. In peak current mode control, the RAMP pin receives the
current signal of the buck converter. In an average current mode setup, the RAMP pin has a linearly
increasing ramp signal. This waveform may be generated either by connecting RAMP directly to CT, or
by connecting both a resistor from VCC to RAMP and a capacitor from RAMP to GND.
RAMP
5
6
I
The output of the +5V on board reference. Bypass this pin with a capacitor to GND. The reference is off
when the chip is in undervoltage lockout mode.o
REF
RT
15
17
16
19
O
I
A resistor to GND programs the charge current of the timing capacitor connected to CT. The charge
current approximately equals that shown in equation(3). The charge current should be less than 500 µA
to keep CT's discharge peak current less than 20 mA, which is CT's maximum practical discharge value.
The discharge time, which sets the maximum duty cycle, is set internally and is influenced by the charge
current.
The source connection for the floating buck switch. The voltage on the SRC pin can exceed VCC but
must be lower than 90 V–VVCC. Also, during turn-off transients of the buck switch, the voltage at SRC
can go to –2V.
SRC
3
4
I
0.77
fOSC
+
(Hz)
RRT CCT
(1)
(2)
RDELAY
tDELAY
+
10*9 (s)
200W
2.5 V
RRT
IRT
+
(3)
4
UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2
www.ti.com
SLUS365A–APRIL 1999–REVISED AUGUST 2005
Terminal Functions (continued)
TERMINAL
N or
I/O
DESCRIPTION
NAME
Q
DW
5Soft-start pin requires a capacitor to GND. During soft-start the output of the voltage error amplifier is
clamped to the soft-start capacitor voltage which is slowly charged by an internal current source. In
UVLO, SS is held low.
SS
4
5
O
A bidirectional pin for the oscillator., used to synchronize several chips to the fastest oscillator. Its input
synchronization threshold is 1.4 V. The SYNC voltage is 3.6 V when the oscillator capacitor, CT, is
discharged. Otherwise it is 0 V. If the recommended synchronization circuit is not used, a 1 kΩ or lower
value resistor from SYNC to GND may be needed to increase the fall time of the signal at SYNC.
SYNC
VCC
19
23
21
27
I
I
A voltage source connected to this pin supplies the power for the UC3827. It is recommended to bypass
this pin to both GND and PGND ground connections with good quality high frequency capacitors
VEA+
VEA-
VEAO
14
16
10
15
18
11
I
I
Non-inverting input of the voltage error amplifier
Inverting input of the voltage error amplifier
Output of the voltage error amplifier
O
Supply voltage for the buck output. The floating driver of the UC3827 uses the bootstrap technique
which requires a reservoir capacitor to store the required energy for the on time of the buck switch. A
diode must be connected from VCC to V+ to charge the reservoir capacitor. This diode must be able to
withstand VIN. The reservoir capacitor must be connected between V+ and SRC.
V+
1
1
I
ELECTRICAL CHARACTERISTICS
Unless otherwise spsecified, VVCC = 15 V, VV+ = 14.3 V, CCT = 340 pF, RRT = 10 kΩ, RDELAY = 24.3 kΩ, VSRC = VGND = VBUCK
=
VPUSH = VPULL outputs no load, TJ = TA
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VCC UVLO, Turn-on
8.3
0.9
8.8
1.2
9.5
1.5
1000
45
V
Hysteresis
V
IVCC
IVCC
Supply current start
Supply current run
IV+ buck high
VVCC = 8 V
µA
mA
mA
32
1
0.2
2
VOLTAGE ERROR AMPLIFIER
IB
0.5
3
µA
mV
dB
MHz
V
VIO
10
AVOL
80
1
95
4
GBW(1)
VOL
Gain bandwidth
Low-level output voltage
High-level output voltage
IVEAO = 0 µA (No load)
IVEAO = 0 µA (No load)
0.3
3
0.5
VOH
2.85
3.20
V
CURRENT SENSE AMPLIFIER
IB
–1
–5
5
µA
mV
dB
MHz
V
VIO
AVOL
80
15
110
29
(1)
GBW
VOL
Gain bandwidth
Low-level output voltage
High-level output voltage
Common mode range(1)
ICEAO = 0 µA (No load)
ICEAO = 0 µA (No load)
0.25
3.3
0.5
2
VOH
3
V
CMRR
-0.3
V
CURRENT ERROR AMPLIFIER
IB
–1
–5
10
µA
mV
dB
VIO
AVOL
80
110
(1) Ensured by design. Not production tested.
5
UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2
www.ti.com
SLUS365A–APRIL 1999–REVISED AUGUST 2005
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise spsecified, VVCC = 15 V, VV+ = 14.3 V, CCT = 340 pF, RRT = 10 kΩ, RDELAY = 24.3 kΩ, VSRC = VGND = VBUCK
=
VPUSH = VPULL outputs no load, TJ = TA
PARAMETER
Gain bandwidth
TEST CONDITIONS
At 100 kHz, Measure Gain
ICEAO = 0 µA (No Load)
ICEAO = 0 µA (No Load)
MIN
TYP
4.5
MAX
0.5
5
UNIT
MHz
V
GBW(1)
VOL
2
0.25
3.5
VOH
3.3
V
CMRR
Common mode range(1)
-0.3
V
OSCILLATOR SECTION
fOSC
Frequency
180
5
220
250
kHz
mA
ICT(dsch)
CT discharge current
3.5V at CT when CT removed
PWM COMPARATOR
DMAX
DMAX
Minimum duty cycle
Maximum duty cycle
200 kHz
200 kHz
0%
85%
91%
95%
BUCK OUTPUT STAGE
tRISE
tFALL
Rise time
Fall tIme
1 nF Load(2)
40
30
1.5
2
100
80
ns
ns
V
1 nF, Load
IBUCK = –15 mA , V+ –BUCK(3)
IBUCK = –150 mA, V+ –BUCK
IBUCK = 15 mA(4)
2.5
2.5
0.4
1.2
VOH
High-level output voltage
Low-level output voltage
(3)
V
0.2
0.7
V
VOL
(4)
IBUCK = 150 mA
V
PUSH/PULL OUTPUT STAGES
tRISE
tFALL
Rise time
1 nF load
1 nF load
UCx827-1 1 nF loads(5)
50
35
100
100
400
500
ns
ns
ns
ns
Fall tIme
Overlap time
Nonoverlapping time
100
100
250
250
(6)
UCx827-2
IPUSH/PULL = –10 mA, VCC – PUSH
2
3
3
V
V
(7)
VOH
High-level output voltage
Low-level output voltage
IPUSH/PULL = –100 mA, VCC –
PUSH(7)
2.5
IPUSH/PULL = 10 mA(7)
IPUSH/PULL = 100 mA(7)
0.2
0.6
0.8
1.2
V
V
VOL
REFERENCE
Reference voltage
Shor-circuit current
Line regulation
4.8
5
–50
5
5.2
–65
20
V
ISC
VREF = 0V
–35
mA
mV
mV
0.5V < VVCC < 20 V
0 mA < IIO < 10 mA
Load regulation
8
20
SOFT START
VOL
ISS
Low-level output voltage saturation
Soft-start current
VVCC = 7 V
250
–12
500
–25
mV
µA
–5
(2) Measure the rise time from when BUCK crosses 1 V until it crosses 9 V.
(3) To force BUCK high, force VCSAO=2.5 V, VCEAO = 2.5 V, a 25-kΩ pulldown resistor from RAMP to ground, and VCT = 0.5 V.
(4) To force BUCK low, force VCSAO = 2.5 V, VCEAO = 2.5 V, a 10-kΩ pulldown resistor from RAMP to ground, and VCT = 3.5 V.
(5) The overlap time is measured from the point at which the rising edge of PUSH/PULL crosses 5 V until the falling edge of PULL/PUSH
crosses 5V.
(6) The non-overlap time is measured from the point at which the falling edge of PUSH/PULL crosses 5 V until the rising edge of
PULL/PUSH crosses 5 V.
(7) To toggle PUSH or PULL into a desired state, pulse CT from 0.5 V to 3.5 V. PUSH and PULL toggle on the rising edge of CT.
6
UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2
www.ti.com
SLUS365A–APRIL 1999–REVISED AUGUST 2005
APPLICATION INFORMATION
V
REF
OSCILLATOR
–
+
2.5 V
V
REF
RT
CT
1.4 V
2.5 V
R
T
S
R
SYNC
2.9 V
0.5 V
C
T
10 kW
VDG−99086
Figure 1. Oscillator Block With External Connections
CIRCUIT BLOCK DESCRIPTION
PWM Oscillator
The oscillator block diagram with external connections is shown in Equation 1. A resistor (RT) connected to pin
RT sets the linear charge current:
2.5 V
I
+
RT
R
RT
(1)
The timing capacitor (CCT) is linearly charged with the charge current forcing the OSC pin to charge to a 3.4 V
threshold. After exceeding this threshold, the RS flip-flop is set driving CLKSYN high and RDEAD low which
discharges CCT. CT continues to discharge until it reaches a 0.5 V threshold and resets the RS flip-flop which
repeats the charging sequence as shown in Figure 2
As shown in Figure 3, several oscillators are synchronized to the highest free running frequency by connecting
100 pF capacitors in series with each CLKSYN pin and connecting the other side of the capacitors together
forming the CLKSYN bus. The CLKSYN bus is then pulled down to ground with a resistance of approximately
10k. Referring to Figure 1, the synchronization threshold is 1.4 V. The oscillator blanks any synchronization pulse
that occurs when OSC is below 2.5 V. This allows units, once they discharge below 2.5 V, to continue through
the current discharge and subsequent charge cycles whether or not other units on the CLKSYN bus are still
synchronizing. This requires the frequency of all free running oscillators to be within 17% of each other to assure
synchronization.
7
UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2
www.ti.com
SLUS365A–APRIL 1999–REVISED AUGUST 2005
APPLICATION INFORMATION (continued)
VAO Current
Command
Charging
Discharging
OSC
2.9 V
0.5 V
3.6 V
THRESHOLD
1.4 V Threshold
CLKSYN
8.5 V
0 V
OUT
VDG−99087
Figure 2. Oscillator and PWM Output Waveform
100 pF
SYNC
OSC1
100 pF
SYNC
OSC2
100 pF
SYNC
OSC3
100 pF
SYNC
OSC10
10 kW
VDG−99085
Figure 3. Oscillator Synchronization Connection Diagram
REVISION HISTORY
REVISION
DATE OF CHANGE
DESCRIPTION
Improved CMRR of CSA from ( 0 - 2 V) to ( -0.3 - 2 V)
Improved CMRR of CEA from ( 0 - 5 V) to ( -0.3 - 5 V)
SLUS365A
8/2005
8
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
UC1827J-1
UC1827L-1
OBSOLETE
CDIP
J
L
24
20
24
TBD
TBD
Call TI
Call TI
Call TI
Call TI
OBSOLETE TO/SOT
UC2827DW-1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
DW
25 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
UC2827DW-2
UC2827DW-2G4
UC2827DWTR-1
DW
DW
DW
24
24
24
25 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
UC2827DWTR-2
UC2827N-1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
PDIP
PDIP
SOIC
DW
N
24
24
24
24
2000
15
TBD
TBD
TBD
CU NIPDAU Level-3-235C-168 HR
Call TI
Call TI
Level-NA-NA-NA
Level-NA-NA-NA
UC2827N-2
N
15
UC3827DW-1
DW
25 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
UC3827DW-1G4
UC3827DW-2
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
DW
DW
24
24
24
24
24
24
25 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
UC3827DWTR-1
UC3827DWTR-1G4
UC3827DWTR-2
UC3827DWTR-2G4
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
UC3827N-1
UC3827N-2
ACTIVE
ACTIVE
PDIP
PDIP
N
N
24
24
15
15
TBD
TBD
Call TI
Call TI
Level-NA-NA-NA
Level-NA-NA-NA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MCDI004A – JANUARY 1995 – REVISED NOVEMBER 1997
J (R-GDIP-T**)
CERAMIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
B
13
24
C
12
1
0.065 (1,65)
0.045 (1,14)
Lens Protrusion (Lens Optional)
0.010 (0.25) MAX
0.090 (2,29)
0.060 (1,53)
0.175 (4,45)
0.140 (3,56)
A
Seating Plane
0.018 (0,46) MIN
0.125 (3,18) MIN
0.022 (0,56)
0.014 (0,36)
0.100 (2,54)
0.012 (0,30)
0.008 (0,20)
24
28
32
40
PINS **
DIM
”A”
NARR
WIDE
NARR
WIDE
NARR
WIDE
NARR
WIDE
0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85)
0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99)
1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53)
1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61)
0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19)
0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)
MAX
MIN
MAX
MIN
”B”
”C”
MAX
MIN
4040084/C 10/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Window (lens) added to this group of packages (24-, 28-, 32-, 40-pin).
D. This package can be hermetically sealed with a ceramic lid using glass frit.
E. Index point is provided on cap for terminal identification.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI006B – SEPTEMBER 2001 – REVISED APRIL 2002
N (R–PDIP–T24)
PLASTIC DUAL–IN–LINE
1.222 (31,04) MAX
24
13
0.360 (9,14) MAX
1
12
0.070 (1,78) MAX
0.200 (5,08) MAX
0.020 (0,51) MIN
0.425 (10,80) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
0’–15’
0.021 (0,53)
0.015 (0,38)
0.010 (0,25) NOM
4040051–3/D 09/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS–010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI008 – OCTOBER 1994
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PIN SHOWN
A
24
13
0.560 (14,22)
0.520 (13,21)
1
12
0.060 (1,52) TYP
0.200 (5,08) MAX
0.020 (0,51) MIN
0.610 (15,49)
0.590 (14,99)
Seating Plane
0.100 (2,54)
0.125 (3,18) MIN
0.010 (0,25) NOM
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
PINS **
M
24
28
32
40
48
52
DIM
1.270
1.450
1.650
2.090
2.450
2.650
A MAX
(32,26) (36,83) (41,91) (53,09) (62,23) (67,31)
1.230
1.410
1.610
2.040
2.390
2.590
A MIN
(31,24) (35,81) (40,89) (51,82) (60,71) (65,79)
4040053/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-011
D. Falls within JEDEC MS-015 (32 pin only)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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