UC1842A-SP [TI]
QML CLASS V, CURRENT-MODE PWM CONTROLLERS; QML V类，电流模式PWM控制器
| 型号： | UC1842A-SP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QML CLASS V, CURRENT-MODE PWM CONTROLLERS |
| 文件： | 总15页 (文件大小：650K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP
www.ti.com ........................................................................................................................................................ SLUS872A–JANUARY 2009–REVISED MAY 2009
QML CLASS V, CURRENT-MODE PWM CONTROLLERS
1
FEATURES
JG PACKAGE
(TOP VIEW)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
QML-V Qualified, SMD 5962-86704
(1) (2)
Rad-Tolerant: 30 kRad (Si) TID
1
2
3
4
8
7
6
5
Comp
VFB
VREF
Optimized for Offline and DC-to-DC Converters
Low Start-Up Current (<0.5 mA)
Trimmed Oscillator Discharge Current
Automatic Feed Forward Compensation
Pulse-by-Pulse Current Limiting
Enhanced Load Response Characteristics
Undervoltage Lockout With Hysteresis
Double-Pulse Suppression
VCC
ISENSE
RT/CT
Output
Gnd
FK PACKAGE
(TOP VIEW)
3
2
1 20 19
18
High-Current Totem-Pole Output
Internally Trimmed Bandgap Reference
500-kHz Operation
N/C
VCC
VC
4
5
6
7
8
VFB
17
16
15
14
N/C
N/C
ISENSE
!Ƶ?!
Output
Low RO Error Amplifier
N/C
N/C
9 10
13
11 12
(1) Radiation tolerance is a typical value based upon initial device
qualification with dose rate = 10 mrad/sec. Radiation Lot
Acceptance Testing is available - contact factory for details.
(2) 5962-8670409VPA currently offered. Contact factory for
additional devices.
DESCRIPTION
The UC1842A/3A/4A/5A family of control IC's is a pin for pin compatible improved version of the UC1842/3/4/5
family.Providing the necessary features to control current-mode switched-mode power supplies, this device has
the following improved features. Start up current is guaranteed to be less than 0.5 mA. Oscillator discharge is
trimmed to 8.3 mA. During undervoltage lockout, the output stage can sink at least 10 mA at less than 1.2 V for
VCC over 5 V.
The difference between members of this family are shown in Table 1.
Table 1. UC184xA Family
MAXIMUM DUTY
PART NO.
UVLO ON
UVLO OFF
CYCLE
< 100%
< 100%
< 50%
UC1842A
UC1843A
UC1844A
UC1845A
16.0 V
8.5 V
10.0 V
7.9 V
16.0 V
8.5 V
10.0 V
7.9 V
< 50%
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP
SLUS872A–JANUARY 2009–REVISED MAY 2009........................................................................................................................................................ www.ti.com
BLOCK DIAGRAM
7
8
5
7
4
6
5
2
1
3
ORDERING INFORMATION(1)
PARENT
PACKAGE(2)
JG (8-CDIP)
FK (20-LCCC)
JG (8-CDIP)
FK (20-LCCC)
JG (8-CDIP)
FK (20-LCCC)
JG (8-CDIP)
FK (20-LCCC)
ORDERABLE PART NUMBER
5962-8670405VPA
5962-8670405VXA
5962-8670406VPA
5962-8670406VXA
5962-8670407VPA
5962-8670407VXA
5962-8670408VPA
5962-8670408VXA
TA
TOP-SIDE MARKING
8670405VPA/UC1842A
UC1842A
–55°C to 125°C
5962-8670405VXA/UC1842ALQMLV
8670406VPA/UC1843A
UC1843A
UC1844A
UC1845A
–55°C to 125°C
–55°C to 125°C
–55°C to 125°C
5962-8670406VXA/UC1843ALQMLV
8670407VPA/UC1844A
5962-8670407VXA/UC1844ALQMLV
8670408VPA/UC1845A
5962-8670408VXA/UC1845ALQMLV
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ORDERING INFORMATION (RADIATION IMPROVED DEVICES)(1)(2)
PARENT
PACKAGE(3)
ORDERABLE PART NUMBER
TA
TOP-SIDE MARKING
UC1843A
JG (8-CDIP)
5962-8670409VPA
–55°C to 125°C
8670409VPA/UC1843A-SP
(1) See Electrical Characteristics (Radiation Improved Devices).
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(3) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
2
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Product Folder Link(s): UC1842A-SP UC1843A-SP UC1844A-SP UC1845A-SP
UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP
www.ti.com ........................................................................................................................................................ SLUS872A–JANUARY 2009–REVISED MAY 2009
ABSOLUTE MAXIMUM RATINGS(1)(2)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage, low-impedance source
Supply current
30 V
Self limiting
±1 A
IO
Output current
Output energy (capacitive load)
5 µJ
VI
Input voltage (VFB, ISENSE
)
–0.3 V to 6.3 V
10 mA
Error amplifier output sink current
Power dissipation (TA = 25°C)
PD
1 W
Tstg
Tlead
Storage temperature range
–65°C to 150°C
300°C
Lead temperature (soldering, 10 seconds)
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground. Currents are positive into, negative out of the specified terminal.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (TA = TJ = –55°C to 125°C), unless otherwise noted.
MIN
12
0
MAX
25
UNIT
V
VCC
Supply voltage
Sink/source output current (continuous or time average)
Reference load current
200
20
mA
mA
0
ELECTRICAL CHARACTERISTICS
VCC = 15 V(1), RT = 10 kΩ, CT = 3.3 nF, TA = TJ = –55°C to 125°C (unless otherwise noted)
PARAMETER
Reference Section
TEST CONDITIONS
MIN
TYP
MAX UNIT
Output voltage
Line regulation
TJ = 25°C, IO = 1 mA
4.95
5
6
5.06
20
V
VIN = 12 V to 25 V
IO = 1 mA to 20 mA
mV
mV
Load regulation
6
25
Temperature stability(2)(3)
Total output variation
Output noise voltage
Long term stability
Short-circuit output current
Oscillator Section
Initial accuracy
0.2
0.4 mV/°C
Over line, load, and temperature
10 Hz ≤ f ≤ 10 kHz, TJ = 25°C
1000 hours, TA = 125°C(2)
4.9
5.1
V
50
5
µV
mV
mA
25
–30
47
–100
–180
TJ = 25°C(4)
52
0.2
5
57
1
kHz
%
Voltage stability
VCC = 12 V to 25 V
TA = MIN to MAX(2)
V pin 4(2)
Temperature stability
Amplitude peak-to-peak
%
1.7
8.3
V
TJ = 25°C
7.8
7.5
8.8
8.8
Discharge current
V pin 4 = 2 V(5)
mA
TJ = Full range
(1) Adjust VCC above the start threshold before setting at 15 V.
(2) Parameters ensured by design and/or characterization, if not production tested.
(3) Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:
Temp Stability = VREF (max) - VREF (min)/TJ (max) - TJ (min). VREF (max) and VREF (min) are the maximum and minimum reference
voltage measured over the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in
temperature.
(4) Output frequency equals ocscillator frequency for the UC1842A and UC1843A. Output frequency is one half oscillator frequency for
UC18444A and UC1845A.
(5) This parameter is measured with RT = 10 kΩ to VREF. This contributes approximately 300 µA of current to the measurement. The total
current flowing into the RT/CT pin will be approximately 300 µA higher than the measured value.
Copyright © 2009, Texas Instruments Incorporated
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Product Folder Link(s): UC1842A-SP UC1843A-SP UC1844A-SP UC1845A-SP
UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP
SLUS872A–JANUARY 2009–REVISED MAY 2009........................................................................................................................................................ www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
VCC = 15 V, RT = 10 kΩ, CT = 3.3 nF, TA = TJ = –55°C to 125°C (unless otherwise noted)
PARAMETER
Error Amp Section
TEST CONDITIONS
MIN
TYP
MAX UNIT
Input voltage
Input bias current
Open-loop voltage gain
Unity-gain bandwidth
PSRR
VComp = 2.5 V
2.45
2.50
–0.3
90
2.55
–1
mV
µA
dB
MHz
dB
mA
mA
V
VO = 2 V to 4 V
TJ = 25°C(6)
65
0.7
60
1
VCC = 12 V to 25 V
70
Output sink current
Output source current
High-level output voltage
Low-level output voltage
Current Sense Section
Gain(7)(8)
VFB = 2.7 V, VComp = 1.1 V
VFB = 2.3 V, VComp = 5 V
2
6
–0.5
5
–0.8
6
VFB = 2.3 V, RL = 15 kΩ to ground
VFB = 2.7 V, RL = 15 kΩ to VREF
0.7
1.1
V
2.85
0.9
3
1
3.15
1.1
V/V
V
Maximum input signal
PSRR
VComp = 5 V(7)
VCC = 12 V to 25 V(7)
70
–2
dB
µA
ns
Input bias current
Delay to output
–10
300
(6)
VISENSE = 0 to 2 V
150
Output Section
ISINK = 20 mA
0.1
1.5
0.4
2.2
V
V
Output low-level voltage
Output high-level voltage
ISINK = 200 mA
ISOURCE = –20 mA
ISOURCE = –200 mA
CL = 1 nF, TJ = 25°C(6)
CL = 1 nF, TJ = 25°C(6)
VCC = 5 V, ISINK = 10 mA
13
12
13.5
13.5
50
V
V
Rise time
150
150
1.2
ns
ns
V
Fall time
50
UVLO saturation
Undervoltage Lockout Section
0.7
UC1842A, UC1844A
UC1843A, UC1845A
UC1842A, UC1844A
UC1843A, UC1845A
15
7.8
9
16
8.4
10
17
9
Start threshold
V
V
11
8.2
Minimum operation voltage after turn-on
PWM Section
7
7.6
UC1842A, UC1843A
UC1844A, UC1845A
94
47
96
48
100
50
0
Maximum duty cycle
%
%
Minimum duty cycle
Total Standby Current
Start-up current
0.3
11
34
0.5
17
mA
mA
V
Operating supply current
VCC zener voltage
VFB = VISENSE = 0 V
ICC = 25 mA
30
(6) Parameters ensured by design and/or characterization, if not production tested.
(7) Parameter measured at trip point of latch with VFB = 0 V.
(8) Gain defined as: G = ΔVComp/ΔVISENSE; VISENSE = 0 to 0.8 V.
4
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Product Folder Link(s): UC1842A-SP UC1843A-SP UC1844A-SP UC1845A-SP
UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP
www.ti.com ........................................................................................................................................................ SLUS872A–JANUARY 2009–REVISED MAY 2009
ELECTRICAL CHARACTERISTICS (RADIATION IMPROVED DEVICES)(1)
VCC = 15 V, RT = 10 kΩ, CT = 3.3 nF, TA = TJ = –55°C to 125°C (unless otherwise noted)
PARAMETER
Reference Section
TEST CONDITIONS
MIN
TYP
MAX UNIT
Output voltage
Line regulation
TJ = 25°C, IO = 1 mA
4.94
5
6
6
5.06
20
V
VCC = 12 V to 25 V
mV
mV
V
Load regulation
IL = 1 mA to 20 mA
25
Total output variation
Output noise voltage
Short-circuit output current
Oscillator Section
Initial accuracy
Over line, load, and temperature
10 Hz ≤ f ≤ 10 kHz, TJ = 25°C
4.9
–30
47
5.1
50
µV
mA
–100
–180
TJ = 25°C
52
0.2
5
57 kHz
Voltage stability
VCC = 12 V to 25 V
TJ = -55°C to 125°C
VRT/CT peak to peak
TJ = 25°C, VRT/CT = 2 V
VRT/CT = 2 V
1
%
%
V
Temperature stability
Amplitude
1.7
8.3
7.8
7.5
8.8
8.8
Discharge current(2)
mA
Error Amp Section
Input voltage
VComp = 2.5 V
2.45
2.50
–0.3
90
2.55
–1
mV
µA
dB
MHz
dB
mA
mA
V
Input bias current
Open-loop voltage gain
Unity-gain bandwidth
PSRR
VO = 2 V to 4 V
TJ = 25°C(3)
65
0.7
60
1
VCC = 12 V to 25 V
70
Output sink current
Output source current
High-level output voltage
Low-level output voltage
Current Sense Section
Gain(4)(5)
VFB = 2.7 V, VComp = 1.1 V
VFB = 2.3 V, VComp = 5 V
VFB = 2.3 V, RL = 15 kΩ to ground
VFB = 2.7 V, RL = 15 kΩ to VREF
2
6
–0.5
5
–0.8
6
0.7
1.1
V
2.85
0.9
3
1
3.15 V/V
Maximum input signal
PSRR
VComp = 5 V(4)
VCC = 12 V to 25 V(4)
1.1
V
70
–2
dB
µA
ns
Input bias current
Delay to output
–10
300
(3)
VISENSE = 0 to 2 V
150
Output Section
ISINK = 20 mA
0.1
1.5
0.4
2.2
V
V
Output low-level voltage
Output high-level voltage
ISINK = 200 mA
ISOURCE = 20 mA
13
12
13.5
13.0
50
V
ISOURCE = 200 mA
CL = 1 nF, TJ = 25°C(3)
CL = 1 nF, TJ = 25°C(3)
VCC = 5 V, ISINK = 10 mA
V
Rise time
150
150
1.2
ns
ns
V
Fall time
50
UVLO saturation
0.7
Undervoltage Lockout Section
Start threshold
7.8
7
8.4
7.6
9
V
V
Minimum operation voltage after turn-on
PWM Section
8.2
(1) See Ordering Information (Radiation Improved Devices).
(2) This parameter is measured with RT = 10 kΩ to VREF. This contributes approximately 300 µA of current to the measurement. The total
current flowing into the RT/CT pin will be approximately 300 µA higher than the measured value.
(3) Parameters ensured by design and/or characterization, if not production tested.
(4) Parameter measured at trip point of latch with VFB = 0 V.
(5) Gain defined as: G = ΔVComp/ΔVISENSE; VISENSE = 0 to 0.8 V.
Copyright © 2009, Texas Instruments Incorporated
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Product Folder Link(s): UC1842A-SP UC1843A-SP UC1844A-SP UC1845A-SP
UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP
SLUS872A–JANUARY 2009–REVISED MAY 2009........................................................................................................................................................ www.ti.com
ELECTRICAL CHARACTERISTICS (RADIATION IMPROVED DEVICES) (continued)
VCC = 15 V, RT = 10 kΩ, CT = 3.3 nF, TA = TJ = –55°C to 125°C (unless otherwise noted)
PARAMETER
Maximum duty cycle
TEST CONDITIONS
MIN
TYP
MAX UNIT
94
96
100
0
%
%
Minimum duty cycle
Total Standby Current
Start-up current
0.3
11
34
0.5
17
mA
mA
V
Operating supply current
VCC zener voltage
VFB = VISENSE = 0 V
ICC = 25 mA
30
6
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Product Folder Link(s): UC1842A-SP UC1843A-SP UC1844A-SP UC1845A-SP
UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP
www.ti.com ........................................................................................................................................................ SLUS872A–JANUARY 2009–REVISED MAY 2009
APPLICATION INFORMATION
Amp can Source and Sink up to 0.5mA, and Sink up to 2mA.
Figure 1. Error Amplifier Configuration
During UVLO, the Output is low.
Figure 2. Undervoltage Lockout
Peak Current (IS) is Determined By The Formula
1.0V
ISMAX ′
RS
A small RC filter may be required to suppress switch transients.
Figure 3. Current-Sense Circuit
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Product Folder Link(s): UC1842A-SP UC1843A-SP UC1844A-SP UC1845A-SP
UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP
SLUS872A–JANUARY 2009–REVISED MAY 2009........................................................................................................................................................ www.ti.com
Figure 4. Output Saturation Characteristics
Figure 5. Error Amplifier Open-Loop Frequency Response
Oscillator Frequency vs Timing Resistance
Maximum Duty Cycle vs Timing Resistor
Figure 6. Oscillation Section
8
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Product Folder Link(s): UC1842A-SP UC1843A-SP UC1844A-SP UC1845A-SP
UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP
www.ti.com ........................................................................................................................................................ SLUS872A–JANUARY 2009–REVISED MAY 2009
High peak currents associated with capacitive loads necessi-
tate careful grounding techniques. Timing and bypass capaci-
tors should be connected close to pin 5 in a single point
ground. The transistor and 5k potentiometer are used to sam-
ple the oscillator waveform and apply an adjustable ramp to
pin 3.
Figure 7. Open-Loop Laboratory Test Fixture
A fraction of the oscillator ramp can be resistively
summed with the current sense signal to provide slope
compensation for converters requiring duty cycles over
50%.
Note that capacitor, C, forms a filter with R2 to suppress
the leading edge switch spikes.
Figure 8. Slope Compensation
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Product Folder Link(s): UC1842A-SP UC1843A-SP UC1844A-SP UC1845A-SP
UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP
SLUS872A–JANUARY 2009–REVISED MAY 2009........................................................................................................................................................ www.ti.com
5. Output Voltage:
Power Supply Specifications
1. Input Voltage
A. +5V, 5%; 1A to 4A load
Ripple voltage: 50mV P-P Max
B. +12V, 3%; 0.1A to 0.3A load
Ripple voltage: 100mV P-P Max
C. -12V , 3%; 0.1A to 0.3A load
Ripple voltage: 100mV P-P Max
95VAC to 130VA
(50 Hz/60Hz)
3750V
40kHz
70%
2. Line Isolation
3. Switching Frequency
4. Efficiency
Full Load
Figure 9. Offline Flyback Regulator
10
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Product Folder Link(s): UC1842A-SP UC1843A-SP UC1844A-SP UC1845A-SP
PACKAGE OPTION ADDENDUM
www.ti.com
9-May-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
5962-8670405VPA
5962-8670405VXA
5962-8670406VPA
5962-8670406VXA
5962-8670407VPA
5962-8670407VXA
5962-8670408VPA
5962-8670408VXA
5962-8670409VPA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
LCCC
CDIP
LCCC
CDIP
LCCC
CDIP
LCCC
CDIP
JG
FK
JG
FK
JG
FK
JG
FK
JG
8
20
8
1
1
1
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
A42
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
A42 N / A for Pkg Type
POST-PLATE N / A for Pkg Type
A42 N / A for Pkg Type
POST-PLATE N / A for Pkg Type
A42 N / A for Pkg Type
POST-PLATE N / A for Pkg Type
A42 N / A for Pkg Type
20
8
20
8
20
8
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-May-2012
OTHER QUALIFIED VERSIONS OF UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP :
Catalog: UC1842A, UC1843A, UC1844A, UC1845A
•
Enhanced Product: UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
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