UC2825Q [TI]
High Speed PWM Controller; 高速PWM控制器
| 型号： | UC2825Q |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed PWM Controller |
| 文件： | 总19页 (文件大小：968K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
application
INFO
UC1825
UC2825
UC3825
available
High Speed PWM Controller
FEATURES
DESCRIPTION
•
Compatible with Voltage or Current Mode The UC1825 family of PWM control ICs is optimized for high fre-
Topologies
quency switched mode power supply applications. Particular care
was given to minimizing propagation delays through the comparators
and logic circuitry while maximizing bandwidth and slew rate of the
error amplifier. This controller is designed for use in either cur-
rent-mode or voltage mode systems with the capability for input volt-
age feed-forward.
•
Practical Operation Switching Frequencies
to 1MHz
•
•
50ns Propagation Delay to Output
High Current Dual Totem Pole Outputs
(1.5A Peak)
Protection circuitry includes a current limit comparator with a 1V
threshold, a TTL compatible shutdown port, and a soft start pin
which will double as a maximum duty cycle clamp. The logic is fully
latched to provide jitter free operation and prohibit multiple pulses at
an output. An under-voltage lockout section with 800mV of hysteresis
assures low start up current. During under-voltage lockout, the out-
puts are high impedance.
•
•
Wide Bandwidth Error Amplifier
Fully Latched Logic with Double Pulse
Suppression
•
•
•
•
Pulse-by-Pulse Current Limiting
Soft Start / Max. Duty Cycle Control
Under-Voltage Lockout with Hysteresis
Low Start Up Current (1.1mA)
These devices feature totem pole outputs designed to source and
sink high peak currents from capacitive loads, such as the gate of a
power MOSFET. The on state is designed as a high level.
BLOCK DIAGRAM
UDG-92030-2
SLUS235A - MARCH 1997 - REVISED MARCH 2004
UC1825
UC2825
UC3825
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (Pins 13, 15). . . . . . . . . . . . . . . . . . . . . . . . 30V
Output Current, Source or Sink (Pins 11, 14)
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A
Pulse (0.5ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0A
Analog Inputs
CONNECTION DIAGRAMS
DIL-16 (Top View)
J or N Package
(Pins 1, 2, 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
(Pin 8, 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
Clock Output Current (Pin 4). . . . . . . . . . . . . . . . . . . . . . . -5mA
Error Amplifier Output Current (Pin 3) . . . . . . . . . . . . . . . . 5mA
Soft Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . . 20mA
Oscillator Charging Current (Pin 5) . . . . . . . . . . . . . . . . . . -5mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Storage Temperature Range. . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . 300°C
PACKAGE PIN FUNCTION
FUNCTION
N/C
INV
NI
PIN
PLCC-20 & LCC-20
(Top View)
Q & L Packages
1
2
3
SOIC-16 (Top View)
DW Package
E/A Out
Clock
N/C
4
5
6
RT
7
CT
8
Ramp
Soft Start
N/C
ILIM/SD
Gnd
Out A
Pwr Gnd
N/C
9
10
11
12
13
14
15
16
17
18
19
20
VC
Out B
VCC
VREF 5.1V
THERMAL RATINGS TABLE
Package
DIL-16J
DIL-16N
PLCC-20
LCC-20
QJA
80-120
90(1)
QJC
28(2)
45
43-75(1)
70-80
50-120(1)
34
20(2)
SOIC-16
35
Q
Q
2
UC1825
UC2825
UC3825
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for , RT = 3.65k, CT = 1nF, VCC
= 15V, -55°C<TA<125°C for the UC1825, –40°C<TA<85°C for the UC2825, and 0°C<TA<70°C for the UC3825, TA=TO.
UC1825
UC3825
PARAMETERS
TEST CONDITIONS
UC2825
MIN
TOP MAX
MIN
TOP MAX UNITS
Reference Section
Output Voltage
TO = 25°C, IO = 1mA
5.05
5.10
2
5.15
20
5.00
5.10
2
5.20
20
V
Line Regulation
10V < VCC < 30V
1mA < IO < 10mA
TMIN < TA < TMAX
Line, Load, Temperature
10Hz < f < 10kHz
TJ = 125°C, 1000hrs.
VREF = 0V
mV
mV
Load Regulation
5
20
5
20
Temperature Stability*
Total Output Variation*
Output Noise Voltage*
Long Term Stability*
Short Circuit Current
Oscillator Section
Initial Accuracy*
0.2
0.4
0.2
0.4 mV/°C
5.00
5.20
4.95
5.25
V
50
5
50
5
µV
mV
mA
25
25
-15
-50
-100
-15
-50
-100
TJ = 2°C
360
400
0.2
5
440
2
360
400
0.2
5
440
2
kHz
%
Voltage Stability*
Temperature Stability*
Total Variation*
10V < VCC < 30V
TMIN < TA < TMAX
Line, Temperature
%
340
3.9
460
340
3.9
460
kHz
Oscillator Section (cont.)
Clock Out High
4.5
2.3
2.8
1.0
1.8
4.5
2.3
2.8
1.0
1.8
V
V
V
V
V
Clock Out Low
2.9
3.0
2.9
3.0
Ramp Peak*
2.6
0.7
1.6
2.6
0.7
1.6
Ramp Valley*
1.25
2.0
1.25
2.0
Ramp Valley to Peak*
Error Amplifier Section
Input Offset Voltage
Input Bias Current
Input Offset Current
Open Loop Gain
CMRR
10
3
15
3
mV
µA
µA
dB
0.6
0.1
95
0.6
0.1
95
1
1
1V < VO < 4V
1.5V < VCM < 5.5V
10V < VCC < 30V
VPIN 3 = 1V
60
75
85
1
60
75
85
1
95
95
dB
PSRR
110
2.5
-1.3
4.7
0 .5
5.5
12
110
2.5
-1.3
4.7
0.5
5.5
12
dB
Output Sink Current
Output Source Current
Output High Voltage
Output Low Voltage
Unity Gain Bandwidth*
Slew Rate*
mA
mA
V
VPIN 3 = 4V
-0.5
4.0
0
-0.5
4.0
0
IPIN 3 = -0.5mA
IPIN 3 = 1mA
5.0
1.0
5.0
1.0
V
3
3
MHz
V/µs
6
6
3
UC1825
UC2825
UC3825
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for , RT = 3.65k, CT = 1nF, VCC
= 15V, -55°C<TA<125°C for the UC1825, –40°C<TA<85°C for the UC2825, and 0°C<TA<70°C for the UC3825, TA=TJ.
UC1825
UC3825
PARAMETERS
TEST CONDITIONS
UC2825
MIN
TOP MAX
MIN
TOP MAX UNITS
PWM Comparator Section
Pin 7 Bias Current
Duty Cycle Range
Pin 3 Zero DC Threshold
Delay to Output*
VPIN 7 = 0V
-1
-5
-1
-5
µA
%
V
0
80
0
85
VPIN 7 = 0V
1.1
1.25
50
1.1
1.25
50
80
20
80
20
ns
Soft-Start Section
Charge Current
VPIN 8 = 0.5V
VPIN 8 = 1V
3
1
9
3
1
9
µA
Discharge Current
mA
Current Limit / Shutdown Section
Pin 9 Bias Current
Current Limit Threshold
Shutdown Threshold
Delay to Output
0 < VPIN 9 < 4V
15
1.1
1.55
80
10
1.1
1.55
80
µA
V
0.9
1.0
1.40
50
0.9
1.0
1.40
50
1.25
1.25
V
ns
Output Section
Output Low Level
IOUT = 20mA
IOUT = 200mA
IOUT = -20mA
IOUT = -200mA
VC = 30V
0.25
1.2
0.40
2.2
0.25
1.2
0.40
2.2
V
V
Output High Level
13.0
12.0
13.5
13.0
100
30
13.0
12.0
13.5
13.0
10
V
V
Collector Leakage
500
60
500
60
µA
ns
Rise/Fall Time*
CL = 1nF
30
Under-Voltage Lockout Section
Start Threshold
8.8
0.4
9.2
0.8
9.6
1.2
8.8
0.4
9.2
0.8
9.6
1.2
V
V
UVLO Hysteresis
Supply Current Section
Start Up Current
ICC
VCC = 8V
1.1
22
2.5
33
1.1
22
2.5
33
mA
mA
VPIN 1, VPIN 7, VPIN 9 = 0V; VPIN 2 = 1V
4
UC1825
UC2825
UC3825
Printed Circuit Board Layout Considerations
High speed circuits demand careful attention to layout
and component placement. To assure proper perfor-
mance of the UC1825 follow these rules: 1) Use a ground
plane. 2) Damp or clamp parasitic inductive kick energy
from the gate of driven MOSFETs. Do not allow the out-
put pins to ring below ground. A series gate resistor or a
shunt 1 Amp Schottky diode at the output pin will serve
this purpose. 3) Bypass VCC, VC, and VREF. Use 0.1µF
monolithic ceramic capacitors with low equivalent series
inductance. Allow less than 1 cm of total lead length for
each capacitor between the bypassed pin and the ground
plane. 4) Treat the timing capacitor, CT, like a bypass ca-
pacitor.
Error Amplifier Circuit
Simplified Schematic
Open Loop Frequency Response
Unity Gain Slew Rate
PWM Applications
Current-Mode
Conventional (Voltage Mode)
5
UC1825
UC2825
UC3825
Oscillator Circuit
Deadtime vs CT (3k RT 100k)
Deadtime vs Frequency
Timing Resistance vs Frequency
160
140
1.0nF
120
100
80
470pF
10k
100k
FREQ (Hz)
1M
Synchronized Operation
Two Units in Close Proximity
Generalized Synchronization
6
UC1825
UC2825
UC3825
Forward Technique for Off-Line Voltage Mode Application
Constant Volt-Second Clamp Circuit
The circuit shown here will achieve a constant
volt-second product clamp over varying input voltages.
The ramp generator components, RT and CR are cho-
sen so that the ramp at Pin 9 crosses the 1V threshold
at the same time the desired maximum volt-second
product is reached. The delay through the functional
nor block must be such that the ramp capacitor can be
completely discharged during the minimum deadtime.
Output Section
Simplified Schematic
Rise/Fall Time (CL=1nF)
Saturation Curves
Rise/Fall Time (CL=10nF)
7
UC1825
UC2825
UC3825
Open Loop Laboratory Test Fixture
UDG-92032-2
This test fixture is useful for exercising many of the As with any wideband circuit, careful grounding and by-
UC1825’s functions and measuring their specifications. pass procedures should be followed. The use of a
ground plane is highly recommended.
Design Example: 50W, 48V to 5V DC to DC Converter - 1.5MHz Clock Frequency
UDG-92033-3
8
PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-87681012A
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Call TI
-55 to 125
5962-
87681012A
UC1825L/
883B
5962-8768101EA
5962-8768101QFA
ACTIVE
ACTIVE
CDIP
CFP
J
16
16
1
1
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-55 to 125
-55 to 125
5962-8768101EA
UC1825J/883B
W
5962-8768101QF
A
UC1825W/883B
UC1825J
ACTIVE
ACTIVE
CDIP
CDIP
J
J
16
16
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
UC1825J
UC1825J883B
5962-8768101EA
UC1825J/883B
UC1825L
ACTIVE
ACTIVE
LCCC
LCCC
FK
FK
20
20
1
1
TBD
TBD
POST-PLATE
POST-PLATE
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
UC1825L
UC1825L883B
5962-
87681012A
UC1825L/
883B
UC1825W883B
ACTIVE
CFP
W
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8768101QF
A
UC1825W/883B
UC2825DW
UC2825DWG4
UC2825DWTR
UC2825DWTRG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
16
16
16
16
40
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
UC2825DW
UC2825DW
UC2825DW
UC2825DW
Green (RoHS
& no Sb/Br)
2000
2000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
UC2825J
UC2825N
ACTIVE
ACTIVE
CDIP
PDIP
J
16
16
1
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
-40 to 85
-40 to 85
UC2825J
UC2825N
N
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
UC2825NG4
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
UC2825N
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
UC2825Q
ACTIVE
PLCC
PLCC
FN
20
20
46
Green (RoHS
& no Sb/Br)
CU SN
CU SN
Level-2-260C-1 YEAR
UC2825Q
UC2825QG3
ACTIVE
FN
46
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
-40 to 85
UC2825Q
UC2825Q
UC2825QTR
OBSOLETE
ACTIVE
PLCC
PLCC
FN
FN
20
20
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
UC2825QTRG3
UC3825DW
UC3825DWG4
UC3825DWTR
UC3825DWTRG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
16
16
16
16
40
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
0 to 70
0 to 70
0 to 70
0 to 70
UC3825DW
UC3825DW
UC3825DW
UC3825DW
Green (RoHS
& no Sb/Br)
2000
2000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
UC3825J
UC3825N
ACTIVE
ACTIVE
CDIP
PDIP
J
16
16
1
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
0 to 70
0 to 70
UC3825J
UC3825N
N
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
UC3825NG4
UC3825Q
ACTIVE
ACTIVE
ACTIVE
PDIP
PLCC
PLCC
N
16
20
20
25
46
46
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU SN
N / A for Pkg Type
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
0 to 70
0 to 70
0 to 70
UC3825N
UC3825Q
UC3825Q
FN
FN
Green (RoHS
& no Sb/Br)
UC3825QG3
Green (RoHS
& no Sb/Br)
CU SN
UC3825QTR
ACTIVE
ACTIVE
PLCC
PLCC
FN
FN
20
20
1000
1000
TBD
Call TI
Call TI
Call TI
Call TI
0 to 70
0 to 70
UC3825Q
UC3825Q
UC3825QTRG3
TBD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2013
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1825, UC2825, UC2825M, UC3825, UC3825M :
Catalog: UC3825, UC2825, UC3825M, UC3825
•
Military: UC2825M, UC1825
•
Space: UC1825-SP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
Addendum-Page 3
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
1
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Copyright © 2013, Texas Instruments Incorporated
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