UC2844AQDR [TI]
Current Mode PWM Controller; 电流模式PWM控制器
| 型号： | UC2844AQDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Current Mode PWM Controller |
| 文件： | 总7页 (文件大小：519K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1842A/3A/4A/5A
UC2842A/3A/4A/5A
UC3842A/3A/4A/5A
Current Mode PWM Controller
FEATURES
DESCRIPTION
•
Optimized for Off-line and DC to DC
The UC1842A/3A/4A/5A family of control ICs is a pin for pin compat-
ible improved version of the UC3842/3/4/5 family. Providing the nec-
essary features to control current mode switched mode power
supplies, this family has the following improved features. Start up cur-
rent is guaranteed to be less than 0.5mA. Oscillator discharge is
trimmed to 8.3mA. During under voltage lockout, the output stage can
sink at least 10mA at less than 1.2V for VCC over 5V.
Converters
•
•
•
•
•
•
•
•
•
•
•
Low Start Up Current (<0.5mA)
Trimmed Oscillator Discharge Current
Automatic Feed Forward Compensation
Pulse-by-Pulse Current Limiting
Enhanced Load Response Characteristics
Under-Voltage Lockout With Hysteresis
Double Pulse Suppression
The difference between members of this family are shown in the table
below.
Maximum Duty
Part #
UVLO On
UVLO Off
Cycle
<100%
<100%
<50%
High Current Totem Pole Output
Internally Trimmed Bandgap Reference
500kHz Operation
UC1842A
UC1843A
UC1844A
UC1845A
16.0V
8.5V
10.0V
7.9V
16.0V
8.5V
10.0V
7.9V
<50%
Low RO Error Amp
BLOCK DIAGRAM
A/B
Note 1:
A = DIL-8 Pin Number. B = SO-14 Pin Number.
Note 2: Toggle flip flop used only in 1844A and 1845A.
9/94
UC1842A/3A/4A/5A
UC2842A/3A/4A/5A
UC3842A/3A/4A/5A
ABSOLUTE MAXIMUM RATINGS (Note 1)
CONNECTION DIAGRAMS
DIL-8, SOIC-8 (TOP VIEW)
J or N, D8 Package
Supply Voltage (Low Impedance Source) . . . . . . . . . . . . . . 30V
Supply Voltage (ICC mA). . . . . . . . . . . . . . . . . . . . . Self Limiting
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A
±
Output Energy (Capacitive Load). . . . . . . . . . . . . . . . . . . . . 5µJ
Analog Inputs (Pins 2, 3) . . . . . . . . . . . . . . . . . . -0.3V to +6.3V
Error Amp Output Sink Current . . . . . . . . . . . . . . . . . . . . 10mA
Power Dissipation at TA ≤ 25°C (DIL-8) . . . . . . . . . . . . . . . . 1W
Storage Temperature Range . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . 300°C
Note 1. All voltages are with respect to Ground, Pin 5. Currents
are positive into, negative out of the specified terminal. Consult
Packaging Section of Databook for thermal limitations and con-
siderations of packages. Pin numbers refer to DIL package only.
PACKAGE PIN FUNCTION
PLCC-20, LCC-20
(TOP VIEW)
Q, L Packages
FUNCTION
N/C
PIN
1
SOIC-14 (TOP VIEW)
D Package
Comp
N/C
VFB
2
3-4
5
N/C
6
ISENSE
N/C
RT/CT
N/C
Pwr Gnd
Gnd
N/C
Output
N/C
VC
VCC
N/C
7
8-9
10
11
12
13
14
15
16
17
18
19
20
VREF
ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for -55°C ≤ TA ≤ 125°C for the
UC184xA; -40°C ≤ TA ≤ 85°C for the UC284xA; 0 ≤ TA ≤ 70°C for the UC384xA; VCC = 15V (Note 5); RT = 10k; CT = 3.3nF; TA = TJ; Pin
numbers refer to DIL-8.
UC184xA\UC284xA
UC384xA
PARAMETER
TEST CONDITIONS
UNITS
MIN. TYP. MAX. MIN. TYP. MAX.
Reference Section
Output Voltage
TJ = 25°C, IO = 1mA
4.95
4.9
5.00
6
5.05
20
4.90
4.82
5.00
6
5.10
20
V
mV
Line Regulation
12 ≤ VIN ≤ 25V
Load Regulation
Temp. Stability
1 ≤ IO ≤ 20mA
6
25
6
25
mV
(Note 2, Note 7)
0.2
0.4
5.1
0.2
0.4
5.18
mV/°C
V
Total Output Variation
Output Noise Voltage
Line, Load, Temp.
10Hz ≤ f ≤ 10kHz
TJ = 25°C (Note 2)
TA = 125°C, 1000Hrs. (Note 2)
50
5
50
5
µV
mV
mA
Long Term Stability
Output Short Circuit
Oscillator Section
Initial Accuracy
25
25
-30
47
-100
-180
-30
47
-100
-180
TJ = 25°C (Note 6)
52
0.2
5
57
1
52
0.2
5
57
1
kHz
%
Voltage Stability
Temp. Stability
12 ≤ VCC ≤ 25V
TMIN ≤ TA ≤ TMAX (Note 2)
VPIN 4 peak to peak (Note 2)
TJ = 25°C, VPIN 4 = 2V (Note 8)
VPIN 4 = 2V (Note 8)
%
Amplitude
1.7
8.3
1.7
8.3
V
Discharge Current
7.8
7.5
8.8
8.8
7.8
7.6
8.8
8.8
mA
mA
2
UC1842A/3A/4A/5A
UC2842A/3A/4A/5A
UC3842A/3A/4A/5A
ELECTRICAL CHARACTERISTICS (cont.) Unless otherwise stated, these specifications apply for -55°C ≤ TA ≤ 125°C for
the UC184xA; -40°C ≤ TA ≤ 85°C for the UC284xA; 0 ≤ TA ≤ 70°C for the UC384xA; VCC = 15V (Note 5); RT = 10k; CT = 3.3nF; TA = TJ;
Pin numbers refer to DIL-8.
UC184xA\UC284xA
UC384xA
PARAMETER
TEST CONDITIONS
UNITS
MIN. TYP. MAX. MIN. TYP. MAX.
Error Amp Section
Input Voltage
Input Bias Current
AVOL
VPIN 1 = 2.5V
2.45
2.50
-0.3
90
1
2.55
-1
2.42 2.50
-0.3
2.58
-2
V
µA
dB
MHz
dB
mA
mA
V
2 ≤ VO ≤ 4V
65
0.7
60
2
65
0.7
60
2
90
1
Unity Gain Bandwidth
PSRR
TJ = 25°C (Note 2)
12 ≤ VCC ≤ 25V
70
6
70
6
Output Sink Current
Output Source Current
VOUT High
VPIN 2 = 2.7V, VPIN 1 = 1.1V
VPIN 2 = 2.3V, VPIN 1 = 5V
VPIN 2 = 2.3V, RL = 15k to ground
VPIN 2 = 2.7V, RL = 15k to Pin 8
-0.5
5
-0.8
6
-0.5
5
-0.8
6
VOUT Low
0.7
1.1
0.7
1.1
V
Current Sense Section
Gain
(Note 3, Note 4)
2.85
0.9
3
1
3.15
1.1
2.85
0.9
3
1
3.15
1.1
V/V
V
Maximum Input Signal
PSRR
VPIN 1 = 5V (Note 3)
12 ≤ VCC ≤ 25V (Note 3)
70
-2
70
-2
dB
µA
ns
Input Bias Current
Delay to Output
Output Section
Output Low Level
-10
-10
VPIN 3 = 0 to 2V (Note 2)
150
300
150
300
ISINK = 20mA
0.1
15
0.4
2.2
0.1
15
0.4
2.2
V
V
ISINK = 200mA
Output High Level
ISOURCE = 20mA
13
12
13.5
13.5
50
13
12
13.5
13.5
50
V
ISOURCE = 200mA
V
Rise Time
TJ = 25°C, CL = 1nF (Note 2)
TJ = 25°C, CL = 1nF (Note 2)
VCC = 5V, ISINK = 10mA
150
150
1.2
150
150
1.2
ns
ns
V
Fall Time
50
50
UVLO Saturation
Under-Voltage Lockout Section
Start Threshold
0.7
0.7
x842A/4A
x843A/5A
x842A/4A
x843A/5A
15
7.8
9
16
8.4
10
17
9.0
11
14.5
7.8
8.5
7.0
16
8.4
10
17.5
9.0
V
V
V
V
Min. Operation Voltage After
TurnOn
11.5
8.2
7.0
7.6
8.2
7.6
PWM Section
Maximum Duty Cycle
x842A/3A
x844A/5A
94
47
96
48
100
50
0
94
47
96
48
100
50
0
%
%
%
Minimum Duty Cycle
Total Standby Current
Start-Up Current
0.3
11
34
0.5
17
0.3
11
34
0.5
17
mA
mA
V
Operating Supply Current
VCC Zener Voltage
VPIN 2 = VPIN 3 = 0V
ICC = 25mA
30
30
Note 2: These parameters, although guaranteed, are not 100%
tested in production.
Note 3: Parameter measured at trip point of latch with VPIN2 = 0.
VREF (max) − VREF (min)
TJ (max) − TJ (min)
VREF (max) and VREF (min) are the maximum & mini-
mum reference voltage measured over the appropriate
temperature range. Note that the extremes in voltage
do not necessarily occur at the extremes in tempera-
ture."
Temp Stability =
.
∆VPIN 1
Note 4: Gain defined as: A =
; 0 ≤ VPIN 3 ≤ 0.8V.
∆VPIN 3
Note 5: Adjust VCC above the start threshold before setting at
15V.
Note 6: Output frequency equals oscillator frequency for the
UC1842A and UC1843A. Output frequency is one half
oscillator frequency for the UC1844A and UC1845A.
Note 7: "Temperature stability, sometimes referred to as average
temperature coefficient, is described by the equation:
Note 8: This parameter is measured with RT = 10kΩ to VREF.
This contributes approximately 300µA of current to the
measurement. The total current flowing into the RT/CT
pin will be approximately 300µA higher than the meas-
ured value.
3
UC1842A/3A/4A/5A
UC2842A/3A/4A/5A
UC3842A/3A/4A/5A
Error Amp Configuration
Error Amp can Source and Sink up to 0.5mA, and Sink up to 2mA.
Under-Voltage Lockout
During UVLO, the Output is low.
Current Sense Circuit
Peak Current (IS) is Determined By The Formula
1.0V
ISMAX ≈
RS
A small RC filter may be required to suppress switch transients.
4
UC1842A/3A/4A/5A
UC2842A/3A/4A/5A
UC3842A/3A/4A/5A
APPLICATIONS DATA (cont.)
Output Saturation Characteristics
Error Amplifier Open-Loop Frequency Response
Oscillator Section
Oscillator Frequency vs Timing Resistance
Maximum Duty Cycle vs Timing Resistor
Open-Loop Laboratory Test Fixture
High peak currents associated with capacitive loads necessi-
tate careful grounding techniques. Timing and bypass capaci-
tors should be connected close to pin 5 in a single point
ground. The transistor and 5k potentiometer are used to sam-
ple the oscillator waveform and apply an adjustable ramp to
pin 3.
5
UC1842A/3A/4A/5A
UC2842A/3A/4A/5A
UC3842A/3A/4A/5A
APPLICATIONS DATA (cont.)
Off-line Flyback Regulator
Power Supply Specifications
5. Output Voltage:
A. +5V, ±5%; 1A to 4A load
Ripple voltage: 50mV P-P Max
B. +12V, ±3%; 0.1A to 0.3A load
Ripple voltage: 100mV P-P Max
C. -12V ,±3%; 0.1A to 0.3A load
Ripple voltage: 100mV P-P Max
1. Input Voltage
95VAC to 130VA
(50 Hz/60Hz)
3750V
40kHz
70%
2. Line Isolation
3. Switching Frequency
4. Efficiency @ Full Load
Slope Compensation
A fraction of the oscillator ramp can be resistively
summed with the current sense signal to provide slope
compensation for converters requiring duty cycles over
50%.
Note that capacitor, C, forms a filter with R2 to suppress
the leading edge switch spikes.
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603)424-3460
6
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