UC2848DWG4 [TI]
2.2A SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PDSO16, GREEN, PLASTIC, SOIC-16;型号: | UC2848DWG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | 2.2A SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PDSO16, GREEN, PLASTIC, SOIC-16 开关 光电二极管 |
文件: | 总18页 (文件大小:999K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
application
INFO
UC1848
UC2848
UC3848
available
Average Current Mode PWM Controller
BLOCK DIAGRAM
FEATURES
• Practical Primary Side Control of
Isolated Power Supplies with DC
Control of Secondary Side Current
• Accurate Programmable Maximum
Duty Cycle Clamp
• Maximum Volt-Second Product Clamp
to Prevent Core Saturation
• Practical Operation Up to 1MHz
• High Current (2A Pk) Totem Pole
Output Driver
• Wide Bandwidth (8MHz) Current Error
Amplifier
• Under Voltage Lockout Monitors VCC,
VIN and VREF
• Output Active Low During UVLO
• Low Startup Current (500µA)
• Precision 5V Reference (1%)
UDG-93003-1
DESCRIPTION
The UC3848 family of PWM control ICs makes primary output driver. The current error amplifier easily interfaces
side average current mode control practical for isolated with an optoisolator from a secondary side voltage sens-
switching converters. Average current mode control in- ing circuit.
sures that both cycle by cycle peak switch current and
A full featured undervoltage lockout (UVLO) circuit is con-
maximum average inductor current are well defined and
tained in the UC3848. UVLO monitors the supply voltage
will not run away in a short circuit situation. The UC3848
to the controller (VCC), the reference voltage (VREF),
can be used to control a wide variety of converter topolo-
and the input line voltage (VIN). All three must be good
before soft start commences. If either VCC or VIN is low,
gies.
In addition to the basic functions required for pulse width
modulation, the UC3848 implements a patented tech-
nique of sensing secondary current in an isolated buck
derived converter from the primary side. A current wave-
form synthesizer monitors switch current and simulates
the inductor current down slope so that the complete cur-
rent waveform can be constructed on the primary side
without actual secondary side measurement. This infor-
mation on the primary side allows for full DC control of
output current.
the supply current required by the chip is only 500µA and
the output is actively held low.
Two on board protection features set controlled limits to
prevent transformer core saturation. Input voltage is mon-
itored and pulse width is constrained to limit the maxi-
mum volt-second product applied to the transformer. A
unique patented technique limits maximum duty cycle
within 3% of a user programmed value.
These two features allow for more optimal use of trans-
formers and switches, resulting in reduced system size
and cost.
The UC3848 circuitry includes a precision reference, a
wide bandwidth error amplifier for average current con-
trol, an oscillator to generate the system clock, latching
PWM comparator and logic circuits, and a high current
Patents embodied in the UC3848 belong to Lambda
Electronics Incorporated and are licensed for use in ap-
plications employing these devices.
SLUS225A - April 1996 - REVISED MARCH 2004
UC1848
UC2848
UC3848
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Pin 15). . . . . . . . . . . . . . . . . . . . . . . . . . . . 22V
Output Current, Source or Sink (Pin 14)
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A
Pulse (0.5 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2A
Power Ground to Ground (Pin 1 to Pin 13) . . . . . . . . . . . ± 0.2V
Analog Input Voltages
Analog Output Currents, Source or Sink (Pins 5 & 10) . . . 5mA
Power Dissipation at TA = 60°C . . . . . . . . . . . . . . . . . . . . . . 1W
Storage Temperature Range . . . . . . . . . . . . . . . −65°C to +150°C
Lead Temperature (Soldering 10 seconds) . . . . . . . . . . +300°C
(Pins 3, 4, 7, 8, 12, 16) . . . . . . . . . . . . . . . . . . . . . –0.3 to 7V
Analog Input Currents, Source or Sink
(Pins 3, 4, 7, 8, 11, 12, 16) . . . . . . . . . . . . . . . . . . . . . . 1mA
CONNECTION DIAGRAMS
PACKAGE PIN FUNCTION
PLCC-20 & LCC-20
(Top View)
Q & L Packages
FUNCTION
N/C
PIN
1
DIL-16, SOIC-16 (Top View)
J, N, or DW Packages
GND
VREF
NI
2
3
4
INV
5
N/C
6
CAO
CT
7
8
VS
9
DMAX
N/C
CDC
CI
IOFF
ION
N/C
PGND
OUT
VCC
UV
10
11
12
13
14
15
16
17
18
19
20
THERMAL RATINGS TABLE
Package
DIL-16J
QJA
80-120
90(1)
QJC
28(2)
45
DIL-16N
SOIC-16DW
PLCC-20
LCC-20
50-100(1)
43-75(1)
70-80
27
34
20(2)(3)
Q
Q
Q
2
UC1848
UC2848
UC3848
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, all specifications are over the junction temperature range
of −55°C to +125°C for the UC1848, −40°C to +85°C for the UC2848, and 0°C to +70°C for the UC3848. Test conditions are: VCC
= 12V, CT = 400pF, CI = 100pF, IOFF = 100µA, CDC = 100nF, Cvs = 100pF, and Ivs = 400µA, TA = TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Real Time Current Waveform Synthesizer
Ion Amplifier
Offset Voltage
Slew Rate (Note 1)
lib
0.95
20
1
1.05
-20
V
25
-2
V/µs
µA
IOFF Current Mirror
Input Voltage
Current Gain
Current Error Amplifier
AVOL
0.95
0.9
1
1
1.05
1.1
V
A/A
60
3
100
dB
mV
µA
Vio
12V ≤ VCC 20V, 0V VCM 5V
10
-3
lib
-0.5
3.3
0.3
1.6
8
Voh
IO = −200µA
IO = 200µA
VO = 1V
V
Vol
0.6
2.0
V
Source Current
GBW Product
Slew Rate (Note 1)
Oscillator
1.4
5
mA
MHz
V/µs
f = 200kHz
8
10
Frequency
TA = 25°C
240
235
1.5
250
1.65
76.5
260
265
1.8
kHz
kHz
V
Ramp Amplitude
Duty Cycle Clamp
Max Duty Cycle
Volt Second Clamp
Max On Time
V(DMAX) = 0.75 • VREF
73.5
900
79.5
1100
14
%
ns
VCC Comparator
Turn-on Threshold
Turn-off Threshold
Hysteresis
13
10
3
V
V
V
9
2.5
3.5
3
UC1848
UC2848
UC3848
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, all specifications are over the junction temperature range
of −55°C to +125°C for the UC1848, −40°C to +85°C for the UC2848, and 0°C to +70°C for the UC3848. Test conditions are: VCC
= 12V, CT = 400pF, CI = 100pF, IOFF = 100µA, CDC = 100nF, Cvs = 100pF, and Ivs = 400µA, TA = TJ.
PARAMETER
UV Comparator
TEST CONDITIONS
MIN
TYP
MAX UNITS
Turn-on Threshold
RHYSTERESIS
Reference
4.1
77
4.35
90
4.6
V
Vuv = 4.2V
TA = 25°C
103
kΩ
VREF
4.95
4.93
5
5.05
5.07
15
V
0 < IO < 10mA, 12 < VCC < 20
12 < VCC < 20V
V
Line Regulation
Load Regulation
4
3
mV
mV
mA
0 < IO < 10mA
15
Short Circuit Current
Output Stage
VREF = 0V
30
50
70
Rise & Fall Time (Note 1)
Output Low Saturation
Cl = 1nF
20
0.25
1.2
45
0.4
2.2
3.0
1.2
ns
V
IO = 20mA
IO = 200mA
IO = -200mA
IO = 20mA
V
Output High Saturation
2.0
V
UVLO Output Low Saturation
0.8
V
ICC
ISTART
VCC = 12V
0.2
0.5
22
0.4
1
mA
mA
mA
ICC (pre-start)
ICC (run)
VCC = 15V, V(UV) = 0
26
APPLICATION INFORMATION
Under Voltage Lockout
When the UV comparator is low, ICC is low (500µA) and
the output is low.
The Under Voltage Lockout block diagram is shown in
Fig 1. The VCC comparator monitors chip supply voltage.
Hysteretic thresholds are set at 13V and 10V to facilitate
off-line applications. If the VCC comparator is low, ICC is
low (<500µA) and the output is low.
When both the UV and VCC comparators are high, the
internal bias circuitry for the rest of the chip is activated.
The CDC pin (see discussion on Maximum Duty Cycle
Control and Soft Start) and the Output are held low until
VREF exceeds the 4.5V threshold of the VREF compara-
tor. When VREF is good, control of the output driver is
transferred to the PWM circuitry and CDC is allowed to
charge.
The UV comparator monitors input line voltage (VIN). A
pair of resistors divides the input line to UV. Hysteretic in-
put line thresholds are programmed by Rv1 and Rv2. The
thresholds are
If any of the three UVLO comparators go low, the UVLO
latch is set, the output is held low, and CDC is dis-
charged. This state will be maintained until all three com-
parators are high and the CDC pin is fully discharged.
VIN(on) = 4.35V • (1 + Rv1/Rv2′) and
VIN(off) = 4.35V • (1 + Rv1/Rv2) where
Rv2′= Rv2||90k.
The resulting hysteresis is
VIN(hys) = 4.35V • Rv1 / 90k.
4
UC1848
UC2848
UC3848
APPLICATION INFORMATION (cont.)
UDG-93004
Oscillator Frequency as a Function of CT
10000
Frequency Decrease as a Function of RT
1000
RT = Open
100
10
10
100
1000
10000
C (pF)
UDG-93006
UDG-93005
5
UC1848
UC2848
UC3848
APPLICATION INFORMATION (cont.)
of the switch. During the off time, switch current drops
abruptly to zero, but the inductor current actually dimin-
ishes with a slope dIL/dt = –VO/L. This down slope must
be synthesized in some manner on the primary side to
provide the entire inductor current waveform for the con-
trol circuit.
The patented current waveform synthesizer (Fig. 4) con-
sists of a unidirectional voltage follower which forces the
voltage on capacitor CI to follow the on time switch cur-
rent waveform. A programmable discharge current syn-
thesizes the off time portion of the waveform. ION is the
input to the follower. The discharge current is pro-
grammed at IOFF.
The follower has a one volt offset, so that zero current
corresponds to one volt at CI. The best utilization of the
UC3848 is to translate maximum average inductor cur-
rent to a 4V signal level. Given N and Ns (the turns ratio
of the power and current sense transformers), proper
scaling of IL to V(CI) requires a sense resistor Rs as cal-
culated from:
UDG-93008-1
Rs = 4V Ns N / IL(max).
Oscillator
Restated, the maximum average inductor current will be
limited to:
A capacitor from the CT pin to GND programs oscillator
frequency, as shown in Fig. 2. Frequency is determined
by:
IL(max) = 4V Ns N/Rs.
IOFF and CI need to be chosen so that the ratio of
dV(CI)/dt to dIL/dt is the same during switch off time as
on time. Recommended nominal off current is 100 A.
This requires
F = 1 / (10k CT).
The sawtooth wave shape is generated by a charging
current of 200 A and a discharge current of 1800 A. The
discharge time of the sawtooth is guaranteed dead time
for the output driver. If the maximum duty cycle control is
defeated by connecting DMAX to VREF, the maximum
duty cycle is limited by the oscillator to 90%. If an adjust-
ment is required, an additional trim resistor RT from CT
to Ground can be used to adjust the oscillator frequency.
RT should not be less than 40k . This will allow up to a
22% decrease in frequency.
CI = (100 A
N Ns L) / (Rs VO(nom))
where L is the output inductor value and VO(nom) is the
converter regulated output voltage.
There are several methods to program IOFF. If accurate
average current control is required during short circuit op-
eration, IOFF must track output voltage. The method
shown in Fig. 4 derives a voltage proportional to VIN
D
Inductor Current Waveform Synthesizer
(Duty Cycle). (In a buck converter, output voltage is pro-
portional to VIN D.) A resistively loaded diode connec-
tion to the bootstrap winding yields a square wave whose
amplitude is proportional to VIN and is duty cycle modu-
lated by the control circuit. Averaging this waveform with
a filter generates a primary side replica of secondary reg-
ulated VO. A single pole filter is shown, but in practice a
two or three pole filter provides better transient response.
Filtered voltage is converted by ROFF to a current to the
IOFF pin to control CI down slope.
Average current mode control is a very useful technique
to control the value of any current within a switching con-
verter. Input current, output inductor current, switch cur-
rent, diode current or almost any other current can be
controlled. In order to implement average current mode
control, the value of the current must be explicitly known
at all times. To control output inductor current (IL) in a
buck derived isolated converter, switch current provides
inductor current information, but only during the on time
6
UC1848
UC2848
UC3848
APPLICATION INFORMATION (cont.)
If the system is not sensitive to short circuit requirements, A third method of generating IOFF is to add a second
Figure 5 shows the simplest method of downslope gener- winding to the output inductor core (Fig. 6). When the
ation: a single resistor (ROFF = 40k) from IOFF to VREF. power switch is off and inductor current flows in the free
wheeling diode, the voltage across the inductor is equal
to the output voltage plus the diode drop. This voltage is
then transformed by the second winding to the primary
side of the converter. The advantages to this approach
are its inherent accuracy and bandwidth. Winding the
second coil on the output inductor core while maintaining
the required isolation makes this a more costly solution.
The discharge current is then 100µA. The disadvantage
to this approach is that the synthesizer continues to gen-
erate a down slope when the switch is off even during
short circuit conditions. Actual inductor down slope is
closer to zero during a short circuit. The penalty is that
the average current is understated by an amount approxi-
mately equal to the nominal inductor ripple current. Out-
put short circuit is therefore higher than the designed In the example, ROFF = VO / 100µA. The 4 • ROFF re-
maximum output current.
sistor is added to compensate the one volt input level of
the IOFF pin. Without this compensation, a minor current
foldback behavior will be observed.
UDG-93009
UDG-93011
UDG-93010
7
UC1848
UC2848
UC3848
APPLICATION INFORMATION (cont.)
Maximum Volt-Second Circuit
Ground Planes
A maximum volt-second product can be programmed by The output driver on the UC3848 is capable of 2A peak
a resistor (Rvs) from VS to VIN and a capacitor (Cvs) currents. Careful layout is essential for correct operation
from VS to ground (Figure 7). VS is discharged while the of the chip. A ground plane must be employed (Fig. 8). A
switch is off. When the output turns on, VS is allowed to unique section of the ground plane must be designated
charge. Since the threshold of the VS comparator is for high di/dt currents associated with the output stage.
much less than VIN, the charging profile at Vs will be es- This point is the power ground to which to PGND pin is
sentially linear. If VS crosses the 4.0V threshold before connected. Power ground can be separated from the rest
the PWM turns the output off, the VS comparator will turn of the ground plane and connected at a single point, al-
the output off for the remainder of the cycle. The maxi- though this is not strictly necessary if the high di/dt paths
mum volt-second product is
are well understood and accounted for. VCC should be
bypassed directly to power ground with a good high fre-
quency capacitor. The sources of the power MOSFET
should connect to power ground as should the return
connection for input power to the system and the bulk in-
put capacitor. The output should be clamped with a high
current Schottky diode to both VCC and PGND. Nothing
else should be connected to power ground.
V
IN • TON(max) = 4.0V • Rvs • Cvs.
Maximum Duty Cycle And Soft Start
A patented technique is used to accurately program max-
imum duty cycle. Programming is accomplished by a di-
vider from VREF to DMAX (Fig. 7). The value
programmed is:
VREF should be bypassed directly to the signal portion
of the ground plane with a good high frequency capacitor.
Low esr/esl ceramic 1 F capacitors are recommended
for both VCC and VREF. The capacitors from CT, CDC,
and CI should likewise be connected to the signal ground
plane.
D(max) = Rd1 / (Rd1 + Rd2).
For proper operation, the integrating capacitor, CDC
,
should be larger than CDC(min) >T(osc) / 80k, where
T(osc) is the oscillator period. CDC also sets the soft start
time constant, so values of CDC larger than minimum may
be desired. The soft start time constant is approximately:
T(ss) = 20k • CDC
.
UDG-93012-1
UDG-93013-1
8
UC1848
UC2848
UC3848
UDG-93014
UDG-93015
9
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
UC1848J
OBSOLETE
LIFEBUY
CDIP
SOIC
J
16
16
TBD
Call TI
Call TI
-55 to 125
-40 to 85
UC2848DW
DW
40
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
UC2848DW
UC2848DWG4
LIFEBUY
SOIC
DW
16
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UC2848DW
UC2848J
OBSOLETE
LIFEBUY
CDIP
SOIC
J
16
16
TBD
Call TI
Call TI
-40 to 85
0 to 70
UC3848DW
DW
40
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
UC3848DW
UC3848DW
UC3848DW
UC3848N
UC3848DWG4
UC3848DWTR
UC3848N
LIFEBUY
LIFEBUY
LIFEBUY
SOIC
SOIC
PDIP
DW
DW
N
16
16
16
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
2000
25
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1848, UC3848 :
Catalog: UC3848
•
Military: UC1848
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UC3848DWTR
SOIC
DW
16
2000
330.0
16.4
10.75 10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
UC3848DWTR
2000
Pack Materials-Page 2
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