UC2907QTR [TI]

Load-Sharing Regulation Controller ; 负载共享调节控制器\n


型号：	UC2907QTR
厂家：	TEXAS INSTRUMENTS
描述：	Load-Sharing Regulation Controller 负载共享调节控制器\n 电源电路电源管理电路控制器
文件：	总7页 (文件大小：271K)
中文：	中文翻译
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UC1907

UC2907

UC3907

Load Share Controller

FEATURES

DESCRIPTION

Fully Differential High Impedance

Voltage Sensing

The UC3907 family of Load Share Controller ICs provides all the necessary

features to allow multiple independent power modules to be paralleled such

that each module supplies only its proportionate share to total load current.

Accurate Current Amplifier for Precise

Current Sharing

This sharing is accomplished by controlling each module’s power stage

with a command generated from a voltage feedback amplifier whose refer-

ence can be independently adjusted in response to a common share bus

voltage. By monitoring the current from each module, the current share bus

circuitry determines which paralleled module would normally have the high-

est output current and, with the designation of this unit as the master, ad-

justs all the other modules to increase their output current to within 2.5% of

that of the master.

Opto Coupler Driving Capability

1.25% Trimmed Reference

Master Status Indication

4.5V TO 35V Operation

The current share bus signal interconnecting all the paralleled modules is a

low-impedance, noise-insensitive line which will not interfere with allowing

each module to act independently should the bus become open or shorted

to ground. The UC3907 controller will reside on the output side of each

power module and its overall function is to supply a voltage feedback loop.

The specific architecture of the power stage is unimportant. Either switch-

ing or linear designs may be utilized and the control signal may be either di-

rectly coupled or isolated though the use of an opto coupler or other

isolated medium.

Other features of the UC3907 include 1.25% accurate reference: a

low-loss, fixed gain current sense amplifier,

fully differential,

high-impedance voltage sensing capability, and a status indicator to desig-

nate which module is performing as master.

BLOCK DIAGRAM

VOLTAGE ERROR AMPLIFIER

(+) SENSE 11

–

12 COMP

VCC (4.5V TO 35V) 10

0.25V

DRIVE

1.75V

OPTO DRIVE

AMPLIFIER

1.0V

–

DRV

GROUND

AMPLIFIER

REF

1.750V

–

GND

20k

50k

(–) SENSE

POWER RTN

ARTIFICIAL GND

VREF

ISET

14 ADJ OUT

ADJUST

AMPLIFIER

50mV

13 ADJ INPUT

–

17.5k

ADJ

C/S OUT

40k

BUFFER

AMPLIFIER

CURRENT SENSE

AMPLIFIER

–

C/S (–)

C/S (+)

100

15 CURRENT SHARE BUS

16 STATUS INDICATE

–

10k

40k

UDG-99052

SLUS165 - MARCH 1999

UC1907

UC2907

UC3907

CONNECTION DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +35V

Opto Out Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +35V

Opto Out Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20mA

Status Indicate Sink Current. . . . . . . . . . . . . . . . . . . . . . +20mA

C/S Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +35V

Share Bus Voltage . . . . . . . . . . . . . . . . . . . . . . . – 0.3V to +35V

Other Analog Inputs and Outputs (Zener clamped)

DIL-16 (Top View)

J or N Package

Maximum Forced Voltage . . . . . . . . . . . . . . . – 0.3V to +10V

Maximum Forced Current. . . . . . . . . . . . . . . . . . . . . . ±10mA

Ground Amp Sink Current . . . . . . . . . . . . . . . . . . . . . . . +50mA

Pins 1, 9, 12, 15 Sink Current. . . . . . . . . . . . . . . . . . . . . +20mA

Storage Temperature Range. . . . . . . . . . . . . – 65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . – 55°C to +150°C

Lead Temperature (Solder 10 Seconds) . . . . . . . . . . . . +300°C

Pin Nos. refer to 16 Pin DIL Package

Currents are positive into, negative out of the specified

terminal. Consult packaging section of databook for thermal

limitations and considerations of package.

PLCC–20, LCC–20 (Top View)

Q PACKAGE, L PACKAGE

SOIC-16 (Top View)

DW Package

ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications apply for T_A= –55°C to +125°C for

UC1907; –40°C to +85°C for UC2907; and 0°C to +70°C for UC3907; V_IN= 15V, T_A=T_J.

PARAMETER

Voltage Amp Section

TEST CONDITIONS

MIN

TYP

MAX UNITS

Input Voltage

COMP = 1V, T_A= 25°C

1.975 2.000 2.025

COMP = 1V, Over Temp

V_IN= 4.5V to 35V

1.960 2.000 2.040

Line Regulation

Load Regulation

Long Term Stability

Total Output Variation

Input Adjust Range

Input Bias Current

Open Loop Gain

Unity Gain Bandwidth

Output Sink Current

Output Source Current

V_OUTHigh

I_LReference = 0.0mA to – 10mA

T_A= 125°C, 1000hrs (Note 2)

Line, Load, Temp

1.960

2.040

115

ADJ OUT from max high to max low

100

µA

kHz

µA

–1

COMP = 0.75V to 1.5V

T_A= 25°C (Note 2)

700

(+) SENSE = 2.2V, COMP = 1V

(+) SENSE = 1.8V, COMP = 1V

(+) SENSE = 1.8V, I_L= – 400µa

(+) SENSE = 2.2V, I_L= +1mA

600

400

1.85

V_OUTLow

0.15

0.40

UC1907

UC2907

UC3907

ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications apply for T_A= –55°C to +125°C for

UC1907; –40°C to +85°C for UC2907; and 0°C to +70°C for UC3907; V_IN= 15V, T_A=T_J.

PARAMETER TEST CONDITIONS

Reference Section

MIN

TYP

MAX UNITS

Output Voltage

T_A= 25°C

1.970 2.000 2.030

1.955 2.000 2.045

Over Operating Temp

VREF = 0.0V

Short Circuit Current

Ground Amp Section

Output Voltage

– 15

– 30

– 60

200

250

300

Common Mode Variation

Load Regulation

(–) SENSE from 0.0V to 2V

I_L= 0.0mA to 20mA, T_A= 25°C

I_L= 0.0mA to 20mA, Over Temp

Adjust Amp Section

Input Offset Voltage

Input Bias Current

Open Loop Gain

ADJ OUT = 1.5V, Vcm = 0.0V

– 2

µA

1.5V≤ ADJ OUT≤ 2.25V

Unity Gain Bandwidth

Transconductance

Output Sink Current

Output Source Current

V_OUTHigh

T_A= 25°C, C_OUT=1µF (Note 2)

I_OUT= – 10µA to +10µA, V_OUT= 1.5V

Vid = 0.0V, ADJ OUT = 1.5V

Vid = 250mV, ADJ OUT = 1.5V

Vid = 250mV, I_OUT= – 50µA

Vid = 0.0V, I_OUT= 50µA

500

1.7

4.5

225

350

2.90

1.15

135

200

2.70

0.75

110

2.20

V_OUTLow

Common Mode Rejection Ratio

Output Gain to V/A

Vcm = 0.0 to 10V

mV/V

V_OUTADJ OUT = 1.5V to 2V

∆(+) SENSE/ ∆ADJ OUT

Current Amp Section

Gain

Vcm = 0.0V, Vid = 50mV to 100mV

Vc/s (+) = Vc/s (–) = 0.0V, T_A= 25°C

Vc/s (+) = Vc/s (–) = 0.0V, Over Temp

Vcm = 0V to 13V

19.2

210

180

19.6

250

20.1

290

330

600

V/V

Output Voltage

Input Offset Change with Common Mode

Input

µV/V

V_OUTHigh

Vid = 1V

14.5

350

V_OUTLow

Vid = – 1V, I_L= 1mA

V_IN= 4.5V to 35V, Vcm = 0.0V

450

Power Supply Rejection Ratio

Slew Rate

0.4

V/µs

Drive Amp Section Rset = 500Ω to Artificial Gnd, Opto Drive = 15V

Voltage Gain

COMP = 0.5V to 1V

(+) SENSE = 2.2V

(+) SENSE = 1.8V

2.3

3.8

2.5

4.1

2.6

4.4

V/V

I_SETV_OUTHigh

I_SETV_OUTLow

270

300

Opto out Voltage Range

Zero Current Input Threshold

Buffer Amp Section

Input Offset Voltage

1.55

1.65

1.75

Input = 1V

kΩ

Output Off Impedance

Output Source Current

Common Mode Rejection Ratio

Power Supply Rejection Ratio

Input = 1V, Output = 1.5V to 2V

Input = 1V, Output = 0.5V

Vcm = 0.3V to 10V

V_IN= 4.5V to 35V

UC1907

UC2907

UC3907

ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications apply for T_A= –55°C to +125°C for

UC1907; –40°C to +85°C for UC2907; and 0°C to +70°C for UC3907; V_IN= 15V, T_A=T_J.

PARAMETER

Under Voltage Lockout Section

Startup Threshold

TEST CONDITIONS

MIN

TYP

MAX UNITS

3.7

4.4

Threshold Hysteresis

Status Indicate Section

V_OUTLow

ADJ OUT = Current Share Bus

ADJ OUT = 1V, V_OUT= 35V

0.2

0.1

0.5

Output Leakage

µA

Total Stand by Current Section

Startup Current

V_IN= UVLO – 0.2V

V_IN= 35V

Operating Current

Note 1: Unless otherwise specified all voltages are with respect to (–) SENSE. Currents are positive into, negative out of the

specified terminal.

Note 2: Guaranteed by design. Not 100% tested in production.

PIN/BLOCK DESCRIPTIONS

clamp of 2.0 Volts. The reference trimming is performed

closed loop, and measured at pin 11, (+) SENSE. The

value is trimmed to 2V ±1.25%.

(–) SENSE (Pin 4) - This is a high-impedance pin in-

tended to allow remote sensing of the system ground,

bypassing any voltage drops which might appear in the

power return line. This point should be considered as

the “true” ground. Unless otherwise stated, all volt-

ages are with respect to this point.

DRIVE AMPLIFIER (Pins 8, 9, 12) - This amplifier is

used as an inverting buffer between the Voltage Ampli-

fier’s output and the medium used to couple the feedback

signal to the power controller. It has a fixed voltage gain

of 2.5 and is usually configured with a current-setting re-

sistor to ground. This establishes a current - sinking out-

put optimized to drive optical couplers biased at any

voltage from 4.5V to 35V, with current levels up to 20mA.

The polarity of this stage is such that an increasing volt-

age at the Voltage Amplifier’s sense input (as, for exam-

ple, at turn on) will increase the opto’s current. In a

nonisolated application, a voltage signal ranging from

0.25V to 4.1V may be taken from the current-setting out-

put but it should be noted that this voltage will also in-

crease with increasing sense voltage and an external

inverter may be required to obtain the correct feedback

polarity.

ARTIFICIAL GROUND (Pin 6) - This is a low impedance

circuit ground which is exactly 250 millivolts above the (–)

SENSE terminal. This offset allows the Ground Buffer

Amplifier negative headroom to return all the control bias

and operating currents while maintaining a high imped-

ance at the (–) SENSE input.

POWER RTN (Pin 5) - This should be the most negative

voltage available and can range from zero to 5V below

the (–) SENSE terminal. It should be connected as close

to the power source as possible so that voltage drops

across the return line and current sensing impedances

lie between this terminal and the (–) SENSE point.

VREF (Pin 7) - The internal Voltage Reference is a

band-gap circuit set at 2.0 Volts with respect to the (–)

SENSE input (1.75V above the ARTIFICIAL GROUND),

and an accuracy of ± 1.5%. This circuit, as well as all the

other chip functions, will work over a supply voltage

range of 4.5V to 35V allowing operation from unregulated

DC, an auxiliary voltage, or the same output voltage that

it is controlling. Under voltage lockout has been included

to insure proper startup by disabling internal bias cur-

rents until the reference rises into regulation.

CURRENT AMPLIFIER (Pins 1, 2, 3) - This amplifier has

differential sensing capability for use with an external

shunt in the power return line. The common-mode range

of its input will accommodate the full range between the

Power Return point and VCC–2V which will allow unde-

fined line impedances on either side of the current shunt.

The gain is internally set at 20 giving the user the ability

to establish the maximum voltage drop across the cur-

rent sense resistor at any value between 50 and 500 mil-

livolts. While the bandwidth of this amplifier may be

reduced with the addition of an external output capacitor

to ground, in most cases this is not required as the com-

pensation of the Adjust Amplifier will typically form the

dominant pole in the adjust loop.

VOLTAGE AMPLIFIER (Pins 11, 12) - This circuit is the

feedback control gain stage for the power module’s out-

put voltage regulation, and overall loop compensation will

normally be applied around this amplifier. Its output will

swing from slightly above the ground return to an internal

UC1907

UC2907

UC3907

PIN/BLOCK DESCRIPTIONS (cont.)

external resistor tolerances. The Adjust Amplifier has a

built-in 50mV offset on its inverting input which will force

the unit acting as the master to have a low output result-

ing in no change to the reference. While this 50mV offset

represents an error in current sharing, the gain of the

current amplifier reduces it to only 2.5mV across the cur-

rent sense resistor. It should also be noted that when the

module is acting independently with no connection to the

Share Bus node, or when the Share Bus node is shorted

to ground, its reference voltage will be unchanged. Since

only the circuit acting as a master will have a low output

from the Adjust Amplifier, this signal is used to activate a

flag output to identify the master should some corrective

action be needed.

BUFFER AMPLIFIER (Pins 1, 15) - This amplifier is a

uni-directional buffer which drives the CURRENT SHARE

BUS - the line which will interconnect all power modules

paralleled for current sharing. Since the Buffer Amplifier

will only source current, it insures that the module with

the highest output current will be the master and drive

the bus with a low-impedance drive capability. All other

Buffer Amplifiers will be inactive with each exhibiting a

10kohm load impedance to ground. The Share Bus ter-

minal is protected against both shorts to ground and ac-

cidental voltages in excess of 50 Volts.

ADJUST AMPLIFIER (Pins 13, 14, 15) - This amplifier

adjusts the individual module’s reference voltage to

maintain equal current sharing. It is a transconductance

type in order that its bandwidth may be limited, and noise

kept out of the reference adjust circuitry, with a simple

capacitor to ground. The function of this amplifier is to

compare its own module output current to the Share Bus

signal - which represents the highest output current - and

force an adjust command which is capable of increasing

the reference voltage as seen by the voltage amplifier by

as much as 100 millivolts. This number stems from the

17.5:1 internal resistor ratio between the Adjust Ampli-

fier’s clamped output and the reference, and represents a

5% total range of adjustment - a value which should be

adequate to compensate for unit-to-unit reference and

STATUS INDICATE (Pin 16) - This pin is an open collec-

tor output intended to indicate the unit which is acting as

the master. It achieves this by sensing when the adjust

amp is in its low state and pulling the status indicate pin

low.

ADDITIONAL INFORMATION

Please refer to additional application information.

[1] Application Note U-129, UC3907 Load Share IC Simplifies

Parallel Power Supply Design by Mark Jordan.

[2] Application Note U-163, UC3902 Load Share Controller and

its Performance in Distributed Power Systems by Laszlo

Balogh.

UDG-94103

Figure 1. Load system diagram.

UC1907

UC2907

UC3907

0-20mA

ISOLATED

CONTROL

UC3907

DRIVE

AMPLIFIER

–

1.0V

0-4V

DIRECT

CONTROL

VOLTAGE ERROR

AMPLIFIER

SET

(+) SENSE

20k

50k

–

RANGE 2.0V-2.1V

REF

MASTER

INDICATE

REF

1.75V

1.750V

REF

0.250V

GND

ADJUST AMPLIFIER

–

BUFFER

AMPLIFIER

50mV

CURRENT

BUS

–

(–) SENSE

20X

–

10k

ARTIFICIAL GND

C/S OUT ADJ IN

PWR RET

CURRENT

SENSE

ADJ

COMP

–

TO PWR

RETURN

FROM LOAD

MODULE LOAD CURRENT

UDG-99053

Figure 2. Load share connection diagram.

UDG-94105

Figure 3. UC3907 In a load-sharing feedback loop for an off-line isolated supply.

UNITRODE CORPORATION

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TEL. (603) 424-2410 • FAX (603) 424-3460

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UC2907QTR [TI]

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