UC3517N [TI]

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型号：	UC3517N
厂家：	TEXAS INSTRUMENTS
描述：	暂无描述电机驱动
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UC1517

UC3517

Stepper Motor Drive Circuit

FEATURES

DESCRIPTION

•

Complete Motor Driver and Encoder

The UC3517 contains four NPN drivers that operate in two-phase

fashion for full-step and half-step motor control. The UC3517

also contains two emitter followers, two monostables, phase de-

coder logic, power-on reset, and low-voltage protection, making it

a versatile system for driving small stepper motors or for control-

ling large power devices.

Continuous Drive Capability 350mA per Phase

Contains all Required Logic for Full and Half

Stepping

•

Bilevel Operation for Fast Step Rates

Operates as a Voltage Doubler

The emitter followers and monostables in the UC3517 are config-

ured to apply higher-voltage pulses to the motor at each step

command. This drive technique, called “Bilevel,” allows faster

stepping than common resistive current limiting, yet generates

less electrical noise than chopping techniques.

Useable as a Phase Generator and/or as a

Driver

•

Power-On Reset Guarantees Safe,

Predictable Power-Up

ABSOLUTE MAXIMUM RATINGS

Second Level Supply, VSS . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Power Dissipation, (Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2W

Phase Output Supply, VMM . . . . . . . . . . . . . . . . . . . . . . . . . 40V Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Logic Supply, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Ambient Temperature, UC1517. . . . . . . . . . . . -55°C to +125°C

Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -.3V to +7V Ambient Temperature, UC3517 . . . . . . . . . . . . . . 0°C to +70°C

Logic Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Storage Temperature . . . . . . . . . . . . . . . . . . . -55°C to +150°C

Output Current, Each Phase . . . . . . . . . . . . . . . . . . . . . . 500mA Note: Consult Packaging section of Databook for thermal

limitations and considerations of package.

Output Current, Emitter Follower . . . . . . . . . . . . . . . . . . -500mA

Power Dissipation, (Note). . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

BLOCK DIAGRAM

8/94

UC1517

UC3517

CONNECTION DIAGRAMS

PACKAGE PIN FUNCTION

PLCC-20, LCC-20

(TOP VIEW)

Q & L PACKAGE

DIL-16 (TOP VIEW)

J or N Package

FUNCTION

N/C

PB2

PB1

GND

PA1

N/C

PA2

DIR

STEP

ØB

N/C

ØA

HSM

INH

N/C

VSS

VCC

Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the

ELECTRICAL CHARACTERISTICS:

UC1517 and 0°C to +70°C for the UC3517, Vcc=5V, VSS = 20V, TA=TJ Pin

numbers refer to DIL-16 package.

UC1517 / UC3517

UNITS

PARAMETER

TEST CONDITIONS

MIN

4.75

TYP

MAX

5.25

Logic Supply, VCC

Second Supply, VSS

Logic Supply Current

Pin 16

Pin 15

VINH = 0.4V

VINH = 4.0V

Input Low Voltage

Pins 6, 7, 10, 11

Pins 6, 7, 10, 11; V = 0V

Pins 6, 7, 10, 11; V = 5V

Pins 1, 2, 4, 5; I = 350mA

Pins 1, 2, 4, 5; V = 39V

Pins 13,14; I = 350mA

Pins 13,14; V = 0V

Pins 8, 9; I = 1.6mA

Pins 1, 2, 4, 5

0.8

Input High Voltage

2.0

Input Low Current

-400

µA

Input High Current

0.85

500

-2

Phase Output Saturation Voltage

Phase Output Leakage Current

Follower Saturation Voltage to VSS

Follower Leakage Current

Output Low Voltage, ØA, ØB

Phase Turn-On Time

0.6

µA

500

0.4

µA

0.1

µs

Ω

Phase Turn-Off Time

Pins 1, 2, 4, 5

1.8

325

Second-Level On Time. TMONO

Logic Input Set-up Time, tS

Logic Input Hold Time, th

STEP Pulse Width, tP

Pins 13,14; Figure 3 Test Circuit

Pins 6, 10; Figure 4

Pin 7; Figure 4

Pin 12

275

400

375

800

Timing Resistor Value

Timing Capacitor Value

Power-On Threshold

100k

500

Pin 12

0.1

Pin 16

4.3

3.8

0.5

Power-Off Threshold

Pin 16

Power Hysteresis

Pin 16

UC1517

UC3517

Figure 3. Test Circuit

Figure 4. Timing Waveforms

PIN DESCRIPTION

VCC: VCC is the UC3517’s logic supply. Connect to a as shown in Figure 8. The sequencing of these outputs is

shown in Figure 5.

regulated 5VDC, and bypass with a 0.1µF ceramic ca-

pacitor to absorb switching transients.

PA1, PA2, PB1, and PB2: The phase outputs pull to

ground sequentially to cause motor stepping, according to

the state diagram of Figure 5. The sequence of stepping

on these lines, as well as with the LA and LB lines is con-

trolled by STEP input, the DIR input, and the HSM input.

Caution: If these outputs or any other IC pins are pulled

too far below ground either continuously or in a transient,

step memory can be lost. It is recommended that these

pins be clamped to ground and supply with high-speed di-

odes when driving inductive loads such as motor wind-

ings or solenoids. This clamping is very important

because one side of the winding can "kick" in a direction

opposite the swing of the other side.

VMM: VMM is the primary motor supply. It connects to the

UC3517 phase outputs through the motor windings. Limit

this supply to less than 40V to prevent breakdown of the

phase output transistors. Select the nominal VMM voltage

for the desired continuous winding current.

VSS: VSS is the secondary motor supply. It drives the LA

and LB outputs of the UC3517 when a monostable in the

UC3517 is active. In the bilevel application, this supply is

applied to the motor to charge the winding inductance

faster than the primary supply could. Typically, Vss is

higher in voltage than VMM, although VSS must be less

than 40V. The VSS supply should have good transient ca-

pability.

LA and LB: These outputs pull to VSS when their corre-

sponding monostable is active, and will remain high until

the monostable time elapses. Before and after, these out-

puts are high-impedance. For detail timing information,

consult Figure 5.

GROUND: The ground pin is the common reference for

all supplies, inputs and outputs.

RC: RC controls the timing functions of the monostables

in the UC3517. It is normally connected to a resistor (RT)

and a capacitor (CT) to ground, as shown in Figure 3.

Monostable on time is determined by the formula TON ≈

0.69 RT CT. To keep the monostable on indefinitely, pull

RC to VCC through a 50k resistor. The UC3517 contains

only one RC pin for two monostables. If step rates com-

parable to TON are commanded, incorrect pulsing can re-

sult, so consider maximum step rates when selecting RT

and CT. Keep TON ≤ T STEP MAX.

STEP: This logic input clocks the logic in the UC3517 on

every falling edge. Like all other UC3517 inputs, this input

is TTL/CMOS compatible, and should not be pulled below

ground.

DIR: This logic input controls the motor rotation direction

by controlling the phase output sequence as shown in

Figure 5. This signal must be stable 400ns before a falling

edge on STEP, and must remain stable through the edge

to insure correct stepping.

ØA and ØB: These logic outputs indicate half-step posi-

tion. These outputs are open-collector, low-current driv-

ers, and may directly drive TTL logic. They can also drive

CMOS logic if a pull-up resistor is provided. Systems

which use the UC3517 as an encoder and use a different

driver can use these outputs to disable the external driver,

HSM: This logic input switches the UC3517 between half-

stepping (HSM = low) and full-stepping (HSM = high) by

controlling the phase output sequence as show in Figure

5. This line requires the same set-up time as the DIR in-

put, and has the same hold requirement.

UC1517

UC3517

used in conjunction with discrete power transistors or

power driver ICs, like the L298. These can be connected

as current gain devices that turn on when the phase out-

puts turn on.

INH: When the inhibit input is high, the phase and θ out-

puts are inhibited (high impedance). STEP pulses re-

ceived while inhibited will continue to update logic in the

IC, but the states will not be reflected at the outputs until

inhibit is pulled low. In stepper motor systems, this can be

used to save power or to allow the rotor to move freely for

manual repositioning.

Bipolar Motor Drive: Bipolar motors can be controlled by

the UC3517 with the addition of bipolar integrated drivers

such as the UC3717A (Figure 8) and the L298, or discrete

devices. Care should be taken with discrete devices to

avoid potential cross-conduction problems.

OPERATING MODES

The UC3517 is a system component capable of many dif-

ferent operating modes, including:

LOGIC FLOW GRAPH

The UC3517 contains a bidirectional counter which is de-

coded to generate the correct phase and Ø outputs. This

counter is incremented on every falling edge of the STEP

input. Figure 5 shows a graph representing the counter

sequence, inputs that determine the next state (DIR and

HSM), and the outputs at each state. Each circle repre-

sents a unique logic state, and the four inside circles rep-

resent the half-step states.

Unipolar Stepper Driver: In its simplest form, the

UC3517 can be connected to a stepper motor as a unipo-

lar driver. LA, LB, RC and Vss are not used, and may be

left open. All other system design considerations men-

tioned above apply, including choice of motor supply

VMM, undershoot diodes and timing considerations.

Unipolar Bilevel Stepper Driver: If increased step rates

are desired, the application circuit of Figure 6 makes use

of the monostables and emitter followers as well as the

configuration mentioned above to provide high-voltage

pulses to the motor windings when the phase is turned

on. For a given dissipation level, this mode offers faster

step rates, and very little additional electrical noise.

The four bits inside the circles represent the phase out-

puts in each state (PA1, PA2, PB1, and PB2). For example,

the circle labeled 1010 is immediately entered when the

device is powered up, and represents PA1 off ("1" or

high), PA2 on ("0" or low), PB1 off ("1" or high) and PB2 on

("0" or low). The ØA and ØB outputs are both low (uniden-

tified).

The choice of monostable components can be estimated

based on the timing relationship of motor current and volt-

age: V = Ldl/dt. Assuming a fixed secondary supply volt-

age (VSS), a fixed winding inductance (LM), a desired

winding peak current (IW), and no back EMF from the mo-

tor, we can estimate that RTCT = 1.449 IWLM/VSS. In

practice, these calculations should be confirmed and ad-

justed to accommodate for effects not modeled.

The arrows in the graph show the state changes. For ex-

ample, if the IC is in state 0110, DIR is high, HSM is high,

and STEP falls, the next state will be 0101, and a pulse

will be generated on the LB line by the monostable.

Inhibit will not effect the logic state, but it will cause all

phase outputs and both Ø outputs to go high (off). A fall-

ing edge on STEP will still cause a state change, but in-

hibit will have to toggle low for the state to be apparent.

Voltage-Doubled Mode: The UC3517 can also be used

to generate higher voltages than available with the sys-

tem power supplies using capacitors and diodes. Figure 9

shows how this might be done, and gives some estimates

for the component values.

A falling edge on STEP with HSM high will cause the

counter to advance to the next full step state regardless

of whether or not it was in a full step state previously.

Higher Current Operation: For systems requiring more

than 350mA of drive per phase, the UC3717A can be

No LA or LB pulses are generated entering half-states.

UC1517

UC3517

Figure 5. Logic Flow Graph

For applications requiring very fast step rates, a zener diode not overshoot past 40V. If the zener diodes are not used and

permits windings to discharge at higher voltages, and higher UC3610 pin 2 is connected directly to Vss then higher Vss can

rates. Driver transistor breakdown must be considered when be used.

selecting Vss and zener voltage to insure that the outputs will

Figure 6. Bilevel Motor Driver

UC1517

UC3517

Experimental selection of RT and CT allow the designer to se- tion can be well controlled. Average power dissipation for the

lect a small amount of winding current overshoot, as shown driver and motor must be considered when designing sys-

above. Although the overshoot may exceed the continuous tems with intentional overshoot, and must stay within conser-

rated current of the winding and the drive transistors, the dura- vative limits for short duty cycles.

Figure 7. Effects of Different RT & CT on Bilevel Systems

In this application, the A and B outputs of the UC3517 are also allows half-step operation of the UC3717. Peak motor

connected to the current program inputs of the UC3717. This winding current will be limited to approximately .42V/R1 by

allows the UC3517 inhibit signal to inhibit the UC3717, and chopping.

Figure 8. Interface to UC3717 Bipolar Driver

UC1517

UC3517

Although component values can be best optimized experimentally, good starting values speed development. For this design,

start with: where:

RT CT = 3 LW/RW LW is winding inductance,

C1 = C2 = LW IR/RW

R1 = R2 = 2.9 TMIN/C1

RW is winding resistance,

IR is rated winding current, and

TMIN is minimum step period expected.

Figure 9. Using the UC3517 as a Voltage Doubler

UNITRODE INTEGRATED CIRCUITS

7 CONTINENTAL BLVD. • MERRIMACK, NH 03054

TEL. (603) 424-2410 • FAX (603) 424-3460

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UC3517N [TI]

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