UC3526AM [TI]
Regulating Pulse Width Modulator;
| 型号： | UC3526AM |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Regulating Pulse Width Modulator |
| 文件： | 总11页 (文件大小：614K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1526
UC2526
UC3526
Regulating Pulse Width Modulator
FEATURES
8 To 35V Operation
DESCRIPTION
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•
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The UC1526 is a high performance monolithic pulse width modulator
circuit designed for fixed-frequency switching regulators and other
power control applications. Included in an 18-pin dual-in-line pack-
age are a temperature compensated voltage reference, sawtooth os-
cillator, error amplifier, pulse width modulator, pulse metering and
setting logic, and two low impedance power drivers. Also included
are protective features such as soft-start and under-voltage lockout,
digital current limiting, double pulse inhibit, a data latch for single
pulse metering, adjustable deadtime, and provision for symmetry cor-
rection inputs. For ease of interface, all digital control ports are TTL
and B-series CMOS compatible. Active LOW logic design allows
wired-OR connections for maximum flexibility. This versatile device
can be used to implement single-ended or push-pull switching regu-
lators of either polarity, both transformerless and transformer cou-
pled. The UC1526 is characterized for operation over the full military
temperature range of -55°C to +125°C. The UC2526 is characterized
for operation from -25°C to +85°C, and the UC3526 is characterized
for operation from 0° to +70°C.
5V Reference Trimmed To ±1%
1Hz To 400kHz Oscillator Range
Dual 100mA Source/Sink Outputs
Digital Current Limiting
Double Pulse Suppression
Programmable Deadtime
Under-Voltage Lockout
Single Pulse Metering
Programmable Soft-Start
Wide Current Limit Common Mode Range
TTL/CMOS Compatible Logic Ports
Symmetry Correction Capability
Guaranteed 6 Unit Synchronization
BLOCK DIAGRAM
6/93
UC1526
UC2526
UC3526
ABSOLUTE MAXIMUM RATINGS (Note 1, 2)
RECOMMENDED OPERATING CONDITIONS (Note 3)
Input Voltage (+VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8V to +35V
Collector Supply Voltage (+VC) . . . . . . . . . . . . . . . . . . . . . +40V Collector Supply Voltage . . . . . . . . . . . . . . . . . . . +4.5V to +35V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V Sink/Source Load Current (each output) . . . . . . . . . 0 to 100mA
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +VIN Reference Load Current . . . . . . . . . . . . . . . . . . . . . . 0 to 20mA
Source/Sink Load Current (each output) . . . . . . . . . . . . . 200mA Oscillator Frequency Range . . . . . . . . . . . . . . . . 1Hz to 400kHz
Reference Load Current. . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Oscillator Timing Resistor . . . . . . . . . . . . . . . . . . . 2kΩ to 150kΩ
Logic Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA Oscillator Timing Capacitor . . . . . . . . . . . . . . . . . . . 1nF to 20µF
Power Dissipation at TA = +25°C (Note 2) . . . . . . . . . . 1000mW Available Deadtime Range at 40kHz. . . . . . . . . . . . . 3% to 50%
Power Dissipation at TC = +25°C (Note 2). . . . . . . . . . 3000mW Operating Ambient Temperature Range
Operating Junction Temperature . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (soldering, 10 seconds) . . . . . . . . . . +300°C
Note 1: Values beyond which damage may occur.
Note 2: Consult packaging section of databook for thermal
limitations and considerations of package.
UC1526 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
UC2526 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C
UC3526 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0°C to +70°C
Note 3: Range over which the device is functional and
parameter limits are guaranteed.
CONNECTION DIAGRAMS
PACKAGE PIN FUNCTION
DIL-18, SOIC-18 (TOP VIEW)
J or N Package, DW Package
PLCC-20, LCC-20
(TOP VIEW)
Q and L Packages
FUNCTION
PIN
N/C
1
2
3
4
+Error
-Error
Comp.
CSS
______
5
Reset
6
- Current Sense
7
+ Current Sense
_________
8
Shutdown
RTIMING
CT
RD
Sync
Output A
VC
N/C
Ground
Output B
+VIN
9
10
11
12
13
14
15
16
17
18
19
20
VREF
ELECTRICAL CHARACTERISTICS: +VIN = 15V, and over operating ambient temperature, unless otherwise
specified, TA = TJ.
PARAMETER
TEST CONDITIONS
UC1526 / UC2526
UC3526
TYP MAX
UNITS
MIN
TYP
MAX
MIN
Reference Section (Note 4)
Output Voltage
TJ = + 25°C
4.95
5.00
10
5.05
20
4.90
5.00
10
5.10
30
V
Line Regulation
+VIN = 8 to 35V
IL = 0 to 20mA
mV
mV
mV
V
Load Regulation
10
30
10
50
Temperature Stability
Over Operating TJ
15
50
15
50
Total Output
Voltage Range
Over Recommended
Operating Conditions
4.90
25
5.00
5.10
4.85
25
5.00
5.15
Short Circuit Current
VREF = 0V
50
100
0.4
50
100
0.4
mA
Under -Voltage Lockout
_______
RESET Output Voltage
VREF = 3.8V
VREF = 4.8V
0.2
4.8
0.2
4.8
V
V
2.4
2.4
Note 4: IL = 0mA.
2
UC1526
UC2526
UC3526
+VIN = 15V, and over operating ambient temperature, unless otherwise
specified, TA = TJ.
ELECTRICAL CHARACTERISTICS:
PARAMETER
TEST CONDITIONS
UC1526 / UC2526
UC3526
TYP MAX
UNITS
MIN
TYP
MAX
MIN
Oscillator Section (Note 5)
Initial Accuracy
TJ = + 25°C
+VIN = 8 to 35V
±3
0.5
7
±8
1
±3
0.5
3
±8
1
%
%
Voltage Stability
Temperature Stability
Minimum Frequency
Maximum Frequency
Sawtooth Peak Voltage
Sawtooth Valley Voltage
Error Amplifier Section (Note 6)
Input Offset Voltage
Input Bias Current
Over Operating TJ
RT = 150kΩ, CT = 20µF
RT = 2kΩ, CT = 1.0nF
+VIN = 35V
10
1
5
%
1
Hz
kHz
V
400
0.5
400
0.5
3.0
1.0
3.5
3.0
1.0
3.5
+VIN = 8V
V
RS ≤ 2kΩ
2
5
2
10
mV
nA
nA
dB
V
-350 -1000
-350 -2000
Input Offset Current
DC Open Loop Gain
HIGH Output Voltage
35
72
100
35
72
200
RL ≥ 10MΩ
64
60
VPIN1-VPIN2 ≥ 150mV, ISOURCE =
100µA
3.6
4.2
3.6
4.2
LOW Output Voltage
Common Mode Rejection
Supply Voltage Rejection
PWM Comparator (Note 5)
Minimum Duty Cycle
VPIN2-VPIN1 ≥ 150mV, ISINK = 100µA
Rs ≤ 12kΩ
0.2
94
80
0.4
0.2
94
80
0.4
V
70
66
70
66
dB
dB
+VIN = 12 to 18V
VCOMPENSATION = +0.4V
VCOMPENSATION = +3.6V
0
0
%
%
Maximum Duty Cycle
45
49
45
49
Digital Ports (SYNC, SHUTDOWN, and RESET)
HIGH Output Voltage
LOW Output Voltage
HIGH Input Current
LOW Input Current
ISOURCE =40µA
ISINK = 3.6mA
VIH = +2.4V
2.4
4.0
0.2
2.4
4.0
0.2
V
V
0.4
0.4
-125
-225
-200
-360
-125
-225
-200
-360
µA
µA
VIL = +0.4V
Current LImit Comparator (Note 7)
Sense Voltage
RS ≤ 50Ω
90
50
100
-3
110
-10
80
50
100
-3
120
-10
mV
Input Bias Current
µA
Soft-Start Section
Error Clamp Voltage
Cs Charging Current
RESET = +0.4V
RESET =+2.4V
0.1
0.4
0.1
0.4
V
100
150
100
150
µA
Output Drivers (Each Output) (Note 8)
HIGH Output Voltage
ISOURCE = 20mA
12.5
12
13.5
13
12.5
12
13.5
13
V
V
ISOURCE = 100mA
ISINK = 20mA
ISINK = 100mA
VC = 40V
LOW Output Voltage
0.2
1.2
50
0.3
2.0
150
0.6
0.2
0.2
1.2
50
0.3
2.0
150
0.6
0.2
V
V
Collector Leakage
Rise Time
µA
µs
µs
CL = 1000pF
CL = 1000pF
0.3
0.1
0.3
0.1
Fall Time
Power Consumption (Note 9)
Standby Current
____________
SHUTDOWN = +0.4V
18
30
18
30
mA
Note 4: IL = 0mA.
Note 5: FOSC = 40kHz (RT = 4.12kΩ ± 1%, CT = 0.1µF ± 1%,
RD = 0Ω)
Note 6: VCM = 0 to +5.2V
Note 8: VC = +15V
Note 9: +VIN = +35V, RT = 4.12kΩ
3
UC1526
UC2526
UC3526
APPLICATIONS INFORMATION
Voltage Reference
The reference regulator of the UC1526 is based on a tem-
perature compensated zener diode. The circuitry is fully
active at supply voltages above +8V, and provides up to
20mA of load current to external circuitry at +5.0V. In sys-
tems where additional current is required, an external
PNP transistor can be used to boost the available current.
A rugged low frequency audio-type transistor should be
used, and lead lengths between the PWM and transistor
should be as short as possible to minimize the risk of os-
cillations. Even so, some types of transistors may require
collector-base capacitance for stability. Up to 1 amp of
load current can be obtained with excellent regulation if
the device selected maintains high current gain.
Figure 2. Under-Voltage Lockout Schematic
Soft-Start Circuit
The soft-start circuit protects the power transistors and
rectifier diodes from high current surges during power
supply turn-on. When supply voltage is first applied to the
_______
UC1526, the under-voltage lockout circuit holds RESET
LOW with Q3. Q1 is turned on, which holds the soft-start
capacitor voltage at zero. The second collector of Q1
clamps the output of the error amplifier to ground, guaran-
teeing zero duty cycle at the driver outputs. When the
_______
supply voltage reaches normal operating range, RESET
will go HIGH. Q1 turns off, allowing the internal 100mA
current source to charge CS. Q2 clamps the error ampli-
fier output to 1VBE above the voltage on CS. As the soft-
Figure 1. Extending Reference Output Current
Under-Voltage Lockout
The under-voltage lockout circuit protects the UC1526 start voltage ramps up to +5V, the duty cycle of the PWM
and the power devices it controls from inadequate supply linearly increases to whatever value the voltage regula-
voltage, If +VIN is too low, the circuit disables the output tion loop requires for an error null.
_______
drivers and holds the RESET pin LOW. This prevents
spurious output pulses while the control circuitry is stabi-
lizing, and holds the soft-start timing capacitor in a dis-
charged state.
The circuit consists of a +1.2V bandgap reference and
comparator circuit which is active when the reference
voltage has risen to 3VBE or +1.8V at 25°C. When the ref-
erence voltage rises to approximately +4.4V, the circuit
_______
enables the output drivers and releases the RESET pin,
allowing a normal soft-start. The comparator has 200mV
of hysteresis to minimize oscillation at the trip point.
When +VIN to the PWM is removed and the reference
_______
drops to +4.2V, the under-voltage circuit pulls RESET
LOW again. The soft-start capacitor is immediately dis-
charged, and the PWM is ready for another soft-start cy-
cle.
Figure 3. Soft-Start Circuit Schematic
Digital Control Ports
The three digital control ports of the UC1526 are bi-direc-
tional. Each pin can drive TTL and 5V CMOS logic di-
rectly, up to a fan-out of 10 low-power Schottky gates.
Each pin can also be directly driven by open-collector
The UC1526 can operate from a +5V supply by connect-
ing the VREF pin to the +VIN pin and maintaining the sup-
ply between +4.8 and +5.2V.
4
UC1526
UC2526
UC3526
APPLICATIONS INFORMATION (cont.)
TTL, open-drain CMOS, and open-collector voltage com-
parators; fan-in is equivalent to 1 low-power Schottky
Multiple devices can be synchronized together by pro-
gramming one master unit for the desired frequency and
then sharing its sawtooth and clock waveforms with the
gate. Each port is normally HIGH; the pin is pulled LOW
______
to activate the particular function. Driving SYNC LOW in-
slave units. All CT terminals are connected to the CT pin
______
itiates a discharge cycle in the oscillator. Pulling
____________
of the master, and all SYNC terminals are likewise con-
______
SHUTDOWN LOW immediately inhibits all PWM output
_______
nected to the SYNC pin of the master. Slave RT termi-
nals are left open or connected to VREF. Slave RD
terminals may be either left open or grounded.
pulses. Holding RESET LOW discharges the soft-start
capacitor. The logic threshold is +1.1V at +25°C. Noise
immunity can be gained at the expense of fan-out with an
external 2k pull-up resistor to +5V.
Error Amplifier
The error amplifier is a transconductance design, with an
output impedance of 2MΩ . Since all voltage gain takes
place at the output pin, the open-loop gain/frequency
characteristics can be controlled with shunt reactance to
ground. When compensated for unity-gain stability with
100pF, the amplifier has an open-loop pole at 800Hz.
The input connections to the error amplifier are deter-
mined by the polarity of the switching supply output volt-
age. For positive supplies, the common-mode voltage is
+5.0V and the feedback connections in Figure 6A are
used. With negative supplies, the common-mode voltage
is ground and the feedback divider is connected between
the negative output and the +5.0V reference voltage, as
shown in Figure 6B.
Figure 4. Digital Control Port Schematic
Oscillator
The oscillator is programmed for frequency and dead time
with three components: RT, CT and RD. Two waveforms
are generated: a sawtooth waveform at pin 10 for pulse
width modulation, and a logic clock at pin 12. The follow-
ing procedure is recommended for choosing timing val-
ues:
Output Drivers
The totem-pole output drivers of the UC1526 are de-
signed to source and sink 100mA continuously and
200mA peak. Loads can be driven either from the output
pins 13 and 16, or from the +VC, as required.
Since the bottom transistor of the totem-pole is allowed to
saturate, there is a momentary conduction path from the
+VC terminal to ground during switching. To limit the re-
sulting current spikes a small resistor in series with pin 14
is always recommended. The resistor value is deter-
mined by the driver supply voltage, and should be chosen
for 200mA peak currents.
1. With RD = 0 (pin 11 shorted to ground) select values
for RT and CT from Figure 7 to give the desired oscillator
period. Remember that the frequency at each driver out-
put is half the oscillator frequency, and the frequency at
the +VC terminal is the same as the oscillator frequency.
2. If more dead time is required, select a large value of
RD. At 40kHz dead time increases by 400ns/Ω .
3. Increasing the dead time will cause the oscillator fre-
quency to decrease slightly. Go back and decrease the
value of RT slightly to bring the frequency back to the
nominal design value.
The UC1526 can be synchronized to an external logic
clock by programming the oscillator to free-run at a fre-
quency 10% slower than the sync frequency. A periodic
______
LOW logic pulse approximately 0.5µs wide at the SYNC
pin will then lock the oscillator to the external frequency.
Figure 5. Oscillator Connections and Waveforms
5
UC1526
UC2526
UC3526
Figure 6. Error Amplifier Connections
Figure 8. Single-Ended Configuration
Figure 7. Push-Pull Configuration
Figure 9. Driving N-channel Power Mosfets
TYPICAL CHARACTERISTICS
Oscillator Period vs RT and CT
Oscillation Period
6
UC1526
UC2526
UC3526
TYPICAL CHARACTERISTICS
Output Driver Deadtime vs RD Value
Under Voltage Lockout Characteristic
Error Amplifier Open Loop Gain vs Frequency
Current Limit Transfer Function
Shutdown Delay
Output Driver Saturation Voltage
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
7
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2005
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CDIP
CDIP
LCCC
LCCC
CDIP
PDIP
Drawing
85515012A
8551501VA
UC1526J
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
18
18
18
20
20
18
18
1
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE Level-NC-NC-NC
A42 SNPB
A42 SNPB
A42 SNPB
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
J
UC1526J883B
UC1526L
J
FK
FK
J
POST-PLATE Level-NC-NC-NC
POST-PLATE Level-NC-NC-NC
UC1526L883B
UC2526J
A42 SNPB
Level-NC-NC-NC
UC2526N
N
20 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
UC2526NG4
UC3526DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
N
18
18
18
18
18
20 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
DW
DW
DW
DW
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC3526DWG4
UC3526DWTR
UC3526DWTRG4
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC3526J
UC3526N
ACTIVE
ACTIVE
CDIP
PDIP
J
18
18
1
TBD
A42 SNPB
Level-NC-NC-NC
N
20 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
UC3526NG4
ACTIVE
PDIP
N
18
20 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2005
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
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