UC3872Q [TI]

FLUORESCENT LIGHT CONTROLLER, 200kHz SWITCHING FREQ-MAX, PQCC20;
UC3872Q
型号: UC3872Q
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

FLUORESCENT LIGHT CONTROLLER, 200kHz SWITCHING FREQ-MAX, PQCC20

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application  
INFO  
UC1872  
UC2872  
UC3872  
available  
Resonant Lamp Ballast Controller  
FEATURES  
DESCRIPTION  
Controls Different Types of Lamps:  
Cold Cathode Fluorescent, Neon, and  
Gas Discharge  
The UC3872 is a resonant lamp ballast controller optimized for driving  
cold cathode fluorescent, neon, and other gas discharge lamps. The res-  
onant power stage develops a sinusoidal lamp drive voltage, and mini-  
mizes switching loss and EMI generation. Lamp intensity adjustment is  
accomplished with a buck regulator, which is synchronized to the external  
power stage’s resonant frequency. Suitable for automotive and battery  
powered applications, the UC3872 draws only 1µA when disabled.  
Zero Voltage Switching (ZVS) of  
Push-Pull Drivers  
Accurate Control of Lamp Current  
Variable Lamp Intensity Control  
1µA Disable Current  
Soft start and open lamp detect circuitry have been incorporated to mini-  
mize component stresses. Open lamp detection is enabled at the comple-  
tion of a soft start cycle. The chip is optimized for smooth duty cycle  
control to 100%.  
4.5V to 24V Operation  
Other features include a precision 1.2% reference, undervoltage lockout,  
and accurate minimum and maximum frequency control.  
Open Lamp Detection Circuitry  
BLOCK DIAGRAM  
3
2
VC  
3.0V  
REF  
AOUT  
VCC 10  
UVLO  
50k  
REF  
9
(HIGH=ENABLE)  
PUSH PULL  
OUTPUTS  
ENBL 11  
N-CHANNEL  
0.1V  
+
COMP  
INV  
4
6
TOGGLE  
T
OPEN  
LAMP  
DETECT  
1
BOUT  
EA  
20µA  
+
50k  
50k  
1.5V  
PWM  
1
+
SS  
CT  
ZD  
5
7
8
200µA  
R
S
0.2V  
OSCILLATOR  
SENSE  
OUT  
12 COUT  
ZERO DETECT  
BUCK DRIVE  
P-CHANNEL  
SYNC  
0.5V  
+
13 PGND  
14  
GND  
UDG-99112  
Note: Pin numbers shown are for DIP package.  
07/99  
UC1872  
UC2872  
UC3872  
CONNECTION DIAGRAMS  
ABSOLUTE MAXIMUM RATINGS  
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 to +10V  
VCC, VC Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +24V  
ZD Input Current  
SOIC-16, SSOP-16 (TOP VIEW)  
DW, M Package  
High Impedance Source . . . . . . . . . . . . . . . . . . . . . . +10mA  
ZD Input Voltage  
Low Impedance Source . . . . . . . . . . . . . . . . . . . . . . . . +24V  
Power Dissipation at TA = 25°C . . . . . . . . . . . . . . . . . . . . . . 1W  
Storage Temperature . . . . . . . . . . . . . . . . . . . 65°C to +150°C  
Lead Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C  
Note 1: Currents are positive into, negative out of the specified  
terminal.  
Note 2: Consult Packaging Section of Databook for thermal limi-  
tations and considerations of package.  
DIL-14 (TOP VIEW)  
N Package  
PLCC-20 (Top View)  
Q Package  
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these parameters apply for TJ = 55°C to +125°C for the  
UC1872, –40°C to +85°C for the UC2872, 0°C to +70°C for the UC3872; VCC= 5V, VC = 15V, VENBL = 5V, CT = 1nF, ZD = 1V.  
PARAMETER  
Reference Section  
TEST CONDITIONS  
MIN  
TYP  
MAX UNITS  
Output Voltage  
TJ = 25°C  
2.963 3.000 3.037  
V
V
Over Temperature  
VCC = 4.75V to 18V  
IO = 0 to 5mA  
2.940 3.000 3.060  
Line Regulation  
Load Regulation  
10  
10  
mV  
mV  
Oscillator Section  
Free Running Frequency  
Maximum Synchronization Frequency  
Charge Current  
TJ = 25°C  
TJ = 25°C  
VCT = 1.5V  
57  
68  
78  
240  
220  
2
kHz  
kHz  
µA  
%
160  
180  
200  
200  
Voltage Stability  
Temperature Stability  
Zero Detect Threshold  
Error Amp Section  
Input Voltage  
4
8
%
0.46  
0.5  
0.56  
V
VO = 2V  
1.445 1.475 1.505  
V
µA  
dB  
V
Input Bias Current  
Open Loop Gain  
0.4  
90  
2  
VO = 0.5 to 3V  
VINV = 1.3V  
65  
Output High  
3.1  
3.5  
3.9  
2
UC1872  
UC2872  
UC3872  
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these parameters apply for TJ = 55°C to +125°C for the  
UC1872, –40°C to +85°C for the UC2872, 0°C to +70°C for the UC3872; VCC= 5V, VC = 15V, VENBL = 5V, CT = 1nF, ZD = 1V.  
PARAMETER  
Error Amp Section (cont.)  
Output Low  
TEST CONDITIONS  
MIN  
TYP  
MAX UNITS  
V
INV = 1.7V  
0.1  
0.2  
V
µA  
Output Source Current  
Output Sink Current  
VINV = 1.3V, VO = 2V  
VINV = 1.7V, VO = 2V  
–350 –500  
10  
0
20  
1
mA  
V
Common Mode Range  
Unity Gain Bandwidth  
Open Lamp Detect Section  
Soft Start Threshold  
Open Lamp Detect Threshold  
Soft Start Current  
VIN-1V  
TJ = 25°C (Note 4)  
MHz  
V
INV = 0V  
2.9  
0.6  
10  
3.4  
1.0  
20  
3.8  
1.4  
40  
V
V
VSS = 4.2V  
VSS = 2V  
µA  
Output Section  
Output Low Level  
IOUT = 0, Outputs A and B  
IOUT = 10mA  
0.05  
0.1  
0.2  
0.4  
2.2  
V
V
IOUT = 100mA  
1.5  
V
Output High Level  
IOUT = 0, Output C  
IOUT = 10mA  
13.9  
13.5  
12.5  
14.9  
14.3  
13.5  
30  
V
V
IOUT = 100mA  
V
Rise Time  
TJ = 25°C, Cl = 1nF (Note 4)  
TJ = 25°C, Cl = 1nF (Note 4)  
80  
80  
ns  
ns  
Fall Time  
30  
Output Dynamics  
Out A and B Duty Cycle  
Out C Max Duty Cycle  
Out C Min Duty Cycle  
Under Voltage Lockout Section  
Startup Threshold Voltage  
Hysteresis  
48  
49.9  
50  
0
%
%
%
VINV = 1V  
VINV = 2V  
100  
3.7  
4.2  
4.5  
V
120  
200  
280  
mV  
Enable Section  
Input High Threshold  
Input Low Threshold  
Input Current  
2
V
V
0.8  
VENBL = 5V  
150  
400  
µA  
Supply Current Section  
VCC Supply Current  
VC Supply Current  
ICC Disabled  
VCC = 24V  
6
5
1
14  
12  
10  
mA  
mA  
µA  
VC = 24V  
VCC = 24V, VENBL = 0V  
Note 3: Unless otherwise specified, all voltages are with respect to ground. Currents are positive into, and negative out of the  
specified terminal.  
Note 4: Guaranteed by design. Not 100% tested in production.  
3
UC1872  
UC2872  
UC3872  
PIN DESCRIPTIONS  
AOUT, BOUT: These outputs provide complementary  
drive signals for the push-pull N-channel MOSFETs.  
Each one is high for 50% of the time, switching states  
each time a zero-detect is sensed.  
INV: This pin is the inverting input to the error amplifier  
and the input for the open lamp detect circuitry. If the  
voltage at INV is below the 1V open lamp detect thresh-  
old, the outputs are disabled.  
PGND: This pin is the high current ground connection for  
the three output drivers.  
COMP: COMP is the output terminal of the error ampli-  
fier. Compensation components are normally connected  
between COMP and INV. Connecting a capacitor from  
this pin to ground limits turn on current and blanks the  
open lamp detect signal allowing the lamp to start.  
REF: This pin is connected to the 3V reference voltage  
which is used for the internal logic. Bypass REF to  
ground with a 0.01µF ceramic capacitor for proper opera-  
tion.  
COUT: This output directly drives the bulk regulator  
P-channel MOSFET. COUT turn-on is synchronized to  
each zero-detect, and therefore switches at twice the fre-  
quency of AOUT and BOUT. The modulator controlling  
COUT is designed to provide smooth control up to 100%  
duty cycle.  
VC: VC is the power supply voltage connection for the  
output drivers. Bypass it to ground with a 0.1µF ceramic  
capacitor for proper operation.  
VCC: VCC is the positive supply voltage for the chip. Its  
operating range is from 4.2V to 24V. Bypass VCC to  
ground with a 0.1µF ceramic capacitor for proper opera-  
tion.  
CT: A capacitor connected between this pin and GND  
ground sets the synchronization frequency range. The  
capacitor is charged with approximately 200µA, creating  
a linear ramp which is used by COUT’s (buck regulator  
driver) PWM comparator.  
ZD: The zero-detect input senses when the trans-  
former’s primary center tap voltage falls to zero to syn-  
chronize the sawtooth voltage waveform on CT. The  
threshold is approximately 0.5V, providing a small  
amount of offset such that with propagation delay,  
zero-volt switching occurs. A resistor (typically 10k)  
should be connected between ZD and the primary cen-  
ter tap to limit input current at turn off.  
ENBL: When ENBL is driven high the device is enabled.  
When ENBL is pulled low, the IC is shut down and typi-  
cally draws 1µA.  
GND: This pin is the ground reference point for the inter-  
nal reference and all thresholds.  
APPLICATION INFORMATION  
Figure 1 shows a complete application circuit using the  
UC3872 Resonant Lamp Ballast Controller. The IC pro-  
vides all drive, control and housekeeping functions. The  
buck output voltage (transformer center-tap) provides the  
zero crossing and synchronization signals.  
form falls to zero. The actual threshold is 0.5 volts,  
providing a small amount of anticipation to offset propa-  
gation delay.  
The synchronization pulse width is the time required for  
the 4mA current sink to discharge the timing capacitor to  
0.1 volts. This pulse width limits the minimum linear con-  
trol range of the buck regulator. The 200µA current  
source charges the capacitor to a maximum of 3 volts. A  
comparator blanks the zero detect signal until the capac-  
itor voltage exceeds 1 volt, preventing multiple synchro-  
nization pulse generation and setting the maximum  
frequency. If the capacitor voltage reaches 3 volts (a zero  
detection has not occurred) an internal clock pulse is  
generated to limit the minimum frequency.  
The buck modulator drives a P-channel MOSFET di-  
rectly, and operates over a 0-100% duty-cycle range.  
The modulation range includes 100%, allowing operation  
with minimal headroom.  
The oscillator and synchronization circuitry are shown in  
Figure 2. The oscillator is designed to synchronize over a  
3:1 frequency range. In an actual application however,  
the frequency range is only about 1.5:1. A zero detect  
comparator senses the primary center-tap voltage, gen-  
erating a synchronization pulse when the resonant wave-  
4
UC1872  
UC2872  
UC3872  
APPLICATION INFORMATION (cont.)  
A unique protection feature incorporated in the UC3872  
is the Open Lamp Detect circuit. An open lamp interrupts  
the current feedback loop and causes very high second-  
ary voltage. Operation in this mode will usually break-  
down the transformer’s insulation, causing permanent  
damage to the converter. The open lamp detect circuit,  
shown in Figure 3 senses the lamp current feedback sig-  
nal at the error amplifier’s input, and shuts down the out-  
puts if insufficient signal is present. Soft start circuitry  
limits initial turn-on currents and blanks the open lamp  
detect signal.  
Other features are included to minimize external circuitry  
requirements. A logic level enable pin shuts down the IC,  
allowing direct connection to a battery. During shut-  
down, the IC typically draws less than 1µA. The UC3872,  
operating from 4.5V to 24V, is compatible with almost all  
battery voltages used in portable computers and auto-  
motive applications. Undervoltage lockout circuitry dis-  
ables operation until sufficient supply voltage is  
available, and a 1% voltage reference insures accurate  
operation.  
UDG-93018-2  
Figure 1. Typical application.  
5
UC1872  
UC2872  
UC3872  
APPLICATIONS INFORMATION  
DISCHARGE  
COMPARATOR  
0.1V  
200µA  
+
MIN FREQ  
CT  
7
R
S
COMPARATOR  
+
Q
3.0V  
MAX FREQ  
COMPARATOR  
4mA  
+
ZD  
1.0V  
0.5V  
CLK  
ZERO DETECT  
8
+
UDG-99005  
Figure 2. UC3872 oscillator section.  
Figure 3. UC3872 open lamp detect circuitry.  
UNITRODE CORPORATION  
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054  
TEL. (603) 424-2410 FAX (603) 424-3460  
6
PACKAGE OPTION ADDENDUM  
www.ti.com  
4-May-2009  
PACKAGING INFORMATION  
Orderable Device  
UC2872DW  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SOIC  
DW  
16  
16  
16  
16  
14  
14  
20  
20  
16  
16  
16  
16  
16  
16  
16  
16  
14  
14  
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
UC2872DWG4  
UC2872DWTR  
UC2872DWTRG4  
UC2872N  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
PLCC  
PLCC  
SOIC  
SOIC  
SOIC  
SOIC  
DW  
DW  
DW  
N
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
25 Green (RoHS & CU NIPDAU N / A for Pkg Type  
no Sb/Br)  
UC2872NG4  
UC2872Q  
N
25 Green (RoHS & CU NIPDAU N / A for Pkg Type  
no Sb/Br)  
FN  
46 Green (RoHS &  
no Sb/Br)  
CU SN  
Level-2-260C-1 YEAR  
UC2872QG3  
UC3872DW  
FN  
46 Green (RoHS &  
no Sb/Br)  
CU SN  
Level-2-260C-1 YEAR  
DW  
DW  
DW  
DW  
DBQ  
DBQ  
DBQ  
DBQ  
N
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
UC3872DWG4  
UC3872DWTR  
UC3872DWTRG4  
UC3872M  
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
SSOP/  
QSOP  
75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
UC3872MG4  
UC3872MTR  
UC3872MTRG4  
UC3872N  
SSOP/  
QSOP  
75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
SSOP/  
QSOP  
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
SSOP/  
QSOP  
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
PDIP  
25 Green (RoHS & CU NIPDAU N / A for Pkg Type  
no Sb/Br)  
UC3872NG4  
PDIP  
N
25 Green (RoHS & CU NIPDAU N / A for Pkg Type  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
4-May-2009  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
29-Jul-2008  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) W1 (mm)  
(mm) (mm) Quadrant  
UC2872DWTR  
UC3872DWTR  
UC3872MTR  
SOIC  
SOIC  
DW  
DW  
16  
16  
16  
2000  
2000  
2500  
330.0  
330.0  
330.0  
16.4  
16.4  
12.4  
10.85  
10.85  
6.4  
10.8  
10.8  
5.2  
2.7  
2.7  
2.1  
12.0  
12.0  
8.0  
16.0  
16.0  
12.0  
Q1  
Q1  
Q1  
SSOP/  
QSOP  
DBQ  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
29-Jul-2008  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
UC2872DWTR  
UC3872DWTR  
UC3872MTR  
SOIC  
SOIC  
DW  
DW  
16  
16  
16  
2000  
2000  
2500  
346.0  
346.0  
346.0  
346.0  
346.0  
346.0  
33.0  
33.0  
29.0  
SSOP/QSOP  
DBQ  
Pack Materials-Page 2  
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