UC3902D [TI]
LOAD SHARE CONTROLLER;
| 型号： | UC3902D |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOAD SHARE CONTROLLER 光电二极管 |
| 文件： | 总10页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC2902
UC3902
SLUS232E − DECEMBER 19, 2002 − REVISED JULY 2011
LOAD SHARE CONTROLLER
FEATURES
DESCRIPTION
D
D
D
D
2.7-V to 20-V Operation
The UC3902 load share controller is an 8-pin
8-Pin Package
device that balances the current drawn from
independent, paralleled power supplies. Load
sharing is accomplished by adjusting each
supplies’ output current to a level proportional to
the voltage on a share bus.
Requires Minimum Number of External
Components
Compatible with Existing Power Supply
Designs Incorporating Remote Output
Voltage Sensin
The master power supply, which is automatically
designated as the supply that regulates to the
highest voltage, drives the share bus with a
voltage proportional to its output current. The
UC3902 trims the output voltage of the other
paralleled supplies so that they each support their
share of the load current. Typically, each supply is
designed for the same current level although that
is not necessary for use with the UC3902. By
appropriately scaling the current sense resistor,
supplies with different output current capability
can be paralleled with each supply providing the
same percentage of their output current capability
for a particular load.
D
D
D
D
Differential Share Bus
Precision Current Sense Amplifier (40 Gain)
UVLO (Undervoltage Lockout) Circuitry
User Programmable Share Loop
Compensation
APPLICATIONS
D
Paralelled Power Supplies
GND
1
8
VCC
BIAS
UVLO
−
SHARE DRIVE AMPLIFIER
+
40R
R
SENSE
2
−
7
6
SHARE+
+
+
CURRENT SENSE
AMPLIFIER
SHARE SENSE AMPLIFIER
−
SHARE−
ERROR AMPLIFIER
+
ADJ
3
4
+
35 mV
0.6 V
−
ADJ AMPLIFIER
+
+
5
COMP
−
2.3 V
ADJR
UDG−01141
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2002 − 2008, Texas Instruments Incorporated
1
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UC2902
UC3902
SLUS232E − DECEMBER 19, 2002 − REVISED JULY 2011
DESCRIPTION (continued)
A differential line is used for the share bus to maximize noise immunity and accommodate different voltage drops
in each power converter’s ground return line. Trimming of each converter’s output voltage is accomplished by
injecting a small current into the output voltage sense line, which requires a small resistance (typically 20 Ω to
100 Ω) to be inserted.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range unless otherwise noted
UC2902
UNIT
UC3902
VCC, ADJ
SENSE
−0.3 to 20
−5 to 5
Input voltage range, V
V
I
ADJR, COMP
SHARE−, SHARE+
SHARE+
−0.3 to 4
−0.3 to 10
−100 mA to 10 mA
−1 mA to 30 mA
−40 to 100
−55 to 105
−65 to 150
300
mA
mA
Output current, I
O
ADJ
Operating free-air temperature range, T
A
Junction temperature range, T
J
°C
Storage temperature, T
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Voltages are with respect to
GND. Currents are positive into, and negative out of the specified terminal.
2
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UC2902
UC3902
SLUS232E − DECEMBER 19, 2002 − REVISED JULY 2011
ELECTRICAL CHARACTERISTICS
T = –40°C to 105°C, (unless otherwise noted)
J
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power SUPPLY SUPPLY CURRENT
SHARE+ = 1 V,
= 20 V
SENSE = 0 V
4
6
6
I
Supply current
mA
CC
V
10
CC
UNDERVOLTAGE LOCKOUT
V
CC
Startup voltage
Hysteresis
SHARE+ = 0.2 V, SENSE = 0 V, COMP = 1 V
SHARE+ = 0.2 V, SENSE = 0 V, COMP = 1 V
2.3
60
2.5
2.7
V
100
140
mV
CURRENT SENSE AMPLIFIER
V
Input offset voltage
SENSE to SHARE gain
Input resistance
0.1 V ≤ V
0.1 V ≤ V
≤ 1.1 V
≤ 1.1 V
−2.5
−41
0.6
−0.5
−40
1
1.5
−39
1.5
mV
V
IO
(SHARE+)
(SHARE+)
R
V
IN
SHARE DRIVE AMPLIFIER
V
= 2.5 V
V
V
V
V
V
V
= −50 mV
= −250 mV
= −250 mV
= 10 mV
CC
(SENSE)
(SENSE)
(SENSE)
(SENSE)
(SENSE)
(SENSE)
1.2
9.6
9.6
1.4
10.0
10.0
20
I
= −1 mA
(SHARE+)
V
I
= 12 V
High-level output voltage,
SHARE+
CC
10.4
10.4
50
V
OH
V
= −1 mA
= −1 mA
(SHARE+)
V
CC
= 20 V
I
(SHARE+)
V
CC
= 2.5 V
I
= −1 mA
(SHARE+)
V
CC
= 12 V
= 10 mV
20
50
V
V
Low-level output voltage, SHARE+
OL
I
= −1 mA
(SHARE+)
mV
dB
V
CC
= 20 V
= 10 mV
20
50
I
= −1 mA
(SHARE+)
V
= 0 mV,
R
= 200 Ω
(SENSE)
(SHARE+)
Output voltage, SHARE+
20
40
O
(SHARE+ to GND)
0 V ≤ V ≤ 1 V,
SENSE used as input to amplifier
(SHARE−)
CMRR
Common mode rejection ratio
50
90
Load on SHARE+, 1 mA ≤ I
≤ −20 mA
LOAD
Load regulation
0
−50
0.26
20
−20
0.38
mV
mA
V
V
V
= −25 mV
(SENSE)
I
Short circuit current
= 0 V,
V = −25 mV
(SENSE)
−85
SC
(SHARE+)
= 10 mV to −90 mV step
(SENSE)
0.12
R
= 200 Ω (SHARE+ to GND)
(SHARE+)
Slew rate
V/μs
V
= −90 mV to 10 mV step
(SENSE)
0.12
0.26
0.38
R
= 200 Ω (SHARE+ to GND)
(SHARE+)
3
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UC2902
UC3902
SLUS232E − DECEMBER 19, 2002 − REVISED JULY 2011
ELECTRICAL CHARACTERISTICS (continued)
T = –40°C to 105°C, (unless otherwise noted)
J
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SHARE SENSE AMPLIFIER
V
V
= 1 V,
= 10 mV
V
= GND
(SHARE+)
(SHARE−)
8
8
15
15
(SENSE)
R
Input impedance
kΩ
IN
R
= 200 Ω (SHARE+ to GND)
= 1 V,
(SHARE+)
V
V
= 10 mV
(SHARE−)
(SENSE)
V
Threshold voltage
V
= 0 V
(SENSE)
41
50
70
60
100
mV
(SHARE)
CMRR
Common mode rejection ratio
0 V ≤ V
≤ 1 V, V
= −2.5 mV
(SHARE−)
(SENSE)
V
= −2.5 mV,
(SENSE)
5 nF capacitor from COMP to GND,
1 kΩ resistor from ADJR to GND
50
50
68
66
dB
DESCRIPTION from SHARE+ to
ADJR
AVOL
V
= −2.5 mV,
(SENSE)
5 nF capacitor from COMP to GND,
150 Ω resistor from ADJR to GND
V
= 0 mV to 10 V step through a 200-Ω
(SHARE+)
Slew rate
resistor, R
= 500 Ω,
0.2
0.5
0.8
V/μs
(COMP)
V
= 10 mV, V = 10 V
(SENSE)
CC
ERROR AMPLIFIER
Transconductance, SHARE+ to
COMP
g
M
200-Ω resistor SHARE+ to GND
3.0
4.5
6.0
mS
V
V
= 1.5 V, SHARE+ ≥ 300 mV
= −10 mV
(COMP)
I
I
High-level output current
−450
−325
−200
OH
(SENSE)
μA
200-Ω resistor SHARE+ to GND,
= 1.5 V, = 10 mV
Low-level output current
Input offset voltage
80
15
−6
150
35
0
250
65
6
OL
V
V
(SENSE)
(COMP)
V
mV
IO
ΔV
ΔV
/
1-kΩ resistor ADJR to GND
−2.5 mV ≤ V ≤ −25 mV
IO
(SENSE)
mV/V
(SENSE)
ADJ AMPLIFIER
200-Ω resistor SHARE+ to GND,
ADJR low voltage
−1
1.4
0
1.8
1
2.1
mV
V
V
= 10 mV
(SENSE)
ADJR high voltage
V
= 10 mV,
V
= 1 V
= 1 V
= 1 V
= 1 V
= 1 V
(SENSE)
(SHARE+)
I
= −0.5 mA,
= 10 mV,
V
V
= 2.5 V,
(ADJR)
(ADJ)
0.96
0.99
1.02
V
(SENSE)
(SHARE+)
I
= −0.5 mA,
= 10 mV,
V
V
= 20 V,
(ADJR)
(ADJ)
0.96
0.96
0.96
0.99
0.99
0.99
1.02
1.02
1.02
V
(SENSE)
(SHARE+)
Current gain ADJR to ADJ
A/A
I
= −10 mA,
= 10 mV,
V
V
= 2.5 V,
(ADJR)
(ADJ)
V
(SENSE)
(SHARE+)
I
= −10 mA,
= 10 mV,
V
V
= 20 V,
(ADJR)
(ADJ)
V
(SENSE)
(SHARE+)
4
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UC2902
UC3902
SLUS232E − DECEMBER 19, 2002 − REVISED JULY 2011
ORDERING INFORMATION
(2)
T
A
PACKAGE
PART NUMBER
SOIC (D)
Plastic DIP (N)
SOIC (D)
UC2902D
UC2902N
UC3902D
UC3902N
−40°C to 85°C
0°C to 70°C
Plastic DIP (N)
(2)
The D package is also available taped and reeled. Add an R suffix to the device type (i.e., bq24901DR) for quantities of 3,000 devices per reel.
N PACKAGE
(TOP VIEW)
D PACKAGE
(TOP VIEW)
8
7
6
5
1
2
3
4
VCC
GND
SENSE
ADJ
GND
SENSE
ADJ
VCC
1
2
3
4
8
7
6
5
SHARE+
SHARE−
COMP
SHARE+
SHARE−
COMP
ADJR
ADJR
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
ADJ
NO.
3
I
O
I/O
−
Current output of the adjust amplifier circuit (NPN collector)
Current adjust amplifier range set (NPN emitter)
Output of the error amplifier, input of the adjust amplifier
Local power supply return and signal ground
Inverting input of the current sense amplifier
Positive input from share bus or drive-to-share bus
Reference for SHARE+ pin
ADJR
4
COMP
GND
5
1
SENSE
SHARE+
SHARE−
VCC
2
I
7
I/O
I
6
8
I
Local power supply (positive)
5
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UC2902
UC3902
SLUS232E − DECEMBER 19, 2002 − REVISED JULY 2011
APPLICATION INFORMATION
The values of five passive components must be determined to configure the UC3902 load share controller. The
output and return lines of each converter are connected together at the load, with current sense resistor R
SENSE
inserted in each negative return line. Another resistor, R , is also inserted in each positive remote sense line.
ADJ
The differential share bus terminals (SHARE+ and SHARE−) of each UC3902 are connected together
respectively, and the SHARE− node is also connected to the system ground. A typical application is illustrated
in Figure 1.
The load share controller design can be executed by following the next few steps:
Step 1.
V
SHARE(max)
R
+
SENSE
A
I
CSA
O(max)
(1)
D
where A
is 40, the gain of the current sense amplifier
CSA
At full load, the voltage drop across the R
resistor is I
× R . Taking into account the gain of the
SENSE
SENSE
O(max)
current sense amplifier, the voltage at full load on the current share bus,
A
I
CSA
O(max)
SENSE
V
+
SHARE(max)
R
(2)
This voltage must stay 1.5-V below V or below 10 V whichever is smaller. V
represents an upper limit
CC
SHARE
but the designer should select the full scale share bus voltage keeping in mind that every volt on the load share
bus increases the master controller’s supply current by approximately 100 μA times the number of slave units
connected parallel.
Step 2.
V
I
ADJ(max)
R
+
G
ADJ(max)
(3)
Care must be taken to ensure that I
are within the device’s capability. For most applications, an I
is low enough so that both the drive current and power dissipation
ADJ(max)
current between 5 mA and 10 mA is
ADJ(max)
acceptable. In a typical application, a 360-Ω R resistor from the ADJR pin to ground sets I
to
G
ADJ(max)
approximately 5 mA.
Step 3.
* ǒI
SENSEǓ
DV
R
O(max)
O(max)
R
+
ADJ
I
ADJ(max)
(4)
R
ADJ
R
ADJ
must be low enough to not affect the normal operation of the converter’s voltage feedback loop. Typical
values are between 20 Ω to100 Ω depending on V , ΔV
and the selected I
value.
O
O(max)
ADJ(max)
Step 4.
R
R
SENSE
g
ADJ
M
ǒf Ǔ
C
+
A
A
CSA
PWR
C
C
2p f
R
R
C
G
LOAD
(5)
6
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UC2902
UC3902
SLUS232E − DECEMBER 19, 2002 − REVISED JULY 2011
The share loop compensation capacitor, C is calculated to produce the desired share loop unity gain crossover
C
frequency, f . The share loop error amplifier’s transconductance, g is nominally 4.5 ms. The values of the
C
M
resistors are already known. Typically, f is set to at least one order of magnitude below the converter’s closed
C
loop bandwidth. The load share circuit is primarily intended to compensate for each converter’s initial output
voltage tolerance and temperature drift, not for differences in their transient response. The term A
is the
PWR(fc)
gain of the power supply measured at the desired share loop crossover frequency, f . This gain can be
C
measured by injecting the measurement signal between the positive output and the positive sense terminal of
the power supply.
Step 5.
1
R
+
C
2p f C
C
C
(6)
A resistor in series with C is required to boost the phase margin of the load share loop. The zero is placed at
C
the load share loop crossover frequency, f .
C
When the system is powered up, the converter with the highest output voltage tends to source the most current
and take control of the share bus. The other converters increase their output voltages until their output currents
are proportional to the share bus voltage minus 50 mV. The converter which in functioning as the master may
change due to warmup drift and differences in load and line transient response of each converter.
ADDITIONAL INFORMATION
Please refer to the following topic for additional application information.
1. Application Note U−163, (TI Literature No. SLUA128) The UC3902 Load Share Controller and Its
Performance in Distributed Power Systems by Laszlo Balogh
7
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PACKAGE MATERIALS INFORMATION
www.ti.com
28-Jul-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UC2902DTR
UC3902DTR
SOIC
SOIC
D
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
6.4
5.2
5.2
2.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Jul-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UC2902DTR
UC3902DTR
SOIC
SOIC
D
D
8
8
2500
2500
340.5
340.5
338.1
338.1
20.6
20.6
Pack Materials-Page 2
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