UCC14240QDWNRQ1_技术文档

UCC14240-Q1

ZHCSOX6C –SEPTEMBER 2021 –REVISED DECEMBER 2022

UCC14240-Q1 汽车类2.0W、24V V_IN、25V V_OUT、高密度、

> 3kV_RMS、隔离式直流/直流模块

1 特性

3 说明

• 采用隔离变压器的完全集成高密度隔离式直流/直流

模块

• 隔离式直流/直流模块，用于驱动：IGBT、SiC FET

• 输入电压范围：21V 至27V，绝对最大值为32V

• 在T_A≤85°C 时输出功率为2.0W，在T_A= 105°C

时输出功率> 1.5W

UCC14240-Q1 是一款符合汽车标准的高隔离电压直

流/直流电源模块，旨在为 IGBT 或 SiC 栅极驱动器供

电。UCC14240-Q1 集成了具有专有架构的变压器和直

流/直流控制器，可实现高效率和超低的发射。高精度

输出电压可提供更好的通道增强，从而实现更高的系统

效率，不会对功率器件栅极造成过应力。

• 可调节的(VDD –VEE) 输出电压（通过外部电阻

器）：在整个温度范围内为18V 至25V，调节精度

为±1.3%

• 可调节的(COM –VEE) 输出电压（通过外部电阻

器）：在整个温度范围内为2.5V 至(VDD –

VEE)，调节精度为±1.3%

• 通过展频调制和集成变压器设计降低电磁发射

• 使能、电源正常、UVLO、OVLO、软启动、短路、

功率限制、欠压、过压和过热保护

UCC14240-Q1 可以高效提供高达 2.0W（典型值）的

隔离输出功率。该模块需要非常少的外部元件，并且具

有片上器件保护功能，可提供额外的特性，例如输入欠

压锁定、过压锁定、输出电压电源正常比较器、过热关

断、软启动超时、可调隔离式正负输出电压、使能引脚

和开漏输出电源正常引脚。

封装信息

可订购器件型号⁽¹⁾

封装尺寸（标称值）

封装

DWN（SSOP，

36）

• CMTI > 150kV/µs

• 符合面向汽车应用的AEC-Q100 标准

UCC14240QDWNRQ1

12.83mm × 7.50mm

– 温度等级1：–40°C ≤T_J≤150°C

– 温度等级1: -40 °C ≤T_A≤125°C

• 功能安全型

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

PG

VDD

C_OUT2

– 有助于进行功能安全系统设计的文档

• 计划的安全相关认证：

R1

R2

R_LIM

ENA

VIN

RLIM

FBVDD

FBVEE

COM

Source/

emitter

– 符合DIN EN IEC 60747-17 (VDE 0884-17) 标

准的4243V_PK基础型隔离

C_OUT1

V_IN

R3

R4

C_OUT3

C_IN

– 符合UL1577 标准且长达1 分钟的3000V_RMS

隔离

GNDP

VEE

– 符合CQC GB4943.1 标准的基本绝缘

• 36 引脚宽体SSOP 封装

简化版应用

2 应用

• 混合动力、电动和动力总成系统(EV/HEV)

– 逆变器和电机控制

– 车载充电器(OBC) 和无线充电器

– 直流/直流转换器

• 电网基础设施

– 电动汽车充电站电源模块

– 直流充电（桩）站

– 串式逆变器

典型上电序列

• 电机驱动器

– 交流逆变器和变频驱动器、机器人伺服驱动器

• 工业运输

– 非公路用车电力驱动

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSE80

UCC14240-Q1

ZHCSOX6C –SEPTEMBER 2021 –REVISED DECEMBER 2022

www.ti.com.cn

Table of Contents

7.2 Functional Block Diagram.........................................17

7.3 Feature Description...................................................17

7.4 Device Functional Modes..........................................24

8 Application and Implementation..................................26

8.1 Application Information............................................. 26

8.2 Typical Application.................................................... 26

8.3 System Examples..................................................... 33

8.4 Power Supply Recommendations.............................34

8.5 Layout....................................................................... 34

9 Device and Documentation Support............................38

9.1 Documentation Support............................................ 38

9.2 接收文档更新通知..................................................... 38

9.3 支持资源....................................................................38

9.4 Trademarks...............................................................38

9.5 Electrostatic Discharge Caution................................38

9.6 术语表....................................................................... 38

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Power Ratings.............................................................6

6.6 Insulation Specifications............................................. 6

6.7 Safety-Related Certifications...................................... 7

6.8 Electrical Characteristics.............................................7

6.9 Safety Limiting Values...............................................10

6.10 Insulation Characteristics........................................11

6.11 Typical Characteristics............................................ 12

7 Detailed Description......................................................16

7.1 Overview...................................................................16

Information.................................................................... 39

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (December 2022) to Revision C (December 2022)

Page

• Updated table notes............................................................................................................................................5

Changes from Revision A (November 2021) to Revision B (December 2022)

Page

• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1

2

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5 Pin Configuration and Functions

GNDP

PG

1

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

VEE

2

VEEA

FBVDD

FBVEE

RLIM

VEE

3

ENA

4

GNDP

VIN

5

6

VIN

7

VEE

GNDP

8

VDD

VEE

9

10

11

12

13

14

15

16

17

18

VEE

图5-1. DWN Package, 36-Pin SSOP (Top View)

表5-1. Pin Functions

TYPE ⁽¹⁾

DESCRIPTION

NAME

GNDP

NO.

1, 2, 5, 8, 9, 10,

11, 12, 13, 14,

15, 16, 17, 18

Primary-side ground connection for VIN. PIN 1,2, and 5 are analog ground. PIN 8, 9, 10, 11, 12,

13, 14, 15, 16, 17, and 18 are power ground. Place several vias to copper pours for thermal relief.

See Layout Guidelines.

G

Active low power-good open-drain output pin. PG remains low when (UVLO ≤V_VIN≤OVLO);

PG

3

4

O

I

(UVP1 ≤(VDD –VEE) ≤OVP1); (UVP2 ≤(COM –VEE) ≤OVP2); T_{J_Primary}

TSHUTP_{PRIMARY_RISE}; and T_{J_secondary}≤TSHUT_{SECONDARY_RISE}

≤

Enable pin. Forcing ENA LOW disables the device. Pull HIGH to enable normal device

functionality. 5.5-V recommended maximum.

ENA

Primary input voltage. PIN 6 is for analog input, and PIN 7 is for power input. For PIN 7, connect

one 10-µF ceramic capacitor from power VIN PIN 7 to power GNDP PIN 8. Connect a 0.1-µF high-

frequency bypass ceramic capacitor close to PIN 7 and PIN 8.

VIN

6, 7

P

Optionally, connect a 330pF 0402 size high-frequency bypass ceramic capacitor close to analog

VIN PIN 6 and GNDP PIN 5.

19, 20, 21, 22,

23, 24, 25,26,

27, 30,31, 36

Secondary-side reference connection for VDD and COM. The VEE pins are used for the high

current return paths.

VEE

VDD

RLIM

G

P

Secondary-side isolated output voltage from transformer. Connect a 2.2-µF and a parallel 0.1-µF

ceramic capacitor from VDD to VEE. The 0.1-µF ceramic capacitor is the high frequency bypass

and must be next to the IC pins. A 4.7-µF or 10-µF ceramic capacitor can be used instead of 2.2 to

further reduce the output ripple voltage.

28, 29

32

Secondary-side second isolated output voltage resistor to limit the source current from VDD to

COM node, and the sink current from COM to VEE. Connect a resistor from RLIM to COM to

regulate the (COM –VEE) voltage. See R_LIMResistor Selection for more detail.

Feedback (COM –VEE) output voltage sense pin used to adjust the output (COM –VEE)

voltage. Connect a resistor divider from COM to VEE so that the midpoint is connected to FBVEE,

and the equivalent FBVEE voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for

high frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic

capacitor for high frequency bypass must be next to the FBVEE and VEEA IC pins on top layer or

back layer connected with vias.

FBVEE

33

I

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表5-1. Pin Functions (continued)

TYPE ⁽¹⁾

DESCRIPTION

NAME

NO.

Feedback (VDD –VEE) output voltage sense pin and to adjust the output (VDD –VEE) voltage.

Connect a resistor divider from VDD to VEE so that the midpoint is connected to FBVDD, and the

equivalent FBVDD voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for high

frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic capacitor

for high frequency bypass must be next to the FBVDD and VEEA IC pins on top layer or back

layer connected with vias.

FBVDD

34

I

Secondary-side analog sense reference connection for the noise sensitive analog feedback inputs,

FBVDD and FBVEE. Connect the low-side feedback resistors and high frequency decoupling filter

capacitor close to the VEEA pin and respective feedback pin FBVDD or FBVEE. Connect to

secondary-side gate drive lowest voltage reference, VEE. Use a single point connection and place

the high frequency decoupling ceramic capacitor close to the VEEA pin. See Layout Guidelines.

VEEA

35

G

(1) P = power, G = ground, I = input, O = output

4

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

Parameter

MIN

–0.3

TYP

MAX

32

UNIT

V

VIN to GNDP

ENA, PG to GNDP

7

V

VDD, RLIM, FBVDD, FBVEE to VEE

32

V

P_{LOSS_MAX}

Total power loss at T_A=25^°C

2.45

2.5

W

Total (VDD –VEE) output power at T_A=25^°C

P_{OUT_VDD_MAX}

Max RLIM pin rms current sourcing from VDD to

I_{RLIM_MAX_RMS_SOURCE}

RLIM. (16% average run time over lifetime of 24,500

hr)

0.125

A_RMS

Max RLIM pin rms current sinking from RLIM to VEE.

(16% average run time over lifetime of 24,500 hr)

I_{RLIM_MAX_RMS_SINK}

A_RMS

T_J

Operating junction temperature range

Storage temperature

150

°C

–40

–65

T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per AEC

Q100-002 ⁽¹⁾

±2000

V

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per AEC

Q100-011 Section 7.2

±500

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

V_VIN

V_ENA

V_PG

MIN

21

0

TYP

MAX

27

UNIT

Primary-side input voltage to GNDP

Enable to GNDP

24

V

5.5

25

Powergood to GNDP

VDD to VEE

0

V_VDD

18

VDD –

V_VEE

COM to VEE

2.5

0

V

VEE

V_FBVDD

V_FBVEE

,

FBVDD, FBVEE to VEE

2.5

5.5

T_A

Ambient temperature

Junction temperature

125

150

°C

–40

T_J

6.4 Thermal Information

DWN (SSOP)

THERMAL METRIC⁽¹⁾

UNIT

36 PINS

52.3

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

°C/W

R_θJC(top)

28.5

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UNIT

DWN (SSOP)

36 PINS

25.9

THERMAL METRIC⁽¹⁾

R_θJB

Ψ_JT

Junction-to-board thermal resistance

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

16.6

25.6

Ψ_JB

R_θJC(bot)

–

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Power Ratings

V_VIN= 24 V, C_IN= 10µF, C_OUT= 2.2 uF, T_J= 150 °C, V_ENA= 5 V

PARAMETER

TEST CONDITIONS

TYP VALUE

UNIT

(VDD –VEE) = 25 V, P_VDD-VEE= 2 W; (COM –

VEE) = 5 V, No Load from (VDD - COM) or (COM

- VEE)

P_D

Power dissipation

1.65

W

6.6 Insulation Specifications

PARAMETER

TEST CONDITIONS

VALUE

UNIT

General

CLR

CPG

External clearance ⁽¹⁾

External creepage ⁽¹⁾

Shortest terminal-to-terminal distance through air

> 8

mm

Shortest terminal-to-terminal distance across the

package surface

Minimum internal gap (internal clearance –

transformer power isolation)

> 120

> 8.6

µm

DTI

CTI

Distance through the insulation

Minimum internal gap (internal clearance –

capacitive signal isolation)

µm

V

Comparative tracking index

Material group

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

> 600

I

I-IV

I-III

Rated mains voltage ≤300 VRMS

Rated mains voltage ≤600 VRMS

Rated mains voltage ≤1000 VRMS

Overvoltage category

DIN EN IEC 60747-17 (VDE 0884-17) (Planned Certification Targets) ⁽²⁾

V_IORM

Maximum repetitive peak isolation voltage

AC voltage (bipolar)

1202

850

V_PK

V_RMS

V_DC

AC voltage (sine wave) Time dependent dielectric

breakdown (TDDB) test

V_IOWM

Maximum working isolation voltage

DC voltage

1202

4243

V_TEST= V_IOTM, t = 60s (qualification);V_TEST= 1.2

× V_IOTM, t = 1 s (100% production)

V_IOTM

V_IMP

Maximum transient isolation voltage

Maximum impulse voltage ⁽³⁾

V_PK

Tested in air, 1.2/50-μs waveform per IEC

62368-1

5000

6500

V_PK

Tested in oil (qualification test), 1.2/50-μs

waveform per IEC 62368-1

V_IOSM

Maximum surge isolation voltage ⁽³⁾

Method a, After Input/Output safety test subgroup

2/3, V_ini= V_IOTM, t_ini= 60 s; V_pd(m)= 1.2 × V_IORM

t_m= 10 s

,

pC

≤5

Method a, After environmental tests subgroup 1,

qpd

Apparent charge ⁽⁴⁾

V_ini= V_IOTM, t_ini= 60 s; V_pd(m)= 1.3 × V_IORM, t_m

10 s

=

Method b1: At routine test (100% production) and

preconditioning (type test); V_ini= 1.2 x V_IOTM, t_ini

1 s; V_pd(m)= 1.5 x V_IORM, t_m= 1 s

=

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PARAMETER

TEST CONDITIONS

V_IO= 0.4 sin (2πft), f = 1 MHz

V_IO= 500 V, T_A= 25°C

VALUE

< 3.5

UNIT

pF

C_IO

R_IO

Barrier capacitance, input to output ⁽⁵⁾

> 10¹²

> 10¹¹

> 10⁹

Ω

Isolation resistance, input to output ⁽⁵⁾

V_IO= 500 V, 100°C ≤T_A≤125°C

V_IO= 500 V at T_S= 150°C

Ω

Pollution degree

Climatic category

2

40/125/21

UL 1577 (Planned Certification Target)

Withstand isolation voltage

V_TEST= V_ISO= 3000 V_RMS, t = 60s (qualification)

V_TEST= 1.2 × V_ISO= 3600 V_RMS, t = 1 s (100%

production)

V_ISO

Withstand isolation voltage

3000

V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.

Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the

isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in

certain cases. Techniques such as inserting grooves and/or ribs on a printed-circuit board are used to help increase these

specifications.

(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings

shall be ensured by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-terminal device

6.7 Safety-Related Certifications

VDE

UL

CQC

Plan to certify according to DIN EN IEC 60747-17

(VDE 0884-17)

Plan to certify under UL 1577 Component

Recognition Program

Plan to certify according to GB4943.1

Basic insulation Maximum transient isolation

voltage, 4243 V_PK; Maximum repetitive peak

isolation voltage, 1202 V_PK; Maximum surge

isolation voltage, 6500 V_PK

Basic insulation, Altitude ≤5000 m, Tropical

Single protection, 3000 V_RMS

File number: (planned)

Climate, 595 V_RMSmaximum working voltage

Certificate number: (planned)

6.8 Electrical Characteristics

Over operating temperature range (–40 °C ≤T_J≤150 °C, 21 V ≤V_VIN≤27 V, C_IN= 10µF, C_OUT= 2.2 µF, V_ENA= 5 V,

R_LIM= 1 kΩ, unless otherwise noted. All typical values at T_A= 25 °C and V_VIN= 24 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

INPUT SUPPLY (Primary-side. All voltages with respect to GNDP)

V_VIN

Input voltage range

Primary-side input voltage to GNDP

V_ENA=0 V; V_VIN= 21 V - 27 V

21

24

27

V

I_{VINQ_OFF}

VIN quiescent current, disabled

700

µA

V_ENA= 5 V; V_VIN= 21 V - 27 V;

(VDD –VEE) = 25-V regulating; I_VDD

_–VEE= 0 mA

VIN operating current, enabled, No

Load

I_{VIN_ON_NO_LOAD}

35

mA

V_ENA=5 V; V_VIN= 21 V - 27 V; (VDD –

VIN operating current, enabled, Full

Load

I_{VIN_ON_FULL_LOAD}

250

VEE) = 25-V regulating; I_{VDD –VEE}

60 mA

=

UVLOP COMPARATOR (Primary-side. All voltages with respect to GNDP)

V_{VIN_ANALOG_UVLO}VIN analog undervoltage lockout rising

8

7

9

8

10

9

V

threshold

P_RISING

V_{VIN_}

VIN analog undervoltage lockout

falling threshold

ANALOG_UVLOP_FALL

ING

VIN undervoltage lockout rising

V_{VIN_UVLOP_RISING}

threshold

19

20

21

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Over operating temperature range (–40 °C ≤T_J≤150 °C, 21 V ≤V_VIN≤27 V, C_IN= 10µF, C_OUT= 2.2 µF, V_ENA= 5 V,

R_LIM= 1 kΩ, unless otherwise noted. All typical values at T_A= 25 °C and V_VIN= 24 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_{VIN_UVLOP_FALLIN}VIN undervoltage lockout falling

17.1

18

18.9

V

threshold

G

OVLO COMPARATOR (Primary-side. All voltages with respect to GNDP)

VIN overvoltage lockout rising

V_{VIN_OVLO_RISE}

threshold

29.45

27.55

31

29

32.55

30.45

V

VIN overvoltage lockout falling

V_{VIN_OVLO_FALLING}

threshold

THERMAL SHUTDOWN COMPARATOR (Primary-side)

TSHUTP_{PRIMARY_}Primary-side over-temperature

First time at power-up Tj needs to be <

130 °C to turn on

140

15

150

20

160

25

°C

shutdown rising threshold ⁽¹⁾

RISE

TSHUTP_{PRIMARY_}Primary-side over-temperature

shutdown hysteresis ⁽¹⁾

HYST

ENA INPUT PIN (Primary-side. All voltages with respect to GNDP)

Input voltage rising threshold, logic

HIGH

V_{EN_IR}

Rising edge

2.1

10

V

Input voltage falling threshold, logic

LOW

V_{EN_IF}

I_EN

Falling edge

V_ENA= 5.0 V

0.8

V

Enable Pin Input Current

5

µA

PG OPEN-DRAIN OUTPUT PIN (Primary-side. All voltages with respect to GNDP)

V_{PG_OUT_LO}

I_{PG_OUT_HI}

PG output-low saturation voltage

PG Leakage current

Sink Current = 5 mA, power good

V_PG= 5.5 V, power not good

0.5

5

V

µA

V_VIN= 24 V; V_ENA= 5 V; (VDD-VEE) =

25 V

F_SW

Switching frequency

11

13

90

15 MHz

kHz

Only during primary-side startup

starting after VIN > UVLOP, and ENA

= HIGH; F_{SS_BURST_P}= 1/8 µs = 125

kHz

Frequency of Spread Spectrum

Modulation (SSM) triangle waveform

F_SSM

SSM Percent change of carrier

frequency during Spread Spectrum

Modulation (SSM) by triangle

waveform

Only during primary-side startup

starting after VIN > UVLOP, and ENA

= HIGH; F_{SS_BURST_P}= 1/8 µs = 125

kHz

SSM Percentage

change of

F_CARRIER

5

%

Timer begins when VIN > UVLOP and

ENA = High and reset when

Powergood pin indicates Good

t_{SOFT_START_TIME_O}

Primary-side soft-start time-out

16

ms

UT

VDD OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE)

V_{VDD_RANGE}

18

25

V

(VDD –VEE) Output voltage range

Secondary-side (VDD –VEE) output

voltage, over load, line and

temperature range, externally adjust

with external resistor divider

(VDD –VEE) Output

voltage DC regulation accuracy

V_{VDD_DC_ACCURAC}

-1.3

1.3

%

Y

VDD REGULATION HYSTERETIC COMPARATOR (Secondary-side. All voltages with respect to VEE)

Feedback regulation reference voltage

for (VDD –VEE)

V_{FBVDD_REF}

2.4675

2.5 2.5325

V

(VDD –VEE) output in regulation

FBVDD Hysteresis comparator

hysteresis settings. Hysteresis at the

FBVDD pin. [The (VDD-VEE)

hysteresis would amplify this FBVDD

hysteresis by the feedback resistor

divider gain.]

V_{FBVDD_HYST}

9

10

12.3

mV

COM OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE)

(VDD –

V_{VEE_RANGE}

2.5

V

(COM –VEE) Output voltage range

VEE)

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Over operating temperature range (–40 °C ≤T_J≤150 °C, 21 V ≤V_VIN≤27 V, C_IN= 10µF, C_OUT= 2.2 µF, V_ENA= 5 V,

R_LIM= 1 kΩ, unless otherwise noted. All typical values at T_A= 25 °C and V_VIN= 24 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Secondary-side (COM –VEE)

output voltage, over load, line and

temperature range, externally adjust

with external resistor

(COM –VEE) Output voltage DC

regulation accuracy

V_{VEE_DC_ACCURACY}

1.3

%

–1.3

divider

COM REGULATION HYSTERETIC COMPARATOR (Secondary-side. All voltages with respect to VEE)

Feedback regulation reference voltage

for (COM –VEE)

V_{FBVEE_REF}

2.4675

2.5 2.5325

0.73

V

(COM –VEE) output in regulation

V_{RLIM_SHORT_CHRG}RLIM pin Short Charge comparator

Rising threshold

rising threshold to exit PWM

_CMP_RISE

t_{RLIM_SHORT_CHRG_}On-Time during RLIM pin Short

RLIM pin < 0.645 V, while FBVEE pin

< 2.48 V

1.2

5

us

Charge PWM mode

ON_TIME

t_{RLIM_SHORT_CHRG_}Off-Time during RLIM pin Short

RLIM pin < 0.645 V, while FBVEE pin

< 2.48 V

Charge PWM mode

OFF_TIME

UVLOS COMPARATOR (Secondary-side. All voltages with respect to VEE)

(VDD –VEE) undervoltage lockout

rising threshold

V_{VDD_UVLO_RISE}

V_{VDD_UVLO_HYST}

Voltage at FBVDD

0.9

0.2

V

(VDD –VEE) undervoltage lockout

hysteresis

OVLOS COMPARATOR (Secondary-side. All voltages with respect to VEE)

(VDD –VEE) overvoltage lockout

rising threshold

V_{VDD_OVLOS_RISE}

Voltage from VDD to VEE, rising

Voltage from VDD to VEE, falling

29.45

27.55

31

29

32.55

30.45

V

V_{VDD_OVLOS_FALLIN}

(VDD –VEE) overvoltage lockout

falling threshold

G

SOFT-START (Secondary-side. All voltages with respect to VEE)

VREF_Voltage_pe

r_Steps

7 Steps of 200mV each, starting from

1.3V and ending at 2.5V.

Voltage per step

0.2

1.3

2.5

V

VREF_Voltage_St VREF voltage at Start of secondary-

art side soft-start

7 Steps of 200mV each, starting from

1.3V and ending at 2.5V.

VREF_Voltage_En VREF voltage at End of secondary-

side soft-start

7 Steps of 200mV each, starting from

1.3V and ending at 2.5V.

d

UVP1, (VDD –VEE) UNDER -VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE)

(VDD –VEE) under-voltage

V_{VDD_UVP_RISE}

2.175

2.25

2.35

V

protection rising threshold, V_UVP

V_REF× 90%

=

(VDD –VEE) undervoltage protection

hysteresis

V_{VDD_UVP_HYST}

20

mV

OVP1, (VDD –VEE) OVER-VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE)

(VDD –VEE) over-voltage protection

V_{VDD_OVP_RISE}

2.7

2.75

2.825

V

rising threshold, V_OVP= V_REF×110%

(VDD –VEE) overvoltage protection

hysteresis

V_{VDD_OVP_HYST}

20

mV

UVP2, (COM –VEE) UNDER -VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE)

(COM –VEE) under-voltage

V_{VEE_UVP_RISE}

2.1

2.25

2.4

V

protection rising threshold, V_UVP

V_REF× 90%

=

(COM –VEE) undervoltage

protection hysteresis

V_{VEE_UVP_HYST}

20

mV

OVP2, (COM –VEE) OVER-VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE)

(COM –VEE) over-voltage protection

V_{VEE_OVP_RISE}

2.7

2.75

2.825

V

rising threshold, V_OVP= V_REF× 110%

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Over operating temperature range (–40 °C ≤T_J≤150 °C, 21 V ≤V_VIN≤27 V, C_IN= 10µF, C_OUT= 2.2 µF, V_ENA= 5 V,

R_LIM= 1 kΩ, unless otherwise noted. All typical values at T_A= 25 °C and V_VIN= 24 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

(COM –VEE) over-voltage protection

hysteresis

V_{VEE_OVP_HYST}

20

mV

THERMAL SHUTDOWN COMPARATOR (Secondary-side)

TSHUTS_SECONDARSecondary -side over-temperature

First time at power-up Tj needs to be <

130^oC to turnon.

145

15

150

20

155

25

°C

shutdown rising threshold ⁽¹⁾

Y_RISE

TSHUTS_SECONDARSecondary-side over-temperature

shutdown hysteresis ⁽¹⁾

Y_HYST

CMTI (Common Mode Transient Immunity)

Positive VEE with respect to GNDP

Negative VEE with respect to GNDP

150

V/ns

CMTI

Common Mode Transient Immunity

–150

INTEGRATED TRANSFORMER (Primary-side to Secondary-side)

Transformer effective turns ratio Secondary side to primary side

N

1.18

-

(1) Functionality tested in production. MIN, TYP, MAX ensured by characterization.

6.9 Safety Limiting Values

PARAMETER

TEST CONDITIONS

MAX

UNIT

R

_θJA= 52.3 °C/W, V_VIN= 27 V, T_J= 150 °C, T_A

=

150

200

mA

25 °C, P_OUT= 2 W ^{(1) (2)}

I_S

Safety input rms current (VDD-VEE)

R_θJA= 52.3 °C/W, V_VIN= 21 V, T_J= 150 °C, T_A

mA

25 °C, P_OUT= 2 W ^{(1) (2)}

Safety power dissipation (input power - output

power)

P_S

T_S

R

_θJA= 52.3 °C/W, T_J= 150 °C, T_A= 25 °C ^{(1) (2)}

2.39

150

W

(1) (2)

Safety temperature

°C

(1) The maximum safety temperature, T_S, has the same value as the maximum junction temperature, T_J, specified for the device. The I_S

and P_Sparameters represent the safety current and safety power respectively. The maximum limits of I_Sand PS should not be

exceeded. These limits vary with the ambient temperature, T_A.

(2) The junction-to-air thermal resistance, R_θJA, in the Thermal Information table is that of a device installed on a high-K test board for

leaded surface-mount packages. Use these equations to calculate the value for each parameter: T_J= T_A+ R_qJA× P, where P is the

power dissipated in the device. T_J(max)= T_S= T_A+ R_θJA× P_S, where T_J(max)is the maximum allowed junction temperature. P_S= I_S

V_I, where V_Iis the maximum input voltage.

×

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6.10 Insulation Characteristics

图6-1. TDDB: Insulation Lifetime Projection for 850 Vrms Working Voltage.

Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown

(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal

device and high voltage applied between the two sides; The insulation breakdown data is collected at various

high voltages switching at 60 Hz over temperature. For basic insulation, VDE standard requires the use of TDDB

projection line with failure rate of less than 1000 part per million (ppm). Even though the expected minimum

insulation lifetime is 20 years at the specified working isolation voltage, VDE basic certification requires

additional safety margin of 20% for working voltage and 30% for lifetime which translates into minimum required

insulation lifetime of 26 years at a working voltage that's 20% higher than the specified value. The TDDB

projection line shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its

lifetime. Based on the TDDB data, the intrinsic capability of the insulation is 850 V_RMSwith a lifetime of 270

years.

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6.11 Typical Characteristics

图6-2. SOA Derating Curves: V_VDD-VEE= 18 V, V_COM-VEE= 5 V, No

图6-3. SOA Derating Curves: V_VDD-VEE= 20 V, V_COM-VEE= 5 V, No

Load.

Load

图6-4. SOA Derating Curves: V_VDD-VEE= 25 V, V_COM-VEE= 5 V, No Load

图6-5. Start-up: VIN = 24 V, V_VDD-VEE= 25 V, V_COM-VEE= 5 V, No 图6-6. Shutdown: VIN = 24 V, V_VDD-VEE= 25 V, V_COM-VEE= 5 V, No

Load

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6.11 Typical Characteristics (continued)

图6-7. Load Transient Response: No Load to 1 W, VIN = 24 V,

图6-8. Load Transient Response: 1 W to No Load, VIN = 24 V,

V_VDD-VEE= 25 V, V_COM-VEE= 5 V

图6-9. V_VDD-VEELoad Regulation: VIN = 21 V, V_VDD-VEE= 25 V,

图6-10. V_VDD-VEELoad Regulation: VIN = 24 V, V_VDD-VEE= 25 V,

V_COM-VEE= 5 V

图6-12. V_COM-VEELoad Regulation: VIN = 21 V, V_VDD-VEE= 25 V,

图6-11. V_VDD-VEELoad Regulation: VIN = 27 V, V_VDD-VEE= 25 V,

V_COM-VEE= 5 V

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6.11 Typical Characteristics (continued)

图6-13. V_COM-VEELoad Regulation: VIN = 24 V, V_VDD-VEE= 25 V,

图6-14. V_COM-VEELoad Regulation: VIN = 27 V, V_VDD-VEE= 25 V,

V_COM-VEE= 5 V

图6-15. Efficiency vs Load on V_VDD-VEE: VIN = 21 V, V_VDD-VEE

=

图6-16. Efficiency vs Load on V_VDD-VEE: VIN = 24 V, V_VDD-VEE=

25 V, V_COM-VEE= 5 V, No Load on V_COM-VEE

图6-18. Input Current vs Load on V_VDD-VEE: VIN = 21 V, V_VDD-VEE

图6-17. Efficiency vs Load on V_VDD-VEE: VIN = 27 V, V_VDD-VEE

=

= 25 V, V_COM-VEE= 5 V, No Load on V_COM-VEE

25 V, V_COM-VEE= 5 V, No Load on V_COM-VEE

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6.11 Typical Characteristics (continued)

图6-19. Input Current vs Load on V_VDD-VEE: VIN = 24 V, V_VDD-VEE

图6-20. Input Current vs Load on V_VDD-VEE: VIN = 27 V, V_VDD-VEE

= 25 V, V_COM-VEE= 5 V, No Load on V_COM-VEE

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7 Detailed Description

7.1 Overview

UCC14240-Q1 device is suitable for applications that have limited board space and require more integration.

These devices are also suitable for very-high voltage applications, where power transformers meeting the

required isolation specifications are bulky and expensive. The low-profile, low-center of gravity, and low weight

provides a higher vibration tolerance than systems using large bulky transformers. The device is easy-to-use and

provides flexibility to adjust both positive and negative output voltages as needed when optimizing the gate

voltage for maximum efficiency while protecting gate oxide from over-stress with its tight voltage regulation

accuracy.

The device integrates a high-efficiency, low-emissions isolated DC/DC converter for powering the gate drive of

SiC or IGBT power devices in traction inverter motor drives, industrial motor drives, or other high voltage DC/DC

converters. This DC/DC converter provides greater than 1.5 W of power.

The integrated DC/DC converter uses switched mode operation and proprietary circuit techniques to reduce

power losses and boost efficiency. Specialized control mechanisms, clocking schemes, and the use of an on-

chip transformer provide high efficiency and low radiated emissions.

The integrated transformer provides power delivery throughout a wide temperature range while maintaining a

3000-V_RMSisolation, and an 850-V_RMScontinuous working voltage. The low isolation capacitance of the

transformer provides high CMTI allowing fast dv/dt switching and higher switching frequencies, while emitting

less noise.

The V_VINsupply is provided to the primary-side power controller that switches the input stage connected to the

integrated transformer. Power is transferred to the secondary-side output stage, and regulated to a level set by

the resistor divider connected between the (VDD – VEE) pin and the FBVDD pin with respect to the VEE pin.

The output voltage is adjustable with external resistor divider allowing a wide (VDD –VEE) range.

For optimal performance ensure to maintain the V_VINinput voltage within the recommended operating voltage

range. Do not exceed the absolute maximum voltage rating to avoid over-stressing the input pins.

A fast hysteretic feedback burst control loop monitors (VDD – VEE) and ensures the output voltage is kept

within the hysteresis with low overshoots and undershoots during load and line transients. The burst control loop

enables efficient operation across full load and allows a wide VOUT adjustability throughout the whole V_VIN

range. The undervoltage lockout (UVLO) protection monitors the input voltage pin, VIN, with hysteresis and input

filter ensuring robust system performance under noisy conditions. The overvoltage lockout (OVLO) protection

monitors the input voltage pin, VIN, protects against over-voltage stress by disabling switching and reducing the

internal peak voltage. Controlled soft-start timing, provided throughout the full power-up time, limits the peak

input inrush current while charging the output capacitor and load.

The UCC14240-Q1 also provides a second output rail, (COM – VEE), that is used as a negative bias for the

gate drivers, allowing quicker turn-off switching for the IGBTs, and also to protect from unwanted turn-on during

fast switching of SiC devices. (COM – VEE) has a simple, yet fast and efficient bias controller to ensure the

positive and negative rails are regulated during the PWM switching. The COM pin can be connected from the

source of SiC device or emitter of an IGBT device. An external current limiting resistor allows the designer to

program the sink and source current peak according to the needs of the gate drive system.

A fault protection and powergood status pin provides a mechanism for the host controller to monitor the status of

the DC/DC converter and provide proper sequencing of power and PWM control signals to the gate driver. Fault

protection includes undervoltage, overvoltage, over-temperature shutdown, and a 100 μs isolated channel

communication interface watchdog timer.

A typical soft-start ramp-up time is approximately 3 ms, but varies based on input voltage, output voltage, output

capacitance, and load. If either output is shorted or over-loaded, the device is not able to power-up within the 16-

ms soft-start watch-dog-timer protection time, so the device latches off for protection. The latch can be reset by

toggling the ENA pin or powering VIN down and up.

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The output load must be kept low until start-up is complete and PG pin is low. When powering up, do not apply a

heavy load to (VDD – VEE) or (COM – VEE) outputs until the /PG pin has indicated power is good (pulling

logic low) to avoid problems providing the power to ramp-up the voltage.

TI recommends to use the PG status indicator as a trigger point to start the PWM signal into the gate driver. PG

output removes any ambiguity as to when the outputs are ready by providing a robust closed loop indication of

when both (VDD –VEE) and (COM –VEE) outputs have reached their regulation threshold within ±10%.

Do not allow the host to begin PWM to gate driver until after PG goes low. This action typically occurs less than

16 ms after V_VIN> V_{VIN_UVLOP}and ENA goes high. The /PG status output indicates the power is good after soft

start of (VDD –VEE) and (COM –VEE) and are within ±10% of regulation.

If the host is not monitoring PG, then ensure that the host does not begin PWM to gate driver until 20 ms after

V_VIN> V_{VIN_UVLOP}and ENA goes high to allow enough time for power to be good after soft start of VDD and

VEE.

7.2 Functional Block Diagram

VIN

VDD

Q1

Q2

Q3

Q4

Source

D1

D3

RLIM

Sink

D2

D4

GNDP

VEE

Gate-drive logic

and

level shifting

Oscillator

SSM

FBVEE

Enable

Power off/on

FBVDD

ENA

PG

Secondary-

side feedback

regulation

and

RX

TX

Primary-side

controller and

fault monitoring

+

fault monitoring

VREF

VEEA

7.3 Feature Description

7.3.1 Power Stage Operation

The UCC14240-Q1 module uses an active full-bridge inverter on the primary-side and a passive full-bridge

rectifier on the secondary-side. The small integrated transformer has a relatively high carrier frequency to reduce

the size for integrating into the 36-pin SOIC package. The power stage carrier frequency operates within 10 MHz

to 16 MHz. The power stage carrier frequency is determined by input voltage with a feed-forward control: when

V_VINis less than 21 V, the frequency is clamped at 16 MHz; when V_VINis higher than 27 V, the frequency is

clamped at 10 MHz; when V_VINis between 21 V and 27 V, the frequency reduces gradually from 16 MHz to 10

MHz as V_VINvoltage rises. Spread spectrum modulation, SSM, is used to reduce emissions. ZVS operation is

maintained to reduce switching power losses.

The UCC14240-Q1 module creates two regulated outputs. It can be configured as a single output converter,

VDD to VEE only, or a dual-output converter, VDD to VEE and COM to VEE. Even though the module uses VEE

as the reference point to create two positive output voltages, the outputs can use COM as the reference point

and become a positive and a negative output.

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These two outputs are controlled independently through hysteresis control. Furthermore, the VDD-VEE is the

main output, and COM to VEE uses the main output as its input to created a second regulated output voltage.

7.3.1.1 VDD-VEE Voltage Regulation

The VDD-VEE output is the main output of the module. The power stage operation is determined by the sensed

VDD-VEE voltage on FBVDD pin. As shown in 图 7-1, the VDD-VEE voltage is sensed through a voltage divider

R_{FBVDD_TOP}and R_{FBVDD_BOT}. When FBVDD voltage stays below the turn-off threshold, roughly 10 mV above the

V_{FBVDD_REF}, the power stage operates, delivers power to the secondary side and makes the VDD-VEE output

voltage rise. After the output reaches the turn-off threshold, the power stage turns off. Output voltage drops

because of the load current. After the output voltage drops below the turn-on threshold, roughly 10 mV below the

V_{FBVDD_REF}, the power stage is turned on again. With the accurate voltage reference and hysteresis control, the

VDD-VEE output voltage can be regulated with high accuracy. To improve the noise immunity, a small capacitor

of 330 pF should be added between FBVDD and VEE pins. Excessive capacitor slows down the hysteresis loop

and can cause excessive output voltage ripple or even stability issue.

Power stage

VIN

VDD

R_{FBVDD_TOP}

FBVDD

GNDP

C_OUT1

–

+

C_FBVDD

R_{FBVDD_BOT}

V_{FBVDD_REF}

VEE

图7-1. VDD-VEE Voltage Regulation

7.3.1.2 COM-VEE Voltage Regulation

COM-VEE output takes VDD-VEE output as its input and creates a regulated output voltage. It can be

considered as an LDO output from VDD-VEE, though the operation principle is not quite the same. Given its

input voltage is VDD-VEE, the maximum output voltage from COM to VEE is the voltage between VDD and

VEE.

The COM-VEE output regulator stage uses the internal high-side or low-side FETs in series with the external

current-limit resistor (R_LIM) to charge or discharge the COM-VEE output voltage. The hysteresis control is used

to control the switching instance of the two FETs, to achieve an accurately regulated COM-VEE voltage. As

shown in 图7-2, the COM-VEE output voltage is sensed through the voltage divider R_{FBVEE_TOP}and R_{FBVEE_BOT}

on FBVEE pin. TI recommends a 330-pF capacitor on FBVEE pin to filter out the switching frequency noise.

When the voltage on FBVEE is below the charging threshold, 20 mV below the V_{FBVEE_REF}, the charging resistor

is kept on and discharging resistor is kept off. COM-VEE output voltage rises. After FBVEE voltage reaches the

stop charging threshold, 20 mV above the V_{FBVEE_REF}, the charging resistor is turned off. Output voltage rise

stops. When the charging resistor is turned off, the discharge resistor is controlled by another hysteresis

controller, based on FBVEE pin voltage, with the same reference voltage V_{FBVEE_REF}, and 20-mV of hysteresis.

The COM-VEE output regulator stage will protect from having the high-side FET stay ON for a long time during a

COM to VEE short. This protection feature is implemented by monitoring the RLIM-pin voltage and controlling

the high-side FET duty-ratio. When the COM pin voltage is lower than 0.645 V while the FBVEE voltage is below

2.48 V, the hysteretic control of the COM-VEE regulator is overridden by an approximately 20 % duty-ratio

control on high-side FET, with a typical on-time of 1.2 μs and off-time of 5 μs in each duty cycle. When the

COM pin voltage is higher than 0.73 V, the duty ratio control is disabled and the hysteretic control resumes to

normal operation.

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VDD

C_OUT2

COM

VDD

RLIM

R_Charge

+

–

V_{FBVEE_REF}

R_LIM

SW

20 mV

R_{FBVEE_TOP}

FBVEE

C_OUT3

SW

+

–

R_Discharge

V_{FBVEE_REF}

1.25 mV

R_{FBVEE_BOT}

C_FBVEE

VEE

图7-2. COM-VEE Voltage Regulation

2.52V

2.50125V

VFBVEE_REF = 2.5V

2.48V

TurnON

Charge FET

TurnON

Charge FET

TurnOFF

CHARGE FET

Discharge Comparitor

Discharge Control

TurnON

Discharge FET

图7-3. COM-VEE Voltage Regulation Diagram

7.3.1.3 Power Handling Capability

The maximum power handling capability is determined by both circuit operation and thermal condition. For a

given output voltage, the maximum power increases with input voltage before triggering the thermal protection.

An over-power-protection (OPP) is implemented to limit maximum output power and reduces power stage RMS

current at high input voltage. The OPP is implemented by a feed-forward control from the input voltage to the

OPP burst duty cycle (D_OPP). The D_OPPadds a "baby" burst within the on-time of "Mama" burst from the main

feedback loop for the (VDD-VEE) regulation. When the input voltage increases, the D_OPPreduces automatically

to limit the averaged output power.

At high ambient temperature, the thermal performance determines the maximum power and safe operating area

(SOA). A protective thermal shut-down is triggered after overtemperature is detected. The high-efficiency and

optimized thermal design for transformer and silicon provide a high power handling capability at high ambient

temperature in a small package (2W for 85^oC and 1.5 W for 105^oC).

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(VDD-VEE)

OPP burst

(VDD-VEE) burst

图7-4. Diagram of Over-Power-Protection with baby burst

7.3.2 Output Voltage Soft Start

UCC14240-Q1 power-up diagram of two output rails with soft start is shown in 图 7-5. After V_VIN> V_{VIN_UVLOP}

and ENA is pulled high, the soft-start sequence starts with burst duty cycle control with soft duty cycle increment.

The burst duty cycle gradually increases from 12.5% to 50% over time by the primary-side control signal

(D_{SS_PRI}), so both V_VDD-VEEand V_COM-VEEincrease ratiometrically with a controlled shallow rising slope. When

V_VDD-VEEis increased above V_{VDD_UVLOS}, there is a sufficient bias voltage for the feedback-loop communication

channel, so the burst feedback control on the secondary side takes over. As a result, the D_{SS_PRI}is pulled high

and does not affect burst duty cycle anymore. The burst duty cycle is determined by comparing V_FBVDDand

V_REF. V_REFincreases from 1.1V to 2.5 V with seven increment steps, where each 0.2-V step lasts 128 µs. After

V_VDD-VEE> V_{VDD_UVP}, /PG is pulled low and the RLIM source-sink regulator for V_COM-VEEis enabled. The polarity

of source or sink current of RLIM pin is determined by comparing V_FBVEEand V_REFso as to keep V_COM-VEEin

tight regulation. The soft-start feature greatly reduces the input inrush current during power-up. In addition, if

V_VDD-VEEcannot reach to V_{VDD_UVLOS}within 16 ms, then the device shuts down in a safe-state. The 16-ms soft-

start time-out protects the module under output short circuit condition before power up.

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VIN

V_{IN_UVLOP}

t_delay

UVLOP

ENA

PG

D = 12.5%

D = 25%

D = 50% D = 100%

D_SS(PRI)

VDD_UVLOS

Comparator_Enable

2.5V

128µs

V_{VDD_OVP}

V_REF

V_{VDD_UVP}

V_{VEE_OVP}

V_{VEE_UVP}

V_{VDD_UVLOS}

V_VDD-VEE

V_COM-VEE

RLIM Comparator_Enable

图7-5. Output voltage Soft-Start Diagram

7.3.3 ENA and PG

The ENA input pin and PG output pin on the primary-side use 5-V TTL and 3.3-V LVTTL level logic thresholds.

The active-high enable input (ENA) pin is used to turn-on the isolated DC/DC converter of the module. Either

3.3-V or 5-V logic rails can be used. Maintain the ENA pin voltage below 5.5 V. After ENA pin voltage becomes

above the enable threshold VEN_IR, UCC14240-Q1 enables, starts switching, goes through the soft-start

process and delivers power to the secondary side. After ENA pin voltage falls below the disable threshold

V

_{EN_IF}, UCC14240-Q1 disables, stops switching.

The ENA pin can also be used to reset the UCC14240-Q1 device after it enters the protection safe-state mode.

After a detected fault, the protection logic will latch off and place the device into a safe state. When all the faults

are cleared, the ENA-pin can be used to clear the UCC14240-Q1 latch by toggling the ENA pin voltage below

V

_{EN_IF}for longer than 150 μs, then toggling back up to 3.3 V or 5 V. The device will then exit the latch-off mode

and we initiate a soft-start. 图7-6 illustrates the latch-off reset timing.

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ENA

150 µs

Latched-off

Latch-off state

Latch-off reset

Run

Power-stage state

Stop

图7-6. Latch-off Reset Using ENA Pin

The active-low power-good (PG) pin is an open-drain output that indicates (short) when the module has no fault

and the output voltages are within ±10% of the output voltage regulation setpoints. Connect a pull-up resistor (>

1 kΩ) from PG pin to either a 5-V or 3.3-V logic rail. Maintain the PG pin voltage below 5.5 V without exceeding

its recommended operating voltage. The logic of PG pin can be illustrated using 图7-7.

1.1×V_{FBVDD_REF}

+

–

FBVDD

+

–

0.9×V_{FBVDD_REF}

Isolation

+

1.1×V_{FBVEE_REF}

PG

–

FBVEE

+

–

0.9×V_{FBVEE_REF}

Protections (Over-temperature, output over

voltage, input UVLO, input OVLO)

+

ENA

V_{EN_IR}/V_{EN_IF}

GNDP

–

图7-7. PG Pin Logic

7.3.4 Protection Functions

UCC14240-Q1 devices are equipped with a full feature of protection functions, include input undervoltage

lockout, overvoltage lockout protections, output undervoltage protection, overvoltage protection, overpower

protection, and over-temperature protection. The input undervoltage and overvoltage lockout protections have

the auto recovery response. All other protections have the latch-off response. After the latch-off-response

protections are triggered, the converter enters a latch off state, stops switching until the latch is reset by either

toggling the ENA pin Off then On, or by lowering the V_VINvoltage below the V_{VIN_ANALOG_UVLOP_FALLING}

threshold, and then above the V_{VIN_UVLOP_RISING}threshold.

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7.3.4.1 Input Undervoltage Lockout

UCC14240-Q1 can take wide input voltage range, from 21 V to 27 V. When the input voltage becomes too low,

the output either cannot be regulated due to the transformer turns ratio limitation, or the converter operates with

too much current stress. Either way, the converter must shut down to protect the system.

The UCC14240-Q1 enters input undervoltage lockout when V_VINvoltage becomes lower than the UVLO

threshold V_{VIN_UVLOP_FALLING}. In UVLO mode, the converter stops switching. After VIN pin voltage becomes

lower than the VIN analog undervoltage lockout falling threshold V_{VIN_VULOP_FALLING}, UCC14240-Q1 resets all

the protections. After that, after the V_VINvoltage becomes above the UVLO threshold V_{VIN_UVLOP_RISING}, the

converter is enabled. Depending on the ENA pin voltage, the converter can start switching, go through the soft-

start process, or in the disable mode, waiting for ENA pin voltage becomes high.

7.3.4.2 Input Overvoltage Lockout

The input overvoltage lockout protection is used to protect the UCC14240-Q1 devices from overvoltage damage.

It has an auto-recovery response. When the V_VINpin voltage becomes higher than the input overvoltage lockout

threshold V_{VIN_OVLO_RISE}, switching stops, converter stops sending energy to the secondary side. After input

overvoltage lockout protection, after V_VINpin voltage drop below the recovery threshold V_{VIN_OVLO_FALLING}

,

depending on the ENA pin voltage status, the converter can either resuming operation, go through the full soft-

start process, or in the disabled mode, wait for ENA pin becomes high. The input overvoltage lockout does not

reset other latch-off protections.

7.3.4.3 Output Overvoltage Protection

The UCC14240-Q1 devices sense the output voltage through FBVDD and FBVEE pins to control the output

voltage. To prevent the output voltage becomes too high, damages the load or UCC14240-Q1 device itself, the

UCC14240-Q1 devices are equipped with the output overvoltage protection. There are two levels of overvoltage

protection, based on the feedback pin voltage, and the output voltage.

During the normal operation, because of load transient, or load unbalancing between two outputs, the output

voltages can exceed its regulation level. Based on the pin voltages on FBVDD and FBVEE, after the voltage

exceeds the threshold, V_{VDD_OVP_RISE}, or V_{VEE_OVP_RISE}(10% above the target regulation voltage), the converter

stops switching immediately.

In rare cases, the voltage divider becomes malfunction and gives the wrong output voltage information. In turn,

the control loop can regulate the output voltages at a wrong voltage level. The UCC14240-Q1 device is also

equipped with a fail-safe overvoltage protection. After the VDD-VEE voltage becomes higher than the

overvoltage protection threshold V_{VDD_OVLOS_RISE}, the converter shuts down immediately. This fail-safe

protection level is set at 31 V. It is meant to protect UCC14240-Q1 devices, instead of the load. The design must

ensure the voltage feedback divider normal operation at all conditions.

The output overvoltage protections have the latch-off response.

7.3.4.4 Overpower Protection

The Over Power Protection, OPP, limits the maximum average output power. When the output is overloaded, it is

important to shutdown the module to prevent it from further damage, or propagating the fault into other portion of

the entire system. Given the extremely high switching frequency, it is not practical to implement the traditional

cycle-by-cycle current limit. Instead, the UCC14240-Q1 device relies on the Over Power Protection (OPP)

working together with the output undervoltage protection.

As discussed in Power Handling Capability, with the input voltage feedforward, and the "baby" burst duty cycle

adjustment, the maximum power delivery capability of the UCC14240-Q1 is well controlled. The impact of OPP

on the relationship between Vin and maximum output power is shown in 图7-8.

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Max

Power

Disable OPP

Enable OPP

Vin

图7-8. Maximum Output Power Under Different Input Voltage Condition

When the load exceeds the maximum power delivery capability, the output voltage starts to droop. When the

output voltage falls below the Under Voltage Protection threshold, the output undervoltage protection is triggered

and the parts latches off into a safe state.

7.3.4.4.1 Output Undervoltage Protection

The output voltage under voltage protection is based on the FBVDD and FBVEE pin voltages. When the FBVDD

pin voltage becomes lower than its UVP threshold V_{VDD_UVP_FALL}, or the FBVEE pin voltage becomes lower than

its UVP threshold V_{VEE_UVP_FALL}, the undervoltage protection is activated. The UCC14240-Q1 stops switching,

and the PG pin becomes open.

During soft start, the output voltages rise from zero. Both FBVDD and FBVEE pin voltage are below the UVP

thresholds. The UVP is disabled during the soft start. If the pin voltage cannot reach the UVP recovery

thresholds (V_{VDD_UVP_RISE}, V_{VEE_UVP_RISE}) after the soft start completes, undervoltage protection is activated.

The UCC14240-Q1 stops switching, and the PG pin becomes open.

The undervoltage protection has a latched-off response. After it is activated, the latch-off state can be cleared by

recycling V_VIN. Toggling ENA pin can also reset the latch-off state. Refer to ENA and PG for details.

7.3.4.5 Overtemperature Protection

UCC14240-Q1 integrates the primary-side, secondary-side power stages, as well as the isolation transformer.

The power loss caused by the power conversion causes the module temperature higher than the ambient

temperature. To ensure the safe operation of the power module, the UCC14240-Q1 device is equipped with

over-temperature protection. Both the primary-side power stage, and the secondary-side power stage

temperatures are sensed and compared with the over-temperature protection threshold. If the primary-side

power stage temperature becomes higher than TSHUTP_{PRIMARY_RISE}, or the secondary-side power stage

temperature becomes higher than TSHUTS_{SECONDARY_RISE}, the module enters over-temperature protection

mode. The module stops switching; PG pin becomes open. After protection, the module enters latch-off mode.

When the power stage temperature drops below the over-temperature recovery threshold, recycling V_VIN, or

toggling ENA pin voltage brings the model out of latch-off mode. Depending on ENA pin voltage, the module

either starts switching, delivering power to the secondary side, or in the standby mode waiting for ENA pin

voltage becomes high.

7.4 Device Functional Modes

Depending on the input and output conditions, ENA pin voltage, as well as the device temperature, the

UCC14240-Q1 operates in one of the below operation modes.

1. Disable mode. In this mode, the module is off, but waiting for ENA pin becoming high to start operate.

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2. Soft-start mode. In this mode, the module starts to deliver power to the secondary side. The primary-side

operation duty cycle and secondary-side references are raised gradually to reduce the stress to the module.

3. Normal operation mode. In this mode, the module operates normally, delivers power to the secondary side.

4. Protection mode, auto-recovery. In this mode, the module is off, due to the input UVLO or OVLO protection.

After the input voltage fault is cleared, depending on the ENA pin voltage condition, it either becomes

disabled mode if the ENA pin voltage is low, or it goes through soft-start mode to the normal operation mode.

5. Protection mode, latched-off. In this mode, the module is off, due to other protections. The module remains

off even the fault causing the protection is cleared. Recycling V_VINoperation must ensure the input voltage

goes below the analog UVLO falling threshold (V_{VIN_ ANALOG_UVLOP_FALLING}) first to reset the latch-off state,

or the ENA pin is toggled Low (OFF) then High (ON).

表 7-1 lists the supply functional modes for this device. The ENA pin has an internal weak pull-down resistance

to ground, but TI does not recommend leaving this pin open.

表7-1. Device Functional Modes

INPUT

ENA

OUTPUTS

Operation Mode

V_{(VDD –VEE)}

V_{(COM –VEE)}

V_VIN

FAULT

PG Open Drain

High

Isolated Output1 Isolated Output2

Protection mode,

auto-recovery

V_VIN< V_{VIN_UVLOP_RISING}

X

OFF

V_{VIN_UVLOP_RISING}< V_VIN

V_{VIN_OVLO_RISING}

<

LOW

HIGH

X

High

Disable mode

V_{VIN_UVLOP_RISING}< V_VIN

V_{VIN_OVLO_RISING}

<

Regulating at

Setpoint

Regulating at

Setpoint

NO FAULT

YES FAULT

X

Low

Normal operation

V_{VIN_UVLOP_RISING}< V_VIN

V_{VIN_OVLO_RISING}

Protection mode,

latched-off

OFF

High

Protection mode,

auto-recovery

V_VIN> V_{VIN_OVLO_RISING}

High

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8 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The UCC14240-Q1 device is suitable for applications that have limited board space and desire more integration.

This device is also suitable for very high voltage applications, where power transformers meeting the required

isolation specifications are bulky and expensive.

8.2 Typical Application

The following figures show the typical application schematics for the UCC14240-Q1 device configurations

supplying an isolated load.

GNDP

PG

VEE

VEEA

FBVDD

FBVEE

RLIM

VEE

VDD

C_OUT2

PG

ENA

R_LIM

GNDP

COM

C_VINA

R_VINA

R_{FBVEE_TOP}

VIN

VEE

VIN

V_IN

VDD

C_IN

GNDP

C_FBVEE

VDD

R_{FBVEE_BOT}

C_OUT3

VEE

R_{FBVDD_TOP}

C_OUT1

C_FBVDD

R_{FBVDD_BOT}

图8-1. Dual Adjustable Output Configuration

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GNDP

PG

VEE

VEEA

FBVDD

FBVEE

RLIM

VEE

VDD

R_{FBVDD_TOP}

PG

ENA

R_LIM

GNDP

R_{FBVDD_BOT}

(op onal)

C_VINA

C_FBVDD

VIN

R_VINA

VEE

VIN

V_IN

VDD

C_IN

GNDP

C_OUT2

VDD

VEE

C_OUT1

图8-2. Single Adjustable Output Configuration

8.2.1 Design Requirements

Designing with the UCC14240-Q1 module is simple. First, choose single output or dual output. Determine the

voltage for each output and then set the regulation through resistor dividers. The gate charge of the power

device determines the amount of output decoupling capacitance needed at the gate driver input. Calculate the

RLIM resistor value for regulating the (COM –VEE) voltage rail for a dual output. Finally, add the recommended

input and output capacitors according to the procedure below.

8.2.2 Detailed Design Procedure

Place ceramic decoupling capacitors as close as possible to the device pins. For the input supply, place the

capacitors between pins 6 to 7 (VIN) and pins 8 to 9 (GNDP). For the isolated output supply, (VDD – VEE),

place the capacitors between pins 28 to 29 (VDD) and pins 30 to 31 (VEE). For the isolated output supply, (COM

– VEE), place an RLIM resistor between the RLIM pin and the gate driver COM supply input. Also place

decoupling capacitors at the gate driver supply pins (COM and VEE) and at gate driver supply pins (VDD and

VEE) with values according to the following component calculation sections. These locations are of particular

importance to all the decoupling capacitors because the capacitors supply the transient current associated with

the fast switching waveforms of the power drive circuits. Ensure the capacitor dielectric material is compatible

with the target application temperature.

8.2.2.1 Capacitor Selection

The UCC14240-Q1 device creates an isolated output VDD-VEE as its main output. The device also creates a

second output COM-VEE, using VDD-VEE as its power source. Because both outputs are isolated from the

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input, and sharing VEE as the common reference point, the UCC14240-Q1 outputs can be configured as dual-

output two-positive, dual-output two-negative, or dual-output one-positive and one-negative. UCC14240-Q1

output can also be used as a single positive output or single negative output.

When the module is configured as dual-output, one-positive output, one-negative output; it is very important to

properly select the output capacitor ratios C_OUT2and C_OUT3to optimize the regulation and avoid causing an

over-voltage or under-voltage fault.

表8-1. Calculated Capacitor Values

CAPACITOR

VALUE (µF)

NOTES

Place a 10-μF and a 0.1-μF high-frequency decoupling capacitor in parallel close to VIN

pins. A capacitance greater than 10uF can be used to reduce the voltage ripple when the

series impedance from the voltage source to the VIN pins is large.

Optionally, connect a 330pF 0402 size high-frequency bypass ceramic capacitor close to

analog VIN PIN 6 and GNDP PIN 5 when the input voltage ripple is large enough to interfere

with the internal input voltage sense signal and the normal startup operation.

For extreme input ripple voltage cases, connect a 4.75-ohm filter resistor to power input,

PIN7, and connect a 10-μF ceramic capacitor from analog VIN PIN 6, to power analog

GNDP.

C_IN

10 + 0.1

In most cases, the RC input filter is not needed. If the filter resistor is not placed, make sure

both PIN 6 and PIN 7 are connected to input voltage.

Add a 2.2-μF and a 0.1-μF capacitor for high-frequency decoupling of (VDD –VEE).

Place close to the VDD and VEE pins. A capacitance greater than 2.2uF can be used to

reduce the output voltage ripple.

C_OUT1

2.2 + 0.1

Bulk charge, decoupling output capacitors are required at the gate driver pins. The C_OUT2

and C_OUT3capacitance ratio is important to optimize the dual output voltage divider accuracy

during charge or discharge switching cycles.

C_OUT2

C_OUT3

See below

The selection of C_OUT2and C_OUT3is based on the gate charge requirement for the gate driver load, the charge

balancing during the start-up, and the expected maximum current loading.

During the startup, the ratio between C_OUT2and C_OUT3must be equal to the ratio between (COM−VEE) and

(VDD−COM) and offset by the loading current from VDD-COM and COM-VEE, to allow both COM to VEE and

VDD to VEE voltages reaches steady state at the same time, as shown in 方程式1.

First calculate the C_OUT2value based on the Gate charge of the power device Q_{G_Total}, whether IGBT or SiC

power MOSFET, and the percent of voltage droop wanted during the turn-on of the gate with respect to the

positive gate voltage applied, VDD to COM.

Q

G_Total

C

=

(1)

OUT2

Percent_Cdroop

× V

VDD − COM

100

where

• Q_{G_Total}is the total gate charge of the power switch

Then calculate the C_OUT3value based on the output voltage ratios, the load current expected, and the variation

of the output capacitors.

C

× V

× I

− I

OUT2

VDD − COM

MAX_POWER

COM − VEE

VDD − COM

C

=

(2)

OUT3

V

× I

− I

COM − VEE

MAX_POWER

where the load I_VDD-COMand I_COM-VEEare the load currents respectively, and the I_{MAX_POWER}is the SOA

Maximum Power (P_{MAX_SOA}) divided by the V_VDD-VEEoutput voltage.

I

= I

+ I

Otℎer_load_VDD −COM

(3)

VDD − COM

Q_Driver_VDD −COM

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I

= I

+ I

Otℎer_load_COM − VEE

(4)

COM − VEE

Q_Driver_COM − VEE

where

• I_(VDD-COM)is the total current from VDD to COM, excluding average gate drive current.

• I_(COM-VEE)is the total current from COM to VEE, excluding average gate drive current.

• I_{Q_DRIVER_VDD-COM}is the maximum quiescent current of the gate driver from (VDD –COM), and any current

pulled from VDD by external logic must be included.

• I_{Q_DRIVER_COM-VEE}is the maximum quiescent current of the gate driver from (COM –VEE),

• I_{Other_load_VDD-COM}is the maximum current pulled from VDD to COM by external logic.

• I_{Other_load_COM-VEE}is the maximum current pulled from COM to VEE by external logic.

and

P

MAX

I

=

(5)

POWER

V

VDD − VEE

The approximate P_MAXvalue can be extracted from the provided SOA curves at the respective ambient

temperature.

Calculate C_OUT3using worst case capacitor values based on expected variation, C_{OUT3_maximum}, and

C_{OUT3_Minimum}. This action makes sure the capacitor ratio tends to push the COM-VEE voltage to a slightly

lower value than the target regulation value during startup.

备注

C_OUT2and C_OUT3are the total capacitance on the VDD and VEE outputs. They include the capacitors from both

the isolated bias supply and the gate driver circuit.

The sizes of C_OUT2and C_OUT3are determined by the gate driver load gate charge and ripple voltage

requirement. C_OUT1can then be used to reduce the total ripple voltage and to soften the start-up time.

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8.2.2.2 R_LIMResistor Selection

When the module is configured as dual-positive or dual-negative outputs, the RLIM resistor is a true current

limiting resistor. Set up the RLIM resistor value as the maximum load current needed for V_COM-VEE, using 方程式

6. I_{VOUT2_max}is the maximum load current for V_COM-VEEoutput.

V

COM − VEE

R

=

− R

(6)

LIM

LIM_INT

I

VDD − COM _max

R_{LIM_INT}is the internal switch resistance value of 30 Ωtypical.

For isolated gate driver applications, one positive and one negative outputs are needed. In this case, VDD-VEE

is the total output voltage, and the middle point becomes the reference point. Because the total voltage between

VDD and VEE is always regulated through the FBVDD feedback, the RLIM pin only must regulate the middle

point voltage so that it can give the correct positive and negative voltages. The RLIM control is achieved through

FBVEE pin as described in COM-VEE Voltage Regulation.

Based on Capacitor Selection, when selecting the output capacitor ratio proportional to the voltage ratio, the

capacitors form a voltage divider. The middle point voltage must naturally give the correct positive and negative

voltages. At the same time, for the gate driver circuit, the gate charge pulled out from the positive rail capacitor

during turn-on is fed back to the negative rail capacitor during turn-off, the two output rail load must always be

balanced. However, due to the gate driver circuit quiescent current unbalancing, and the two-rail capacitance

tolerances, the middle point voltage can move away with time. The RLIM pin provides an opposite current to

keep the middle point voltage at the correct level.

As illustrated in 图8-3 (a), without considering the gate charge, the gate driver circuit quiescent current loads the

positive rail and negative rail differently. The net current shows up as a DC offset current to the middle point.

As illustrated in 图 8-3 (b), every time the gate driver circuit turns-on the main power switch, it pulls the charge

out of the positive and negative rail output capacitors. When the module power stage provides energy to the

secondary side, refreshing those capacitors, the same charge is fed into both capacitors. If the capacitor values

are perfect, the voltage rise in the capacitors will be proportional. The positive and negative voltages would not

change. However, due to the capacitor tolerances, the capacitor values are not perfectly matched. The voltages

will rise at different ratios with the smaller capacitor rising faster. Over time, the middle point voltage, COM,

would pull to a different value. A load across one of the capacitors will pull towards a voltage imbalance. The

RLIM function counteract the voltage imbalance and bring the COM voltage back into regulation.

VDD=Q/C_OUT2

VEE=Q/C_OUT3

ISO Driver

I_{q_off}=I_{q_VDD}−I_{q_VEE}

VDD/ VEE=C_OUT3/C_OUT2

VDD

RLIM

VEE

VDD

RLIM

VEE

Q

C_OUT2

I_{q_VDD}

VIN

VDD

VEE

VIN

COM

I_{q_off}

OUT

COM

VEE

COM

Q

COM

I_{q_VEE}

GNDP

C_OUT3

GNDP

COM

VEE

(a) Load current unbalancing

(b) Capacitance unbalancing

图8-3. Source of voltage unbalancing

Considering these two effects, the RLIM must provide enough current to compensate this offset current. The

RLIM must be low enough to provide enough current, but not too low otherwise the middle point voltage is

corrected at each turn on and turn off edge of the gate driver and excessive power loss is generated.

The R_LIMresistor chosen can provide enough current for the load using the following equations, whichever has

lower R_LIMvalue. 方程式 7 shows source current due to capacitor variation and gate driver quiescent current

(I_Q). 方程式8 shows sink current due to capacitor variation and I_Q.

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R

(7)

(8)

LIM_MAX

VDD − COM

=

C

× 1 − ∆ C

C

OUT3

× 1 − ∆ C

OUT3

× 1 − ∆ C

OUT3

+ C

−

× Q

× f

+

I

− I

COM − VEE VDD − COM

G_Total

SW

C

+ C

OUT2

OUT3

OUT2

OUT3

− R

LIM_INT

R

LIM_MAX

VEE − COM

=

C

× 1 − ∆ C

C

OUT2

× 1 − ∆ C

OUT2

+ C × 1 − ∆ C

OUT3

OUT2

× Q

× f

− I

COM − VEE VDD − COM

G_Total

SW

+ C

C

OUT2

OUT3

OUT2

OUT3

− R

LIM_INT

Select RLIM value to be the lowest of either 1) the RLIM needed for capacitor imbalance and the load, or 2) the

RLIM needed to respond to a 10% overshoot of V_COM-VEEwithin 1.5 ms with the given load current.

V

COM − VEE

R

=

− R

(9)

LIM_MAX_for_oversℎoot

LIM_INT

0 . 10 × V

VDD − COM

C

×

+ I

− I

VDD − COM COM − VEE

OUT3_max

1 . 5 ms

where

• Q_{G_Total}is the total gate charge of power switch.

• f_SWis the switching frequency of gate drive load.

R_LIMvalue determines response time of (COM – VEE) regulation. Too low an R_LIMvalue can cause oscillation

and can overload (VDD – VEE). Too high an R_LIMvalue can give offset errors, due to slow response. If R_LIMis

greater than above calculations, then there is not enough current available to replenish the charge to the output

capacitors, causing a charge imbalance where the voltage is not able to maintain regulation, and eventually

exceeds the OVP2 or UVP2 FAULT thresholds and shutting down the device for protection. Choose R_LIMvalue

to be 10% less than the smaller value of the two calculated results.

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8.2.3 Application Curves

The PMP23223 is a reference design that pairs the complementary UCC14240-Q1 isolated DC/DC power

module with the UCC21732-Q1 isolated gate driver for a SiC power MOSFET or IGBT power module. The

following waveforms show the controlled soft start for both positive and negative rails. Also shown, is the fast

and highly accurate voltage regulation during gate driver switching from 1 kHz to 35 kHz. See PMP23223

reference design test report for more details.

图8-4. Power-Up Sequence.

图8-5. Ripple voltage: VEE-COM Switching 100-nF

Load at 1 kHz.

图8-6. Ripple voltage: VDD-VEE Switching 100-nF 图8-7. Ripple voltage: VEE-COM Switching 100-nF

Load at 1 kHz. Load at 35 kHz.

图8-8. Ripple voltage: VDD-VEE Switching 100-nF 图8-9. Gate Waveform Switching 100 nF at 1 kHz.

Load at 35 kHz.

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图8-10. Gate Waveform Switching 100 nF at 35kHz.

8.3 System Examples

The UCC14240-Q1 module is designed to allow a microcontroller host to enable it with the ENA pin for proper

system sequencing. The PG output also allows the host to monitor the status of the module. The /PG pin goes

low when there are no faults and the output voltage is within ±10% of the set target output voltage. The output

voltage is meant to power a gate driver for either IGBT or SiC FET power device. The host can start sending

PWM control to the gate driver after the PG pin goes low to ensure proper sequencing. Shown below is the

system diagram for the dual-output configuration and a system diagram for the single output configuration.

VIN

VDD

VISO1 = 25V

VDD

VIN

CIN

GNDP

COUT2

Buck

RLIM

COUT1

EMITTER/

SOURCE

400-800V

RLIM

Open- Drain

From Battery

COM

/PG

COUT3

ENA

5V/3.3V

VEE

EMITTER/

SOURCE

Microcontroller

VDD

VCC

5V/3.3V

VVCCCC

^/PP^GG^_BIAS

PWM

Control

GATE

VEE

PWM

EN

ON_BIAS

To Motor

GNDP

-

Similar Isolated DC DC + Isolated Gate Driver Block as Above

图8-11. Dual Output System Configuration

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VIN

VDD

VISO1 = 25V

VDD

VIN

CIN

GNDP

Buck

RLIM

COUT

400-800V

RLIM

Open- Drain

From Battery

/PG

ENA

5V/3.3V

GATE

VEE

EMITTER

/ SOURCE

EMITTER

/ SOURCE

Microcontroller

VDD

VCC

5V/3.3V

VVCCCC

^/PP^GG^_BIAS

PWM

Control

GATE

VEE

PWM

EN

ON_BIAS

To Motor

GNDP

-

Similar Isolated DC DC + Isolated Gate Driver Block as Above

图8-12. Single Output System Configuration

8.4 Power Supply Recommendations

The recommended input supply voltage (V_VIN) for UCC14240-Q1 is between 21 V and 27 V. To help ensure

reliable operation, adequate decoupling capacitors must be located as close to supply pins as possible. Local

bypass capacitors must be placed between the VIN and GNDP pins at the input; between VDD and VEE at the

isolated output supply; and COM and VEE at the lower voltage output supply. TI recommends low ESR, ceramic

surface mount capacitors. TI further suggests placing two such capacitors: one with a value of 2.2 μF for supply

bypassing and an additional 0.1-μF capacitor in parallel for high frequency filtering. The input supply must have

an appropriate current rating to support output load required by the end application.

8.5 Layout

8.5.1 Layout Guidelines

The UCC14240-Q1 integrated isolated power solution simplifies system design and reduces board area usage.

Follow these guidelines for proper PCB layout to achieve optimum performance.

• Place decoupling capacitors as close as possible to the device pins. For the input supply, place the

capacitors between pin 7 (power VIN) and pins 8–18 (power GNDP), and place the capacitors between pin 6

(analog VIN) and pins 1, 2, and 5 (analog GNDP). For the isolated output supply, place the capacitors

between pin 28, 29 (VDD) and pins 19–25, 30–31, 35–36 (VEE). This location is of particular importance

to the input decoupling capacitor because this capacitor supplies the transient current associated with the fast

switching waveforms of the power drive circuits.

The capacitors between pin 6 (analog VIN) and pins 1, 2, and 5 (analog GNDP) are optional and

recommended.

• Because the device does not have a thermal pad for heat-sinking, the device dissipates heat through the

respective GND pins. Ensure that enough copper (preferably a connection to the ground plane) is present on

GNDP and VEE pins for best heat-sinking.

• If space and layer count allow, TI recommends to connect the VIN, GNDP, VDD, and VEE pins to internal

ground or power planes through multiple vias. Alternatively, make the traces that are connected to these pins

as wide as possible to minimize losses.

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• Minimize capacitive coupling between the RLIM pin and the FBVEE pin by separating the traces while

routing, and if possible use a via near the FBVEE pin to route the feedback connection through a different

layer.

• A minimum of four layers is recommended to accomplish a good thermal PCB design. Inner layers can be

used to create a high-frequency bypass capacitor between GNDP and VEE, which in turn mitigates radiated

emissions.

• Pay close attention to the spacing between primary ground plane (GNDP) and secondary ground plane

(VEE) on the outer layers of the PCB. The effective creepage and clearance of the system is reduced if the

two ground planes have a lower spacing than that of the UCC1413x-Q1 package.

• To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or

copper below the UCC14240-Q1 module.

8.5.2 Layout Example

The layout example shown in the following figures is from the evaluation board UCC14240-Q1EVM,

UCC14240EVM-052, and based on the 图8-1 design.

图8-13. UCC14240-Q1EVM, PCB Top Layer, Assembly

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图8-14. UCC14240-Q1EVM, Signal Layer 2 (Same as Layer 3)

图8-15. UCC14240-Q1EVM, Signal Layer 3 (Same as Layer 2)

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图8-16. UCC14240-Q1EVM, PCB Bottom Layer, Assembly (Mirrored View)

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9 Device and Documentation Support

9.1 Documentation Support

9.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs Requiring

Single, Positive or Dual, Positive/Negative Bias Power user's guide

• Texas Instruments, Isolation Glossary

9.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

9.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	UCC14240QDWNRQ1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类 2.0W、24Vin、25Vout、高密度、> 3kVRMS、隔离式直流/直流模块 \| DWN \| 36 \| -40 to 125
文件：	总44页 (文件大小：2931K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC14240QDWNRQ1 [TI]

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