UCC21520-Q1 [TI]

具有双输入、禁用引脚、死区时间的汽车类 4A/6A、5.7kVRMS 隔离式双通道栅极驱动器;


型号：	UCC21520-Q1
厂家：	TEXAS INSTRUMENTS
描述：	具有双输入、禁用引脚、死区时间的汽车类 4A/6A、5.7kVRMS 隔离式双通道栅极驱动器栅极驱动驱动器
文件：	总51页 (文件大小：2057K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Support &

Community

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

用于汽车的 UCC21520-Q1、UCC21520A-Q1 4A、6A、5.7kV_RMS隔离式

双通道栅极驱动器

1 特性

3 说明

•

符合汽车应用要求

具有符合 AEC-Q100 标准的下列结果

UCC21520-Q1 是隔离式双通道栅极驱动器，具有 4A

峰值拉电流和 6A 峰值灌电流。该器件设计用于驱动高

达 5MHz 的功率 MOSFET、IGBT 和 SiC MOSFET，

具有一流的传播延迟和脉宽失真度。

–

器件温度 1 级

器件 HBM ESD 分类等级 H2

器件 CDM ESD 分类等级 C6

输入侧通过一个 5.7kV_RMS增强型隔离层与两个输出驱

动器隔离，共模瞬态抗扰度 (CMTI) 的最小值为

100V/ns。两个二次侧驱动器之间采用内部功能隔离，

支持高达 1500 V_DC的工作电压。

•

通用：双路低侧、双路高侧或半桥驱动器

工作温度范围：–40 至 +125°C

开关参数：

–

19ns 典型传播延迟

10ns 最小脉冲宽度

5ns 最大延迟匹配度

6ns 最大脉宽失真度

每个驱动器可配置为两个低侧驱动器、两个高侧驱动器

或一个死区时间 (DT) 可编程的半桥驱动器。禁用引脚

可同时关断两个输出，在保持开路或接地时允许器件正

常运行。作为一种失效防护机制，初级侧逻辑故障会强

制两个输出为低电平。

•

共模瞬态抗扰度 (CMTI) 大于 100 V/ns

浪涌抗扰度高达 12.8kV

每个器件接受高达 25V 的 VDD 电源电压。凭借 3V 至

18V 的宽输入电压 VCCI 范围，该驱动器非常适合连

接模拟和数字控制器。所有电源电压引脚都具有欠压锁

定 (UVLO) 保护功能。

隔离栅寿命 > 40 年

4A 峰值拉电流，6A 峰值灌电流输出

TTL 和 CMOS 兼容输入

3V 至 18V 输入 VCCI 范围，可连接数字和模拟控

制器

凭借上述所有高级功能，UCC21520-Q1 可以实现高

效率、高功率密度和稳健性。

•

高达 25V 的 VDD 输出驱动电源

–

5V 和 8V VDD UVLO 选项

•

可通过编程的重叠和死区时间

抑制短于 5ns 的输入脉冲和噪声瞬态

可针对电源排序快速禁用

安全相关认证：

器件比较⁽¹⁾

器件编号

UCC21520-Q1

UCC21520A-Q1

封装

UVLO 级别

DW SOIC (16)

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

–

8000V_PK增强型隔离，符合 DIN V VDE V

0884-11:2017-01 标准

符合 UL 1577 标准且长达 1 分钟的 5.7kV_RMS

隔离

功能方框图

VCCI 3,8

16 VDDA

15 OUTA

14 VSSA

获得 CSA 认证，符合 IEC 60950-1、IEC

62368-1、IEC 61010-1 和 IEC 60601-1 终端设

备标准

Driver

DEMOD UVLO

MOD

INA

DIS

–

获得 GB4943.1-2011 CQC 认证

Disable,

UVLO

and

13 NC

12 NC

Functional Isolation

2 应用

Deadtime

11 VDDB

10 OUTB

•

HEV 和 BEV 电池充电器

Driver

INB

MOD

DEMOD UVLO

直流/直流和交流/直流电源中的隔离式转换器

电机驱动和直流-交流太阳能逆变器

不间断电源 (UPS)

GND

VSSB

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSCQ2

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

7.5 Power-up UVLO Delay to OUTPUT........................ 16

7.6 CMTI Testing........................................................... 17

Detailed Description ............................................ 18

8.1 Overview ................................................................. 18

8.2 Functional Block Diagram ....................................... 18

8.3 Feature Description................................................. 19

8.4 Device Functional Modes........................................ 23

Application and Implementation ........................ 26

9.1 Application Information............................................ 26

9.2 Typical Application .................................................. 26

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings ............................................................ 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Power Ratings........................................................... 5

6.6 Insulation Specifications............................................ 6

6.7 Safety-Related Certifications..................................... 7

6.8 Safety-Limiting Values .............................................. 7

6.9 Electrical Characteristics........................................... 8

6.10 Switching Characteristics........................................ 9

6.11 Insulation Characteristics Curves ......................... 10

6.12 Typical Characteristics.......................................... 11

Parameter Measurement Information ................ 15

7.1 Propagation Delay and Pulse Width Distortion....... 15

7.2 Rising and Falling Time ......................................... 15

7.3 Input and Disable Response Time.......................... 15

7.4 Programable Dead Time ........................................ 16

10 Power Supply Recommendations ..................... 37

11 Layout................................................................... 38

11.1 Layout Guidelines ................................................. 38

11.2 Layout Example .................................................... 39

12 器件和文档支持 ..................................................... 41

12.1 文档支持 ............................................................... 41

12.2 认证....................................................................... 41

12.3 接收文档更新通知 ................................................. 41

12.4 社区资源................................................................ 41

12.5 商标....................................................................... 41

12.6 静电放电警告......................................................... 41

12.7 术语表 ................................................................... 41

13 机械、封装和可订购信息....................................... 41

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision A (May 2018) to Revision B

Page

•

已更改将 UCC21520A-Q1“预告信息”销售状态更改成了“初始发行版”。................................................................................ 1

Added detailed description for DISABLE Pin and DT Pin ...................................................................................................... 3

Changed t_PWDin the switching characteristic section............................................................................................................. 9

已添加 feature descriptions for UVLO delay to OUTPUT .................................................................................................... 16

已添加 bullet "It is recommended..." bullet to the component placement in the Layout Guidelines. ................................... 38

Changes from Original (October 2017) to Revision A

Page

•

已添加在该数据表中添加了 UCC21520A-Q1 器件（5V UVLO 选项） ................................................................................. 1

已添加添加了 UCC21520A-Q1 预告信息。........................................................................................................................... 1

Changed t_PWDin the switching characteristic section............................................................................................................. 9

已添加 typical curves of 5-V UVLO hysteresis and ON-OFF thresholds.............................................................................. 12

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

5 Pin Configuration and Functions

DW Package

16-Pin SOIC

Top View

INA

INB

VDDA

OUTA

VSSA

VCCI

GND

DISABLE

VDDB

OUTB

VSSB

VCCI

Not to scale

Pin Functions

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled

low internally if left open. It is recommended to tie this pin to ground if not used to achieve

better noise immunity. Bypass using a ≈1nF low ESR/ESL capacitor close to DIS pin when

connecting to a micro controller with distance.

DISABLE

Programmable dead time function.

Tying DT to VCCI allows the outputs to overlap. Leaving DT open sets the dead time to <15

ns. Placing a 500-Ω to 500-kΩ resistor (RDT) between DT and GND adjusts dead time

according to: DT (in ns) = 10 x R_DT(in kΩ). It is recommended to parallel a ceramic

capacitor, 2.2 nF or above, close to the DT pin with R_DTto achieve better noise immunity.

GND

INA

Primary-side ground reference. All signals in the primary side are referenced to this ground.

Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin is

pulled low internally if left open. It is recommended to tie this pin to ground if not used to

achieve better noise immunity.

Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin is

pulled low internally if left open. It is recommended to tie this pin to ground if not used to

achieve better noise immunity.

INB

–

No Internal connection.

No internal connection.

–

No internal connection.

OUTA

OUTB

Output of driver A. Connect to the gate of the A channel FET or IGBT.

Output of driver B. Connect to the gate of the B channel FET or IGBT.

Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor

located as close to the device as possible.

VCCI

VDDA

Primary-side supply voltage. This pin is internally shorted to pin 3.

Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL

capacitor located as close to the device as possible.

Secondary-side power for driver B. Locally decoupled to VSSB using low ESR/ESL capacitor

located as close to the device as possible.

VDDB

VSSA

VSSB

Ground for secondary-side driver A. Ground reference for secondary side A channel.

Ground for secondary-side driver B. Ground reference for secondary side B channel.

(1) P =Power, G= Ground, I= Input, O= Output

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

Input bias pin supply voltage

Driver bias supply

VCCI to GND

VDDA-VSSA, VDDB-VSSB

V_VDDA+0.3,

V_VDDB+0.3

OUTA to VSSA, OUTB to VSSB

–0.3

–2

Output signal voltage

OUTA to VSSA, OUTB to VSSB,

Transient for 200 ns

V_VDDA+0.3,

V_VDDB+0.3

INA, INB, DIS, DT to GND

INA, INB Transient for 50ns

VSSA-VSSB, VSSB-VSSA

–0.3

–5

V_VCCI+0.3

1500

Input signal voltage

Channel to channel voltage

(2)

Junction temperature, T_J

–40

–65

150

°C

Storage temperature, T_stg

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) To maintain the recommended operating conditions for T_J, see the Thermal Information.

6.2 ESD Ratings

VALUE

±4000

±1500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

VCCI

VCCI Input supply voltage

Driver output bias supply

VDDA,

VDDB

UCC21520A-Q1 5-V UVLO version

UCC21520-Q1 8-V UVLO version

6.5

9.2

VDDA,

VDDB

Driver output bias supply

T_A

T_J

Ambient Temperature

Junction Temperature

–40

125

130

°C

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

6.4 Thermal Information

UCC21520-Q1

UNIT

THERMAL METRIC⁽¹⁾

DW-16 (SOIC)

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

67.3

34.4

32.1

18.0

31.6

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Power Ratings

VALUE

1.05

UNIT

P_D

Power dissipation by UCC21520-Q1

P_DI

Power dissipation by transmitter side of

UCC21520-Q1

VCCI = 18 V, VDDA/B = 12 V, INA/B = 3.3 V,

3 MHz 50% duty cycle square wave 1-nF

load

0.05

P_DA, P_DB

Power dissipation by each driver side of

UCC21520-Q1

0.5

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

6.6 Insulation Specifications

PARAMETER

TEST CONDITIONS

Shortest pin-to-pin distance through air

VALUE

> 8

UNIT

CLR

CPG

External clearance⁽¹⁾

External creepage⁽¹⁾

Shortest pin-to-pin distance across the package surface

> 8

Minimum internal gap (internal clearance) of the double

insulation (2 × 10.5 µm)

DTI

CTI

Distance through insulation

>21

µm

Comparative tracking index

Material group

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

> 600

Rated mains voltage ≤ 600 V_RMS

Rated mains voltage ≤ 1000 V_RMS

I-IV

I-III

Overvoltage category per

IEC 60664-1

DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01⁽²⁾

Maximum repetitive peak

isolation voltage

V_IORM

AC voltage (bipolar)

2121

V_PK

AC voltage (sine wave); time dependent dielectric breakdown

(TDDB), test (See 图 1)

1500

2121

8000

V_RMS

V_DC

V_PK

Maximum working isolation

voltage

V_IOWM

DC voltage

Maximum transient isolation V_TEST= V_IOTM, t = 60 sec (qualification)

V_IOTM

V_IOSM

voltage

V_TEST= 1.2 × V_IOTM, t = 1 s (100% production)

Maximum surge isolation

voltage⁽³⁾

Test method per IEC 62368-1, 1.2/50 µs waveform,

V_TEST= 1.6 × V_IOSM= 12800 V_PK(qualification)

8000

V_PK

Method a, After Input/Output safety test subgroup 2/3.

V_ini= V_IOTM, t_ini= 60s;

V_pd(m)= 1.2 X V_IORM= 2545 V_PK, t_m= 10s

Method a, After environmental tests subgroup 1.

V_ini= V_IOTM, t_ini= 60s;

q_pd

Apparent charge⁽⁴⁾

V_pd(m)= 1.6 X V_IORM= 3394 V_PK, t_m= 10s

Method b1; At routine test (100% production) and

preconditioning (type test)

V_ini= 1.2 × V_IOTM; t_ini= 1s;

V_pd(m)= 1.875 * V_IORM= 3977 V_PK, t_m= 1s

Barrier capacitance, input to

output⁽⁵⁾

C_IO

R_IO

V_IO= 0.4 sin (2πft), f =1 MHz

1.2

V_IO= 500 V at T_A= 25°C

> 10¹²

> 10¹¹

> 10⁹

Isolation resistance, input to

output⁽⁵⁾

V_IO= 500 V at 100°C ≤ T_A≤ 125°C

V_IO= 500 V at T_S=150°C

Pollution degree

Climatic category

40/125/21

UL 1577

V_TEST= V_ISO= 5700 V_RMS, t = 60 sec. (qualification),

V_ISO

Withstand isolation voltage

5700

V_RMS

V_TEST= 1.2 × V_ISO= 6840V_RMS, t = 1 sec (100% production)

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care

should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on

the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.

Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by

means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-pin device.

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

6.7 Safety-Related Certifications

VDE

CSA

CQC

Certified according to DIN V VDE V

0884-11:2017-01,

and DIN EN 60950-1 (VDE 0805

Teil 1):2014-08

Recognized under UL

1577 Component

Recognition Program

Certified according to IEC 60950-1, IEC

62368-1, IEC 61010-1 and IEC 60601-1

Certified according to GB

4943.1-2011

Reinforced insulation per CSA 60950-1-

07+A1+A2 and IEC 60950-1 2nd

Ed.+A1+A2, 800 V_RMSmaximum working

voltage (pollution degree 2, material group I)

Reinforced insulation per CSA 62368-1-14

and IEC 62368-1 2nd Ed., 800 V_RMS

maximum working voltage (pollution degree

2, material group I);

Basic insulation per CSA 61010-1-12+A1

and IEC 61010-1 3rd Ed., 600 V_RMS

maximum working voltage (pollution degree

2, material group III);

Reinforced Insulation Maximum

Transient Isolation voltage, 8000

Reinforced Insulation,

Altitude ≤ 5000 m,

Tropical Climate 660 V_RMS

maximum working voltage

V_PK

Maximum Repetitive Peak Isolation

Voltage, 2121 V_PK

;

Single protection, 5700

V_RMS

;

Maximum Surge Isolation Voltage,

8000 V_PK

2 MOPP (Means of Patient Protection) per

CSA 60601- 1:14 and IEC 60601-1

Ed.3+A1, 250 V_RMSmaximum working

voltage

Certificate number:

CQC16001155011

Certification number: 40040142

Master contract number : 220991

File number: E181974

6.8 Safety-Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.

PARAMETER

TEST CONDITIONS

SIDE

MIN

TYP

MAX

UNIT

_θJA= 67.3ºC/W, VDDA/B = 12 V, T_A

DRIVER A,

DRIVER B

25°C, T_J= 150°C

See 图 2

Safety output supply

current

I_S

R_θJA= 67.3ºC/W, VDDA/B = 25 V, T_A

DRIVER A,

DRIVER B

25°C, T_J= 150°C

See 图 2

INPUT

DRIVER A

DRIVER B

TOTAL

900

_θJA= 67.3ºC/W, T_A= 25°C, T_J= 150°C

P_S

T_S

Safety supply power

Safety temperature⁽¹⁾

°C

See 图 3

900

1850

150

(1) The maximum safety temperature, T_S, has the same value as the maximum junction temperature, T_J, specified for the device. The I_S

and P_Sparameters represent the safety current and safety power respectively. The maximum limits of I_Sand P_Sshould not be

exceeded. These limits vary with the ambient temperature, T_A.

The junction-to-air thermal resistance, R_θJA, in the Thermal Information table is that of a device installed on a high-K test board for

leaded surface-mount packages. Use these equations to calculate the value for each parameter:

T_J= T_A+ R_θJA× P, where P is the power dissipated in the device.

T_J(max)= T_S= T_A+ R_θJA× P_S, where T_J(max)is the maximum allowed junction temperature.

P_S= I_S× V_I, where V_Iis the maximum input voltage.

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

6.9 Electrical Characteristics

V_VCCI= 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA= V_VDDB= 12 V, 1-µF capacitor from VDDA and VDDB to

VSSA and VSSB, T_A= –40°C to +125°C, (unless otherwise noted)

PARAMETER

SUPPLY CURRENTS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_VCCI

VCCI quiescent current

V_INA= 0 V, V_INB= 0 V

1.5

1.0

2.0

1.8

I_VDDA

I_VDDB

VDDA and VDDB quiescent current V_INA= 0 V, V_INB= 0 V

(f = 500 kHz) current per channel,

C_OUT= 100 pF

I_VCCI

VCCI operating current

2.0

2.5

I_VDDA

I_VDDB

(f = 500 kHz) current per channel,

C_OUT= 100 pF

VDDA and VDDB operating current

VCCI UVLO THRESHOLDS

V_{VCCI_ON}

V_{VCCI_OFF}

V_{VCCI_HYS}

Rising threshold

2.55

2.35

2.7

2.5

0.2

2.85

2.65

Falling threshold VCCI_OFF

Threshold hysteresis

UCC21520A-Q1 VDD UVLO THRESHOLDS (5-V UVLO Version)

V_{VDDA_ON}

V_{VDDB_ON}

Rising threshold VDDA_ON,

VDDB_ON

5.7

5.4

6.0

5.7

0.3

6.3

V_{VDDA_OFF}

V_{VDDB_OFF}

Falling threshold VDDA_OFF,

VDDB_OFF

V_{VDDA_HYS}

V_{VDDB_HYS}

Threshold hysteresis

UCC21520-Q1 VDD UVLO THRESHOLDS (8-V UVLO Version)

V_{VDDA_ON,}

V_{VDDB_ON}

Rising threshold VDDA_ON,

VDDB_ON

8.3

7.8

8.7

8.2

0.5

9.2

8.7

V_{VDDA_OFF,}

V_{VDDB_OFF}

Falling threshold VDDA_OFF,

VDDB_OFF

V_{VDDA_HYS,}

V_{VDDB_HYS}

Threshold hysteresis

INA, INB AND DISABLE

V_INAH, V_INBH

V_DISH

Input high voltage

Input low voltage

1.6

0.8

1.8

V_INAL, V_INBL

V_DISL

1.2

V_{INA_HYS}

V_{INB_HYS}

V_{DIS_HYS}

Input hysteresis

0.8

Negative transient, ref to GND, 50

ns pulse

Not production tested, bench test

only

V_INA, V_INB

–5

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

Electrical Characteristics (continued)

V_VCCI= 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA= V_VDDB= 12 V, 1-µF capacitor from VDDA and VDDB to

VSSA and VSSB, T_A= –40°C to +125°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT

C_VDD= 10 µF, C_LOAD= 0.18 µF, f

= 1 kHz, bench measurement

I_OA+, I_OB+

Peak output source current

Peak output sink current

C_VDD= 10 µF, C_LOAD= 0.18 µF, f

= 1 kHz, bench measurement

I_OA-, I_OB-

I_OUT= –10 mA, T_A= 25°C, R_OHA

R_OHBdo not represent drive pull-

up performance. See t_RISEin

Switching Characteristics and

Output Stage for details.

R_OHA, R_OHB

Output resistance at high state

R_OLA, R_OLB

V_OHA, V_OHB

Output resistance at low state

Output voltage at high state

I_OUT= 10 mA, T_A= 25°C

0.55

V_VDDA, V_VDDB= 12 V, I_OUT= –10

mA, T_A= 25°C

11.95

V_VDDA, V_VDDB= 12 V, I_OUT= 10

mA, T_A= 25°C

V_OLA, V_OLB

Output voltage at low state

5.5

DEADTIME AND OVERLAP PROGRAMMING

Pull DT pin to VCCI

Overlap determined by INA INB

DT pin is left open, min spec

characterized only, tested for

outliers

Dead time

R_DT= 20 kΩ

160

200

240

6.10 Switching Characteristics

V_VCCI= 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA= V_VDDB= 12 V, 1-µF capacitor from VDDA and VDDB to

VSSA and VSSB, T_A= –40°C to +125°C, (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_RISE

Output rise time, 20% to 80%

measured points

C_OUT= 1.8 nF

t_FALL

t_PWmin

t_PDHL

t_PDLH

Output fall time, 90% to 10%

measured points

C_OUT= 1.8 nF

Minimum pulse width

Output off for less than minimum,

C_OUT= 0 pF

Propagation delay from INx to OUTx

falling edges

Propagation delay from INx to OUTx

rising edges

t_PWD

t_DM

Pulse width distortion |t_PDLH– t_PDHL

Propagation delays matching

between VOUTA, VOUTB

f = 100 kHz

High-level common-mode transient

immunity

INA and INB both are tied to VCCI;

V_CM=1500V; (See CMTI Testing)

|CM_H|

|CM_L|

100

V/ns

Low-level common-mode transient

immunity

INA and INB both are tied to GND;

V_CM=1500V; (See CMTI Testing)

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

6.11 Insulation Characteristics Curves

1.E+11

Safety Margin Zone: 1800 V_RMS, 254 Years

Operating Zone: 1500 V_RMS, 135 Years

TDDB Line (<1 PPM Fail Rate)

1.E+10

87.5%

1.E+9

1.E+8

1.E+7

1.E+6

1.E+5

1.E+4

1.E+3

20%

1.E+2

1.E+1

500 1500 2500 3500 4500 5500 6500 7500 8500 9500

Stress Voltage (V_RMS

)

图 1. Reinforced Isolation Capacitor

Life Time Projection

100

2000

I_VDDA/Bfor VDD=12V

I_VDDA/Bfor VDD=25V

1600

1200

800

400

100

150

200

100

150

200

Ambient Temperature (°C)

D001

图 2. Thermal Derating Curve for Safety-Related Limiting

图 3. Thermal Derating Curve for Safety-Related Limiting

Current

(Current in Each Channel with Both Channels Running

Simultaneously)

Power

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

6.12 Typical Characteristics

VDDA = VDDB= 12 V, VCCI = 3.3 V, T_A= 25°C, No load unless otherwise noted.

VDD=12v

VDD=25v

VDD= 12V

VDD= 25V

800

1600

2400

3200

4000

4800

5600

500

1000

1500

2000

2500

3000

Frequency (kHz)

D001

图 4. Per Channel Current Consumption vs. Frequency (No

图 5. Per Channel Current Consumption (I_VDDA/B) vs.

Load, VDD = 12 V or 25 V)

Frequency (1-nF Load, VDD = 12 V or 25 V)

50kHz

250kHz

500kHz

1MHz

VDD= 12V

VDD= 25V

85 100

-40 -20

80 100 120 140 160

Frequency (kHz)

Temperature (èC)

D001

图 6. Per Channel Current Consumption (I_VDDA/B) vs.

图 7. Per Channel (I_VDDA/B) Supply Current Vs. Temperature

Frequency (10-nF Load, VDD = 12 V or 25 V)

(No Load, Different Switching Frequencies)

1.6

1.2

0.8

0.4

1.8

1.6

1.4

1.2

VDD= 12V

VDD= 25V

VCCI= 3.3V

VCCI= 5V

-40

-20

100 120 140

-20

100 120 140

Temperature (èC)

D001

图 8. Per Channel (I_VDDA/B) Quiescent Supply Current vs

图 9. I_VCCIQuiescent Supply Current vs Temperature (No

Temperature (No Load, Input Low, No Switching)

Load, Input Low, No Switching)

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

Typical Characteristics (接下页)

VDDA = VDDB= 12 V, VCCI = 3.3 V, T_A= 25°C, No load unless otherwise noted.

Output Pull-Up

Output Pull-Down

t_RISE

t_FALL

-40

-20

100 120 140

Load (nF)

Temperature (èC)

D001

图 10. Rising and Falling Times vs. Load (VDD = 12 V)

图 11. Output Resistance vs. Temperature

Rising Edge (t_PDLH

Falling Edge (t_PDHL

)

Rising Edge (t_PDLH)

Falling Edge (t_PDHL

)

-40

-20

100 120 140

15 18

Temperature (èC)

VCCI (V)

D001

图 12. Propagation Delay vs. Temperature

图 13. Propagation Delay vs. VCCI

2.5

-1

-3

-5

-2.5

Rising Edge

Falling Edge

-5

-40

-20

100 120 140

Temperature (èC)

VDDA/B (V)

D001

图 14. Pulse Width Distortion vs. Temperature

图 15. Propagation Delay Matching (t_DM) vs. VDD

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

Typical Characteristics (接下页)

VDDA = VDDB= 12 V, VCCI = 3.3 V, T_A= 25°C, No load unless otherwise noted.

350

330

310

290

270

250

2.5

-2.5

Rising Edge

Falling Edge

-5

-40

-20

100 120 140

-40

-20

100 120 140

Temperature (èC)

D001

图 16. Propagation Delay Matching (t_DM) vs. Temperature

图 17. VDD 5-V UVLO Hysteresis vs. Temperature

550

530

510

490

470

450

6.5

5.5

V_{VDD_ON}

V_{VDD_OFF}

-40

-20

100 120 140

-40

-20

100 120 140

Temperature (èC)

D001

图 18. VDD 5-V UVLO Threshold vs. Temperature

图 19. VDD 8-V UVLO Hysteresis vs. Temperature

900

860

820

780

740

700

VCC=3.3V

VCC=5V

VCC=12V

V_{VDDA_ON}

V_{VDDA_OFF}

-40

-20

100 120 140

-40

-20

100 120 140

Temperature (èC)

D001

图 20. VDD 8-V UVLO Threshold vs. Temperature

图 21. IN/DIS Hysteresis vs. Temperature

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

Typical Characteristics (接下页)

VDDA = VDDB= 12 V, VCCI = 3.3 V, T_A= 25°C, No load unless otherwise noted.

1.2

1.14

1.08

1.02

0.96

0.9

1.92

1.84

1.76

1.68

1.6

VCC=3.3V

VCC= 5V

VCC=12V

VCC=3.3V

VCC= 5V

VCC=12V

-40

-20

100 120 140

-40

-20

100 120 140

Temperature (èC)

D001

图 22. IN/DIS Low Threshold

图 23. IN/DIS High Threshold

1500

1200

900

600

300

-6

R_DT= 20kW

R_DT= 100kW

-17

-28

-39

-50

R_DT= 20kW

R_DT= 100kW

-40

-20

100 120 140

-40

-20

100 120 140

Temperature (èC)

D001

图 24. Dead Time vs. Temperature (with R_DT= 20 kΩ and 100

kΩ)

图 25. Dead Time Matching vs. Temperature (with R_DT= 20

kΩ and 100 kΩ)

-2

-6

1 nF Load

10 nF Load

100

200

300

400

500

600

700

800

Time (ns)

D001

图 26. Typical Output Waveforms

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

7 Parameter Measurement Information

7.1 Propagation Delay and Pulse Width Distortion

图 27 shows how one calculates pulse width distortion (t_PWD) and delay matching (t_DM) from the propagation

delays of channels A and B. It can be measured by ensuring that both inputs are in phase and disabling the dead

time function by shorting the DT Pin to VCC.

INA/B

tPDHLA

tPDLHA

tDM

OUTA

OUTB

tPDLHB

tPDHLB

tPWDB = |tPDLHB t tPDHLB|

图 27. Overlapping Inputs, Dead Time Disabled

7.2 Rising and Falling Time

图 28 shows the criteria for measuring rising (t_RISE) and falling (t_FALL) times. For more information on how short

rising and falling times are achieved see Output Stage

90%

80%

t_RISE

t_FALL

20%

10%

图 28. Rising and Falling Time Criteria

7.3 Input and Disable Response Time

图 29 shows the response time of the disable function. It is recommended to bypass using a ≈1nF low ESR/ESL

capacitor close to DIS pin when connecting DIS pin to a micro controller with distance. For more information, see

Disable Pin .

INA

DIS High

Response Time

DIS

DIS Low

Response Time

OUTA

t_PDLH

90%

t_PDHL

10%

图 29. Disable Pin Timing

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

7.4 Programable Dead Time

Leaving the DT pin open or tying it to GND through an appropriate resistor (R_DT) sets a dead-time interval. For

more details on dead time, refer to Programmable Dead Time (DT) Pin.

INA

INB

90%

OUTA

10%

tPDHL

tPDLH

90%

OUTB

10%

tPDHL

Dead Time

(Set by RDT

Dead Time

(Determined by Input signals if

)

longer than DT set by RDT

)

图 30. Dead-Time Switching Parameters

7.5 Power-up UVLO Delay to OUTPUT

Before the driver is ready to deliver a proper output state, there is a power-up delay from the UVLO rising edge

to output and it is defined as t_{VCCI+ to OUT}for VCCI UVLO (typically 40us) and t_{VDD+ to OUT}for VDD UVLO (typically

50us). It is recommended to consider proper margin before launching PWM signal after the driver's VCCI and

VDD bias supply is ready. 图 31 and 图 32 show the power-up UVLO delay timing diagram for VCCI and VDD.

If INA or INB are active before VCCI or VDD have crossed above their respective on thresholds, the output will

not update until t_{VCCI+ to OUT}or t_{VDD+ to OUT}after VCCI or VDD crossing its UVLO rising threshold. However, when

either VCCI or VDD receive a voltage less than their respective off thresholds, there is <1µs delay, depending on

the voltage slew rate on the supply pins, before the outputs are held low. This asymmetric delay is designed to

ensure safe operation during VCCI or VDD brownouts.

VCCI,

INx

VCCI,

INx

V_{VCCI_ON}

V_{VCCI_OFF}

VDDx

t_{VCCI+ to OUT}

t_{VDD+ to OUT}

V_{VDD_ON}

V_{VDD_OFF}

OUTx

图 31. VCCI Power-up UVLO Delay

图 32. VDDA/B Power-up UVLO Delay

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

7.6 CMTI Testing

图 33 is a simplified diagram of the CMTI testing configuration.

VCC

VDD

VDDA

INA

OUTA

VSSA

INB

VCC

VCCI

GND

Functional

Isolation

DIS

VDDB

OUTB

VSSB

VCCI

GND

VSS

Common Mode Surge

Generator

图 33. Simplified CMTI Testing Setup

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

8 Detailed Description

8.1 Overview

In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are

often placed between the output of control devices and the gates of power transistors. There are several

instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors.

This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V

logic signal capable of only delivering a few mA.

The UCC21520-Q1 is a flexible dual gate driver which can be configured to fit a variety of power supply and

motor drive topologies, as well as drive several types of transistors, including SiC MOSFETs. The UCC21520-Q1

has many features that allow it to integrate well with control circuitry and protect the gates it drives such as:

resistor-programmable dead time (DT) control, a DISABLE pin, and under voltage lock out (UVLO) for both input

and output voltages. The UCC21520-Q1 also holds its outputs low when the inputs are left open or when the

input pulse is not wide enough. The driver inputs are CMOS and TTL compatible for interfacing to digital and

analog power controllers alike. Each channel is controlled by its respective input pins (INA and INB), allowing full

and independent control of each of the outputs.

8.2 Functional Block Diagram

INA

16 VDDA

200 kW

Driver

MOD

DEMOD

VCCI

15 OUTA

14 VSSA

UVLO

VCCI 3,8

UVLO

GND

13 NC

12 NC

Deadtime

Control

Functional Isolation

DIS

11 VDDB

200 kW

Driver

MOD

DEMOD

UVLO

10 OUTB

INB

VSSB

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

8.3 Feature Description

8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)

The UCC21520-Q1 has an internal under voltage lock out (UVLO) protection feature on the supply circuit blocks

between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than V_{VDD_ON}at device

start-up or lower than V_{VDD_OFF}after start-up, the VDD UVLO feature holds the effected output low, regardless of

the status of the input pins (INA and INB).

When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an

active clamp circuit that limits the voltage rise on the driver outputs (Illustrated in 图 34 ). In this condition, the

upper PMOS is resistively held off by R_Hi-Zwhile the lower NMOS gate is tied to the driver output through R_CLAMP

In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS device,

typically around 1.5 V, when no bias power is available.

VDD

R_{HI_Z}

Output

Control

OUT

R_CLAMP

R_CLAMPis activated

during UVLO

VSS

图 34. Simplified Representation of Active Pull Down Feature

The VDD UVLO protection has a hysteresis feature (V_{VDD_HYS}). This hysteresis prevents chatter when there is

ground noise from the power supply. Also this allows the device to accept small drops in bias voltage, which is

bound to happen when the device starts switching and operating current consumption increases suddenly.

The input side of the UCC21520-Q1 also has an internal under voltage lock out (UVLO) protection feature. The

device isn't active unless the voltage, VCCI, is going to exceed V_{VCCI_ON}on start up. And a signal will cease to be

delivered when that pin receives a voltage less than V_{VCCI_OFF}. And, just like the UVLO for VDD, there is

hystersis (V_{VCCI_HYS}) to ensure stable operation.

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

Feature Description (接下页)

All versions of the UCC21520-Q1 can withstand an absolute maximum of 30 V for VDD, and 20 V for VCCI.

表 1. UCC21520-Q1 VCCI UVLO Feature Logic

CONDITION

INPUTS

OUTPUTS

INA

INB

OUTA

OUTB

VCCI-GND < V_{VCCI_ON}during device start up

VCCI-GND < V_{VCCI_OFF}after device start up

表 2. UCC21520-Q1 VDD UVLO Feature Logic

CONDITION

INPUTS

OUTPUTS

INA

INB

OUTA

OUTB

VDD-VSS < V_{VDD_ON}during device start up

VDD-VSS < V_{VDD_OFF}after device start up

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

8.3.2 Input and Output Logic Table

Assume VCCI, VDDA, VDDB are powered up. See VDD, VCCI, and Under Voltage Lock Out (UVLO) for more information on

UVLO operation modes.

表 3. INPUT/OUTPUT Logic Table⁽¹⁾

INPUTS

OUTPUTS

DISABLE

NOTE

INA

INB

OUTA

OUTB

L or Left Open

If Dead Time function is used, output transitions occur after the

dead time expires. See Programmable Dead Time (DT) Pin

DT is left open or programmed with R_DT

DT pin pulled to VCCI

Left Open Left Open L or Left Open

(1) "X" means L, H or left open.

8.3.3 Input Stage

The input pins (INA, INB, and DIS) of the UCC21520-Q1 are based on a TTL and CMOS compatible input-

threshold logic that is totally isolated from the VDD supply voltage. The input pins are easy to drive with logic-

level control signals (Such as those from 3.3-V micro-controllers), since the UCC21520-Q1 has a typical high

threshold (V_INAH) of 1.8 V and a typical low threshold of 1 V, which vary little with temperature (see 图 22,图 23).

A wide hysterisis (V_{INA_HYS}) of 0.8 V makes for good noise immunity and stable operation. If any of the inputs are

ever left open, internal pull-down resistors force the pin low. These resistors are typically 200 kΩ (See Functional

Block Diagram). However, it is still recommended to ground an input if it is not being used.

Since the input side of the UCC21520-Q1 is isolated from the output drivers, the input signal amplitude can be

larger or smaller than VDD, provided that it doesn’t exceed the recommended limit. This allows greater flexibility

when integrating with control signal sources, and allows the user to choose the most efficient VDD for their

chosen gate. That said, the amplitude of any signal applied to INA or INB must never be at a voltage higher than

VCCI.

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

8.3.4 Output Stage

The UCC21520-Q1 output stages feature a pull-up structure which delivers the highest peak-source current

when it is most needed, during the Miller plateau region of the power-switch turn on transition (when the power

switch drain or collector voltage experiences dV/dt). The output stage pull-up structure features a P-channel

MOSFET and an additional Pull-Up N-channel MOSFET in parallel. The function of the N-channel MOSFET is to

provide a brief boost in the peak-sourcing current, enabling fast turn on. This is accomplished by briefly turning

on the N-channel MOSFET during a narrow instant when the output is changing states from low to high. The on-

resistance of this N-channel MOSFET (R_NMOS) is approximately 1.47 Ω when activated.

The R_OHparameter is a DC measurement and it is representative of the on-resistance of the P-channel device

only. This is because the Pull-Up N-channel device is held in the off state in DC condition and is turned on only

for a brief instant when the output is changing states from low to high. Therefore the effective resistance of the

UCC21520-Q1 pull-up stage during this brief turn-on phase is much lower than what is represented by the R_OH

parameter. Therefore, the value of R_OHbelies the fast nature of the UCC21520-Q1's turn-on time.

The pull-down structure in the UCC21520-Q1 is simply composed of an N-channel MOSFET. The R_OL

parameter, which is also a DC measurement, is representative of the impedance of the pull-down state in the

device. Both outputs of the UCC21520-Q1 are capable of delivering 4-A peak source and 6-A peak sink current

pulses. The output voltage swings between VDD and VSS provides rail-to-rail operation, thanks to the MOS-out

stage which delivers very low drop-out.

VDD

R_OH

Shoot-

R_NMOS

Input

Signal

Through

Prevention

Circuitry

OUT

VSS

R_OL

Pull Up

图 35. Output Stage

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

8.3.5 Diode Structure in the UCC21520-Q1

图 36 illustrates the multiple diodes involved in the ESD protection components of the UCC21520-Q1. This

provides a pictorial representation of the absolute maximum rating for the device.

VCCI

3,8

VDDA

30 V

15 OUTA

14 VSSA

20 V 20 V

INA

INB

DIS

11 VDDB

10 OUTB

30 V

GND

VSSB

图 36. ESD Structure

8.4 Device Functional Modes

8.4.1 Disable Pin

Setting the DISABLE pin high shuts down both outputs simultaneously. Grounding (or left open) the DISABLE pin

allows the UCC21520-Q1 to operate normally. The DISABLE response time is in the range of 20ns and quite

responsive , which is as fast as propagation delay. The DISABLE pin is only functional (and necessary) when

VCCI stays above the UVLO threshold. It is recommended to tie this pin to ground if the DISABLE pin is not used

to achieve better noise immunity, and it is recommended to bypass using a ≈1nF low ESR/ESL capacitor close to

DIS pin when connecting DIS pin to a micro controller with distance.

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

Device Functional Modes (接下页)

8.4.2 Programmable Dead Time (DT) Pin

The UCC21520-Q1 allows the user to adjust dead time (DT) in the following ways:

8.4.2.1 Tying the DT Pin to VCC

Outputs completely match inputs, so no dead time is asserted. This allows outputs to overlap.

8.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins

If the DT pin is left open, the dead time duration (t_DT) is set to <15 ns. One can program t_DTby placing a resistor,

R_DT, between the DT pin and GND. The appropriate R_DTvalue can be determined from from 公式 1, where R_DT

is in kΩ and t_DTis in ns:

t_DT» 10 ´ R_DT

(1)

The steady state voltage at DT pin is around 0.8 V, and the DT pin current will be less than 10uA when

R_DT=100kΩ. Therefore, It is recommended to parallel a ceramic capacitor, 2.2nF or above, close to the chip with

R_DTto achieve better noise immunity and better deadtime matching between two channels, especially when the

dead time is larger than 300ns. The major consideration is that the current through the R_DTis used to set the

dead time, and this current decreases as R_DTincreases.

An input signal’s falling edge activates the programmed dead time for the other signal. The output signals’ dead

time is always set to the longer of either the driver’s programmed dead time or the input signal’s own dead time.

If both inputs are high simultaneously, both outputs will immediately be set low. This feature is used to prevent

shoot-through, and it doesn’t affect the programmed dead time setting for normal operation. Various driver dead

time logic operating conditions are illustrated and explained in 图 37:

INA

INB

OUTA

OUTB

图 37. Input and Output Logic Relationship With Input Signals

Condition A: INB goes low, INA goes high. INB sets OUTB low immediately and assigns the programmed dead

time to OUTA. OUTA is allowed to go high after the programmed dead time.

Condition B: INB goes high, INA goes low. Now INA sets OUTA low immediately and assigns the programmed

dead time to OUTB. OUTB is allowed to go high after the programmed dead time.

Condition C: INB goes low, INA is still low. INB sets OUTB low immediately and assigns the programmed dead

time for OUTA. In this case, the input signal’s own dead time is longer than the programmed dead time. Thus,

when INA goes high, it immediately sets OUTA high.

Condition D: INA goes low, INB is still low. INA sets OUTA low immediately and assigns the programmed dead

time to OUTB. INB’s own dead time is longer than the programmed dead time. Thus, when INB goes high, it

immediately sets OUTB high.

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

Device Functional Modes (接下页)

Condition E: INA goes high, while INB and OUTB are still high. To avoid overshoot, INA immediately pulls

OUTB low and keeps OUTA low. After some time OUTB goes low and assigns the programmed dead time to

OUTA. OUTB is already low. After the programmed dead time, OUTA is allowed to go high.

Condition F: INB goes high, while INA and OUTA are still high. To avoid overshoot, INB immediately pulls

OUTA low and keeps OUTB low. After some time OUTA goes low and assigns the programmed dead time to

OUTB. OUTA is already low. After the programmed dead time, OUTB is allowed to go high.

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The UCC21520-Q1 effectively combines both isolation and buffer-drive functions. The flexible, universal

capability of the UCC21520-Q1 (with up to 18-V VCCI and 25-V VDDA/VDDB) allows the device to be used as a

low-side, high-side, high-side/low-side or half-bridge driver for MOSFETs, IGBTs or SiC MOSFETs. With

integrated components, advanced protection features (UVLO, dead time, and disable) and optimized switching

performance; the UCC21520-Q1 enables designers to build smaller, more robust designs for enterprise, telecom,

automotive, and industrial applications with a faster time to market.

9.2 Typical Application

The circuit in 图 38 shows a reference design with the UCC21520-Q1 driving a typical half-bridge configuration

which could be used in several popular power converter topologies such as synchronous buck, synchronous

boost, half-bridge/full bridge isolated topologies, and 3-phase motor drive applications.

VDD

VCC

R_BOOT

HV DC-Link

C_IN

VCC

VDDA

INA

INB

R_OFF

R_ON

PWM-A

R_IN

OUTA

VSSA

PWM-B

R_GS

C_BOOT

C_IN

VCCI

GND

DIS

C_VCC

Functional

Isolation

VDD

Analog

Digital

Disable

VDDB

R_OFF

R_ON

C_DT

≥2.2nF

R_DIS

C_DIS

OUTB

VSSB

R_GS

C_VDD

VCCI

R_DT

VSS

图 38. Typical Application Schematic

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

Typical Application (接下页)

9.2.1 Design Requirements

表 4 lists reference design parameters for the example application: UCC21520-Q1 driving 1200-V SiC-MOSFETs

in a high side-low side configuration.

表 4. UCC21520-Q1 Design Requirements

PARAMETER

Power transistor

VCC

VALUE

UNITS

C2M0080120D

5.0

VDD

Input signal amplitude

Switching frequency (f_s)

DC link voltage

3.3

100

800

kHz

9.2.2 Detailed Design Procedure

9.2.2.1 Designing INA/INB Input Filter

It is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay)

the signal at the output. However, a small input R_IN-C_INfilter can be used to filter out the ringing introduced by

non-ideal layout or long PCB traces.

Such a filter should use an R_INin the range of 0 Ω to100 Ω and a C_INbetween 10 pF and 100 pF. In the

example, an R_IN= 51 Ω and a C_IN= 33 pF are selected, with a corner frequency of approximately 100 MHz.

When selecting these components, it is important to pay attention to the trade-off between good noise immunity

and propagation delay.

9.2.2.2 Select External Bootstrap Diode and its Series Resistor

The bootstrap capacitor is charged by VDD through an external bootstrap diode every cycle when the low side

transistor turns on. Charging the capacitor involves high-peak currents, and therefore transient power dissipation

in the bootstrap diode may be significant. Conduction loss also depends on the diode’s forward voltage drop.

Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver

circuit.

When selecting external bootstrap diodes, it is recommended that one chose high voltage, fast recovery diodes

or SiC Schottky diodes with a low forward voltage drop and low junction capacitance in order to minimize the loss

introduced by reverse recovery and related grounding noise bouncing. In the example, the DC-link voltage is 800

V_DC. The voltage rating of the bootstrap diode should be higher than the DC-link voltage with a good margin.

Therefore, a 1200-V SiC diode, C4D02120E, is chosen in this example.

A bootstrap resistor, R_BOOT, is used to reduce the inrush current in D_BOOTand limit the ramp up slew rate of

voltage of VDDA-VSSA during each switching cycle, especially when the VSSA(SW) pin has an excessive

negative transient voltage. The recommended value for R_BOOTis between 1 Ω and 20 Ω depending on the diode

used. In the example, a current limiting resistor of 2.2 Ω is selected to limit the inrush current of bootstrap diode.

The estimated worst case peak current through D_Bootis,

V_DD- V_BDF

20V - 2.5V

2.2W

I_{DBoot pk}

ö 8A

(

)

R_Boot

where

•

V_BDFis the estimated bootstrap diode forward voltage drop at 8 A.

(2)

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

9.2.2.3 Gate Driver Output Resistor

The external gate driver resistors, R_ON/R_OFF, are used to:

1. Limit ringing caused by parasitic inductances/capacitances.

2. Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery.

3. Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss.

4. Reduce electromagnetic interference (EMI).

As mentioned in Output Stage, the UCC21520-Q1 has a pull-up structure with a P-channel MOSFET and an

additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peak

source current can be predicted with:

≈

∆

’

V_DD- V_BDF

R_NMOS||R_OH+R_ON+R_{GFET _Int}

I_OA+= min 4A,

∆

◊

(3)

≈

∆

’

V_DD

I_OB+= min 4A,

∆

R_NMOS||R_OH+ R_ON+ R_{GFET _Int}

◊

where

•

R_ON: External turn-on resistance.

R_{GFET_INT}: Power transistor internal gate resistance, found in the power transistor datasheet.

I_O+= Peak source current – The minimum value between 4 A, the gate driver peak source current, and the

calculated value based on the gate drive loop resistance.

(4)

In this example:

V_DD- V_BDF

R_NMOS||R_OH+ R_ON+ R_{GFET _Int}1.47W || 5W + 2.2W + 4.6W

V_DD20V

R_NMOS||R_OH+ R_ON+ R_{GFET _Int}1.47W || 5W + 2.2W + 4.6W

20V - 0.8V

I_OA+

ö 2.4A

ö 2.5A

(5)

(6)

I_OB+

Therefore, the high-side and low-side peak source current is 2.4 A and 2.5 A respectively. Similarly, the peak

sink current can be calculated with:

≈

∆

’

V_DD- V_BDF- V_GDF

R_OL+ R_OFF||R_ON+ R_{GFET_Int}

I_OA-= min 6A,

∆

◊

(7)

≈

∆

’

V_DD- V_GDF

R_OL+ R_OFF||R_ON+ R_{GFET _Int}

I_OB-= min 6A,

∆

◊

where

•

R_OFF: External turn-off resistance;

V_GDF: The anti-parallel diode forward voltage drop which is in series with R_OFF. The diode in this example is an

MSS1P4.

•

I_O-: Peak sink current – the minimum value between 6 A, the gate driver peak sink current, and the calculated

value based on the gate drive loop resistance.

(8)

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

In this example,

V_DD- V_BDF- V_GDF

R_OL+ R_OFF||R_ON+ R_{GFET _Int}

20V - 0.8V - 0.75V

0.55W + 0W + 4.6W

I_OA-

ö 3.6A

(9)

V_DD- V_GDF

20V-0.75V

I_OB-=

ö 3.7A

R_OL+ R_OFF||R_ON+ R_{GFET _Int}0.55W + 0W + 4.6W

(10)

Therefore, the high-side and low-side peak sink current is 3.6 A and 3.7 A respectively.

Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic

inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and

undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other

hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (C_ISS) of the power

transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close to the

parasitic ringing period.

9.2.2.4 Estimate Gate Driver Power Loss

The total loss, P_G, in the gate driver subsystem includes the power losses of the UCC21520 -Q1 (P_GD) and the

power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not

included in P_Gand not discussed in this section.

P_GDis the key power loss which determines the thermal safety-related limits of the UCC21520-Q1, and it can be

estimated by calculating losses from several components.

The first component is the static power loss, P_GDQ, which includes quiescent power loss on the driver as well as

driver self-power consumption when operating with a certain switching frequency. P_GDQis measured on the

bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and

ambient temperature. 图 4 shows the per output channel current consumption vs. operating frequency with no

load. In this example, V_VCCI= 5 V and V_VDD= 20 V. The current on each power supply, with INA/INB switching

from 0 V to 3.3 V at 100 kHz is measured to be I_VCCI= 2.5 mA, and I_VDDA= I_VDDB= 1.5 mA. Therefore, the P_GDQ

can be calculated with

= V_VCCIìI_VCCI+ V_VDDAìI_DDA+ V_VDDBìI_DDBö 72mW

GDQ

(11)

The second component is switching operation loss, P_GDO, with a given load capacitance which the driver charges

and discharges the load during each switching cycle. Total dynamic loss due to load switching, P_GSW, can be

estimated with

P_GSW= 2 ì V_DDì Q_Gì f_SW

where

•

Q_Gis the gate charge of the power transistor.

(12)

If a split rail is used to turn on and turn off, then VDD is going to be equal to difference between the positive rail

to the negative rail.

So, for this example application:

P_GSW= 2 ì 20V ì 60nC ì100kHz = 240mW

(13)

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

Q_Grepresents the total gate charge of the power transistor switching 800 V at 20 A, and is subject to change

with different testing conditions. The UCC21520-Q1 gate driver loss on the output stage, P_GDO, is part of P_GSW

P_GDOwill be equal to P_GSWif the external gate driver resistances are zero, and all the gate driver loss is

dissipated inside the UCC21520-Q1. If there are external turn-on and turn-off resistances, the total loss will be

distributed between the gate driver pull-up/down resistances and external gate resistances. Importantly, the pull-

up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A, however,

it will be non-linear if the source/sink current is saturated. Therefore, P_GDOis different in these two scenarios.

Case 1 - Linear Pull-Up/Down Resistor:

≈

’

P_GSW

R_OH||R_NMOS

R_OL

P_GDO

∆

◊

R_OH||R_NMOS+R_ON+R_{GFET _Int}R_OL+R_OFF||R_ON+ R_{GFET _Int}

(14)

In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC21520-Q1

gate driver loss can be estimated with:

≈

∆

’

◊

240mW

5W ||1.47W

0.55W

P_GDO

ö 30mW

5W ||1.47W + 2.2W + 4.6W 0.55W + 0W + 4.6W

(15)

Case 2 - Nonlinear Pull-Up/Down Resistor:

T_{R _ Sys}

T_{F_ Sys}

P_GDO= 2 ì f_SWì 4A ì

V - V

t dt + 6A ì

( )

V_OUTA/Bt dt

( )

…

(

)

OUTA/B

—

…

⁄

where

•

V_OUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off transient, and it can be

simplified that a constant current source (4 A at turn-on and 6 A at turn-off) is charging/discharging a load

capacitor. Then, the V_OUTA/B(t) waveform will be linear and the T_{R_Sys}and T_{F_Sys}can be easily predicted.

(16)

For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the P_GDO

will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up and pull-

down based on the above discussion. Therefore, total gate driver loss dissipated in the gate driver UCC21520-

Q1, P_GD, is:

P_GD= P_GDQ+ P

GDO

(17)

which is equal to 102 mW in the design example.

9.2.2.5 Estimating Junction Temperature

The junction temperature (T_J) of the UCC21520-Q1 can be estimated with:

T_J= T_C+ Y_JT´ P_GD

where

•

T_Cis the UCC21520-Q1 case-top temperature measured with a thermocouple or some other instrument, and

Ψ_JTis the Junction-to-top characterization parameter from the Thermal Information table. (18)

Using the junction-to-top characterization parameter (Ψ_JT) instead of the junction-to-case thermal resistance

(R_ΘJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal

energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the

total energy is released through the top of the case (where thermocouple measurements are usually conducted).

R_ΘJCcan only be used effectively when most of the thermal energy is released through the case, such as with

metal packages or when a heatsink is applied to an IC package. In all other cases, use of R_ΘJCwill inaccurately

estimate the true junction temperature. Ψ_JTis experimentally derived by assuming that the amount of energy

leaving through the top of the IC will be similar in both the testing environment and the application environment.

As long as the recommended layout guidelines are observed, junction temperature estimates can be made

accurately to within a few degrees Celsius. For more information, see the Semiconductor and IC Package

Thermal Metrics application report.

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

9.2.2.6 Selecting VCCI, VDDA/B Capacitor

Bypass capacitors for VCCI, VDDA, and VDDB are essential for achieving reliable performance. It is

recommended that one choose low ESR and low ESL surface-mount multi-layer ceramic capacitors (MLCC) with

sufficient voltage ratings, temperature coefficients and capacitance tolerances. Importantly, DC bias on an MLCC

will impact the actual capacitance value. For example, a 25-V, 1-µF X7R capacitor is measured to be only 500

nF when a DC bias of 15 V_DCis applied.

9.2.2.6.1 Selecting a VCCI Capacitor

A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total

current consumption, which is only a few mA. Therefore, a 50-V MLCC with over 100 nF is recommended for this

application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or

electrolytic capacitor, with a value over 1 µF, should be placed in parallel with the MLCC.

9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor

A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for

gate drive current transients up to 6 A, and needs to maintain a stable gate drive voltage for the power transistor.

The total charge needed per switching cycle can be estimated with

I_VDD@100kHz No Load

(

)

1.5mA

Q_Total= Q_G+

= 60nC +

= 75nC

f_SW

100kHz

where

•

Q_G: Gate charge of the power transistor.

I_VDD: The channel self-current consumption with no load at 100kHz.

(19)

(20)

Therefore, the absolute minimum C_Bootrequirement is:

Q_Total

75nC

C_Boot

= 150nF

DV_VDDA0.5V

where

•

ΔV_VDDAis the voltage ripple at VDDA, which is 0.5 V in this example.

In practice, the value of C_Bootis greater than the calculated value. This allows for the capacitance shift caused by

the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients.

Therefore, it is recommended to include a safety-related margin in the C_Bootvalue and place it as close to the

VDD and VSS pins as possible. A 50-V 1-µF capacitor is chosen in this example.

C_Boot= 1ꢀF

(21)

To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor with

a low capacitance value, in this example a 100 nF, in parallel with C_Bootto optimize the transient performance.

注

Too large C_BOOTis not good. C_BOOTmay not be charged within the first few cycles and

V_BOOTcould stay below UVLO. As a result, the high-side FET does not follow input signal

command. Also during initial C_BOOTcharging cycles, the bootstrap diode has highest

reverse recovery current and losses.

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

9.2.2.6.3 Select a VDDB Capacitor

Chanel B has the same current requirements as Channel A, Therefore, a VDDB capacitor (Shown as C_VDDin 图

38) is needed. In this example with a bootstrap configuration, the VDDB capacitor will also supply current for

VDDA through the bootstrap diode. A 50-V, 10-µF MLCC and a 50-V, 220-nF MLCC are chosen for C_VDD. If the

bias power supply output is a relatively long distance from the VDDB pin, a tantalum or electrolytic capacitor, with

a value over 10 µF, should be used in parallel with CVDD.

9.2.2.7 Dead Time Setting Guidelines

For power converter topologies utilizing half-bridges, the dead time setting between the top and bottom transistor

is important for preventing shoot-through during dynamic switching.

The UCC21520-Q1 dead time specification in the electrical table is defined as the time interval from 90% of one

channel’s falling edge to 10% of the other channel’s rising edge (see

图 30). This definition ensures that the dead time setting is independent of the load condition, and guarantees

linearity through manufacture testing. However, this dead time setting may not reflect the dead time in the power

converter system, since the dead time setting is dependent on the external gate drive turn-on/off resistor, DC-

Link switching voltage/current, as well as the input capacitance of the load transistor.

Here is a suggestion on how to select an appropriate dead time for UCC21520-Q1:

DT_Setting= DT_Req+ T_{F_Sys}+ T_{R _Sys}- T_{D on}

(

)

where

•

DT_setting: UCC21520-Q1 dead time setting in ns, DT_Setting= 10 × RDT(in kΩ).

DT_Req: System required dead time between the real V_GSsignal of the top and bottom switch with enough

margin, or ZVS requirement.

•

T_{F_Sys}: In-system gate turn-off falling time at worst case of load, voltage/current conditions.

T_{R_Sys}: In-system gate turn-on rising time at worst case of load, voltage/current conditions.

T_D(on): Turn-on delay time, from 10% of the transistor gate signal to power transistor gate threshold.

(22)

In the example, DT_Settingis set to 250 ns.

It should be noted that the UCC21520-Q1 dead time setting is decided by the DT pin configuration (See

Programmable Dead Time (DT) Pin), and it cannot automatically fine-tune the dead time based on system

conditions. It is recommended to parallel a ceramic capacitor, 2.2 nF or above, close to the DT pin with R_DTto

achieve better noise immunity.

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

9.2.2.8 Application Circuits with Output Stage Negative Bias

When parasitic inductances are introduced by non-ideal PCB layout and long package leads (e.g. TO-220 and

TO-247 type packages), there could be ringing in the gate-source drive voltage of the power transistor during

high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of unintended turn-on

and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep such ringing below

the threshold. Below are a few examples of implementing negative gate drive bias.

图 39 shows the first example with negative bias turn-off on the channel-A driver using a Zener diode on the

isolated power supply output stage. The negative bias is set by the Zener diode voltage. If the isolated power

supply, V_A, is equal to 25 V, the turn-off voltage will be –5.1 V and turn-on voltage will be 25 V – 5.1 V ≈ 20 V.

The channel-B driver circuit is the same as channel-A, therefore, this configuration needs two power supplies for

a half-bridge configuration, and there will be steady state power consumption from R_Z.

HV DC-Link

VDDA

R_OFF

C_A1

V_A

C_IN

R_Z

25 V

R_ON

OUTA

VSSA

C_A2

V_Z= 5.1 V

Functional

Isolation

VDDB

OUTB

VSSB

图 39. Negative Bias with Zener Diode on Iso-Bias Power Supply Output

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

图 40 shows another example which uses two supplies (or single-input-double-output power supply). Power

supply V_A+determines the positive drive output voltage and V_A–determines the negative turn-off voltage. The

configuration for channel B is the same as channel A. This solution requires more power supplies than the first

example, however, it provides more flexibility when setting the positive and negative rail voltages.

HV DC-Link

VDDA

OUTA

R_OFF

R_ON

C_A1

V_A+

C_IN

C_A2

V_A-

VSSA

Functional

Isolation

VDDB

OUTB

VSSB

图 40. Negative Bias with Two Iso-Bias Power Supplies

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

The last example, shown in 图 41, is a single power supply configuration and generates negative bias through a

Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply and the

bootstrap power supply can be used for the high side drive. This design requires the least cost and design effort

among the three solutions. However, this solution has limitations:

1. The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, which means the negative bias

voltage will change when the duty cycle changes. Therefore, converters with a fixed duty cycle (~50%) such as variable frequency

resonant convertors or phase shift convertors favor this solution.

2. The high side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range, which means the low side

switch must turn-on or have free-wheeling current on the body (or anti-parallel) diode for a certain period during each switching cycle to

refresh the bootstrap capacitor. Therefore, a 100% duty cycle for the high side is not possible unless there is a dedicated power supply

for the high side, like in the other two example circuits.

VDD

R_BOOT

HV DC-Link

VDDA

C_Z

V_Z

R_OFF

R_ON

OUTA

VSSA

C_IN

C_BOOT

R_GS

Functional

Isolation

VDD

VDDB

C_Z

V_Z

R_OFF

R_ON

OUTB

VSSB

C_VDD

R_GS

VSS

图 41. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

9.2.3 Application Curves

图 42 and 图 43 shows the bench test waveforms for the design example shown in 图 38 under these conditions:

VCC = 5 V, VDD = 20 V, f_SW= 100 kHz, V_DC-Link= 0 V.

Channel 1 (Yellow): UCC21520-Q1 INA pin signal.

Channel 2 (Blue): UCC21520-Q1 INB pin signal.

Channel 3 (Pink): Gate-source signal on the high side power transistor.

Channel 4 (Green): Gate-source signal on the low side power transistor.

In 图 42, INA and INB are sent complimentary 3.3-V, 50% duty-cycle signals. The gate drive signals on the

power transistor have a 250-ns dead time, shown in the measurement section of 图 42. The dead-time matching

is less than 1 ns with the 250-ns dead-time setting.

图 43 shows a zoomed-in version of the waveform of 图 42, with measurements for propagation delay and

rising/falling time. Cursors are also used to measure dead time. Importantly, the output waveform is measured

between the power transistors’ gate and source pins, and is not measured directly from the driver OUTA and

OUTB pins. Due to the split on and off resistors (R_on,R_off) and different sink and source currents, different rising

(16 ns) and falling time (9 ns) are observed in 图 43.

图 42. Bench Test Waveform for INA/B and OUTA/B

图 43. Zoomed-In bench-test waveform

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

10 Power Supply Recommendations

The recommended input supply voltage (VCCI) for the UCC21520-Q1 is between 3 V and 18 V. The output bias

supply voltage (VDDA/VDDB) range depends on which version of UCC21520-Q1 one is using. The lower end of

this bias supply range is governed by the internal under voltage lockout (UVLO) protection feature of each

device. One mustn’t let VDD or VCCI fall below their respective UVLO thresholds (For more information on

UVLO see VDD, VCCI, and Under Voltage Lock Out (UVLO)). The upper end of the VDDA/VDDB range depends

on the maximum gate voltage of the power device being driven by the UCC21520-Q1. The UCC21520-Q1 have

a recommended maximum VDDA/VDDB of 25 V.

A local bypass capacitor should be placed between the VDD and VSS pins. This capacitor should be positioned

as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is further

suggested that one place two such capacitors: one with a value of ≈10-µF for device biasing, and an additional

≤100-nF capacitor in parallel for high frequency filtering.

Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount of

current drawn by the logic circuitry within the input side of the UCC21520-Q1, this bypass capacitor has a

minimum recommended value of 100 nF.

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

One must pay close attention to PCB layout in order to achieve optimum performance for the UCC21520-Q1.

Below are some key points.

Component Placement:

•

Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins

and between the VDD and VSS pins to support high peak currents when turning on the external power

transistor.

•

To avoid large negative transients on the switch node VSSA (HS) pin, the parasitic inductances between the

source of the top transistor and the source of the bottom transistor must be minimized.

It is recommended to place the dead-time setting resistor, R_DT, and its bypassing capacitor close to DT pin of

the UCC21520-Q1.

It is recommended to bypass using a ≈1nF low ESR/ESL capacitor, C_DIS, close to DIS pin when connecting to

a µC with distance.

Grounding Considerations:

•

It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal

physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the

transistors. The gate driver must be placed as close as possible to the transistors.

•

Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSB-

referenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor is

recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This

recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and

area on the circuit board is important for ensuring reliable operation.

High-Voltage Considerations:

•

To ensure isolation performance between the primary and secondary side, one should avoid placing any PCB

traces or copper below the driver device. A PCB cutout is recommended in order to prevent contamination

that may compromise the UCC21520-Q1’s isolation performance.

•

For half-bridge, or high-side/low-side configurations, where the channel A and channel B drivers could

operate with a DC-link voltage up to 1500 V_DC, one should try to increase the creepage distance of the PCB

layout between the high and low-side PCB traces.

Thermal Considerations:

•

A large amount of power may be dissipated by the UCC21520-Q1 if the driving voltage is high, the load is

heavy, or the switching frequency is high (refer to Estimate Gate Driver Power Loss for more details). Proper

PCB layout can help dissipate heat from the device to the PCB and minimize junction to board thermal

impedance (θ_JB).

•

Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority

on maximizing the connection to VSSA and VSSB (see 图 45 and 图 46). However, high voltage PCB

considerations mentioned above must be maintained.

If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and

VSSB pins to internal ground or power planes through multiple vias of adequate size. However, keep in mind

that there shouldn’t be any traces/coppers from different high voltage planes overlapping.

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

11.2 Layout Example

图 44 shows a 2-layer PCB layout example with the signals and key components labeled.

图 44. Layout Example

图 45 and 图 46 shows top and bottom layer traces and copper.

注

There are no PCB traces or copper between the primary and secondary side, which

ensures isolation performance.

UCC21520-Q1

UCC21520A-Q1

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

www.ti.com.cn

Layout Example (接下页)

PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the

creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node

VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.

图 46. Bottom Layer Traces and Copper

图 45. Top Layer Traces and Copper

图 47 and 图 48 are 3D layout pictures with top view and bottom views.

注

The location of the PCB cutout between the primary side and secondary sides, which

ensures isolation performance.

图 47. 3-D PCB Top View

图 48. 3-D PCB Bottom View

UCC21520-Q1

UCC21520A-Q1

www.ti.com.cn

ZHCSGY8B –OCTOBER 2017–REVISED JULY 2018

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档

请参阅如下相关文档：

•

隔离相关术语

12.2 认证

UL 在线认证目录，“FPPT2.E181974 非光学隔离器件 - 组件”证书编号：20160516-E181974,

VDE Pruf- und Zertifizierungsinstitut 认证，工厂监督合格证书

CQC 在线认证目录，“GB4943.1-2011，数字隔离器证书”证书编号：CQC16001155011

CSA 在线认证目录，“CSA 合格证书”证书编号：70097761，主合同编号：220991

12.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.7 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

UCC21520AQDWQ1

UCC21520AQDWRQ1

UCC21520QDWQ1

UCC21520QDWRQ1

ACTIVE

SOIC

RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 125

UCC21520AQ

2000 RoHS & Green

40 RoHS & Green

2000 RoHS & Green

NIPDAU

UCC21520AQ

UCC21520Q

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UCC21520AQDWRQ1

UCC21520QDWRQ1

SOIC

2000

330.0

16.4

10.75 10.7

2.7

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

UCC21520AQDWRQ1

UCC21520QDWRQ1

SOIC

2000

356.0

350.0

356.0

350.0

356.0

35.0

43.0

35.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

UCC21520AQDWQ1

UCC21520QDWQ1

SOIC

506.98

507

12.7

12.83

12.7

4826

5080

4826

6.6

507

506.98

Pack Materials-Page 3

GENERIC PACKAGE VIEW

DW 16

7.5 x 10.3, 1.27 mm pitch

SOIC - 2.65 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224780/A

www.ti.com

PACKAGE OUTLINE

DW0016B

SOIC - 2.65 mm max height

SOIC

10.63

9.97

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

14X 1.27

10.5

10.1

NOTE 3

8.89

0.51

0.31

16X

7.6

7.4

2.65 MAX

0.25

C A

NOTE 4

0.33

0.10

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.3

0.1

0 - 8

1.27

0.40

DETAIL A

TYPICAL

(1.4)

4221009/B 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

www.ti.com

EXAMPLE BOARD LAYOUT

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (2)

16X (1.65)

SEE

DETAILS

SEE

DETAILS

16X (0.6)

SYMM

14X (1.27)

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4221009/B 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (1.65)

16X (2)

16X (0.6)

SYMM

14X (1.27)

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

4221009/B 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

UCC21520-Q1 [TI]

相关型号：

UCC21520ADW

UCC21520ADWR

UCC21520AQDWQ1

UCC21520AQDWRQ1

UCC21520DW

UCC21520DWR

UCC21520QDWQ1

UCC21520QDWRQ1

UCC21521

UCC21521ADW

UCC21521ADWR

UCC21521CDW