UCC21756-Q1_技术文档

UCC21756-Q1

ZHCSON5 –APRIL 2023

UCC21756-Q1 适用于SiC/IGBT 并具有主动保护、隔离式模拟感应和高CMTI 的

汽车类10A 拉电流/灌电流增强型隔离式单通道栅极驱动器

输入侧通过 SiO₂电容隔离技术与输出侧相隔离，支持

高达 1.5kV_RMS的工作电压、12.8kV_PK的浪涌抗扰

1 特性

• 5.7kV_RMS单通道隔离式栅极驱动器

• 具有符合AEC-Q100 标准的下列特性：

度，隔离层寿命超过 40 年，并提供较低的器件间偏

移，共模噪声抗扰度(CMTI) 大于150V/ns。

– 器件温度等级0：-40°C 至+150°C 环境工作温

度范围

– 器件HBM ESD 分类等级3A

– 器件CDM ESD 分类等级C6

• 功能安全质量管理型

UCC21756-Q1 包括先进的保护特性，如快速过流和短

路检测、故障报告、有源米勒钳位以及输入和输出侧电

源 UVLO（用于优化 SiC 和 IGBT 开关行为和稳健

性）。可以利用隔离式模拟至PWM 传感器更轻松地进

行温度或电压检测，从而进一步提高驱动器的多功能性

并较少系统设计工作量、尺寸和成本。

– 有助于进行功能安全系统设计的文档

• 高达2121V_pk的SiC MOSFET 和IGBT

• 33V 最大输出驱动电压(VDD-VEE)

• ±10A 驱动强度和分离输出

• 150V/ns 最小CMTI

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

UCC21756-Q1

SOIC-16

10.3mm × 7.5mm

• 具有200ns 快速响应时间和5V 阈值的DESAT 保

护

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 4A 内部有源米勒钳位

• 发生故障时的900mA 软关断

• 具有PWM 输出的隔离式模拟传感器

APWM

AIN

DESAT

COM

1

2

3

4

5

6

7

8

16

15

– 采用NTC、PTC 或热敏二极管进行温度感应

– 高电压直流链路或相电压

VCC

RST/EN

FLT

14

13

12

11

10

9

• 过流警报FLT 和通过RST/EN 重置

• 针对RST/EN 的快速启用/禁用响应

• 抑制输入引脚上的<40ns 噪声瞬态和脉冲

• RDY 上的12V VDD UVLO（具有电源正常指示功

能）

• 具有高达5V 过冲/欠冲瞬态电压抗扰度的输入/输出

• 130ns（最大）传播延迟和30ns（最大）脉冲/器件

间偏移

OUTH

VDD

RDY

INÅ

OUTL

CLMPI

VEE

IN+

GND

• SOIC-16 DW 封装，爬电距离和间隙> 8mm

• 工作结温范围：-40°C 至+150°C

Not to scale

器件引脚配置

2 应用

• 适用于EV 的牵引逆变器

• 车载充电器和充电桩

• 用于HEV/EV 的直流/直流转换器

3 说明

UCC21756-Q1 是一款电隔离单通道栅极驱动器，设计

用于直流工作电压高达 2121V 的 SiC MOSFET 和

IGBT，具有先进的保护功能、出色的动态性能和稳健

性。UCC21756-Q1 具有高达 ±10A 的峰值拉电流和灌

电流。

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSEN8

UCC21756-Q1

ZHCSON5 –APRIL 2023

www.ti.com.cn

Table of Contents

8 Detailed Description......................................................22

8.1 Overview...................................................................22

8.2 Functional Block Diagram.........................................23

8.3 Feature Description...................................................23

8.4 Device Functional Modes..........................................29

9 Applications and Implementation................................30

9.1 Application Information............................................. 30

9.2 Typical Application.................................................... 30

10 Power Supply Recommendations..............................42

11 Layout...........................................................................43

11.1 Layout Guidelines................................................... 43

11.2 Layout Example...................................................... 44

12 Device and Documentation Support..........................45

12.1 Device Support....................................................... 45

12.2 Documentation Support.......................................... 45

12.3 接收文档更新通知................................................... 45

12.4 支持资源..................................................................45

12.5 Trademarks.............................................................45

12.6 静电放电警告.......................................................... 45

12.7 术语表..................................................................... 45

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Power Ratings.............................................................5

6.6 Insulation Specifications............................................. 5

6.7 Safety Limiting Values.................................................6

6.8 Electrical Characteristics.............................................7

6.9 Switching Characteristics............................................9

6.10 Insulation Characteristics Curves........................... 10

6.11 Typical Characteristics.............................................11

7 Parameter Measurement Information..........................15

7.1 Propagation Delay.................................................... 15

7.2 Input Deglitch Filter...................................................16

7.3 Active Miller Clamp................................................... 17

7.4 Undervoltage Lockout (UVLO)..................................17

7.5 Desaturation (DESAT) Protection............................. 20

Information.................................................................... 45

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

April 2023

*

Initial release

2

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5 Pin Configuration and Functions

APWM

VCC

RST/EN

FLT

AIN

DESAT

COM

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

OUTH

VDD

RDY

INÅ

OUTL

CLMPI

VEE

IN+

GND

Not to scale

图5-1. UCC21756-Q1 DW SOIC (16) Top View

表5-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

Isolated analog sensing input, parallel a small capacitor to COM for better noise immunity. Tie to COM if

unused.

AIN

1

I

DESAT

COM

2

3

4

I

Desaturation current protection input. Tie to COM if unused.

Common ground reference, connecting to emitter pin for IGBT and source pin for SiC-MOSFET

Gate driver output pullup

P

O

OUTH

Positive supply rail for gate drive voltage. Bypass with a >10-µF capacitor to COM to support specified gate

driver source peak current capability. Place decoupling capacitor close to the pin.

VDD

5

6

7

P

O

I

OUTL

CLMPI

Gate driver output pulldown

Internal Active Miller clamp, connecting this pin directly to the gate of the power transistor. Leave floating or

tie to VEE if unused.

Negative supply rail for gate drive voltage. Bypass with a >10-µF capacitor to COM to support specified gate

driver sink peak current capability. Place decoupling capacitor close to the pin.

VEE

8

P

GND

IN+

9

P

I

Input power supply and logic ground reference

10

11

Non-inverting gate driver control input. Tie to VCC if unused.

Inverting gate driver control input. Tie to GND if unused.

I

IN–

Power good for VCC-GND and VDD-COM. RDY is open-drain configuration and can be paralleled with other

RDY signals.

RDY

FLT

12

13

O

Active low fault alarm output upon overcurrent or short circuit. FLT is in open-drain configuration and can be

paralleled with other faults.

The RST/EN serves two purposes:

1) Enables or shuts down the output side. The FET is turned off by a regular turn-off, if pin EN is set to low;

2) Resets the DESAT condition signaled on the FLT pin if the pin RST/EN is set to low for more than 1000

ns. A reset of signal FLT is asserted at the rising edge of pin RST/EN.

RST/EN

14

I

For automatic RESET function, this pin only serves as an EN pin. Enable or shutdown the output side. The

FET is turned off by a regular turn-off, if pin EN is set to low. Tie to IN+ for automatic reset.

Input power supply from 3 V to 5.5 V. Bypass with a >1-µF capacitor to GND. Place decoupling capacitor

close to the pin.

VCC

15

16

P

APWM

O

Isolated analog sensing PWM output. Leave floating if unused.

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

6

UNIT

V

VCC

VDD

VEE

V_MAX

VCC - GND

VDD - COM

36

V

–0.3

VEE - COM

0.3

V

–17.5

VDD - VEE

36

V

–0.3

DC

VCC

VCC+5.0

VDD+0.3

5

V

GND–0.3

GND–5.0

COM–0.3

–0.3

IN+, IN-, RST/EN

Transient, less than 100 ns ⁽²⁾

V

DESAT

AIN

V

Reference to COM

DC

V

VDD

VDD+5.0

VCC

20

V

VEE–0.3

VEE–5.0

GND–0.3

OUTH, OUTL, CLMPI

Transient, less than 100 ns ⁽²⁾

V

RDY, FLT, APWM

V

I_FLT, I_RDY

I_APWM

T_J

FLT and RDY pin input current

APWM pin output current

Junction Temperature

mA

°C

20

150

–40

–65

T_stg

Storage Temperature

150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and

this may affect device reliability, functionality, performance, and shorten the device lifetime

(2) Values are verified by characterization on bench.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per AEC Q100-002⁽⁽¹⁾⁾

HBM ESD classification level 3A

±4000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per AEC Q100-011

CDM ESD classification level C6

±1500

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

3

MAX

UNIT

V

VCC

VDD

VEE

V_MAX

VCC-GND

5.5

33

VDD-COM

13

V

VEE-COM

-16

0

V

VDD-VEE

33

V

Reference to GND, High level input voltage

Reference to GND, Low level input voltage

Minimum pulse width that reset the fault

Ambient temperature

0.7xVCC

0

VCC

0.3xVCC

V

IN+, IN-,

RST/EN

V

t_RST/EN

T_A

1000

–40

ns

°C

125

150

T_J

Junction temperature

English Data Sheet: SLUSEN8

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6.4 Thermal Information

UCC21756-Q1

DW (SOIC)

16 PINS

68.3

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

27.5

32.9

Junction-to-top characterization parameter

Junction-to-board characterization parameter

14.1

32.3

Ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Power Ratings

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

985

20

UNIT

mW

P_D

Maximum power dissipation (both sides)

Maximum power dissipation (side-1)

Maximum power dissipation (side-2)

VCC = 5V, VDD-COM = 20V, COM-VEE =

5V, IN+/–= 5V, 150kHz, 50% Duty Cycle

for 10nF load, T_a= 25℃

P_D1

P_D2

965

6.6 Insulation Specifications

PARAMETER

GENERAL

TEST CONDITIONS

VALUE

UNIT

CLR

CPG

External clearance⁽¹⁾

Shortest terminal-to-terminal distance through air

> 8

mm

Shortest terminal-to-terminal distance across the

package surface

External creepage⁽⁽¹⁾⁾

DTI

CTI

Distance through the insulation

Comparative tracking index

Material Group

Minimum internal gap (internal clearance)

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664–1

> 17

> 600

I

µm

V

I-IV

I-III

Rated mains voltage ≤300 V_RMS

Rated mains voltage ≤600 V_RMS

Rated mains voltage ≤1000 V_RMS

Overvoltage Category per IEC 60664–1

DIN EN IEC 60747-17 (VDE 0884-17)⁽⁽²⁾⁾

V_IORMMaximum repetitive peak isolation voltage

AC voltage (bipolar)

2121

1500

2121

8000

V_PK

V_RMS

V_DC

V_PK

AC voltage (sine wave); time-dependent dielectric

breakdown (TDDB) test

V_IOWM

Maximum isolation working voltage

Maximum impulse voltage

DC voltage

Tested in air, 1.2/50-μs waveform per IEC

62368-1

V_IMP

V_TEST= V_IOTM, t = 60 s (qualification test)

V_PK

V_IOTM

Maximum transient isolation voltage

Maximum surge isolation voltage⁽³⁾

V_TEST= 1.2 × V_IOTM, t = 1 s (100% production

test)

V_PK

Test method per IEC 62368-1, 1.2/50 µs

waveform

V_IOSM

12800

V_PK

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UNIT

6.6 Insulation Specifications (continued)

PARAMETER

TEST CONDITIONS

VALUE

Method a: After I/O safety test subgroup 2/3, V_ini

=V_IOTM, t_ini= 60 s; V_pd(m)= 1.2 × V_IORM= 2545

V_PK, t_m= 10 s

≤5

Method a: After environmental tests subgroup

1,V_ini= V_IOTM, t_ini= 60 s; V_pd(m)= 1.6 × V_IORM

3394 V_PK, t_m= 10 s

q_pd

Apparent charge⁽⁴⁾

=

pC

≤5

Method b1: At routine test (100% production) and

preconditioning (type test), V_ini= V_IOTM, t_ini= 1 s;

V_pd(m)= 1.875 × V_IORM= 3977 V_PK, t_m= 1 s

≤5

C_IO

R_IO

Barrier capacitance, input to output⁽⁵⁾

Insulation resistance, input to output⁽⁵⁾

~ 1

pF

V_IO= 0.5 × sin (2πft), f = 1 MHz

V_IO= 500 V, T_A= 25°C

≥10¹²

≥10¹¹

≥10⁹

2

V_IO= 500 V, 100°C ≤T_A≤125°C

V_IO= 500 V at T_S= 150°C

Ω

Pollution degree

Climatic category

40/125/21

UL 1577

V_TEST= V_ISO= 5700 V_RMS, t = 60 s (qualification),

V_TEST= 1.2 × V_ISO= 6840 V_RMS, t = 1 s (100%

production)

V_ISO

Withstand isolation voltage

5700

V_RMS

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be

taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the

printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques

such as inserting grooves and ribs on the PCB are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured

by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-pin device.

6.7 Safety Limiting Values

Safety limiting⁽¹⁾intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure

of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to

overheatthe die and damage the isolation barrier, potentially leading to secondary system failures.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R

_θJA= 68.3°C/W, V_DD= 15 V, V_EE= -5V,

61

T_J= 150°C, T_A= 25°C

_θJA= 68.3°C/W, V_DD= 20 V, V_EE= -5V,

T_J= 150°C, T_A= 25°C

_θJA= 68.3°C/W, V_DD= 20 V, V_EE= -5V,

T_J= 150°C, T_A= 25°C

I_S

Safety input, output, or supply current

mA

R

49

R

P_S

T_S

Safety input, output, or total power

Maximum safety temperature

1220

150

mW

°C

(1) The maximum safety temperature, T_S, has the same value as the maximum junction temperature, T_J, specified for the device. The I_S

and P_Sparameters represent the safety current and safety power respectively. The maximum limits of I_Sand P_Sshould not be

exceeded. These limits vary with the ambient temperature, T_A. The junction-to-air thermal resistance, R_qJA, in the Thermal Information

table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value

for each parameter: T_J= T_A+ R_qJA´ P, where P is the power dissipated in the device. T_J(max)= T_S= T_A+ R_qJA´ P_S, where T_J(max)is the

maximum allowed junction temperature. P_S= I_S´ V_I, where VI is the maximum supply voltage.

English Data Sheet: SLUSEN8

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6.8 Electrical Characteristics

VCC = 3.3 V or 5.0 V, 1-µF capacitor from VCC to GND, VDD–COM = 20 V, 18 V or 15 V, COM–VEE = 5 V, 8 V or 15 V,

C_L= 100pF, –40°C<T_J<150°C (unless otherwise noted)⁽¹⁾⁽²⁾

.

Parameter

TEST CONDITIONS

MIN

TYP

MAX UNIT

VCC UVLO THRESHOLD AND DELAY

V_{VCC_ON}

2.55

2.35

2.7

2.5

0.2

10

2.85

2.65

V

V_{VCC_OFF}

V_{VCC_HYS}

t_VCCFIL

VCC - GND

V

VCC UVLO deglitch time

µs

t_{VCC+ to OUT}

t_{VCC- to OUT}

t_{VCC+ to RDY}

t_{VCC- to RDY}

VCC UVLO on delay to output high

VCC UVLO off delay to output low

VCC UVLO on delay to RDY high

VCC UVLO off delay to RDY low

28

5

37.8

10

50

15

50

15

IN+ = VCC, IN–= GND

30

5

37.8

10

RST/EN = VCC

VDD UVLO THRESHOLD AND DELAY

V_{VDD_ON}

10.5

9.9

12

10.7

0.8

5

12.8

11.8

V

V_{VDD_OFF}

V_{VDD_HYS}

t_VDDFIL

VDD - COM

V

VDD UVLO deglitch time

µs

t_{VDD+ to OUT}

t_{VDD- to OUT}

t_{VDD+ to RDY}

t_{VDD- to RDY}

VDD UVLO on delay to output high

VDD UVLO off delay to output low

VDD UVLO on delay to RDY high

VDD UVLO off delay to RDY low

2

5

8

10

15

IN+ = VCC, IN–= GND

5

10

RST/EN = VCC

VCC, VDD QUIESCENT CURRENT

OUT(H) = High, f_S= 0Hz, AIN=2V

OUT(L) = Low, f_S= 0Hz, AIN=2V

OUT(H) = High, f_S= 0Hz, AIN=2V

OUT(L) = Low, f_S= 0Hz, AIN=2V

2.5

1.45

3.6

3

2

4

2.75

5.9

mA

I_VCCQVCC quiescent current

4

I_VDDQ

VDD quiescent current

3.1

3.7

5.3

LOGIC INPUTS - IN+, IN- and RST/EN

V_INH

V_INL

V_INHYS

I_IH

Input high threshold

Input low threshold

1.85

1.52

0.33

90

2.31

V

VCC=3.3V

0.99

Input threshold hysteresis

V

Input high level input leakage current V_IN= VCC

uA

kΩ

I_IL

Input low level input leakage current

Input pins pull down resistance

Input pins pull up resistance

V_IN= GND

-90

55

R_IND

R_INU

55

IN+, IN–and RST/EN deglitch (ON

and OFF) filter time

T_INFIL

f_S= 50kHz

28

40

60

ns

T_RSTFIL

Deglitch filter time to reset FLT

500

650

800

GATE DRIVER STAGE

I_OUTHPeak source current

I_OUTL

10

A

C_L= 0.18µF, f_S= 1kHz

Peak sink current

(3)

R_OUTH

R_OUTL

V_OUTH

V_OUTL

Output pull-up resistance

Output pull-down resistance

High level output voltage

Low level output voltage

I_OUTH= -0.1A

2.5

0.3

17.5

60

Ω

I_OUTL= 0.1A

I_OUTH= -0.2A, VDD = 18V

I_OUTL= 0.2A

V

mV

ACTIVE PULLDOWN

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6.8 Electrical Characteristics (continued)

VCC = 3.3 V or 5.0 V, 1-µF capacitor from VCC to GND, VDD–COM = 20 V, 18 V or 15 V, COM–VEE = 5 V, 8 V or 15 V,

C_L= 100pF, –40°C<T_J<150°C (unless otherwise noted)⁽¹⁾⁽²⁾

.

Parameter

TEST CONDITIONS

MIN

TYP

MAX UNIT

I_OUTL(typ)= 0.1×I_OUTL(typ)

VDD=OPEN, VEE=COM

,

V_OUTPD

Output active pull down on OUTL

1.5

2.0

2.5

V

INTERNAL ACTIVE MILLER CLAMP

V_CLMPTHMiller clamp threshold voltage

Reference to VEE

I_CLMPI= 1A

1.5

2.0

2.5

V

A

VEE +

0.5

V_CLMPI

Output low clamp voltage

I_CLMPI

Output low clamp current

4.0

0.6

15

V_CLMPI= 0V, VEE = –2.5V

I_CLMPI= 0.2A

R_CLMPI

t_DCLMPI

Miller clamp pull down resistance

Miller clamp ON delay time

Ω

C_L= 1.8nF

50

ns

SHORT CIRCUIT CLAMPING

OUT = High, I_OUT(H)= 500mA,

t_CLP=10µs

V_CLP-OUT(H)

0.9

V

_OUTH–VDD

_OUTL–VDD

OUT = High, I_OUT(L)= 500mA,

t_CLP=10µs

V_CLP-OUT(L)

1.8

1.0

V

V_CLP-CLMPI

V_CLMPI-VDD

OUT = High, I_CLMPI= 20mA, t_CLP=10µs

DESAT PROTECTION

I_CHG

Blanking capacitor charge current

V_DESAT= 2.0V

V_DESAT= 6.0V

430

10.0

4.6

500

15.0

5

570

µA

mA

V

I_DCHG

Blanking capacitor discharge current

Detection threshold

V_DESAT

t_DESATLEB

t_DESATFIL

5.47

450

230

Leading edge blank time

DESAT deglitch filter

150

50

200

140

ns

DESAT propagation delay to OUTL

90%

t_DESATOFF

t_DESATFLT

150

400

200

580

300

750

ns

DESAT to FLT low delay

INTERNAL SOFT TURN OFF

I_STOSoft turn-off current on fault condition VDD-VEE = 20 V, OUTL = 8 V

ISOLATED TEMPERATURE SENSE AND MONITOR (AIN–APWM)

500

900

1200

mA

V_AIN

Analog sensing voltage range

Internal current source

0.6

196

380

4.5

209

420

V

uA

kHz

%

I_AIN

V_AIN=2.5V, -40°C< T_J< 150°C

V_AIN=2.5V

203

400

10

f_APWM

BW_AIN

APWM output frequency

AIN-APWM Bandwidth

V_AIN=0.6V

V_AIN=2.5V

V_AIN=4.5V

86.5

48.5

7.5

88

89.5

51.5

11.5

D_APWM

APWM Duty Cycle

50

%

10

%

FLT AND RDY REPORTING

VDD UVLO RDY low minimum holding

time

t_RDYHLD

0.55

1

ms

t_FLTMUTE

R_ODON

V_ODL

Output mute time on fault

Open drain output on resistance

Open drain low output voltage

Reset fault through RST/EN

I_ODON= 5mA

30

Ω

0.3

V

COMMON MODE TRANSIENT IMMUNITY

CMTI Common-mode transient immunity

150

V/ns

(1) Currents are positive into and negative out of the specified terminal.

(2) All voltages are referenced to COM unless otherwise notified.

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(3) For internal PMOS only. Refer to Driver Stage for effective pull-up resistance.

6.9 Switching Characteristics

VCC = 5.0 V, 1-µF capacitor from VCC to GND, VDD - COM = 20V, 18V or 15V, COM - VEE = 3 V, 5 V or 8 V, C_L= 100pF,

-40℃<T_J<150℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

60

TYP

90

MAX

130

30

UNIT

ns

t_PDLH

t_PDHL

PWD

t_sk-pp

t_r

Propagation delay time low-to-high

60

90

ns

Pulse width distortion (t_PDHL-t_PDLH

)

ns

Part to part skew

Rising or falling propagation delay

C_L= 10nF

30

ns

Driver output rise time

33

27

ns

t_f

Driver output fall time

C_L= 10nF

ns

f_MAX

Maximum switching frequency

1

MHz

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6.10 Insulation Characteristics Curves

图6-1. Reinforced Isolation Capacitor Life Time Projection

80

60

40

20

0

1400

1200

1000

800

600

400

200

0

VDD=15V; VEE=-5V

VDD=20V; VEE=-5V

0

25

50

75

100

125

150

0

20

40

60

80

100

120

140

160

Ambient Temperature (^oC)

Safe

图6-2. Thermal Derating Curve for Limiting Current per VDE

图6-3. Thermal Derating Curve for Limiting Power per VDE

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6.11 Typical Characteristics

22

20

18

16

14

12

10

8

22

20

18

16

14

12

10

8

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

6

4

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D016

D017

图6-4. Output High Drive Current vs Temperature

图6-5. Output Low Driver Current vs Temperature

6

4

VCC = 3.3V

VCC = 5V

VCC = 3.3V

VCC = 5V

5.5

3.5

5

4.5

4

3

2.5

2

3.5

1.5

3

1

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D015

D014

IN+ = High

IN- = Low

IN+ = Low

IN- = Low

图6-6. I_VCCQSupply Current vs Temperature

图6-7. I_VCCQSupply Current vs Temperature

5

4.5

4

6

5.5

5

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

3.5

3

4.5

4

2.5

3.5

2

3

30

70

110

150 190

Frequency (kHz)

230

270

310

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D018

D012

图6-8. I_VCCQSupply Current vs Input Frequency

IN+ = High

IN- = Low

图6-9. I_VDDQSupply Current vs Temperature

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6.11 Typical Characteristics (continued)

6

10

9

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

5.5

5

8

7

4.5

4

6

5

4

3.5

3

2

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

30

70

110

150

190

Frequency (kHz)

230

270

310

D013

D019

IN+ = Low

IN- = Low

图6-11. I_VDDQSupply Current vs Input Frequency

图6-10. I_VDDQSupply Current vs Temperature

4

3.5

3

14

13.5

13

12.5

12

2.5

2

11.5

11

10.5

10

1.5

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D002

D001

图6-13. VDD UVLO vs Temperature

图6-12. VCC UVLO vs Temperature

100

90

80

70

60

50

100

90

80

70

60

50

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D022

D021

V_CC= 3.3 V

V_DD=18 V

R_OFF= 0 Ω

C_L= 100 pF

V_CC= 3.3V

V_DD=18V

R_OFF= 0Ω

C_L= 100pF

R_ON= 0 Ω

R_ON= 0Ω

图6-15. Propagation Delay t_PDHLvs Temperature

图6-14. Propagation Delay t_PDLHvs Temperature

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6.11 Typical Characteristics (continued)

60

50

40

30

20

10

50

40

30

20

10

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D023

D024

V_CC= 3.3 V

V_DD=18 V

C_L= 10 nF

V_CC= 3.3 V

V_DD=18 V

C_L= 10 nF

R_ON= 0 Ω

R_OFF= 0 Ω

R_ON= 0 Ω

R_OFF= 0 Ω

图6-16. t_rRise Time vs Temperature

图6-17. t_fFall Time vs Temperature

3

2.75

2.5

2.25

2

1.75

1.5

1.25

1

2.25

2

1.75

1.5

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D025

D008

图6-19. V_CLP-OUT(H)Short Circuit Clamping Voltage vs

图6-18. V_OUTPDOutput Active Pulldown Voltage vs Temperature

Temperature

2

1.75

1.5

2.6

2.45

2.3

2.15

2

1.25

1

1.85

1.7

0.75

0.5

1.55

1.4

0.25

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

D026

D007

图6-20. V_CLP-OUT(L)Short Circuit Clamping Voltage vs

图6-21. V_CLMPTHMiller Clamp Threshold Voltage vs

Temperature

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6.11 Typical Characteristics (continued)

8.5

7.5

6.5

5.5

4.5

3.5

2.5

1.5

0.5

18

17

16

15

14

13

12

11

10

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

D011

D010

图6-22. I_CLMPIMiller Clamp Sink Current vs Temperature

图6-23. t_DCLMPIMiller Clamp ON Delay Time vs Temperature

420

300

290

280

270

260

250

240

230

220

210

200

380

340

300

260

220

180

140

100

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

D002

D003

图6-24. t_DESATLEBDESAT Leading Edge Blanking Time vs

图6-25. t_DESATOFFDESAT Propagation Delay to OUT(L) 90% vs

Temperature

320

310

300

290

280

270

260

250

240

230

220

680

660

640

620

600

580

560

540

520

500

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

D005

D004

图6-27. t_DESATFILDESAT Deglitch Filter vs Temperature

图6-26. t_DESATFLTDESAT Sense to /FLT Low Delay Time vs

Temperature

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6.11 Typical Characteristics (continued)

560

550

540

530

520

510

500

490

480

470

460

450

440

20

19

18

17

16

15

14

13

12

11

10

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D008

D009

图6-28. I_CHGDESAT Charging Current vs Temperature

图6-29. I_DCHGDESAT Discharge Current vs Temperature

7 Parameter Measurement Information

7.1 Propagation Delay

7.1.1 Non-Inverting and Inverting Propagation Delay

图7-1 shows the propagation delay measurement for non-inverting configurations. 图7-2 shows the propagation

delay measurement with the inverting configurations.

50%

IN+

INÅ

t_PDLH

t_PDHL

90%

10%

OUT

图7-1. Non-Inverting Logic Propagation Delay Measurement

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IN+

INÅ

50%

t_PDLH

t_PDHL

90%

OUT

10%

图7-2. Inverting Logic Propagation Delay Measurement

7.2 Input Deglitch Filter

To increase the robustness of gate driver over noise transient and accidental small pulses on the input pins, for

example, IN+, IN–, RST/EN, a 40-ns deglitch filter filters out the transients and ensures there is no faulty output

responses or accidental driver malfunctions. When the IN+ or IN– PWM pulse is smaller than the input deglitch

filter width, T_INFIL, there are no responses on the OUT drive signal. 图 7-3 and 图 7-4 show the IN+ pin ON and

OFF pulse deglitch filter effect. 图7-5 and 图7-6 show the IN–pin ON and OFF pulse deglitch filter effect.

IN+

t_PWM< T_INFIL

IN+

INÅ

OUT

图7-3. IN+ ON Deglitch Filter

图7-4. IN+ OFF Deglitch Filter

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IN+

INÅ

t_PWM< T_INFIL

INÅ

OUT

图7-5. IN–ON Deglitch Filter

图7-6. IN–OFF Deglitch Filter

7.3 Active Miller Clamp

7.3.1 Internal On-Chip Active Miller Clamp

For a gate driver application with a unipolar bias supply or a bipolar supply with a small negative turn-off voltage,

an active Miller clamp can help add a additional low impedance path to bypass the Miller current and prevent the

high dV/dt introduced unintentional turn-on through the Miller capacitance. 图 7-7 shows the timing diagram for

an on-chip internal Miller clamp function.

IN

(”IN+‘ Å ”INÅ‘)

t_DCLMPI

V_CLMPTH

OUT

HIGH

CLMPI

Ctrl.

LOW

图7-7. Timing Diagram for Internal Active Miller Clamp Function

7.4 Undervoltage Lockout (UVLO)

Undervoltage lockout (UVLO) is one of the key protection features designed to protect the system in case of bias

supply failures on VCC, primary side power supply, and VDD, secondary side power supply.

7.4.1 VCC UVLO

The VCC UVLO protection details are discussed in this section. 图 7-8 shows the timing diagram illustrating the

definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM.

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IN

(”IN+‘ Å ”INÅ‘)

t_VCCFIL

t_{VCCÅ to OUT}

V_{VCC_ON}

V_{VCC_OFF}

VCC

VDD

COM

VEE

t_{VCC+ to OUT}

90%

V_CLMPTH

OUT

RDY

10%

t_{VCC+ to RDY}

t_RDYHLD

t_{VCCÅ to RDY}

Hi-Z

VCC

APWM

图7-8. VCC UVLO Protection Timing Diagram

7.4.2 VDD UVLO

The VDD UVLO protection details are discussed in this section. 图 7-9 shows the timing diagram illustrating the

definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM.

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IN

(”IN+‘ Å ”INÅ‘)

t_VDDFIL

VDD

t_{VDDÅ to OUT}

V_{VDD_ON}

V_{VDD_OFF}

COM

VEE

VCC

t_{VDD+ to OUT}

V_CLMPTH

OUT

RDY

90%

t_RDYHLD

10%

t_{VDD+ to RDY}

t_{VDDÅ to RDY}

Hi-Z

VCC

APWM

图7-9. VDD UVLO Protection Timing Diagram

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7.5 Desaturation (DESAT) Protection

7.5.1 DESAT Protection with Soft Turn-OFF

DESAT function is used to detect V_DSfor SiC-MOSFETs or V_CEfor IGBTs under overcurrent conditions. 图 7-10

shows the timing diagram of DESAT operation with soft turn-off during the turning on transition.

IN

(‘IN+’ ‘IN ’)

V_DESAT

t_DESATLEB

t_DESATFIL

DESAT

t_DESATOFF

90%

GATE

V_CLMPTH

t_DESATFLT

t_FLTMUTE

Hi-Z

FLT

t_RSTFIL

RST/EN

HIGH

Hi-Z

OUTH

OUTL

LOW

Hi-Z

LOW

图7-10. DESAT Protection with Soft Turn-OFF During Turn-ON Transition

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图7-11 shows the timing diagram of DESAT protection while the power device is already turned on.

IN

(”IN+‘ Å ”INÅ‘)

V_DESAT

t_DESATLEB

t_DESATFIL

DESAT

t_DESATOFF

90%

GATE

V_CLMPTH

t_DESATFLT

t_FLTMUTE

Hi-Z

FLT

t_RSTFIL

RST/EN

HIGH

Hi-Z

OUTH

OUTL

LOW

Hi-Z

LOW

图7-11. DESAT Protection with Soft Turn-OFF While Power Device is ON

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8 Detailed Description

8.1 Overview

The device is an advanced isolated gate driver with state-of-art protection and sensing features for SiC

MOSFETs and IGBTs. The device can support up to 2121-V DC operating voltage based on SiC MOSFETs and

IGBTs, and can be used to above 10-kW applications such as HEV/EV traction inverter, motor drive, on-board

and off-board battery charger, solar inverter, and so forth. The galvanic isolation is implemented by the

capacitive isolation technology, which can realize a reliable reinforced isolation between the low voltage

DSP/MCU and high voltage side.

The ±10-A peak sink and source current of the device can drive the SiC MOSFET modules and IGBT modules

directly without an extra buffer. The driver can also be used to drive higher power modules or parallel modules

with external buffer stage. The input side is isolated with the output side with a reinforced isolation barrier based

on capacitive isolation technology. The device can support up to 1.5-kV_RMSworking voltage, 12.8-kV_PKsurge

immunity with longer than 40 years isolation barrier life. The strong drive strength helps to switch the device fast

and reduce the switching loss, while the 150-V/ns minimum CMTI ensures the reliability of the system with fast

switching speed. The small propagation delay and part-to-part skew can minimize the deadtime setting, so the

conduction loss can be reduced.

The device includes extensive protection and monitor features to increase the reliability and robustness of the

SiC MOSFET and IGBT based systems. The 12-V output side power supply UVLO is suitable for switches with

gate voltage ≥ 15 V. The active Miller clamp feature prevents the false turn on causing by Miller capacitance

during fast switching. The device has the state-of-art DESAT detection time, and fault reporting function to the

low voltage side DSP/MCU. The soft turn off is triggered when the DESAT fault is detected, minimizing the short

circuit energy while reducing the overshoot voltage on the switches.

The isolated analog to PWM sensor can be used as switch temperature sensing, DC bus voltage sensing,

auxiliary power supply sensing, and so on. The PWM signal can be fed directly to DSP/MCU or through a low-

pass filter as an analog signal.

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8.2 Functional Block Diagram

CLMPI

OUTH

7

4

6

10

11

15

9

IN+

INt

55kQ

PWM Inputs

MOD

DEMOD

Output Stage

t

ON/OFF Control

STO

VCC

OUTL

VDD

VCC

UVLO

VCC Supply

5

GND

RDY

UVLO

LDO[s for VEE,

COM and channel

3

8

COM

VEE

12

13

14

16

Fault Decode

FLT

DESAT Protection

Analog 2 PWM

2

DESAT

Fault Encode

RST/EN

50kQ

PWM Driver

AIN

1

APWM

DEMOD

MOD

8.3 Feature Description

8.3.1 Power Supply

The input side power supply VCC can support a wide voltage range from 3 V to 5.5 V. The device supports both

unipolar and bipolar power supply on the output side, with a wide range from 13 V to 33 V from VDD to VEE.

The negative power supply with respect to switch source or emitter is usually adopted to avoid false turn on

when the other switch in the phase leg is turned on. The negative voltage is especially important for SiC

MOSFET due to its fast switching speed.

8.3.2 Driver Stage

The device has ±10-A peak drive strength and is suitable for high power applications. The high drive strength

can drive a SiC MOSFET module, IGBT module or paralleled discrete devices directly without extra buffer stage.

The device can also be used to drive higher power modules or parallel modules with extra buffer stage.

Regardless of the values of VDD, the peak sink and source current can be kept at 10 A. The driver features an

important safety function wherein, when the input pins are in floating condition, the OUTH/OUTL is held in LOW

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state. The split output of the driver stage is depicted in 图8-1. The driver has rail-to-rail output by implementing a

hybrid pull-up structure with a P-Channel MOSFET in parallel with an N-Channel MOSFET, and an N-Channel

MOSFET to pulldown. The pull-up NMOS is the same as the pull down NMOS, so the on resistance R_NMOSis

the same as R_OL. The hybrid pull-up structure delivers the highest peak-source current when it is most needed,

during the Miller plateau region of the power semiconductor turn-on transient. The R_OHin 图 8-1 represents the

on-resistance of the pull-up P-Channel MOSFET. However, the effective pull-up resistance is much smaller than

R_OH. Because the pullup N-Channel MOSFET has much smaller on-resistance than the P-Channel MOSFET,

the pullup N-Channel MOSFET dominates most of the turn-on transient, until the voltage on OUTH pin is about 3

V below VDD voltage. The effective resistance of the hybrid pullup structure during this period is about 2 x R_OL

.

Then the P-Channel MOSFET pulls up the OUTH voltage to VDD rail. The low pullup impedance results in

strong drive strength during the turn-on transient, which shortens the charging time of the input capacitance of

the power semiconductor and reduces the turn on switching loss. The output pull-up and pull-down resistance

can be found in the Electrical Characteristics table.

The pulldown structure of the driver stage is implemented solely by a pulldown N-Channel MOSFET. This

MOSFET can ensure the OUTL voltage be pulled down to VEE rail. The low pulldown impedance not only

results in high sink current to reduce the turn-off time, but also helps to increase the noise immunity considering

the Miller effect.

VDD

R_OH

R_NMOS

OUTH

Input

Signal

Anti Shoot-

through

Circuitry

OUTL

R_OL

图8-1. Gate Driver Output Stage

8.3.3 VCC and VDD Undervoltage Lockout (UVLO)

The device implements the internal UVLO protection feature for both input and output power supplies VCC and

VDD. When the supply voltage is lower than the threshold voltage, the driver output is held as LOW. The output

only goes HIGH when both VCC and VDD are out of the UVLO status. The UVLO protection feature not only

reduces the power consumption of the driver itself during low power supply voltage condition, but also increases

the efficiency of the power stage. For SiC MOSFET and IGBT, the on-resistance reduces while the gate-source

voltage or gate-emitter voltage increases. If the power semiconductor is turned on with a low VDD value, the

conduction loss increases significantly and can lead to a thermal issue and efficiency reduction of the power

stage. The device implements 12-V threshold voltage of VDD UVLO, with 800-mV hysteresis. This threshold

voltage is suitable for both SiC MOSFET and IGBT.

The UVLO protection block features with hysteresis and deglitch filter, which help to improve the noise immunity

of the power supply. During the turn on and turn off switching transient, the driver sources and sinks a peak

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transient current from the power supply, which can result in sudden voltage drop of the power supply. With

hysteresis and UVLO deglitch filter, the internal UVLO protection block will ignore small noises during the normal

switching transients.

The timing diagrams of the UVLO feature of VCC and VDD are shown in 图7-8, and 图7-9. The RDY pin on the

input side is used to indicate the power good condition. The RDY pin is open drain. During UVLO condition, the

RDY pin is held in low status and connected to GND. Normally the pin is pulled up externally to VCC to indicate

the power good. The AIN-APWM function stops working during the UVLO status. The APWM pin on the input

side will be held LOW.

8.3.4 Active Pulldown

The device implements an active pulldown feature to ensure the OUTH/OUTL pin clamping to VEE when the

VDD is open. The OUTH/OUTL pin is in high-impedance status when VDD is open, the active pulldown feature

can prevent the output be false turned on before the device is back to control.

VDD

OUTL

R_a

Control

Circuit

VEE

COM

图8-2. Active Pulldown

8.3.5 Short Circuit Clamping

During short circuit condition, the Miller capacitance can cause a current sinking to the OUTH/OUTL/CLMPI pin

due to the high dV/dt and boost the OUTH/OUTL/CLMPI voltage. The short circuit clamping feature of the device

can clamp the OUTH/OUTL/CLMPI pin voltage to be slightly higher than VDD, which can protect the power

semiconductors from a gate-source and gate-emitter overvoltage breakdown. This feature is realized by an

internal diode from the OUTH/OUTL/CLMPI to VDD.

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VDD

D₁D₂D₃

OUTH

Control

Circuitry

OUTL

CLMPI

图8-3. Short Circuit Clamping

8.3.6 Internal Active Miller Clamp

Active Miller clamp feature is important to prevent the false turn-on while the driver is in OFF state. In

applications which the device can be in synchronous rectifier mode, the body diode conducts the current during

the deadtime while the device is in OFF state, the drain-source or collector-emitter voltage remains the same

and the dV/dt happens when the other power semiconductor of the phase leg turns on. The low internal pull-

down impedance of UCC21756-Q1 can provide a strong pulldown to hold the OUTL to VEE. However, external

gate resistance is usually adopted to limit the dV/dt. The Miller effect during the turn on transient of the other

power semiconductor can cause a voltage drop on the external gate resistor, which boost the gate-source or

gate-emitter voltage. If the voltage on V_GSor V_GEis higher than the threshold voltage of the power

semiconductor, a shoot through can happen and cause catastrophic damage. The active Miller clamp feature of

UCC21756-Q1 drives an internal MOSFET, which connects to the device gate. The MOSFET is triggered when

the gate voltage is lower than V_CLMPTH, which is 2 V above VEE, and creates a low impedance path to avoid the

false turn on issue.

V_CLMPTH

VCC

OUTH

+

3V to 5.5V

IN+

œ

CLMPI

OUTL

Control

Circuitry

µC

MOD

DEMOD

IN-

VEE

COM

VCC

图8-4. Active Miller Clamp

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8.3.7 Desaturation (DESAT) Protection

The UCC21756-Q1 implements a fast overcurrent and short circuit protection feature to protect the IGBT module

from catastrophic breakdown during fault. The DESAT pin has a typical 5-V threshold with respect to COM, the

source or emitter of the power semiconductor. When the input is in a floating condition or the output is held in low

state, the DESAT pin is pulled down by an internal MOSFET and held in the LOW state, which prevents the

overcurrent and short circuit fault from false triggering. The internal current source of the DESAT pin is activated

only during the driver ON state, which means the overcurrent and short circuit protection feature only works

when the power semiconductor is in the ON state. The internal pulldown MOSFET helps to discharge the voltage

of the DESAT pin when the power semiconductor is turned off. The UCC21756-Q1 features a 200-ns internal

leading edge blanking time after the OUTH switches to high state. The internal current source is activated to

charge the external blanking capacitor after the internal leading edge blanking time. The typical value of the

internal current source is 500 µA.

VDD

D_HV

R

DESAT

+

–

DESAT Fault

C _BLK

+

V_DESAT

–

Control

Logic

COM

图8-5. DESAT Protection

8.3.8 Soft Turn-Off

The device initiates a soft turn-off when the overcurrent and short circuit protection are triggered. When the

overcurrent and short circuit faults occur, the IGBT transits from the active region to the desaturation region very

quickly. The channel current is controlled by the gate voltage and decreases softly; thus, the overshoot of the

IGBT is limited and prevents the overvoltage breakdown. There is a tradeoff between the overshoot voltage and

short circuit energy. The turn-off speed should be slow to limit the overshoot-voltage, but the shutdown time

should not be too long that the large energy dissipation can breakdown the device. The 900-mA soft turn-off

current of the device ensures the power switches are safely turned off during short circuit events. 图 7-10 shows

the soft turn-off timing diagram.

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VDD

DESAT

R

D_HV

+

–

C_BLK

+

V_DESAT

–

Control

Logic

COM

Soft Turn-off

OUTL

VEE

图8-6. Soft Turn-Off

8.3.9 Fault (FLT), Reset and Enable (RST/EN)

The FLT pin of UCC21756-Q1 is open drain and can report a fault signal to the DSP/MCU when the fault is

detected through the DESAT pin. The FLT pin is pulled down to GND after the fault is detected, and is held low

until a reset signal is received from RST/EN. The device has a fault mute time t_FLTMUTE, within which the device

ignores any reset signal.

The RST/EN is pulled down internally by a 50-kΩ resistor, and is thus disabled by default when this pin is

floating. It must be pulled up externally to enable the driver. The pin has two purposes:

• To reset the FLT pin. If the RST/EN pin is pulled low for more than t_RSTFILafter the mute time t_FLTMUTE, then

the fault signal is reset and FLT returns to a high impedance state upon the next rising edge applied to the

RST/EN pin.

• To enable and shut down the device. If the RST/EN pin is pulled low for longer than t_RSTFIL, the driver is

disabled and OUTL is activated to pull down the gate of the IGBT or SiC MOSFET. The pin must be pulled up

externally to enable the part; otherwise, the device is disabled by default.

8.3.10 Isolated Analog to PWM Signal Function

The device features an isolated analog to PWM signal function from AIN to APWM pin, which allows the isolated

temperature sensing, high voltage dc bus voltage sensing, and so on. An internal current source I_AINin AIN pin

is implemented in the device to bias an external thermal diode or temperature sensing resistor. The device

encodes the voltage signal V_AINto a PWM signal, passing through the reinforced isolation barrier, and output to

APWM pin on the input side. The PWM signal can either be transferred directly to DSP/MCU to calculate the

duty cycle, or filtered by a simple RC filter as an analog signal. The AIN voltage input range is from 0.6 V to 4.5

V, and the corresponding duty cycle of the APWM output ranges from 88% to 10%. The duty cycle increases

linearly from 10% to 88% while the AIN voltage decreases from 4.5 V to 0.6 V. This corresponds to the

temperature coefficient of the negative temperature coefficient (NTC) resistor and thermal diode. When AIN is

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floating, the AIN voltage is 5 V and the APWM operates at 400 kHz with approximately 10% duty cycle. The

accuracy of the duty cycle is ±3% across temperature without one time calibration. The accuracy can be

improved using calibration. The accuracy of the internal current source I_AINis ±3% across temperature.

The isolated analog to PWM signal feature can also support other analog signal sensing, such as the high

voltage DC bus voltage, and so on. The internal current source I_AINshould be taken into account when designing

the potential divider if sensing a high voltage.

UCC217xx

In Module or

Discrete

VCC

VDD

13V to

33V

+

3V to 5.5V

APWM

œ

AIN

+

DEMOD

MOD

µC

R_filt

C_filt

OSC

GND

COM

Thermal

Diode

NTC or

PTC

图8-7. Isolated Analog to PWM Signal

表8-1. Function Table

8.4 Device Functional Modes

表8-1 lists the device function.

INPUT

IN+

OUTPUT

OUTH/

OUTL

VCC

VDD

VEE

IN-

RST/EN

AIN

RDY

FLT

CLMPI

APWM

PU

PD

PU

PD

PU

X

Low

HiZ

Low

HiZ

Low

HiZ

Low

HiZ

Low

HiZ

Low

P^*

PU

X

Low

X

Open

PU

X

Open

PU

X

Low

High

Low

HiZ

PU

Low

X

High

PU

High

Low

P^*

PU

High

P^*

PU

P^*

PU: Power Up (VCC ≥ 2.85 V, VDD ≥ 13.1 V, VEE ≤ 0 V); PD: Power Down (VCC ≤ 2.35 V, VDD ≤ 9.9 V);

X: Irrelevant; P^*: PWM Pulse; HiZ: High Impedance

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9 Applications and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The device is very versatile because of the strong drive strength, wide range of output power supply, high

isolation ratings, high CMTI and superior protection and sensing features. The 1.5-kVRMS working voltage and

12.8-kVPK surge immunity can support up both SiC MOSFET and IGBT modules with DC bus voltage up to

2121 V. The device can be used in both low power and high power applications such as the traction inverter in

HEV/EV, on-board charger and charging pile, motor driver, solar inverter, industrial power supplies, and so on.

The device can drive the high power SiC MOSFET module, IGBT module or paralleled discrete device directly

without external buffer drive circuit based on NPN/PNP bipolar transistor in totem-pole structure, which allows

the driver to have more control to the power semiconductor and saves the cost and space of the board design.

The device can also be used to drive very high power modules or paralleled modules with external buffer stage.

The input side can support power supply and microcontroller signal from 3.3 V to 5 V, and the device level shifts

the signal to output side through reinforced isolation barrier. The device has wide output power supply range

from 13 V to 33 V and support wide range of negative power supply. This allows the driver to be used in SiC

MOSFET applications, IGBT application, and many others. The 12-V UVLO benefits the power semiconductor

with lower conduction loss and improves the system efficiency. As a reinforced isolated single channel driver, the

device can be used to drive either a low-side or high-side driver.

The device features extensive protection and monitoring features, which can monitor, report and protect the

system from various fault conditions.

• Fast detection and protection for the overcurrent and short circuit fault. The semiconductor is shutdown when

the fault is detected and FLT pin is pulled down to indicate the fault detection. The device is latched unless

reset signal is received from the RST/EN pin.

• Soft turn-off feature to protect the power semiconductor from catastrophic breakdown during overcurrent and

short circuit fault. The shutdown energy can be controlled while the overshoot of the power semiconductor is

limited.

• UVLO detection to protect the semiconductor from excessive conduction loss. Once the device is detected to

be in UVLO mode, the output is pulled down and RDY pin indicates the power supply is lost. The device is

back to normal operation mode once the power supply is out of the UVLO status. The power good status can

be monitored from the RDY pin.

• Analog signal seensing with isolated analog to PWM signal feature. This feature allows the device to sense

the temperature of the semiconductor from the thermal diode or temperature sensing resistor, or dc bus

voltage with resistor divider. A PWM signal is generated on the low voltage side with reinforced isolated from

the high voltage side. The signal can be fed back to the microcontroller for the temperature monitoring,

voltage monitoring, and and so on.

• The active Miller clamp feature protects the power semiconductor from false turn on.

• Enable and disable function through the RST/EN pin

• Short circuit clamping

• Active pulldown

9.2 Typical Application

图 9-1 shows the typical application of a half bridge using two UCC21756-Q1 isolated gate drivers. The half

bridge is a basic element in various power electronics applications such as traction inverter in HEV/EV to convert

the DC current of the electric vehicle’s battery to the AC current to drive the electric motor in the propulsion

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system. The topology can also be used in motor drive applications to control the operating speed and torque of

the AC motors.

UCC

217XX

1

2

3

4

5

6

PWM

3-Phase

Input

1

2

3

4

5

6

µC

M

APWM

FLT

UCC

217XX

图9-1. Typical Application Schematic

9.2.1 Design Requirements

The design of the power system for end equipment should consider some design requirements to ensure the

reliable operation of the device through the load range. The design considerations include the peak source and

sink current, power dissipation, overcurrent and short circuit protection, AIN-APWM function for analog signal

sensing, and so on.

A design example for a half bridge based on IGBT is given in this subsection. The design parameters are shown

in 表9-1.

表9-1. Design Parameters

PARAMETER

Input Supply Voltage

IN-OUT Configuration

Positive Output Voltage VDD

Negative Output Voltage VEE

DC Bus Voltage

VALUE

5 V

Noninverting

15 V

–5 V

800 V

Peak Drain Current

300 A

Switching Frequency

Switch Type

50 kHz

IGBT Module

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9.2.2 Detailed Design Procedure

9.2.2.1 Input Filters for IN+, IN-, and RST/EN

In the applications of traction inverter or motor drive, the power semiconductors are in hard switching mode. With

the strong drive strength of the device, the dV/dt can be high, especially for SiC MOSFET. Noise cannot only be

coupled to the gate voltage due to the parasitic inductance, but also to the input side as the non-ideal PCB

layout and coupled capacitance.

The device features a 40-ns internal deglitch filter to IN+, IN- and RST/EN pin. Any signal less than 40 ns can be

filtered out from the input pins. For noisy systems, external low-pass filter can be added externally to the input

pins. Adding low-pass filters to IN+, IN- and RST/EN pins can effectively increase the noise immunity and

increase the signal integrity. When not in use, the IN+, IN- and RST/EN pins should not be floating. IN- should be

tied to GND if only IN+ is used for noninverting input to output configuration. The purpose of the low-pass filter is

to filter out the high frequency noise generated by the layout parasitics. While choosing the low-pass filter

resistors and capacitors, both the noise immunity effect and delay time should be considered according to the

system requirements.

9.2.2.2 PWM Interlock of IN+ and IN-

The device features the PWM interlock for IN+ and IN- pins, which can be used to prevent the phase leg shoot

through issue. As shown in 表8-1, the output is logic low while both IN+ and IN- are logic high. When only IN+ is

used, IN- can be tied to GND. To utilize the PWM interlock function, the PWM signal of the other switch in the

phase leg can be sent to the IN- pin. As shown in 图 9-2, the PWM_T is the PWM signal to top side switch, the

PWM_B is the PWM signal to bottom side switch. For the top side gate driver, the PWM_T signal is given to the

IN+ pin, while the PWM_B signal is given to the IN- pin; for the bottom side gate driver, the PWM_B signal is

given to the IN+ pin, while PWM_T signal is given to the IN- pin. When both PWM_T and PWM_B signals are

high, the outputs of both gate drivers are logic low to prevent the shoot through condition.

IN+

IN-

R_ON

OUTH

OUTL

R_OFF

PWM_T

PWM_B

R_ON

IN+

IN-

OUTH

OUTL

R_OFF

图9-2. PWM Interlock for a Half Bridge

9.2.2.3 FLT, RDY, and RST/EN Pin Circuitry

Both FLT and RDY pin are open-drain output. The RST/EN pin has 50-kΩ internal pulldown resistor, so the

driver is in OFF status if the RST/EN pin is not pulled up externally. A 5-kΩ resistor can be used as pullup

resistor for the FLT, RDY, and RST/EN pins.

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To improve the noise immunity due to the parasitic coupling and common-mode noise, low-pass filters can be

added between the FLT, RDY, and RST/EN pins and the microcontroller. A filter capacitor between 100 pF to

300 pF can be added.

3.3V to 5V

VCC

15

1µF

0.1µF

GND

IN+

9

10

INt

11

5kQ

5kQ 5kQ

FLT

12

13

100pF

RDY

100pF

RST/EN

14

16

100pF

APWM

图9-3. FLT, RDY, and RST/EN Pins Circuitry

9.2.2.4 RST/EN Pin Control

RST/EN pin has two functions. It is used to enable or shutdown the outputs of the driver and to reset the fault

signaled on the FLT pin after DESAT is detected. RST/EN pin needs to be pulled up to enable the device; when

the pin is pulled down, the device is in disabled status. By default the driver is disabled with the internal 50-kΩ

pulldown resistor at this pin.

When the driver is latched after DESAT is detected, the FLT pin and output are latched low and need to be reset

by the RST/EN pin. The microcontroller must send a signal to RST/EN pin after the fault to reset the driver. The

driver will not respond until after the mute time t_FLTMUTE. The reset signal must be held low for at least t_RSTFIL

after the mute time.

This pin can also be used to automatically reset the driver. The continuous input signal IN+ or IN- can be applied

to RST/EN pin. There is no separate reset signal from the microcontroller when configuring the driver this way. If

the PWM is applied to the noninverting input IN+, then IN+ can also be tied to RST/EN pin. If the PWM is applied

to the inverting input IN-, then a NOT logic is needed between the PWM signal from the microcontroller and the

RST/EN pin. Using either configuration results in the driver being reset in every switching cycle without an extra

control signal from microcontroller tied to RST/EN pin. One must ensure the PWM off-time is greater than t_RSTFIL

in order to reset the driver in cause of a DESAT fault.

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3.3V to 5V

0.1µF

3.3V to 5V

0.1µF

VCC

15

1µF

GND

IN+

GND

IN+

9

10

INt

5kQ

11

5kQ

11

5kQ

FLT

12

13

12

13

100pF

RDY

100pF

RST/EN

APWM

RST/EN

APWM

14

16

14

16

图9-4. Automatic Reset Control

9.2.2.5 Turn-On and Turn-Off Gate Resistors

The device features split outputs OUTH and OUTL, which enables the independent control of the turn-on and

turn-off switching speeds. The turn-on and turn-off resistances determine the peak source and sink current,

which control the switching speed. Meanwhile, the power dissipation in the gate driver should be considered to

ensure the device is in the thermal limit. At first, the peak source and sink current are calculated as:

VDD - VEE

R_{OH_EFF}+R_ON+R_{G _Int}

I_{source _ pk}= min(10A,

I_{sink _ pk}= min(10A,

)

VDD - VEE

R_OL+R_OFF+R_{G _Int}

)

(1)

Where

• R_{OH_EFF}is the effective internal pullup resistance of the hybrid pullup structure, shown in 图8-1, which is

approximately 2 x R_OL, about 0.7 Ω. This is the dominant resistance during the switching transient of the pull

up structure.

• R_OLis the internal pulldown resistance, about 0.3 Ω.

• R_ONis the external turn-on gate resistance.

• R_OFFis the external turn-off gate resistance.

• R_{G_Int}is the internal resistance of the SiC MOSFET or IGBT module.

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VDD

C_ies=C_gc+C_ge

+

C_gc

VDD

R_{OH_EFF}

t

OUTH

OUTL

R_ON

R_{G_Int}

R_OFF

C_ge

+

VEE

R_OL

t

VEE

COM

图9-5. Output Model for Calculating Peak Gate Current

For example, for an IGBT module based system with the following parameters:

• Q_g= 3300 nC

• R_{G_Int}= 1.7 Ω

• R_ON=R_OFF= 1 Ω

The peak source and sink current in this case are:

VDD - VEE

R_{OH_EFF}+R_ON+R_{G _Int}

I_{source _ pk}= min(10A,

) ö 5.9A

VDD - VEE

R_OL+R_OFF+R_{G _Int}

I_{sink _ pk}= min(10A,

) ö 6.7A

(2)

Using 1-Ω external gate resistance, the peak source current is 5.9 A, the peak sink current is 6.7 A. The

collector-to-emitter dV/dt during the turn-on switching transient is dominated by the gate current at the Miller

plateau voltage. The hybrid pullup structure ensures the peak source current at the Miller plateau voltage, unless

the turn-on gate resistor is too high. The faster the collector-to-emitter, V_ce, voltage rises to V_DC, the smaller the

turn-on switching loss. The dV/dt can be estimated as Q_gc/I_{source_pk}. For the turn-off switching transient, the

drain-to-source dV/dt is dominated by the load current, unless the turn-off gate resistor is too high. After V_ce

reaches the DC bus voltage, the power semiconductor is in SATURATION mode and the channel current is

controlled by V_ge. The peak sink current determines the dI/dt, which dominates the V_cevoltage overshoot

accordingly. If using relatively large turn-off gate resistance, the V_ceovershoot can be limited. The overshoot can

be estimated by:

DV = L_stray∂I_load/ ((R_OFF+R_OL+R_{G_Int})∂C_ies∂ln(V_plat/ V ))

ce

th

(3)

Where

• L_strayis the stray inductance in power switching loop, as shown in 图9-6.

• I_loadis the load current, which is the turn-off current of the power semiconductor.

• C_iesis the input capacitance of the power semiconductor.

• V_platis the plateau voltage of the power semiconductor.

• V_this the threshold voltage of the power semiconductor.

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L_DC

L_c1

L_stray=L_DC+L_e1+L_c1+L_e1+L_c1

R_G

L_load

t

+

L_e1

+

VDC

t

L_c2

VDD

C_gc

C_ies=C_gc+C_ge

R_G

OUTH

OUTL

COM

C_ge

L_e2

图9-6. Stray Parasitic Inductance of IGBTs in a Half-Bridge Configuration

The power dissipation should be taken into account to maintain the gate driver within the thermal limit. The

power loss of the gate driver includes the quiescent loss and the switching loss, which can be calculated as:

P

= P_Q+P

DR

SW

(4)

P_Qis the quiescent power loss for the driver, which is I_q× (VDD-VEE) = 5 mA × 20 V = 0.100 W. The quiescent

power loss is the power consumed by the internal circuits, such as the input stage, reference voltage, logic

circuits, and protection circuits when the driver is switching, when the driver is biased with VDD and VEE, and

the charging and discharging current of the internal circuit when the driver is switching. The power dissipation

when the driver is switching can be calculated as:

R_{OH_EFF}

2 R_{OH_EFF}+R_ON+R_{G _Int}R_OL+R_OFF+R_{G _Int}

R_OL

1

P

=

∂(

+

)∂(VDD - VEE)∂ f_sw∂Q_g

SW

(5)

Where

• Q_gis the gate charge required at the operation point to fully charge the gate voltage from VEE to VDD.

• f_swis the switching frequency.

In this example, the P_SWcan be calculated as:

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R_{OH_EFF}

2 R_{OH_EFF}+ R_ON+ R_{G _Int}R_OL+R_OFF+R_{G _Int}

R_OL

1

P

=

∂(

+

)∂(VDD - VEE)∂ f_sw∂Q_g= 0.505W

SW

(6)

(7)

Thus, the total power loss is:

P =P +P = 0.10W +0.505W = 0.605W

DR

Q

SW

When the board temperature is 125°C, the junction temperature can be estimated as:

T_j= T + y_jb∂P ö 150^oC

b

DR

(8)

Therefore, for the application in this example, with 125°C board temperature, the maximum switching frequency

is ~50 kHz to keep the gate driver in the thermal limit. By using a lower switching frequency or increasing

external gate resistance, the gate driver can be operated at a higher switching frequency.

9.2.2.6 Overcurrent and Short Circuit Protection

A standard desaturation circuit can be applied to the DESAT pin. If the voltage of the DESAT pin is higher than

the threshold V_DESAT, the soft turn-off is initiated. A fault will be reported to the input side to DSP/MCU. The

output is held to LOW after the fault is detected, and can only be reset by the RST/EN pin. The state-of-art

overcurrent and short circuit detection time helps to ensure a short shutdown time for SiC MOSFET and IGBT.

If DESAT pin is not in use, it must be tied to COM to avoid overcurrent fault false triggering.

• Fast reverse recovery high voltage diode is recommended in the desaturation circuit. A resistor is

recommended in series with the high voltage diode to limit the inrush current.

• A Schottky diode is recommended from COM to DESAT to prevent driver damage caused by negative

voltage.

• A Zener diode is recommended from COM to DESAT to prevent driver damage caused by positive voltage.

9.2.2.7 Isolated Analog Signal Sensing

The isolated analog signal sensing feature provides a simple isolated channel for the isolated temperature

detection, voltage sensing, and so on. One typical application of this function is the temperature monitor of the

power semiconductor. Thermal diodes or temperature sensing resistors are integrated in the SiC MOSFET or

IGBT module close to the dies to monitor the junction temperature. The device has an internal 200-μA current

source with ±3% accuracy across temperature, which can forward bias the thermal diodes or create a voltage

drop on the temperature sensing resistors. The sensed voltage from the AIN pin is passed through the isolation

barrier to the input side and transformed to a PWM signal. The duty cycle of the PWM changes linearly from

10% to 88% when the AIN voltage changes from 4.5 V to 0.6 V and can be represented using 方程式9.

D_APWM(%) = -20 * V_AIN+100

(9)

9.2.2.7.1 Isolated Temperature Sensing

A typical application circuit is shown in 图 9-7. To sense temperature, the AIN pin is connected to the thermal

diode or thermistor which can be discrete or integrated within the power module. A low-pass filter is

recommended for the AIN input. Since the temperature signal does not have a high bandwidth, the low-pass

filter is mainly used for filtering the noise introduced by the switching of the power device, which does not require

stringent control for propagation delay. The filter capacitance for C_filtcan be chosen between 1 nF to 100 nF and

the filter resistance R_filtbetween 1 Ω to 10 Ω according to the noise level.

The output of APWM is directly connected to the microcontroller to measure the duty cycle dependent on the

voltage input at AIN, using 方程式9.

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UCC217xx

In Module or

Discrete

VCC

VDD

AIN

13V to

33V

+

3V to 5.5V

APWM

œ

+

DEMOD

MOD

µC

R_filt

C_filt

OSC

GND

COM

Thermal

Diode

NTC or

PTC

图9-7. Thermal Diode or Thermistor Temperature Sensing Configuration

When a high-precision voltage supply for VCC is used on the primary side of the device, the duty cycle output of

APWM may also be filtered and the voltage measured using the microcontroller's ADC input pin, as shown in 图

9-8. The frequency of APWM is 400 kHz, so the value for R_{filt_2}and C_{filt_2}should be such that the cutoff

frequency is below 400 kHz. Temperature does not change rapidly, thus the rise time due to the RC constant of

the filter is not under a strict requirement.

UCC217xx

VDD

In Module or

Discrete

VCC

13V to

33V

+

œ

3V to 5.5V

APWM

œ

AIN

+

DEMOD

MOD

µC

R_{filt_1}

R_{filt_2}

C_{filt_2}

GND

OSC

C_{filt_1}

COM

Thermal

Diode

NTC or

PTC

图9-8. APWM Channel with Filtered Output

The example below shows the results using a 4.7-kΩNTC, NTCS0805E3472FMT, in series with a 3-kΩresistor

and also the thermal diode using four diode-connected MMBT3904 NPN transistors. The sensed voltage of the 4

MMBT3904 thermal diodes connected in series ranges from about 2.5 V to 1.6 V from 25°C to 135°C,

corresponding to 50% to 68% duty cycle. The sensed voltage of the NTC thermistor connected in series with the

3-kΩ resistor ranges from about 1.5 V to 0.6 V from 25°C to 135°C, corresponding to 70% to 88% duty cycle.

The voltage at VAIN of both sensors and the corresponding measured duty cycle at APWM is shown in 图9-9.

English Data Sheet: SLUSEN8

38

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2.7

90

84

2.4

2.1

1.8

1.5

1.2

0.9

Thermal Diode V_AIN

NTC V_AIN

Thermal Diode APWM

NTC APWM

78

72

66

60

54

0.6

20

48

140

40

60

80

Temperature (èC)

100

120

VAIN

图9-9. Thermal Diode and NTC V_AINand Corresponding Duty Cycle at APWM

The duty cycle output has an accuracy of ±3% throughout temperature without any calibration, as shown in 图

9-10 but with single-point calibration at 25°C, the duty accuracy can be improved to ±1%, as shown in 图9-11.

1.5

Thermal Diode APWM Duty Error

NTC APWM Duty Error

1.25

1

0.75

0.5

0.25

0

-0.25

20

40

60

80

Temperature (èC)

100

120

140

APWM

图9-10. APWM Duty Error Without Calibration

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0.8

0.6

0.4

0.2

0

Thermal Diode APWM Duty Error

NTC APWM Duty Error

-0.2

20

40

60

80

Temperature (èC)

100

120

140

APWM

图9-11. APWM Duty Error with Single-Point Calibration

9.2.2.7.2 Isolated DC Bus Voltage Sensing

The AIN to APWM channel may be used for other applications such as the DC-link voltage sensing, as shown in

图 9-12. The same filtering requirements as given above may be used in this case, as well. The number of

attenuation resistors, R_{atten_1}through R_{atten_n}, is dependent on the voltage level and power rating of the resistor.

The voltage is finally measured across R_{LV_DC}to monitor the stepped-down voltage of the HV DC-link which

must fall within the voltage range of AIN from 0.6 V to 4.5 V. The driver should be referenced to the same point

as the measurement reference; thus, in the case shown below, the UCC21756-Q1 is driving the lower IGBT in

the half-bridge and the DC-link voltage measurement is referenced to COM. The internal current source I_AIN

should be taken into account when designing the resistor divider. The AIN pin voltage is:

R_{LV _DC}

n

V_AIN

=

∂ V_DC+R_{LV _DC}∂I_AIN

R_{LV _DC}

+

R

atten _ i

ƒ

i=1

(10)

R_{atten_1}

R_{atten_2}

UCC217xx

VDD

VCC

R_{atten_n}

13V to

33V

+

3V to 5.5V

APWM

œ

C_DC

+

AIN

DEMOD

MOD

µC

R_filt

C_filt

R_{filt_2}

C_{filt_2}

GND

R_{LV_DC}

OSC

COM

图9-12. DC-Link Voltage Sensing Configuration

English Data Sheet: SLUSEN8

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9.2.2.8 Higher Output Current Using an External Current Buffer

To increase the IGBT gate drive current, a noninverting current buffer (such as the NPN/PNP buffer shown in 图

9-13) can be used. Inverting types are not compatible with the desaturation fault protection circuitry and must be

avoided. The MJD44H11/MJD45H11 pair is appropriate for peak currents up to 15 A, the D44VH10/ D45VH10

pair is up to 20-A peak.

In the case of an overcurrent detection, the soft turn-off (STO) is activated. External components must be added

to implement STO instead of normal turn-off speed when an external buffer is used. C_STOsets the timing for soft

turn-off and R_STOlimits the inrush current to below the current rating of the internal FET (10A). R_STOshould be at

least (VDD-VEE)/10. The soft turn-off timing is determined by the internal current source of 900 mA and the

capacitor C_STO. C_STOis calculated using 方程式11.

I_STO∂ t_STO

VDD

-

VEE

C_STO

=

(11)

• I_STOis the internal STO current source, 900 mA.

• t_STOis the desired STO timing.

VDD

R_OH

C_ies=C_gc+C_ge

R_NMOS

OUTH

C_gc

R_{G_2}

R_{G_1}

R_{G_Int}

OUTL

C_ge

R_OL

C_STO

COM

VEE

R_STO

图9-13. Current Buffer for Increased Drive Strength

9.2.3 Application Curves

图9-14. PWM Input (yellow) and Driver Output (blue)

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Step Input (0.6 V to 4.5 V)

APWM Output

图9-15. AIN Step Input (green) and APWM Output (pink)

10 Power Supply Recommendations

During the turn-on and turn-off switching transient, the peak source and sink current is provided by the VDD and

VEE power supply. The large peak current is possible to drain the VDD and VEE voltage level and cause a

voltage droop on the power supplies. To stabilize the power supply and ensure a reliable operation, a set of

decoupling capacitors are recommended at the power supplies. Considering the device has ±10-A peak drive

strength and can generate high dV/dt, a 10-µF bypass cap is recommended between VDD and COM, VEE and

COM. A 1-µF bypass cap is recommended between VCC and GND due to less current comparing with output

side power supplies. A 0.1-µF decoupling cap is also recommended for each power supply to filter out high

frequency noise. The decoupling capacitors must be low ESR and ESL to avoid high frequency noise, and

should be placed as close as possible to the VCC, VDD and VEE pins to prevent noise coupling from the system

parasitics of PCB layout.

English Data Sheet: SLUSEN8

42

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11 Layout

11.1 Layout Guidelines

Due to the strong drive strength of the device, careful considerations must be taken in PCB design. Below are

some key points:

• The driver should be placed as close as possible to the power semiconductor to reduce the parasitic

inductance of the gate loop on the PCB traces.

• The decoupling capacitors of the input and output power supplies should be placed as close as possible to

the power supply pins. The peak current generated at each switching transient can cause high dI/dt and

voltage spike on the parasitic inductance of PCB traces.

• The driver COM pin should be connected to the Kelvin connection of SiC MOSFET source or IGBT emitter. If

the power device does not have a split Kelvin source or emitter, the COM pin should be connected as close

as possible to the source or emitter terminal of the power device package to separate the gate loop from the

high power switching loop.

• Use a ground plane on the input side to shield the input signals. The input signals can be distorted by the

high frequency noise generated by the output side switching transients. The ground plane provides a low-

inductance filter for the return current flow.

• If the gate driver is used for the low side switch which the COM pin connected to the dc bus negative, use the

ground plane on the output side to shield the output signals from the noise generated by the switch node; if

the gate driver is used for the high side switch, which the COM pin is connected to the switch node, ground

plane should not overlap with any low-side circuitry, and it should be routed independently from the source/

emitter power path.

• If ground plane is not used on the output side, separate the return path of the DESAT and AIN ground loop

from the gate loop ground which has large peak source and sink current.

• No PCB trace or copper is allowed under the gate driver. A PCB cutout is recommended to avoid any noise

coupling between the input and output side which can contaminate the isolation barrier.

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11.2 Layout Example

图11-1. Layout Example

English Data Sheet: SLUSEN8

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12 Device and Documentation Support

12.1 Device Support

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

• Isolation Glossary

12.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

12.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: UCC21756-Q1

English Data Sheet: SLUSEN8

GENERIC PACKAGE VIEW

DW 16

7.5 x 10.3, 1.27 mm pitch

SOIC - 2.65 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224780/A

www.ti.com

PACKAGE OUTLINE

DW0016B

SOIC - 2.65 mm max height

S

C

A

L

E

1

.

5

0

SOIC

C

10.63

9.97

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

14X 1.27

16

1

2X

10.5

10.1

NOTE 3

8.89

8

9

0.51

0.31

16X

7.6

7.4

B

2.65 MAX

0.25

C A

B

NOTE 4

0.33

0.10

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.3

0.1

0 - 8

1.27

0.40

DETAIL A

TYPICAL

(1.4)

4221009/B 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

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EXAMPLE BOARD LAYOUT

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (2)

1

16X (1.65)

SEE

DETAILS

SEE

DETAILS

1

16

16X (0.6)

SYMM

14X (1.27)

R0.05 TYP

9

8

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4221009/B 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (1.65)

16X (2)

1

16

16X (0.6)

SYMM

14X (1.27)

8

9

8

9

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

4221009/B 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	UCC21756-Q1
厂家：	TEXAS INSTRUMENTS
描述：	Automotive, ± 10-A isolated single-channel gate driver with active protection and isolated sensing
文件：	总51页 (文件大小：2647K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC21756-Q1 [TI]

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