UCC23513DWY [TI]

具有 8 和 12V UVLO 选项的 5.7kVrms、4A/5A 单通道光兼容隔离式栅极驱动器 | DWY | 6 | -40 to 125;


型号：	UCC23513DWY
厂家：	TEXAS INSTRUMENTS
描述：	具有 8 和 12V UVLO 选项的 5.7kVrms、4A/5A 单通道光兼容隔离式栅极驱动器 \| DWY \| 6 \| -40 to 125 栅极驱动光电二极管接口集成电路驱动器
文件：	总40页 (文件大小：9852K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC23513

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SLUSD31E – OCTOBER 2018 – REVISED AUGUST 2020

UCC23513, 4-A Source, 5-A Sink, 5.7-kV_RMSOpto-Compatible

Single-Channel Isolated Gate Driver

immunity (CMTI), low propagation delay, and small

1 Features

pulse width distortion. Tight process control results in

small part-to-part skew. The input stage is an

emulated diode (e-diode) which means long term

reliability and excellent aging characteristics

compared to traditional LEDs. It is offered in a

stretched SO6 package with >8.5mm creepage and

clearance, and a mold compound from material group

I which has a comparative tracking index (CTI) >600V.

UCC23513's high performance and reliability makes it

ideal for use in all types of motor drives, solar

inverters, industrial power supplies, and appliances.

The higher operating temperature opens up

•

5.7-kV_RMSsingle channel isolated gate driver with

opto-compatible input

•

Pin-to-pin, drop in upgrade for opto isolated gate

drivers

•

4.5-A source / 5.3-A sink, peak output current

14-V to 33-V output driver supply voltage

– 8-V (B) and 12-V VCC UVLO Options

Rail-to-rail output

105-ns (maximum) propagation delay

25-ns (maximum) part-to-part delay matching

35-ns (maximum) pulse width distortion

150-kV/μs (minimum) common-mode transient

immunity (CMTI)

•

opportunities for applications not previously able to be

supported by traditional optocouplers.

Device Information ⁽¹⁾

•

Isolation barrier life >50 Years

13-V reverse polarity voltage handling capability

on input stage

BODY SIZE

(NOM)

PART NUMBER

PACKAGE

Stretched

SO-6

7.5 mm x

4.68 mm

UCC23513

•

Stretched SO-6 package with >8.5-mm creepage

and clearance

Operating junction temperature, T_J: –40°C to

+150°C

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Safety-related certifications:

– 8000-V_PKreinforced isolation per DIN V VDE

V0884-11: 2017-01

– 5.7-kV_RMSisolation for 1 minute per UL 1577

– CQC certification per GB4943.1-2011

V_CC

ANODE

UVLO

2 Applications

V_OUT

•

Industrial motor-control drives

Industrial power supplies, UPS

Solar inverters

Induction heating

V_EE

CATHODE

3 Description

The UCC23513 drivers are opto-compatible, single-

channel, isolated gate drivers for IGBTs, MOSFETs

and SiC MOSFETs, with 4.5-A source and 5.3-A sink

peak output current and 5.7-kV_RMSreinforced

Functional Block Diagram of UCC23513 (SO6)

isolation rating. The high supply voltage range of 33-V

allows the use of bipolar supplies to effectively drive

IGBTs and SiC power FETs. UCC23513 can drive

both low side and high side power FETs. Key features

and characteristics bring significant performance and

reliability upgrades over standard opto-coupler based

gate drivers while maintaining pin-to-pin compatibility

in both schematic and layout design. Performance

highlights include high common mode transient

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Function.....................................3

Pin Functions.................................................................... 3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................4

6.5 Power Ratings.............................................................5

6.6 Insulation Specifications ............................................ 6

6.7 Safety-Related Certifications...................................... 7

6.8 Safety Limiting Values.................................................7

6.9 Electrical Characteristics.............................................8

6.10 Switching Characteristics..........................................8

6.11 Insulation Characteristics Curves..............................9

6.12 Typical Characteristics............................................10

7 Parameter Measurement Information..........................13

7.1 Propagation Delay, Rise Time and Fall Time............13

7.2 I_OHand I_OLtesting.....................................................13

7.3 CMTI Testing.............................................................13

8 Detailed Description......................................................14

8.1 Overview...................................................................14

8.2 Functional Block Diagram.........................................15

8.3 Feature Description...................................................15

8.4 Device Functional Modes..........................................19

9 Application and Implementation..................................20

9.1 Application Information............................................. 20

9.2 Typical Application.................................................... 21

10 Power Supply Recommendations..............................27

11 Layout...........................................................................28

11.1 Layout Guidelines................................................... 28

11.2 Layout Example...................................................... 29

11.3 PCB Material...........................................................31

12 Mechanical, Packaging, and Orderable

Information.................................................................... 32

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (October 2019) to Revision E ()

Page

•

Added B version with 8-V UVLO.........................................................................................................................1

Changes from Revision C (June 2019) to Revision D ()

Page

•

Changed Minimum internal gap unit from mm to µm. ........................................................................................6

Changes from Revision B (June 2019) to Revision C ()

Page

•

Changed marketing status from Advance Information to initial release. ............................................................1

Changed device functional modes table...........................................................................................................19

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5 Pin Configuration and Function

ANODE

V_CC

V_OUT

CATHODE

V_EE

Figure 5-1. UCC23513 , UCC23513B Package SO-6 Top View

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

ANODE

CATHODE

NO.

Anode

Cathode

No Connection

V_CC

Positive output supply rail

Negative output supply rail

Gate-drive output

V_EE

V_OUT

(1) P = Power, G = Ground, I = Input, O = Output

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Average Input Current

Peak Transient Input Current

Reverse Input Voltage

Output supply voltage

Output signal voltage

Junction temperature

Storage temperature

I_F(AVG)

I_F(TRAN)<1us pulse, 300pps

V_R(MAX)

V_CC– V_EE

-0.3

V_OUT– V_CC

V_OUT– V_EE

0.3

-0.3

-40

-65

(2)

T_J

150

°C

T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) To maintain the recommended operating conditions for T_J, see the Section 6.4.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS–001⁽¹⁾

±4000

Electrostatic

discharge

V_(ESD)

Charged device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX UNIT

UCC23513

(12-V UVLO Version)

V_CC

Output Supply Voltage (V_CC– V_EE)

UCC23513B

(8-V UVLO Version)

I_F(ON)

V_F(OFF)

T_J

Input Diode Forward Current (Diode "ON")

Anode voltage - Cathode voltage (Diode "OFF")

Junction temperature

-13

-40

0.9

150

125

°C

T_A

Ambient temperature

6.4 Thermal Information

UCC23513, UCC23513B

THERMAL METRIC⁽¹⁾

SO6

6 Pins

126

UNIT

R_θJA

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

66.1

62.8

29.6

60.8

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Ψ_JB

(1) For more information about traditional and new thermal metrics, see the http://www.ti.com/lit/SPRA953 application report.

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6.5 Power Ratings

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Maximum power dissipation on input and

output⁽¹⁾

P_D

750

V_CC= 20 V, I_F= 10mA 10-kHz, 50% duty

cycle, square wave,180-nF load, T_A=25^oC

P_D1

P_D2

Maximum input power dissipation⁽²⁾

Maximum output power dissipation

740

(1) Derate at 6 mW/°C beyond 25°C ambient temperature

(2) Recommended maximum P_D1= 40mW. Absolute maximum P_D1= 55mW

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6.6 Insulation Specifications

SPECIFIC

ATION

PARAMETER

TEST CONDITIONS

UNIT

CLR

CPG

External clearance⁽¹⁾

External Creepage⁽¹⁾

Shortest terminal-to-terminal distance through air >8.5

Shortest terminal-to-terminal distance across the

package surface

>8.5

DTI

CTI

Distance through the insulation

Comparative tracking index

Material Group

Minimum internal gap (internal clearance)

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

>17

>600

µm

Rated mains voltage ≤ 600 V_RMS

Rated mains voltage ≤ 1000 V_RMS

I-IV

I-III

Overvoltage category per IEC 60664-1

DIN V VDE 0884-11 (VDE V 0884-11)⁽²⁾

V_IORMMaximum repetitive peak isolation voltage

AC voltage (bipolar)

1500

1060

1500

8000

V_PK

V_RMS

V_DC

AC voltage (sine wave); time-dependent dielectric

breakdown (TDDB) test; see Figure 1

V_IOWM

Maximum isolation working voltage

DC voltage

V_TEST= V_IOTM, t = 60 sec (qualification)

V_TEST= 1.2 × V_IOTM, t = 1 s (100% production)

V_IOTM

V_IOSM

Maximum transient isolation voltage

Maximum surge isolation voltage⁽³⁾

V_PK

Test method per IEC 62368, 1.2/50 ms waveform,

V_TEST= 1.6 x V_IOSM= 12800 V_PK(qualification)

8000

≤5

V_PK

Method a: After I/O safety test subgroup 2/3,V_ini

V_IOTM

t_ini= 60 s; V_pd(m)= 1.2 x V_IORM= 1800 V_PK, t_m

10 s

Method a: After environmental tests subgroup 1,

q_pd

Apparent charge⁽⁴⁾

V_ini= V_IOTM, t_ini= 60 s; V_pd(m)= 1.6 x V_IORM

2400 V_PK, t_m= 10 s

≤5

Method b1: At routine test (100% production) and

preconditioning (type test), V_ini= V_IOTM, t_ini= 1 s; ≤5

V_pd(m)= 1.875 x V_IORM= 2813 V_PK, t_m= 1 s

C_IO

R_IO

Barrier capacitance, input to output⁽⁵⁾

Insulation resistance, input to output⁽⁵⁾

V_IO= 0.4 x sin (2πft), f = 1 MHz

V_IO= 500 V, T_A= 25°C

0.5

>10¹²

>10¹¹

>10⁹

V_IO= 500 V, 100°C ≤ T_A≤ 125°C

V_IO= 500 V at T_S= 150°C

Pollution degree

Climatic category

40/125/21

UL 1577

V_TEST= V_ISO= 5700 V_RMS, t = 60 s (qualification),

V_TEST= 1.2 x V_ISO= 6840 V_RMS, t = 1 s (100%

production)

V_ISO

Withstand isolation voltage

5700

V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.

Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the

isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in

certain cases. Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these

specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured

by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-pin device.

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6.7 Safety-Related Certifications

VDE

CQC

Certified according to DIN V VDE V 0884-11: Certified according to UL 1577 Component

Certified according to GB4943.1-2011

2017-01

Recognition Program

Reinforced insulation Maximum transient

isolation voltage, 8000 V_PK

Maximum repetitive peak isolation voltage,

1500 V_PK

;

Reinforced insulation, Altitude ≤ 5000 m,

Tropical Climate

Single protection, 5700 V_RMS

File number: E181974⁽¹⁾

;

Maximum surge isolation voltage, 8000 V_PK

Certification number: 40040142⁽¹⁾

In progress

(1) UCC23513B certification in progress

6.8 Safety Limiting Values

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R_qJA= 126°C/W, V_I= 15 V, T_J= 150°C,

T_A= 25°C

I_S

Safety input, output, or supply current

R_qJA= 126°C/W, V_I= 30 V, T_J= 150°C,

T_A= 25°C

P_S

T_S

Safety input, output, or total power

Maximum safety temperature⁽¹⁾

R_qJA= 126°C/W, T_J= 150°C, T_A= 25°C

750

150

°C

(1) The maximum safety temperature, T_S, has the same value as the maximum junction temperature, T_J, specified for the device. The I_S

and P_Sparameters represent the safety current and safety power respectively. The maximum limits of I_Sand P_Sshould not be

exceeded. These limits vary with the ambient temperature, T_A. The junction-to-air thermal resistance, R_qJA, in the Thermal Information

table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value

for each parameter: T_J= T_A+ R_qJA´ P, where P is the power dissipated in the device. T_J(max)= T_S= T_A+ R_qJA´ P_S, where T_J(max)is

the maximum allowed junction temperature. P_S= I_S´ V_I, where VI is the maximum supply voltage.

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6.9 Electrical Characteristics

Unless otherwise noted, all typical values are at T_A= 25°C, V_CC–V_EE= 15V, V_EE= GND. All min and max

specifications are at recommended operating conditions (T_J= -40C to 150°C, I_F(on)= 7 mA to 16 mA, V_EE= GND,

V_CC= 15 V to 30 V, V_F(off)= –5V to 0.8V)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT

I_FLH

Input Forward Threshold Current Low to High V_OUT> 5 V, Cg = 1 nF

1.5

1.8

0.9

2.8

2.1

V_F

Input Forward Voltage

I_F=10 mA

2.4

V_{F_HL}

ΔV_F/ΔT

V_R

Threshold Input Voltage High to Low

Temp Coefficient of Input Forward Voltage

Input Reverse Breakdown Voltage

Input Capacitance

V < 5 V, Cg = 1 nF

I_F=10 mA

1.35 mV/°C

I_R= 10 uA

C_IN

F = 0.5 MHz

OUTPUT

I_F= 10 mA, V_CC=15V,

C_LOAD=0.18uF,

C_VDD=10uF, pulse

width <10us

I_OH

High Level Peak Output Current

4.5

5.3

V_F= 0 V, V_CC=15V,

C_LOAD=0.18uF,

C_VDD=10uF, pulse

width <10us

I_OL

Low Level Peak Output Current

High Level Output Voltage

3.5

I_F= 10 mA, I_O= -20mA

(with respect to VCC)

0.07

0.18

VCC

0.36

V_OH

I_F= 10 mA, I_O= 0 mA

V_F= 0 V, I_O= 20 mA

I_F= 10 mA, I_O= 0 mA

V_F= 0 V, I_O= 0 mA

V_OL

Low Level Output Voltage

2.2

I_{CC_H}

I_{CC_L}

Output Supply Current (Diode On)

Output Supply Current (Diode Off)

UNDER VOLTAGE LOCKOUT, UCC23513 (12-V UVLO Version)

UVLO_R

UVLO_F

Under Voltage Lockout VCC rising

Under Voltage Lockout VCC falling

V_{CC_Rising,}I_F=10 mA

V_{CC_Falling}, I_F=10 mA

12.5

11.5

1.0

13.5

12.5

UVLO_HYSUVLO Hysteresis

UNDER VOLTAGE LOCKOUT, UCC23513B (8-V UVLO Version)

UVLO_R

UVLO_F

Under Voltage Lockout VCC rising

Under Voltage Lockout VCC falling

V_{CC_Rising,}I_F=10 mA

V_{CC_Falling}, I_F=10 mA

7.8

8.5

7.75

0.75

9.2

7.05

8.45

UVLO_HYSUVLO Hysteresis

6.10 Switching Characteristics

Unless otherwise noted, all typical values are at T_A= 25°C, V_CC-V_EE= 30 V, V_EE= GND. All min and max

specifications are at recommended operating conditions (T_J= -40 to 150°C, I_F(ON)= 7 mA to 16 mA, V_EE= GND,

V_CC= 15 V to 30 V, V_F(OFF)= –5V to 0.8V)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_r

Output-signal Rise Time

Output-signal Fall Time

Propagation Delay, Low to High

Propagation Delay, High to Low

t_f

Cg = 1nF

F_SW= 20 kHz, (50% Duty Cycle)

VCC=15V

t_PLH

t_PHL

105

Pulse Width Distortion |t_PHL

t_PLH

–

t_PWD

Cg = 1nF

F_SW= 20 kHz, (50% Duty Cycle)

VCC=15V, I_F=10mA

Part-to-Part Skew in Propagation

Delay Between any Two Parts⁽¹⁾

t_sk(pp)

µs

t_{UVLO_rec}

UVLO Recovery Delay

V_CCRising from 0V to 15V

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Unless otherwise noted, all typical values are at T_A= 25°C, V_CC-V_EE= 30 V, V_EE= GND. All min and max

specifications are at recommended operating conditions (T_J= -40 to 150°C, I_F(ON)= 7 mA to 16 mA, V_EE= GND,

V_CC= 15 V to 30 V, V_F(OFF)= –5V to 0.8V)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Common-mode Transient

Immunity (Output High)

I_F= 10 mA, V_CM= 1500 V, V_CC= 30 V,

T_A= 25°C

CMTI_H

CMTI_L

150

kV/µs

Common-mode Transient

Immunity (Output Low)

V_F= 0 V, V_CM= 1500 V, V_CC= 30 V, T_A=

25°C

150

kV/µs

(1) t_sk(pp)is the magnitude of the difference in propagation delay times between the output of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads ensured by characterization.

6.11 Insulation Characteristics Curves

800

600

400

200

V_CC=15V

V_CC=30V

T_A(°C)

100

125

150

T_A(°C)

100

125

150

D014

D015

Figure 6-2. Thermal Derating Curve for Limiting

Power per VDE

Figure 6-1. Thermal Derating Curve for Limiting

Current per VDE

1.E+12

Safety Margin Zone: 1275 V_RMS, 412 Years

Operating Zone: 1060 V_RMS, 220 Years

1.E+11

87.5%

TDDB Line (<1 PPM Fail Rate)

412 Yrs

1.E+10

220 Yrs

1.E+09

1.E+08

1.E+07

VDE Safety Margin Zone

1.E+06

1.E+05

Operating Zone

1.E+04

20%

1.E+03

1.E+02 1060 V_RMS

1275 V_RMS

2200

1.E+01

200

1200

3200

4200

5200

6200

Applied Voltage (V_RMS

)

Figure 6-3. Reinforced Isolation Capacitor Life Time Projection

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6.12 Typical Characteristics

V_CC= 15 V, 1-µF capacitor from V_CCto V_EE, C_LOAD= 1 nF for timing tests and 180nF for I_OHand I_OLtests, T_J= –

40°C to +150°C, (unless otherwise noted)

1.5

1.45

1.4

6.6

6.3

ICC H

ICC L

IOH

IOL

1.35

1.3

5.7

5.4

5.1

4.8

4.5

4.2

3.9

3.6

3.3

1.25

1.2

1.15

1.1

1.05

0.95

-40 -20

80 100 120 140 160

-40 -20

80 100 120 140 160

Temp (èC)

D002

Temp (èC)

D001

Figure 6-5. Supply currents versus Temperature

C_LOAD= 180-nF

Figure 6-4. Output Drive currents versus

Temperature

1.4

3.5

3.4

3.3

3.2

3.1

ICC H

ICC L

1.3

1.2

1.1

2.9

2.8

2.7

2.6

-40 -20

80 100 120 140 160

15.5

20.5

23 25.5

V_CC(V)

30.5

33 35

Temp (èC)

D004

D003

Figure 6-7. Forward threshold current versus

Temperature

Figure 6-6. Supply current versus Supply Voltage

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t_PDLH

t_PDHL

t_PDLH

t_PDHL

-40 -20

80 100 120 140 160

I_F(mA)

Temp (èC)

D006

D005

C_LOAD= 1-nF

Figure 6-9. Propagation delay versus Forward

current

Figure 6-8. Propagation delay versus Temperature

0.9

0.85

0.8

300

280

260

240

220

200

180

160

140

120

0.75

0.7

0.65

0.6

0.55

0.5

0.45

-40 -20

80 100 120 140 160

-40 -20

80 100 120 140 160

Temp (èC)

D007

D008

I_OUT= 0mA

I_OUT= 20mA

(sourcing)

Figure 6-10. V_OH(No Load) versus Temperature

Figure 6-11. V_OH(20mA Load) versus Temperature

t_PLH

t_PHL

-40 -20

80 100 120 140 160

Temp (èC)

V_CC(V)

D009

D010

Figure 6-13. Propagation delay versus Supply

voltage

I_OUT= 20mA

(sinking)

Figure 6-12. V_OLversus Temperature

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2.8

2.6

2.4

2.2

2.1

1.9

1.8

1.7

1.6

1.8

1.6

1.4

1.2

10 12 14 16 18 20 22 24 25

I_F(mA)

80 100 120 140 160 180 200

Freq (KHz)

D012

D011

Figure 6-14. Supply current versus Frequency

T_A= 25°C

Figure 6-15. Forward current versus Forward

voltage drop

2.3

2.28

2.26

2.24

2.22

2.2

2.18

2.16

2.14

2.12

2.1

2.08

-40 -20

80 100 120 140 160

Temp (èC)

D013

I_F= 10mA

Figure 6-16. Forward Voltage Drop Versus Temperature

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7 Parameter Measurement Information

7.1 Propagation Delay, Rise Time and Fall Time

Figure 7-1 shows the propagation delay from the input forward current I_F, to V_OUT. This figures also shows the

circuit used to measure the rise (t_r) and fall (t_f) times and the propagation delays t_PDLHand t_PDHL

ANODE

V_CC

270Q

I_F

V_OUT

t_{PD_LH}

t_{PD_HL}

15V

1nF

80%

50%

20%

V_EE

CATHODE

V_OUT

t_r

t_f

Figure 7-1. I_Fto V_OUTPropagation Delay, Rise Time and Fall Time

7.2 I_OHand I_OLtesting

Figure 7-2 shows the circuit used to measure the output drive currents I_OHand I_OL. A load capacitance of 180nF

is used at the output. The peak dv/dt of the capacitor voltage is measured in order to determine the peak source

and sink currents of the gate driver.

ANODE

V_CC

270Q

I_F

V_OUT

I_OH

15V

I_OL

180nF

V_EE

CATHODE

Figure 7-2. I_OHand I_OL

7.3 CMTI Testing

Figure 7-3 is the simplified diagram of the CMTI testing. Common mode voltage is set to 1500V. The test is

performed with I_F= 6mA (VOUT= High) and I_F= 0mA (V_OUT= LOW). The diagram also shows the fail criteria for

both cases. During the application on the CMTI pulse with I_F= 6mA, if V_OUTdrops from VCC to ½VCC it is

considered as a failure. With I_F= 0mA, if V_OUTrises above 1V, it is considered as a failure.

e-diode off

V_CM

e-diode on

V_CM

ANODE

V_CC

150Q

1500V

I_F

V_OUT

30V

V_OUT

1nF

30V

15V

V_EE

CATHODE

Fail Threshold

V_OUT

V_CM=1500V

Figure 7-3. CMTI Test Circuit for UCC23513

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8 Detailed Description

8.1 Overview

UCC23513 is a single channel isolated gate driver, with an opto-compatible input stage, that can drive IGBTs,

MOSFETs and SiC FETs. It has 4A peak output current capability with max output driver supply voltage of 33V.

The inputs and the outputs are galvanically isolated. UCC23513 is offered in an industry standard 6 pin (SO6)

package with >8.5mm creepage and clearance. It has a working voltage of 1060-V_RMS, reinforced isolation rating

of 5.7-kV_RMSfor 60s and a surge rating of 8-kV_PK. It is pin-to-pin compatible with standard opto isolated gate

drivers. While standard opto isolated gate drivers use an LED as the input stage, UCC23513uses an emulated

diode (or "e-diode") as the input stage which does not use light emission to transmit signals across the isolation

barrier. The input stage is isolated from the driver stage by dual, series HV SiO₂capacitors in full differential

configuration that not only provides reinforced isolation but also offers best-in-class common mode transient

immunity of > 150 kV/us. The e-diode input stage along with capacitive isolation technology gives UCC23513

several performance advantages over standard opto isolated gate drivers. They are as follows:

1. Since the e-diode does not use light emission for its operation, the reliability and aging characteristics of

UCC23513 are naturally superior to those of standard opto isolated gate drivers.

2. Higher ambient operating temperature range of 125°C, compared to only 105°C for most opto isolated gate

drivers

3. The e-diode forward voltage drop has less part-to-part variation and smaller variation across temperature.

Hence, the operating point of the input stage is more stable and predictable across different parts and

operating temperature.

4. Higher common mode transient immunity than opto isolated gate drivers

5. Smaller propagation delay than opto isolated gate drivers

6. Due to superior process controls achievable in capacitive isolation compared to opto isolation, there is less

part-to-part skew in the prop delay, making the system design simpler and more robust

7. Smaller pulse width distortion than opto isolated gate drivers

The signal across the isolation has an on-off keying (OOK) modulation scheme to transmit the digital data across

a silicon dioxide based isolation barrier (see Figure 8-1). The transmitter sends a high-frequency carrier across

the barrier to represent one digital state and sends no signal to represent the other digital state. The receiver

demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. The

UCC23513 also incorporates advanced circuit techniques to maximize the CMTI performance and minimize the

radiated emissions from the high frequency carrier and IO buffer switching. Figure 8-2 shows conceptual detail of

how the OOK scheme works.

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8.2 Functional Block Diagram

Receiver

Transmitter

V_CC

I_F

Anode

UVLO

V_BIAS

R_NMOS

R_OH

V_EE

Level

Shift /

Pre

V_OUT

Amplifier

Oscillator

Demodulator

V_clamp

driver

R_OL

Cathode

V_EE

Figure 8-1. Conceptual Block Diagram of a Isolated Gate Driver with an Opto Emulated Input Stage (SO6

pkg)

I_FIN

Carrier signal

through isolation

barrier

RX OUT

Figure 8-2. On-Off Keying (OOK) Based Modulation Scheme

8.3 Feature Description

8.3.1 Power Supply

Since the input stage is an emulated diode, no power supply is needed at the input.

The output supply, V_CC, supports a voltage range from 14V to 33V. For operation with bipolar supplies, the

power device is turned off with a negative voltage on the gate with respect to the emitter or source. This

configuration prevents the power device from unintentionally turning on because of current induced from the

Miller effect. The typical values of the V_CCand V_EEoutput supplies for bipolar operation are 15V and -8V with

respect to GND for IGBTs, and 20V and -5V for SiC MOSFETs.

For operation with unipolar supply, the V_CCsupply is connected to 15V with respect to GND for IGBTs, and 20V

for SiC MOSFETs. The V_EEsupply is connected to 0V.

8.3.2 Input Stage

The input stage of UCC23513 is simply the e-diode and therefore has an Anode (Pin 1) and a Cathode (Pin 3).

Pin 2 has no internal connection and can be left open or connected to ground. The input stage does not have a

power and ground pin. When the e-diode is forward biased by applying a positive voltage to the Anode with

respect to the Cathode, a forward current I_Fflows into the e-diode. The forward voltage drop across the e-diode

is 2.1V (typ). An external resistor should be used to limit the forward current. The recommended range for the

forward current is 7mA to 16mA. When I_Fexceeds the threshold current I_FLH(2.8mA typ.) a high frequency signal

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is transmitted across the isolation barrier through the high voltage SiO₂capacitors. The HF signal is detected by

the receiver and V_OUTis driven high. See Section 9.2.2.1 for information on selecting the input resistor. The

dynamic impedance of the e-diode is very small(<1.0Ω) and the temperature coefficient of the e-diode forward

voltage drop is <1.35mV/°C. This leads to excellent stability of the forward current I_Facross all operating

conditions. If the Anode voltage drops below V_{F_HL}(0.9V), or reverse biased, the gate driver output is driven low.

The reverse breakdown voltage of the e-diode is >15V. So for normal operation, a reverse bias of up to 13V is

allowed. The large reverse breakdown voltage of the e-diode enables UCC23513 to be operated in interlock

architecture (see example in Figure 8-3) where V_SUPcan be as high as 12V. The system designer has the

flexibility to choose a 3.3V, 5.0V or up to 12V PWM signal source to drive the input stage of UCC23513 using an

appropriate input resistor. The example shows two gate drivers driving a set of IGBTs. The inputs of the gate

drivers are connected as shown and driven by two buffers that are controlled by the MCU. Interlock architecture

prevents both the e-diodes from being "ON" at the same time, preventing shoot through in the IGBTs. It also

ensures that if both PWM signals are erroneously stuck high (or low) simultaneously, both gate driver outputs will

be driven low.

V_SUP

ANODE

V_CC

HSON from MCU

GND

UVLO

To High Side

Gate

V_OUT

V_SUP

V_EE

CATHODE

LSON from MCU

GND

ANODE

V_CC

UVLO

To Low Side

Gate

V_OUT

CATHODE

V_EE

Figure 8-3. Interlock

8.3.3 Output Stage

The output stages of the UCC23513 family feature a pullup structure that delivers the highest peak-source

current when it is most needed which is during the Miller plateau region of the power-switch turnon transition

(when the power-switch drain or collector voltage experiences dV/dt). The output stage pullup structure features

a P-channel MOSFET and an additional pull-up N-channel MOSFET in parallel. The function of the N-channel

MOSFET is to provide a brief boost in the peak-sourcing current, enabling fast turnon. Fast turnon is

accomplished by briefly turning on the N-channel MOSFET during a narrow instant when the output is changing

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states from low to high. The on-resistance of this N-channel MOSFET (R_NMOS) is approximately 5.1 Ω when

activated.

Table 8-1. UCC23513 and UCC23513B On-Resistance

R_NMOS

R_OH

R_OL

UNIT

5.1

9.5

0.40

The R_OHparameter is a DC measurement and is representative of the on-resistance of the P-channel device

only. This parameter is only for the P-channel device because the pullup N-channel device is held in the OFF

state in DC condition and is turned on only for a brief instant when the output is changing states from low to high.

Therefore, the effective resistance of the UCC23513 pullup stage during this brief turnon phase is much lower

than what is represented by the R_OHparameter, yielding a faster turn on. The turnon-phase output resistance is

the parallel combination R_OH|| R_NMOS

The pulldown structure in the UCC23513 is simply composed of an N-channel MOSFET. The output voltage

swing between V_CCand V_EEprovides rail-to-rail operation because of the MOS-out stage which delivers very low

dropout.

V_CC

UVLO

R_NMOS

R_OH

V_EE

Level

Shift /

Pre

V_OUT

Demodulator

driver

R_OL

V_EE

Figure 8-4. Output Stage

8.3.4 Protection Features

8.3.4.1 Undervoltage Lockout (UVLO)

UVLO function is implemented for V_CCand V_EEpins to prevent an under-driven condition on IGBTs and

MOSFETs. When V_CCis lower than UVLO_Rat device start-up or lower than UVLO_Fafter start-up, the voltage-

supply UVLO feature holds the effected output low, regardless of the input forward current as shown in Table

8-2. The V_CCUVLO protection has a hysteresis feature (UVLO_hys). This hysteresis prevents chatter when the

power supply produces ground noise which allows the device to permit small drops in bias voltage, which occurs

when the device starts switching and operating current consumption increases suddenly.

When V_CCdrops below UVLO_F, a delay, t_{UVLO_rec}occurs on the output when the supply voltage rises above

UVLO_Ragain.

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10mA

I_F

V_CC

UVLO_R

UVLO_F

V_CC

t_{UVLO_rec}

V_OUT

Figure 8-5. UVLO functionality

8.3.4.2 Active Pulldown

The active pull-down function is used to pull the IGBT or MOSFET gate to the low state when no power is

connected to the V_CCsupply. This feature prevents false IGBT and MOSFET turn-on by clamping V_OUTpin to

approximately 2V.

When the output stage of the driver is in an unbiased condition (V_CCfloating), the driver outputs (see Figure 8-4)

are held low by an active clamp circuit that limits the voltage rise on the driver outputs. In this condition, the

upper PMOS & NMOS are held off while the lower NMOS gate is tied to the driver output through an internal

500-kΩ resistor. In this configuration, the lower NMOS device effectively clamps the output (V_OUT) to less than

2V.

8.3.4.3 Short-Circuit Clamping

The short-circuit clamping function is used to clamp voltages at the driver output and pull the output pin V_OUT

slightly higher than the V_CCvoltage during short-circuit conditions. The short-circuit clamping function helps

protect the IGBT or MOSFET gate from overvoltage breakdown or degradation. The short-circuit clamping

function is implemented by adding a diode connection between the dedicated pins and the V_CCpin inside the

driver. The internal diodes can conduct up to 500-mA current for a duration of 10 µs and a continuous current of

20 mA. Use external Schottky diodes to improve current conduction capability as needed.

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8.4 Device Functional Modes

Table 8-2 lists the functional modes for UCC23513

Table 8-2. Function Table for UCC23513 and UCC23513B with VCC Rising

e-diode

VCC

V_OUT

Low

High

OFF (I_F< I_FLH

)

0V - 33V

ON (I_F> I_FLH

)

0V - UVLO_R

UVLO_R- 33V

ON ( (I_F> I_FLH

)

Table 8-3. Function Table for UCC23513 and UCC23513B with VCC Falling

e-diode

VCC

V_OUT

OFF (I_F< I_FLH

)

0V - 33V

Low

High

ON (I_F> I_FLH

)

UVLO_F- 0V

33V - UVLO_F

ON ( (I_F> I_FLH

)

8.4.1 ESD Structure

Figure 8-6 shows the multiple diodes involved in the ESD protection components of the UCC23513 device . This

provides pictorial representation of the absolute maximum rating for the device.

V_CC

Anode

40V

20V

V_OUT

40V

2.5V

36V

Cathode

V_EE

Figure 8-6. ESD Structure

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

UCC23513 is asingle channel, isolated gate driver with opto-compatible input for power semiconductor devices,

such as MOSFETs, IGBTs, or SiC MOSFETs. It is intended for use in applications such as motor control,

industrial inverters, and switched-mode power supplies. It differs from standard opto isolated gate drivers as it

does not have an LED input stage. Instead of an LED, it has an emulated diode (e-diode). To turn the e-diode

"ON", a forward current in the range of 7mA to 16mA should be driven into the Anode. This will drive the gate

driver output High and turn on the power FET. Typically, MCU's are not capable of providing the required forward

current. Hence a buffer has to be used between the MCU and the input stage of UCC23513 . Typical buffer

power supplies are either 5V or 3.3V. A resistor is needed between the buffer and the input stage of the

UCC23513 to limit the current. It is simple, but important to choose the right value of resistance. The resistor

tolerance, buffer supply voltage tolerance and output impedance of the buffer, have to be considered in the

resistor selection. This will ensure that the e-diode forward current stays within the recommended range of 7mA

to 16mA. Detailed design recommendations are given in the Section 9.1. The current driven input stage offers

excellent noise immunity that is need in high power motor drive systems, especially in cases where the MCU

cannot be located close to the isolated gate driver. UCC23513 offers best in class CMTI performance of

>150kV/us at 1500V common mode voltages.

The e-diode is capable of 25mA continuous in the forward direction. The forward voltage drop of the e-diode has

a very tight part to part variation (1.8V min to 2.4V max). The temperature coefficient of the forward drop is

<1.35mV/°C. The dynamic impedance of the e-diode in the forward biased region is ~1Ω. All of these factors

contribute in excellent stability of the e-diode forward current. To turn the e-diode "OFF", the Anode - Cathode

voltage should be <0.8V, or I_Fshould be <I_FLH. The e-diode can also be reverse biased up to 13V (14V abs max)

in order to turn it off and bring the gate driver output low. The large reverse breakdown voltage of the input stage

provides system designers the flexibility to drive the input stage with 12V PWM signals without the need for an

additional clamping circuit on the Anode and Cathode pin.

The output power supply for UCC23513 can be as high as 33V (35V abs max). The output power supply can be

configured externally as a single isolated supply up to 33V or isolated bipolar supply such that V_CC-V_EEdoes not

exceed 33V, or it can be bootstrapped (with external diode & capacitor) if the system uses a single power supply

with respect to the power ground. Typical quiescent power supply current from V_CCis 1.2mA (max 2.2mA).

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9.2 Typical Application

The circuit in Figure 9-1, shows a typical application for driving IGBTs.

V_SUP

R_EXT/2

ANODE

I_F

V_CC

15V

V_OUT

R_GON

R_{G_int}

V_F

R_GOFF

V_EE

CATHODE

R_EXT/2

PWM

GND

Figure 9-1. Typical Application Circuit for UCC23513 and UCC23513B to Drive IGBT

9.2.1 Design Requirements

Table 9-1 lists the recommended conditions to observe the input and output of the UCC23513 gate driver.

Table 9-1. UCC23513 and UCC23513B Design Requirements

PARAMETER

VALUE

UNIT

V_CC

I_F

kHz

Switching frequency

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9.2.2 Detailed Design Procedure

9.2.2.1 Selecting the Input Resistor

The input resistor limits the current that flows into the e-diode when it is forward biased. The threshold current

I_FLHis 2.8 mA typ. The recommended operating range for the forward current is 7 mA to 16 mA (e-diode ON). All

the electrical specifications are guaranteed in this range. The resistor should be selected such that for typical

operating conditions, I_Fis 10 mA. Following are the list of factors that will affect the exact value of this current:

1. Supply Voltage V_SUPvariation

2. Manufacturer's tolerance for the resistor and variation due to temperature

3. e-diode forward voltage drop variation (at I_F=10 mA, V_F= typ 2.1 V, min 1.8 V, max 2.4 V, with a temperature

coefficient < 1.35 mV/°C and dynamic impedance < 1 Ω)

See Figure 9-2 for the schematic using a single NMOS and split resistor combination to drive the input stage of

UCC23513 . The input resistor can be selected using the equation shown.

V_SUP

R_EXT/2

ANODE

I_F

V_CC

V_OUT

V_F

V_EE

CATHODE

R_EXT/2

PWM

GND

V_SUPF V_F

R_EXT

F R_M1

I_F

Figure 9-2. Configuration 1: Driving the input stage of UCC23513 with a single NMOS and split resistors

Driving the input stage of UCC23513 using a single buffer is shown in Figure 9-3 and using 2 buffers is shown in

Figure 9-4

V_SUP

I_F

ANODE

V_CC

R_EXT/2

PWM (From MCU)

GND

V_F

V_EE

R_EXT/2

CATHODE

GND

V_SUPF V_F

R_EXT

F R_{OH_buf}

I_F

Figure 9-3. Configuration 2: Driving the input stage of UCC23513 with one Buffer and split resistors

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V_SUP

I_F

ANODE

V_CC

R_EXT/2

PWM (From MCU)

GND

V_F

V_SUP

V_EE

R_EXT/2

CATHODE

PWM (From MCU)

V_SUPF V_F

R_EXT

F (R_{OH_buf}+ R_{OL_buf})

I_F

Figure 9-4. Configuration 3: Driving the input stage of UCC23513 with 2 buffers and split resistors

Table 9-2 shows the range of values for R_EXTfor the 3 different configurations shown in Figure 9-2, Figure 9-3

and Figure 9-4.The assumptions used in deriving the range for R_EXTare as follows:

1. Target forward current I_Fis 7mA min, 10mA typ and 16mA max

2. e-diode forward voltage drop is 1.8V to 2.4V

3. V_SUP(Buffer supply voltage) is 5V with ±5% tolerance

4. Manufacturer's tolerance for R_EXTis 1%

5. NMOS resistance is 0.25Ω to 1.0Ω (for configuration 1)

6. R_OH(buffer output impedance in output "High" state) is 13Ω min, 18Ω typ and 22Ω max

7. R_OL(buffer output impedance in "Low" state) is 10Ω min, 14Ω typ and 17Ω max

Table 9-2. R_EXTValues to Drive The Input Stage

R_EXT

Configuration

Min

218

Typ

Max

331

Single NMOS and

R_EXT

290

Single Buffer and

R_EXT

204

194

272

259

311

294

Two Buffers and R_EXT

9.2.2.2 Gate Driver Output Resistor

The external gate-driver resistors, R_G(ON)and R_G(OFF)are used to:

1. Limit ringing caused by parasitic inductances and capacitances

2. Limit ringing caused by high voltage or high current switching dv/dt, di/dt, and body-diode reverse recovery

3. Fine-tune gate drive strength, specifically peak sink and source current to optimize the switching loss

4. Reduce electromagnetic interference (EMI)

The output stage has a pull up structure consisting of a P-channel MOSFET and an N-channel MOSFET in

parallel. The combined peak source current is 4.5 A Use Equation 1 to estimate the peak source current as an

example.

V_CCF V_GDF

I_OH= minH4.5A,

(R_NMOS||R_OH+ R_GON+ R_GFET

)

INT

(1)

where

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•

R_GONis the external turnon resistance.

R_{GFET_Int}is the power transistor internal gate resistance, found in the power transistor data sheet. We will

assume 0Ω for our example

•

I_OHis the peak source current which is the minimum value between 4.5A, the gate-driver peak source

current, and the calculated value based on the gate-drive loop resistance.

V_GDFis the forward voltage drop for each of the diodes in series with R_GONand R_GOFF. The diode drop for

this example is 0.7 V.

In this example, the peak source current is approximately 1.7A as calculated in Equation 1.

15 F 0.7

I_OH= minH4.5A,

I = 1.72A

(5.sÀ||9.wÀ + wÀ + rÀ)

(3)

(4)

Similarly, use Equation 1 to calculate the peak sink current.

V_CCF V_GDF

I_OL= minH5.3A,

(R_OL+ R_GOFF+ R_GFET

)

INT

where

•

R_GOFFis the external turnoff resistance.

I_OLis the peak sink current which is the minimum value between 5.3A, the gate-driver peak sink current, and

the calculated value based on the gate-drive loop resistance.

In this example, the peak sink current is the minimum of Equation 1 and 5.3A.

15 F 0.7

I_OL= minH5.3A,

I = 1.38A

(0.vÀ + srÀ + rÀ)

(6)

The diodes shown in series with each, R_GONand R_GOFF, in Figure 9-1 ensure the gate drive current flows

through the intended path, respectively, during turn-on and turn-off. Note that the diode forward drop will reduce

the voltage level at the gate of the power switch. To achieve rail-to-rail gate voltage levels, add a resistor from

the V_OUTpin to the power switch gate, with a resistance value approximately 20 times higher than R_GONand

R_GOFF. For the examples described in this section, a good choice is 100 Ω to 200 Ω.

Note

The estimated peak current is also influenced by PCB layout and load capacitance. Parasitic

inductance in the gate-driver loop can slow down the peak gate-drive current and introduce overshoot

and undershoot. Therefore, TI strongly recommends that the gate-driver loop should be minimized.

Conversely, the peak source and sink current is dominated by loop parasitics when the load

capacitance (C_ISS) of the power transistor is very small (typically less than 1 nF) because the rising

and falling time is too small and close to the parasitic ringing period.

9.2.2.3 Estimate Gate-Driver Power Loss

The total loss, P_G, in the gate-driver subsystem includes the power losses (P_GD) of the UCC23513 device and

the power losses in the peripheral circuitry, such as the external gate-drive resistor.

The P_GDvalue is the key power loss which determines the thermal safety-related limits of the UCC23513 device,

and it can be estimated by calculating losses from several components.

The first component is the static power loss, P_GDQ, which includes power dissipated in the input stage (P_{GDQ_IN}

as well as the quiescent power dissipated in the output stage (P_{GDQ_OUT}) when operating with a certain

switching frequency under no load. P_{GDQ_IN}is determined by I_Fand V_Fand is given by Equation 1. The

)

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P_{GDQ_OUT}parameter is measured on the bench with no load connected to V_OUTpin at a given V_CC, switching

frequency, and ambient temperature. In this example, V_CCis 15 V. The current on the power supply, with PWM

switching at 10 kHz, is measured to be I_CC= 1.33 mA . Therefore, use Equation 1 to calculate P_{GDQ_OUT}

P_{GDQ _IN}= Û V_F* I_F

(7)

(8)

P_{GDQ _OUT}= V_CC* I_CC

The total quiescent power (without any load capacitance) dissipated in the gate driver is given by the sum of

Equation 1 and Equation 1 as shown in Equation 1

P_GDQ= P_{GDQ _IN}+ P_{GDQ _OUT}= 10 mW + 20mW = 30mW

(9)

The second component is the switching operation loss, P_GDSW, with a given load capacitance which the driver

charges and discharges the load during each switching cycle. Use Equation 1 to calculate the total dynamic loss

from load switching, P_GSW

P_GSW= V_CC2ìQ_Gì f_SW

(10)

where

Q_Gis the gate charge of the power transistor at V_CC

•

So, for this example application the total dynamic loss from load switching is approximately 18 mW as calculated

in Equation 1.

P_GSW= 15 V ì120 nC ì10 kHz = 18 mW

(11)

Q_Grepresents the total gate charge of the power transistor switching 520 V at 50 A, and is subject to change

with different testing conditions. The UCC23513 gate-driver loss on the output stage, P_GDO, is part of P_GSW

P_GDOis equal to P_GSWif the external gate-driver resistance and power-transistor internal resistance are 0 Ω, and

all the gate driver-loss will be dissipated inside the UCC23513 . If an external turn-on and turn-off resistance

exists, the total loss is distributed between the gate driver pull-up/down resistance, external gate resistance, and

power-transistor internal resistance. Importantly, the pull-up/down resistance is a linear and fixed resistance if

the source/sink current is not saturated to 4.5A/5.3A, however, it will be non-linear if the source/sink current is

saturated. Therefore, P_GDOis different in these two scenarios.

Case 1 - Linear Pull-Up/Down Resistor:

R_OH||R_NMOS

R_OL

GSW

GDO

R_OH||R_NMOS+ R_GON+ R_{GFET_int}R_OL+ R_GOFF+ R_{GFET_int}

(12)

In this design example, all the predicted source and sink currents are less than 4.5 A and 5.3 A, therefore, use

Equation 1 to estimate the UCC23513 gate-driver loss.

18 mW

9.5À||5.1À

0.4À

GDO

I = 3.9 mW

9.5À||5.1À + 5.1À + 0À 0.4À + 10À + 0À

(13)

Case 2 - Nonlinear Pull-Up/Down Resistor:

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F_Sys

R_Sys

GDO

= f_swx f4.5A x

(V_CCF V_OUT(t))dt + 5.3A x

V_OUT(t) dtj

(14)

where

•

V_OUT(t)is the gate-driver OUT pin voltage during the turnon and turnoff period. In cases where the output is

saturated for some time, this value can be simplified as a constant-current source (4.5 A at turnon and 5.3 A

at turnoff) charging or discharging a load capacitor. Then, the V_OUT(t)waveform will be linear and the T_{R_Sys}

and T_{F_Sys}can be easily predicted.

For some scenarios, if only one of the pullup or pulldown circuits is saturated and another one is not, the P_GDOis

a combination of case 1 and case 2, and the equations can be easily identified for the pullup and pulldown

based on this discussion.

Use Equation 1 to calculate the total gate-driver loss dissipated in the UCC23513 gate driver, P_GD

P_GD= P_GDQ+ P_GDO= 30mW + 3.9mW = 33.9mW

(15)

(16)

9.2.2.4 Estimating Junction Temperature

Use Equation 1 to estimate the junction temperature (T_J) of UCC23513 .

T_J= T_C+ Y_JTìP_GD

where

•

T_Cis the UCC23513 case-top temperature measured with a thermocouple or some other instrument.

Ψ_JTis the junction-to-top characterization parameter from the table.

Using the junction-to-top characterization parameter (Ψ_JT) instead of the junction-to-case thermal resistance

(R_θJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal

energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the

total energy is released through the top of the case (where thermocouple measurements are usually conducted).

The R_θJCresistance can only be used effectively when most of the thermal energy is released through the case,

such as with metal packages or when a heat sink is applied to an IC package. In all other cases, use of R_θJCwill

inaccurately estimate the true junction temperature. The Ψ_JTparameter is experimentally derived by assuming

that the dominant energy leaving through the top of the IC will be similar in both the testing environment and the

application environment. As long as the recommended layout guidelines are observed, junction temperature

estimations can be made accurately to within a few degrees Celsius.

9.2.2.5 Selecting V_CCCapacitor

Bypass capacitors for V_CCis essential for achieving reliable performance. TI recommends choosing low-ESR

and low-ESL, surface-mount, multi-layer ceramic capacitors (MLCC) with sufficient voltage ratings, temperature

coefficients, and capacitance tolerances. A 50-V, 10-μF MLCC and a 50-V, 0.22-μF MLCC are selected for the

C_VCCcapacitor. If the bias power supply output is located a relatively long distance from the V_CCpin, a tantalum

or electrolytic capacitor with a value greater than 10 μF should be used in parallel with C_VCC

Note

DC bias on some MLCCs will impact the actual capacitance value. For example, a 25-V, 1-μF X7R

capacitor is measured to be only 500 nF when a DC bias of 15-V_DCis applied.

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10 Power Supply Recommendations

The recommended input supply voltage (V_CC) for the UCC23513 device is from 14V to 33V. The lower limit of

the range of output bias-supply voltage (V_CC) is determined by the internal UVLO protection feature of the

device. V_CCvoltage should not fall below the UVLO threshold for normal operation, or else the gate-driver

outputs can become clamped low for more than 20 μs by the UVLO protection feature. The higher limit of the

V_CCrange depends on the maximum gate voltage of the power device that is driven by the UCC23513 device,

and should not exceed the recommended maximum V_CCof 33 V. A local bypass capacitor should be placed

between the V_CCand V_EEpins, with a value of 220-nF to 10-μF for device biasing. TI recommends placing an

additional 100-nF capacitor in parallel with the device biasing capacitor for high frequency filtering. Both

capacitors should be positioned as close to the device as possible. Low-ESR, ceramic surface-mount capacitors

are recommended.

If only a single, primary-side power supply is available in an application, isolated power can be generated for the

secondary side with the help of a transformer driver such as Texas Instruments' SN6501 or SN6505A. For such

applications, detailed power supply design and transformer selection recommendations are available in SN6501

Transformer Driver for Isolated Power Supplies data sheet and SN6505A Low-Noise 1-A Transformer Drivers for

Isolated Power Supplies data sheet.

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11 Layout

11.1 Layout Guidelines

Designers must pay close attention to PCB layout to achieve optimum performance for the UCC23513 . Some

key guidelines are:

•

Component placement:

– Low-ESR and low-ESL capacitors must be connected close to the device between the V_CCand V_EEpins

to bypass noise and to support high peak currents when turning on the external power transistor.

– To avoid large negative transients on the V_EEpins connected to the switch node, the parasitic inductances

between the source of the top transistor and the source of the bottom transistor must be minimized.

Grounding considerations:

– Limiting the high peak currents that charge and discharge the transistor gates to a minimal physical area

is essential. This limitation decreases the loop inductance and minimizes noise on the gate terminals of

the transistors. The gate driver must be placed as close as possible to the transistors.

High-voltage considerations:

•

– To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces

or copper below the driver device. A PCB cutout or groove is recommended in order to prevent

contamination that may compromise the isolation performance.

Thermal considerations:

– A large amount of power may be dissipated by the UCC23513 if the driving voltage is high, the load is

heavy, or the switching frequency is high. Proper PCB layout can help dissipate heat from the device to

the PCB and minimize junction-to-board thermal impedance (θ_JB).

– Increasing the PCB copper connecting to the V_CCand V_EEpins is recommended, with priority on

maximizing the connection to V_EE. However, the previously mentioned high-voltage PCB considerations

must be maintained.

– If the system has multiple layers, TI also recommends connecting the V_CCand V_EEpins to internal ground

or power planes through multiple vias of adequate size. These vias should be located close to the IC pins

to maximize thermal conductivity. However, keep in mind that no traces or coppers from different high

voltage planes are overlapping.

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11.2 Layout Example

Figure 11-1 shows a PCB layout example with the signals and key components labeled.

A. No PCB traces or copper are located between the primary and secondary side, which ensures isolation performance.

Figure 11-1. Layout Example

Figure 11-2 and Figure 11-3 show the top and bottom layer traces and copper.

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Figure 11-2. Top-Layer Traces and Copper

Figure 11-3. Bottom-Layer Traces and Copper (Flipped)

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Figure 11-4 shows the 3D layout of the top view of the PCB.

A. The location of the PCB cutout between primary side and secondary sides ensures isolation performance.

Figure 11-4. 3-D PCB View

11.3 PCB Material

Use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternatives because of

lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the self-

extinguishing flammability-characteristics.

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

100

850

100

850

(1)

(2)

(3)

(4/5)

(6)

UCC23513BDWY

UCC23513BDWYR

UCC23513DWY

ACTIVE

SOIC

DWY

Green (RoHS

& no Sb/Br)

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

UC23513B

ACTIVE

DWY

Green (RoHS

& no Sb/Br)

NIPDAU

UC23513B

UCC23513

DWY

Green (RoHS

& no Sb/Br)

UCC23513DWYR

DWY

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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15-Aug-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

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24-Jul-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UCC23513DWYR

SOIC

DWY

850

330.0

16.4

12.05 5.08

4.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Jul-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC DWY

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

UCC23513DWYR

850

Pack Materials-Page 2

PACKAGE OUTLINE

SOIC -3.55 mm max height

SOIC

DWY0006A

11.75

11.25

SEATING PLANE

PIN 1 ID

AREA

0.1 C

6X 1.27

SYMM

2.54

4.78

4.58

0.51

0.28

SYMM

0.25

C A

3.55 MAX

7.60

7.40

0.304

0.204

SEE DETAIL

(3.18)

GAGE PLANE 0.25

ꢀꢁꢂ

0.30

0.10

1.00

0.50

DETAIL A

TYPICAL

4223977/A 01/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed

0.15 per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.70 per side.

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EXAMPLE BOARD LAYOUT

SOIC - 3.55 mm max height

SOIC

DWY0006A

SYMM

6X(1.905)

SEE DETAILS

SYMM

6X(0.76)

6X(1.27)

(10.75)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MAX

ALL AROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDER MASK DETAAILS

4223977/A 01/2018

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

SOIC - 3.55 mm max height

SOIC

DWY0006A

SYMM

6X(1.905)

SEE DETAILS

SYMM

6X(0.76)

6X(1.27)

(10.75)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 6X

4223977/A 01/2018

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

UCC23513DWY [TI]

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