UCC24624DT [TI]
用于 LLC 转换器的高频双路同步整流器控制器 | D | 8 | -40 to 125;
| 型号： | UCC24624DT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于 LLC 转换器的高频双路同步整流器控制器 | D | 8 | -40 to 125 控制器 开关 光电二极管 转换器 |
| 文件： | 总38页 (文件大小：2192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
适用于LLC 谐振转换器的UCC24624 双通道同步整流器控制器
1 特性
3 说明
• 230V VD 引脚额定值
• 23ns 关断延迟，支持LLC 运行频率高于谐振频率
并支持高达625kHz 的开关频率
UCC24624 高性能同步整流器 (SR) 控制器专用于 LLC
谐振转换器，以便使用 SR MOSFET 替代有损耗二极
管输出整流器并提高整体系统效率。
• 比例栅极驱动器，可延长SR 导通时间
• 可调节关断阈值，可最大限度地减小体二极管导通
时间
• 具有180µA 低待机电流的自动待机模式检测
• 具有内部钳位的4.25V 至26V 宽VDD 工作电压范
围
• 自适应导通延迟，可实现更佳的DCM 振铃抑制
• 双通道互锁，可防止击穿
• 适用于N 沟道MOSFET、具有1.5A 拉电流和4A
灌电流能力的集成式栅极驱动器
UCC24624 SR 控制器使用漏源极电压检测方法来实现
对 SR MOSFET 的开关控制。实现了比例栅极驱动
器，以延长SR 导通时间并最大限度地缩短体二极管导
通时间。为了补偿由 SR MOSFET 寄生电感导致的偏
移电压，UCC24624 实现了可调节正向关断阈值，以
适应不同的 SR MOSFET 封装。UCC24624 具有内置
的 475ns 导通时间消隐和固定的 650ns 关断时间消隐
功能，以避免 SR 错误导通和关断。UCC24624 还集
成了双通道互锁功能，可防止两个 SR 同时导通。该器
件具有 230V 电压检测引脚和 28V 绝对最大 VDD 额定
值，可直接用于输出电压高达 24.75V 的转换器。内部
钳位允许控制器通过在 VDD 上添加外部电流限制电阻
器来轻松支持36V 输出电压。
• 8 引脚SOIC 封装
2 应用
• 台式计算机、一体式计算机、ATX 和服务器电源
• 交流/直流适配器
器件信息
• LCD、LED 和OLED 电视
封装尺寸（标称值）
器件型号
UCC24624
封装
SOIC (8)
• 工业交流/直流和隔离式直流/直流电源
• 电动工具充电器、LED 照明电源
• 使用UCC24624 并借助WEBENCH® Power
Designer 创建定制设计方案
4.90mm × 3.91mm
空白
Q1
Lr
Vout
Vin
Cr
Q2
UCC24624
S1
S2
VG1
VG2
VDD
VD2
VSS
PGND
REG
VD1
典型应用原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSD48
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
Table of Contents
8.1 Overview...................................................................10
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................20
9 Application and Implementation..................................21
9.1 Application Information............................................. 21
9.2 Typical Application.................................................... 21
10 Power Supply Recommendations..............................25
11 Layout...........................................................................27
11.1 Layout Guidelines................................................... 27
11.2 Layout Example...................................................... 27
12 Device and Documentation Support..........................29
12.1 Device Support....................................................... 29
12.2 Receiving Notification of Documentation Updates..29
12.3 Community Resources............................................29
12.4 Trademarks.............................................................29
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................2
6 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Timing Requirements..................................................7
7.7 Typical Characteristics................................................8
8 Detailed Description......................................................10
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (November 2018) to Revision C (March 2022)
Page
• REG pin description............................................................................................................................................3
• Power Management..........................................................................................................................................12
• Run Mode......................................................................................................................................................... 20
• Power Supply Recommendations.....................................................................................................................25
Changes from Revision A (July 2018) to Revision B (November 2018)
Page
• 初始发行版。...................................................................................................................................................... 1
5 说明（续）
通过基于平均开关频率的内置待机模式检测，UCC24624 可自动进入待机模式，无需使用外部组件。180µA 的低
待机模式电流可帮助满足现代空载功耗要求（如 CoC 和 DoE 规定）。UCC24624 可与 UCC25630x LLC 和
UCC28056 PFC 控制器搭配使用，以实现高效率，同时保持出色的轻载和空载性能。其他 PFC 控制器（如
UCC28064A、UCC28180 和 UCC28070）可用于实现更高的功率级别。1.5A 峰值拉电流和 4A 峰值灌电流驱动
能力使UCC24624 能够支持高达1kW 的LLC 转换器。
Copyright © 2022 Texas Instruments Incorporated
2
Submit Document Feedback
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
6 Pin Configuration and Functions
VG1
1
2
3
4
8
7
6
5
VG2
VDD
VD2
VSS
PGND
REG
VD1
图6-1. D Package 8-Pin SOIC Top View
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
VG1 is the controlled MOSFET gate drive for channel 1. Connect VG1 to the gate of the channel 1 SR
MOSFET through a small series resistor using short PCB traces to achieve optimal switching
performance. The VG1 output can achieve 1.5-A peak source current, and 4-A peak sink current
when connected to a large N-channel power MOSFET.
1
VG1
O
PGND is the power return pin of the UCC24624. The IC bias current and high peak current from the
gate drivers return to this pin. Short PCB traces and the ceramic bypass capacitor are required to
minimize the high slew rate current impacts to the IC operation. The PGND should be connected
directly to the SR MOSFET source pins.
2
PGND
-
REG is the internal linear regulator output and the device's internal bias pin. An internal linear
regulator from VDD to REG generates a well-regulated 11-V voltage. TI recommends putting a 2.2-
μF bypass capacitor from REG pin to PGND pin. Before REG pin reaches VREGON, one of the drain
3
4
REG
VD1
O
I
voltages (VD1 or VD2) must switch above VTHARM
.
VD1 is the channel 1 SR MOSFET drain voltage sensing input. Connect this pin to channel 1 SR
MOSFET drain pin. The layout should avoid the VD1 pin trace sharing the power path to minimize the
impacts of parasitic inductance.
VSS is used to sense the voltage drop across the SR MOSFETs. Since both channels are sharing the
same VSS pin to sense the MOSFET voltage, special attention is required. The layout should avoid
the VSS pin trace sharing the power path to minimize the impacts of parasitic inductor. See 节11.2 for
more details. A resistor can be added between VSS pin and SR MOSFET source pins to adjust the
SR turn-off threshold if it is needed.
5
VSS
I
VD2 is the channel 2 SR MOSFET drain voltage sensing input. Connect this pin to channel 2 SR
MOSFET drain pin. The layout must avoid the VD2 pin trace sharing the power path to minimize the
impacts of parasitic inductance.
6
7
VD2
VDD
I
I
VDD is the internal linear regulator input. Connect this pin to the output voltage when the output
voltage is less than 24.75 V. When the output voltage is higher than 24.75 V, add a series resistor
between LLC output voltage and the VDD pin to limit the internal clamping circuit current.
VG2 is the controlled MOSFET gate drive for channel 2. Connect VG2 to the gate of the channel 2
MOSFET through a small series resistor using short PCB traces to achieve optimal switching
performance. The VG2 output can achieve 1.5-A peak source current and 4-A peak sink current when
connected to a large N-channel power MOSFET.
8
VG2
O
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.7
–2
MAX
28
UNIT
VDD(3)
V
V
V
V
V
Input voltage(1) VD1, VD2
230
230
VD1, VD2 for IVD1, IVD2 ≤–10 mA and less than 300 ns
VG1, VG2
Output voltage
REG
VREG+0.7
13.5
–0.3
Output current,
peak
VG1 or VG2(2) pulsed, tPULSE ≤4 ms, duty cycle ≤1%
±4
A
TJ
Junction temperature
Storage temperature
125
150
°C
°C
–40
–65
Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) In normal use, VG1 or VG2 is connected to the gate of a power MOSFET through a small resistor. When used this way, VG1 or
VG2current is limited by the UCC24624 and no absolute maximum output current considerations are required. The series resistor shall
beselected to minimize overshoot and ringing due to series inductance of the VG1 or VG2 output and power-MOSFET gate-drive
loop.Continuous VG1 or VG2 current is subject to the maximum operating junction temperature limitation.
(3) VDD is internally clamped at 27.5 V typical with 15 mA of sink current capability.
7.2 ESD Ratings
VALUE
±2000
±1000
UNIT
V
All pins except pins 4 and 6
Pins 4 and 6
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)
V
V(ESD) Electrostatic discharge
Charged device model (CDM), per
JEDEC specificationJESD22-
C101(2)
All pins
±500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2022 Texas Instruments Incorporated
4
Submit Document Feedback
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.25
0.1
NOM
MAX
UNIT
V
VVDD
CVDD
CREG
Supply voltage
26
VDD bypass capacitor
REG pin bypass capacitor
µF
µF
V
2.2
VVD1, VVD2 Voltage on sensing pins
200
625
125
–0.5
fSW
TJ
Switching frequency
Junction temperature
kHz
°C
-40
7.4 Thermal Information
DEVICE
THERMAL METRIC(1)
D (SOIC)
8 PINS
108.4
43.5
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
53.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.9
ΨJT
52.8
ΨJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
7.5 Electrical Characteristics
At VVDD = 12 VDC, CVG1 = CVG2 = 0 pF, CREG = 2.2 µF VVD1 = VVD2 = 0 V, –40°C ≤TJ = TA ≤+125°C, all voltages are with
respect to PGND, and currents are positive into and negative out of the specified terminal, unless otherwise noted. Typical
values are at TJ = +25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BIAS SUPPLY
IVDDSTART
VDD current, REG under voltage
VDD current, run
VVDD = 4 V, VVD1 = VVD2 = 0 V
VVDD = 12 V
5
0.77
0.7
150
1.1
1
275
1.5
µA
mA
mA
µA
µA
V
IVDDRUN
VVDD = 5 V
1.5
110
180
180
27.5
200
200
29.5
VVDD = 12 V, 25℃
VVDD = 5 V, 25℃
IVDD = 15 mA
IVDDSTBY
VDDCLAMP
VDD current, standby mode
VDD clamp voltage
100
24.75
UNDER VOLTAGE LOCKOUT (UVLO)
VREGON
REG turn-on threshold
REG turn-off threshold
REG UVLO hysteresis
4.1
3.63
4.5
4
4.8
4.25
V
V
V
VREGOFF
VREGHYST
0.450
0.500
0.555
VREGHYST = VREGON –VREGOFF
MOSFET VOLTAGE SENSING
VTHVGON
VTHVGOFF
SR turn-on threshold
SR turn-off threshold
VVD1, or VVD2 falling
VVD1, or VVD2 rising
mV
mV
–435
–265
–160
2
10.5
18
VSS pin offset current for turn-off
threshold adjustment
IVS_OFFSET
260
330
400
0
µA
VTHPGD_LO
VTHPGD_HI
VTHARM
Low-level regulation threshold
High-level regulation threshold
SR turn-on re-arming threshold
Bias current on VD1 or VD2
mV
mV
V
–80
–165
1.4
–35
–100
1.5
–40
1.7
IVDBIAS
GATE DRIVER
RVG_PU
VVD1 = VVD2 = -150 mV
0
0.5
µA
–10
VG pull-up resistance
VG pull-down resistance
VG high clamp level
3.5
0.2
9.95
1
6.5
0.9
10.9
20
11.25
1.5
Ω
Ω
V
RVG_PD
VGHI
IVG = 0 mA
11.68
100
175
2.4
VGUV
VG output low voltage, VDD low bias VVDD = 4 V, IVG = 25 mA
mV
mV
A
VGLO
VG output low voltage
VVDD = 12 V, IVG = 100 mA
5
100
1.5
4
IVGSOURCE
IVGSINK
REG SUPPLY
VREG
VG maximum source current(1)
VG maximum sink current(1)
0.9
2.6
6.7
A
REG pin regulation level
Load regulation on REG
VVDD = 15 V, ILOAD_REG = 0 mA
9.9
9
11
25
11.9
75
V
VREGLG
VVDD = 15 V, ILOAD_REG = 0 mA to 30 mA
mV
V
VREGDO
IREGSC
REG drop out on passthrough mode VVDD = 5 V, ILOAD_REG = 0 mA to 10 mA
0.1
4.5
41
0.28
9.5
60
0.5
13
REG short circuit current
REG current limit
VVDD = 12 V, VREG = 0 V
VVDD = 12 V, VREG = 8 V
mA
mA
IREGLIM
95
(1) Ensured by design. Not production tested.
Copyright © 2022 Texas Instruments Incorporated
6
Submit Document Feedback
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
7.6 Timing Requirements
At VVDD = 12 VDC, CVG1 = CVG2 = 0 pF, CREG = 2.2 µF, VVD1 = VVD2 = 0 V, –40°C ≤TJ = TA ≤+125°C, all voltages are with
respect to PGND, and currents are positive into and negative out of the specified terminal, unless otherwise noted. Typical
values are at TJ = +25°C.
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
GATE DRIVER
SR turn-on propagation delay, for
both channels
VVD1, VVD2 moves from 4.7 V to -0.5 V in
5 ns
tdVGON
110
155
23
225
40
ns
ns
SR turn-off propagation delay, for
both channels
VVD1, VVD2 moves from -0.5 V to 4.7 V in
5 ns
tdVGOFF
5.5
13
trVG
tfVG
VVG1, VVG2 rise time
VVG1, VVG2 fall time
10% to 90%, VVDD = 12 V, CVG = 6.8 nF
90% to 10%, VVDD = 12 V, CVG = 6.8 nF
23
19
40
35
ns
ns
BLANKING TIME
tONMIN
On-time blanking
325
180
440
475
275
650
625
370
855
ns
ns
ns
tMGPU
Minimum gate pullup time
Off-time blanking
IVG1, IVG2 = 1.5 A
tOFFMIN
STANDBY
tSTBY_DET
Standby mode detection-time
5.5
7.5
9
10
ms
Average frequency entering standby
mode
fSLEEP
fWAKE
6.55
12.2
kHz
Average frequency coming out of
standby mode
11.5
15.6
21
kHz
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
7.7 Typical Characteristics
4.5
4.45
4.4
1.5
1.4
1.3
1.2
1.1
1
4.35
4.3
4.25
4.2
UVLO ON
UVLO OFF
4.15
4.1
0.9
0.8
0.7
0.6
0.5
4.05
4
5-V VDD
12-V VDD
3.95
3.9
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Junction Temperature (oC)
Junction Temperature (oC)
D001
D002
图7-1. UVLO Thresholds vs Temperature
CVG1 = CVG2 = 0 pF
VVD1= VVD2 = 1 V
图7-2. Bias Supply Current vs Temperature (No
Switching)
0
11.6
12-V VDD
5-V VDD
11.4
11.2
11
-50
-100
10.8
10.6
10.4
10.2
10
-150
-200
-250
-300
-350
-400
-450
-500
9.8
9.6
9.4
9.2
9
8.8
8.6
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Junction Temperature (oC)
Junction Temperature (oC)
D003
D004
图7-3. SR Turn-on Threshold Voltage vs
图7-4. SR Turn-off Threshold Voltages vs
Temperature
Temperature
11
10.95
10.9
-20
-22
-24
-26
-28
-30
-32
-34
-36
-38
-40
-42
-44
-46
-48
-50
10.85
10.8
10.75
10.7
10.65
10.6
ILOAD_REG = 0 mA
ILOAD_REG = 30 mA
10.55
10.5
-40
-20
0
20
40
60
80
100 120 140
Junction Temperature (oC)
D006
-40
-20
0
20
40
60
80
100 120 140
Junction Temperature (oC)
图7-6. REG Pin Voltage vs Temperature at
D005
Different Loading Conditions
图7-5. Proportional Gate Drive Threshold vs
Temperature
Copyright © 2022 Texas Instruments Incorporated
8
Submit Document Feedback
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
675
650
625
600
575
550
525
500
475
450
0.3
0.28
0.26
0.24
0.22
0.2
On-time Blanking
Off-time Blanking
0.18
0.16
0.14
-40
-40
-20
0
20
40
60
80
100 120 140
-20
0
20
40
60
80
100 120 140
Junction Temperature (oC)
Junction Temperature (oC)
D008
D007
图7-8. Blanking Time vs Temperature
ILOAD_REG = 10 mA
图7-7. REG Dropout in Pass-through Mode vs
Temperature
195
190
185
180
175
170
165
160
155
150
145
140
135
26
25.6
25.2
24.8
24.4
24
23.6
23.2
22.8
22.4
22
21.6
21.2
20.8
20.4
20
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Junction Temperature (oC)
Junction Temperature (oC)
D010
D009
图7-10. SR Turn-off Propagation Delay vs
图7-9. SR Turn-on Delay Time vs Temperature
Temperature
205
200
195
190
185
180
175
337.5
335
332.5
330
327.5
325
322.5
320
317.5
315
12-V VDD
5-V VDD
170
312.5
165
-40
-40
-20
0
20
40
60
80
100 120 140
-20
0
20
40
60
80
100 120 140
Junction Temperature (oC)
Junction Temperature (oC)
D012
D011
图7-12. VSS Pin Offset Current vs Temperature
图7-11. Standby Current vs Temperature
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
8 Detailed Description
8.1 Overview
The UCC24624 is a high performance synchronous rectifier (SR) controller for LLC resonant converter
applications. It integrates two channels of SR control into a single 8-pin SOIC package, minimizes the external
components, and simplifies PCB layout. The UCC24624 synchronous rectifier controller uses drain-to-source
voltage (VDS) sensing to determine the SR MOSFET conduction interval. The SR MOSFET is turned on when
its VDS falls below –265-mV turn-on threshold, and is turned off when VDS rises above the turn-off threshold
(the turn-off threshold is user programmable at 10.5 mV or greater). The SR conduction voltage drop is
continuously monitored and regulated to minimize the conduction loss and body diode conduction time. The
extremely fast turn-off comparator and driving circuit allows the fast turn off of SR MOSFETs, even when the LLC
converter operates above its resonant frequency. Fixed 475-ns minimum on-time blanking allows the controller
to support the SR operating at up to 625-kHz switching frequency. The 650-ns minimum off-time blanking makes
the IC more robust against the noise caused by the parasitic ringing. The two channels have interlock logic to
prevent shoot-through between the two SR MOSFETs. To minimize standby power, automatic standby mode
disables the gate pulses when the average switching frequency of the converter becomes lower than 9 kHz.
When the load increases such that the average switching frequency on channel 1 rises above 15.6 kHz, the
controller resumes normal SR operation. In standby mode, two channels are turned off and the gate-drive
outputs are actively held low. Other functionality are disabled during standby mode to minimize the IC current
consumption. The wide VDD range and gate driver clamp make the controller applicable for different output
voltage applications. With an internal voltage clamp on the VDD pin, the UCC24624 can be directly powered by
an output voltage higher than 24.75 V with a series resistor between VDD and the LLC converter output.
Copyright © 2022 Texas Instruments Incorporated
10
Submit Document Feedback
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
8.2 Functional Block Diagram
VDD
REG
START
11-V Linear
Regulator
REG
UVLO
POWER & FAULT
MANAGEMENT
STBY
27.5V
PROPORTIONAL
GATE DRIVE
CONTROL
GATE
DRIVER
VD1
VG1
Turn-on
comparator, CH1
œ
+
-265mV
SR2 ON
START
ARM1
Minimum
OFF time
(-35mV)
S
R
Q
Q
Prop-DRV
threshold
SR1 ON
Turn-off
comparator, CH1
PGND
+
œ
VTHOFF
FREQUENCY
DETECTION
ARM1
Minimum
ON time
SR1 ON
STBY
REG
+
ARM1
œ
1.5V
PROPORTIONAL
GATE DRIVE
CONTROL
GATE
DRIVER
VD2
VG2
Turn-on
comparator, CH2
œ
+
-265mV
SR1 ON
START
ARM2
Minimum
OFF time
(-35mV)
S
R
Q
Q
Prop-DRV
threshold
SR2 ON
Turn-off
comparator, CH2
VTHOFF
+
10.5 mV
œ
VTHOFF
VSS
ARM2
Minimum
ON time
330 µA
+
ARM2
œ
1.5V
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
11
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
8.3 Feature Description
8.3.1 Power Management
The UCC24624 synchronous-rectifier (SR) controller is powered from the REG pin through an internal linear
regulator between the VDD pin and the REG pin. This configuration allows for optimal design of the gate driver
stage to achieve fast driving speed, low driving loss and high noise immunity.
A typical application diagram of UCC24624 is shown in 图 8-1. In most cases, the UCC24624 can be directly
powered from the LLC resonant converter output (See 节8.4.3 for more details). Both SR MOSFETs are located
in the secondary side current return paths for easier voltage sensing, IC biasing, and gate driving.
Q1
Lr
Vout
Vin
Cr
Q2
UCC24624
S1
S2
1
2
3
4
8
7
6
5
VG1
VG2
VDD
VD2
VSS
PGND
REG
VD1
图8-1. UCC24624 Application Diagram in LLC Resonant Converter
During start-up, the output voltage rises from 0 V. With the rise of the output voltage, the internal linear regulator
operates in a pass-through mode, and the REG pin voltage rises together with the output voltage. The UVLO
function of UCC24624 monitors the voltage on REG pin instead of VDD pin. Before the REG pin voltage
increases above the UVLO on threshold (VREGON), UCC24624 consumes the minimum current of IVDDSTART
.
Once the REG pin voltage rises above the UVLO on threshold, the device starts to consume the full operating
current, including IVDDRUN and the gate driving currents, and controls the on and off of the SR MOSFETs.
When VDD voltage is above approximately 11 V, the internal linear regulator operates in the regulator mode. The
REG pin voltage is now well regulated to 11 V. This allows the optimal driving voltage for the SR MOSFET
without increasing the gate driver loss for typical power MOSFETs. The internal regulator is rated at 30 mA of
load regulation capability for higher switching frequency operation, or driving high SR MOSFET gate
capacitances. It is required to have sufficient bypass capacitance on the REG pin to ensure stable operation of
the linear regulator. A 2.2-μF X5R or better ceramic bypass capacitor is recommended.
When VDD voltage falls below 11 V, the internal linear regulator operates in the pass-through mode again.
Depending on the load current, the regulator has a voltage drop of approximately 0.2 V. The UCC24624
continues to operate during this mode until the REG pin voltage drops below the UVLO turn-off level (VREGOFF).
A basic timing diagram of the VDD and the REG pin voltages can be found in 图8-2.
Copyright © 2022 Texas Instruments Incorporated
12
Submit Document Feedback
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
VVDD
VREG
VREG
VVDD
VON
VOFF
t
t
SR Control Enable (internal signal)
图8-2. Timing diagram for VDD and REG
The UCC24624 VDD may be connected directly to the converter output when the output voltage is less than
VDDCLAMP minimum value of 24.75 V. However, for the applications where the output voltage is higher than that
level, including special conditions such as over voltage transients, the UCC24624 can still work with some
simple modification. To allow UCC24624 to operate with higher output voltages, UCC24624 is equipped with an
internal voltage clamp, at 27.5 V typical clamping voltage. Add a series resistor between the LLC converter
output voltage and the UCC24624 VDD pin, as shown in 图 8-3. This way the voltage on VDD is limited by the
internal clamp. The clamp current must be kept less than 15 mA. For example, at 36-V output, use a resistor
larger than 750 Ω. Because the gate drive voltage is only 11 V, this added resistor still allows enough voltage on
the gate drive to maintain the reliable operation of the SRs. Furthermore, the current consumption of the SR
controller is mainly caused by the SR MOSFET gate charge. The added resistor won't increase the power
consumption if the clamping circuit is not activated. Instead, it relocates some loss from the UCC24624 to the
resistor and improves the thermal handling of the UCC24624.
Q1
Lr
Vout
Vin
Cr
Q2
UCC24624
S1
S2
VG1
VG2
VDD
VD2
VSS
PGND
REG
VD1
图8-3. UCC24624 Configuration for an Output Voltage Higher Than 24.75 V
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
13
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
8.3.2 Synchronous Rectifier Control
The UCC24624 SR controller determines the conduction time of the SR-MOSFET by comparing the drain-to-
source voltage of the MOSFET against a turn-on threshold and a turn-off threshold. The gate driver output is
driven high when the VDS of the MOSFET becomes more negative than VTHVGON and is driven low when VDS
becomes more positive than VTHVGOFF as illustrated in 图8-4.
VDS
ISD
VTHVGOFF
t
VTHREG
VTHVGON
VGATE
90%
10%
tr_VG
t
tdVGON
图8-4. SR Operation Principle
Note that before SR MOSFET turns on, there is a small delay caused by the internal comparator delay and the
gate driver delay. During the delay time, the SR MOSFET body diode is conducting. For LLC resonant
converters, this delay is essential for appropriate operation. Due to the large junction capacitors of the SR
MOSFETs, the SR often sees a leading-edge current spike early in the conduction period, follow by the real
conduction current. Normally, a prolonged minimum on time can override this spike to make the circuit operate
normally. However, this causes large negative current that transfer the energy from the output to the input and
reduces the overall converter efficiency. In UCC24624, 155-ns turn-on delay is added, to help ignore the leading
edge spike.
When the SR MOSFET body diode is conducting, VD pin becomes negative relative to the VSS pin by the body
diode drop. The VD and VSS pins must be connected directly to the SR MOSFET pins to avoid any overlapping
of sensing paths to the power path and minimize the negative voltage and ringing caused by parasitic
inductance. Low package inductance MOSFETs, such as in SON package, are preferred to minimize this effect
as well.
Besides the simple comparator, UCC24624 also includes a proportional gate drive feature. For many SR
controllers, the SR MOSFET is turned on with the full driving voltage. In this way, the conduction loss can be
minimized. However, this method has a few major drawbacks. Because the turn-off threshold is a fixed value,
often to prevent negative current, the SR is turned off before the current reaches zero. This causes some SR
MOSFET body diode conduction time and increases the conduction loss. Another issue is associated with the
LLC converter operating above the resonant frequency. When the converter operates above the resonant
frequency, the SR current slope (di/dt) at turn-off could be as high as 150 A/μs. This high current slope could
cause negative current if the SR controller has long turn-off propagation delays. Furthermore, the time to
discharge the SR MOSFET gate voltage from its full driving voltage to its threshold level introduces another
delay. This further increases the negative current.
Copyright © 2022 Texas Instruments Incorporated
14
Submit Document Feedback
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
Instead of always keeping the SR MOSFET on with the full gate-drive voltage, UCC24624 reduces its gate-drive
voltage when the voltage drop across the SR MOSFET drain to source becomes more than –35 mV (less
negative, closer to zero when current approaching zero). During this time, UCC24624 reduces its gate drive
voltage from 11 V to close to the SR MOSFET's threshold voltage, and tries to regulate the SR MOSFET VDS
voltage to –35 mV (VTHPGD_LO). This brings two major benefits to the application: a) Preventing the SR
premature turn off, which causes extra loss associated with body diode conduction b) Shorter turn-off delay
since the SR MOSFET gate voltage is already reduced close to the MOSFET threshold voltage level and the SR
MOSFET can be turned off with virtually no delay.
The SR MOSFET is only driven high with its full driving capability of 1.5 A during the gate driver minimum pull-up
time tMGPU. After that, the SR MOSFET gate is kept high by a weak current source of approximately 200 µA.
Keep the resistor between the SR MOSFET gate and source larger than 100 kΩ to ensure the full driving
voltage and a minimized conduction loss.
Due to the sinusoidal current shape in the secondary side SR MOSFETs in an LLC resonant converter, the
proportional gate drive could start to reduce the SR gate voltage even at the current rising edge. This increases
the conduction loss and reduces the converter efficiency. In UCC24624, the proportional gate drive is disabled
during the first half of the SR conduction time, based on the previous cycle's SR conduction time. Therefore, the
gate drive voltage is only reduced during the SR current falling edge and this helps to maintain the low
conduction loss. The gate drive voltage is forced to reduce if the SR voltage drop does not reach the
proportional gate-drive threshold VTHPGD_LO within the 90% of the previous cycle on time. And the proportional
gate drive now tries to regulate the VDS to –100 mV (VTHPGD_HI). This further ensures the fast turn-off speed for
high di/dt conditions.
To prevent the SR MOSFET premature turn off caused by the large package inductance, an offset resistor can
be added between the VSS pin and the SR MOSFET source pins to further increase the turn off threshold. See
below section for the details of choosing the resistor value.
8.3.3 Turn-off Threshold Adjustment
When SR MOSFETs are implemented in LLC converters, they are often turned off too early, which creates long
body diode conduction times. This results in more power loss, lower efficiency, and higher thermal stress.
The SR MOSFET early turn off is caused by the parasitic inductance in the SR voltage sensing path. As
illustrated in 图 8-5, the VDS voltage sensed by the synchronous rectifier controller (VSENSE) is the combination
of the MOSFET on-state resistor voltage drop VSR, together with the voltage drops on parasitic inductors LD and
LS. A better layout approach can minimize these parasitic inductors. However, the minimum value it can achieve
is the package inductance of the SR MOSFET. With different packages, this parasitic inductance could vary from
2 to 10 nH.
VSENSE
-
+
VSR
LD
LS
ISR
SR
图8-5. SR Controller Sensed Voltage
The overall sensed voltage can be represented by 方程式1.
@+54
@P
:
;
8
5'05'
= Fd+54 × 4&5KJ + .& + .5 ×
h
(1)
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
15
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
Because of the sinusoidal current shape and high output current, the current slope (di/dt) creates a significant
voltage drop across the package inductance. This causes the SR controller to detect a smaller voltage drop and
turn off the SR MOSFET early.
To overcome this issue, UCC24624 implements several techniques.
First, the proportional gate drive feature is implemented. As discussed earlier, the proportional gate drive
reduces the SR MOSFET gate drive voltage when the SR current is small, and increases its voltage drop. This
increased voltage drop could overwhelm the offset voltage introduced by the package inductance. Thus the SR
MOSFET conduction time is extended.
Second, the turn-off threshold is set at 10.5 mV, instead of typically being set as a negative threshold. Because
of the high di/dt and unavoidable SR package inductance, positive voltage is always expected at zero SR
current. The positive turn-off threshold allows the SR MOSFET to continue conduction toward the end of the
intended conduction period without the concern of causing negative SR current because of anticipating the
positive offset voltage on the package inductances.
Last, UCC24624 also allows the user to further increase the turn-off threshold to accommodate higher parasitic
inductance MOSFET packages, such as TO-220 packages. As illustrated in 图 8-6, UCC24624 has an internal
current source that flows out of the VSS pin. By connecting a resistor from the VSS pin to the SR MOSFET
source, the voltage drop across the external resistor increases the turn-off threshold. This increased turn-off
threshold makes it more suitable for TO-220 packages. Less than 70-mV offset is recommended. When using
the low inductance MOSFET packages, such as SON5x6, the external resistor is not needed because the
proportional gate drive alone can take care of the offset caused by the smaller package inductance.
备注
To ensure normal system operation, VSS pin must never be kept open.
VD1,
VD2
Turn-off
comparator
+
VTHOFF
œ
SR
10.5 mV
Roffset
VSS
330 µA
UCC24624
图8-6. Adjustable Turn-off Threshold
The internal current source is at 330 µA and the external offset resistor value is recommended to be less than
212 Ω. The offset resistor Roffset can be calculated by using 方程式2 with the desired turn-off threshold VTHOFF
.
86*1(( F 10.5I8
4KBBOAP
=
330ä#
(2)
This added offset voltage only changes the SR turn-off threshold, while the proportional gate drive threshold
remains the same.
Copyright © 2022 Texas Instruments Incorporated
16
Submit Document Feedback
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
8.3.4 Noise Immunity
To ensure reliable SR operation and to avoid false turn-on and turn-off, features such as blanking time, adaptive
turn-on delay, and interlock logic are implemented. As illustrated in 图 8-7, the SR control is blanked by the on-
time blanking, off-time blanking and two-channel interlock logic.
VVD2
VTHARM
VVD2
VVD2
VVD2
ISD2
VTHVGOFF
VTHREG
t
VTHVGON
VVD1
VVD1
VTHARM
VTHARM
ISD1
ISD1
VTHVGOFF
VTHREG
VTHVGOFF
VTHREG
t
VTHVGON
VTHVGON
S1 Gate
S2 Gate
S1 Gate
t
t
t
t
S1 on-time
blanking
S2 on-time
blanking
S1 on-time
blanking
S1 off-time
blanking
S1 off-time
blanking
S2 off-time
blanking
S2 gate prohibited
by interlock
S1 gate prohibited
by interlock
S2 gate prohibited
by interlock
图8-7. Blanking Time and Interlock Logic in UCC24624
8.3.4.1 On-Time Blanking
Right after the SR MOSFET turn on, the SR is driven fully on. For the LLC resonant converter, the SR current
rises from zero. It is desired to keep the SR on during this situation and allow the current to rise to a high enough
level to maintain the full conduction time. In UCC24624, after the SR is turned on, a minimum on time blanking of
475 ns is implemented. During the on-time blanking time, the SR keeps conducting regardless of its drain to
source voltage. This on-time blanking limits the maximum switching frequency of the LLC converter to 625 kHz.
8.3.4.2 Off-Time Blanking
When the converter operates in burst mode, during the off period of the secondary side synchronous rectifiers,
there is large parasitic ringing (DCM ring) caused by the transformer magnetizing inductance and the switch
node capacitance. During the first few ringing cycles of the off period, there is a good chance that the SR
MOSFET drain voltage will resonate below the SR controller turn-on threshold. The SR MOSFET could be
falsely turned on at these instances, which could introduce extra power loss and EMI noise.
In UCC24624, a fixed 650-ns off-time blanking period is implemented. After the SR is turned off, and after its
drain voltage rises above 1.5 V, the SR won't turn on again for at least the off-time blanking time, regardless of
its drain to source voltage. Additional adaptive turn-on delay is also implemented to further enhance the noise
immunity capability during burst mode operation.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
17
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
8.3.4.3 Two-Channel Interlock
In LLC converters, the two SR MOSFETs are directly connected with the transformer secondary side. If for any
reason, both SRs turn on at the same time, the transformer secondary side is shorted. This could cause large
current and destructive component failures.
To prevent this shoot-through current of the two SR MOSFETs, UCC24624 include a two-channel interlock
mechanism. The turn-on of one SR MOSFET, prevents the turn-on of the other SR MOSFET, as illustrated in 图
8-7.
8.3.4.4 SR Turn-on Re-arm
After been turned off in each switching cycle, the VG1 and VG2 outputs may only turn on again when the
controller has been armed for the new switching cycle. The controller is armed for each successive SR cycle
only at off-time blanking TOFFMIN expiring after the VD pin voltage rises 1.5 V above the VSS pin.
8.3.4.5 Adaptive Turn-on Delay
To further enhance noise immunity of the SR controller, UCC24624 implements an adaptive turn-on delay.
During most operating conditions, 155-ns of turn-on delay is applied to both channel's turn-on stage. However, at
a lighter load, or during burst off period, this turn-on delay is increased to further enhance the noise immunity
and allow the controller to reject the leading edge current spike and DCM ring. In these conditions, the turn-on
delay is increased to 275 ns. The turn-on delay increasing can be observed in below conditions.
• Burst mode operation. During LLC normal operation, two SR MOSFETs are turned on and off alternatively, in
a complementary fashion. However, during burst operation, after one SR MOSFET turns off, the other SR
MOSFET stays off. This gives the indication of the LLC converter entering the burst-mode operation. In
UCC24624, after one channel SR is turned off, its turn-on delay for the next turn-on is increased to 275 ns,
for improved DCM ring rejection capability. If the other channel SR is turned on after this channel SR turning
off, the LLC is still in normal operating mode. The turn-on delay is reset to the 155-ns value. Otherwise,
UCC24624 detects the LLC entering burst-mode operation and the SR turn-on delay stays at 275 ns to help
reject the DCM ring. This adaptive turn-on delay allows long turn-on delay during burst mode operation, with
shorter delay during normal operation to minimize the conduction loss.
• Short SR conduction time. At light load, the SR current could start with a short leading edge spike of positive
current, followed by the negative current, and then the full positive current, as shown in 图8-8. This is caused
by the SR parasitic capacitance and the LLC resonant behavior. When the negative current appears, the SR
is turned off with minimum on time (on-time blanking). This is the indication that the leading edge current
spike causes abnormal operation. Once the short SR conduction time is detected, the IC sets the turn-on
delay to 275 ns. This long turn-on delay can further help to reject the leading edge current spike. It also helps
to provide better DCM ring rejection during burst mode operation, since the burst mode operation only
happens at light load. This increased turn-on delay time is reset when the SR voltage drop is more than 40
mV (VDS more negative than -40 mV) at the middle of its conduction time for 8 consecutive cycles.
Copyright © 2022 Texas Instruments Incorporated
18
Submit Document Feedback
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
SR
current
0
SR
gate
0
Ton_min
图8-8. SR current with leading edge spike
To avoid the DCM ring turn on and SR leading edge current spike, an extra resistor can be added between the
SR MOSFET drain and UCC24624 VD pins, as shown in 图 8-9. The extra resistor helps to further improve the
noise immunity. Furthermore, this resistor also limits the negative current flowing into the VD pins, during SR
body diode conduction time. A resistor value around 1 kΩis recommended if this resistor is needed.
UCC24624
1k
VG1
VG2
VDD
VD2
VSS
PGND
REG
VD1
1k
图8-9. UCC24624 configuration with VD resistors
8.3.5 Gate Voltage Clamping
With the wide VDD voltage range capability, UCC24624 clamps the gate driver voltage to a maximum level of 11
V to allow fast driving speed, low driving loss, and compatibility with different MOSFETs. The 11-V level is
chosen to minimize the conduction loss for non-logic level MOSFETs. The gate-driver voltage clamp is achieved
through the regulated REG pin voltage. When the VDD voltage is above 11 V, the linear regulator regulates the
REG pin voltage to 11 V, which is also the power supply of the gate driver stage. This way, the MOSFET gate is
well clamped at 11 V, regardless of how high the VDD voltage is. When the VDD voltage is getting close to or
below the programmed REG pin regulation voltage, UCC24624 can no longer regulate the REG pin voltage.
Instead, it enters a pass-through mode where the REG pin voltage follows the VDD pin voltage minus a smaller
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
19
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
linear regulator dropout voltage. During this time, the gate driver voltage is lower than its programmed value but
still provides the SR driving capability. The UCC24624 is disabled once the REG pin voltage drops below its
UVLO OFF level VREGOFF
.
8.3.6 Standby Mode
With stringent efficiency standards such as Department of Energy (DoE) level VI and Code of Conduct (CoC)
version 5 tier 2, external power supplies are expected to maintain a very low standby power at no load
conditions. It is essential for the SR controller to enter the low power standby mode to help reduce the no load
power consumption.
During standby mode, the power converter loss allocation is quite different compared with heavy load. At heavier
load, both conduction loss and switching loss are quite high. However, at light load, the conduction loss
becomes insignificant and switching loss dominates the total loss. To help improve the standby power, modern
power supply controllers often enter burst mode to save the switching loss. Furthermore, in each burst switching
cycle, the energy delivered is maximized to minimize the number of switching cycles needed and further reduces
the switching loss.
Traditionally, the SR controller monitors the SR conduction time to distinguish the normal operation mode or the
standby mode. Because of the burst mode operation, the converter is equivalently operating at a much higher
power level with long SR conduction time. This criterion is no longer suitable for the modern power supply
controller designed for delivering minimum standby power.
Instead, in UCC24624, a frequency based standby mode detection is used. UCC24624 continuously monitors
the average switching frequency of SR channel 1. Once the average switching frequency of channel 1 SR
MOSFET drops below 9 kHz for 7.5 ms, the UCC24624 enters the standby mode, stops SR MOSFETs
switching, and reduces its current consumption to IVDDSTBY. During standby mode, the SR switching cycle is
continuously monitored through the body diode conduction. Once the average switching frequency is more than
15.6 kHz within 7.5 ms, the SR MOSFET operation is enabled again. UCC24624 ignores the first SR switching
cycle after coming out of standby mode to make sure the SR isn't turned on in the middle of the switching cycle.
8.4 Device Functional Modes
8.4.1 UVLO Mode
UCC24624 uses the REG pin voltage to detect UVLO instead of the VDD pin voltage. When the REG voltage
has not yet reached the VREGON threshold, or has fallen below the UVLO threshold VREGOFF, the device
operates in the low-power UVLO mode. In this mode, most internal functions are disabled and VDD current is
IVDDSTART. If the REG pin is above 2 V, there is an active pull down from VG1 and VG2 to PGND to prevent the
SR from falsely turning on due to noise. When the REG pin voltage is less than 2 V, there is a weak pull down
from VG1 and VG2 to PGND and this also prevents noise from turning on SR MOSFETs. The device exits UVLO
mode when REG increases above the VREGON threshold.
8.4.2 Standby Mode
Standby mode is a low-power operating mode to help achieve low standby power for the entire power supply.
UCC24624 detects the average operation frequency of channel 1 SR MOSFET and enters or exits the standby
mode operation automatically. VDD current reduces to IVDDSTBY level. During standby mode, the majority of the
SR control functions are disabled, except the switching frequency monitoring and the active pull down on the
gate drivers.
8.4.3 Run Mode
Run mode is the normal operating mode of the controller, when not in UVLO mode, or standby mode. In this
mode, VDD current is higher because all internal control and timing functions are operating and the VG1 and
VG2 outputs are driving the MOSFETs for synchronous rectification. VDD current is the sum of IVDDRUN plus the
average current necessary to drive the load on the VG1 and VG2 outputs. The VG1 and VG2 voltages are
automatically adjusted based on the SR MOSFET drain-to-source voltages. Before REG pin voltage reaches
VREGON threshold, one of the drain-to-source voltages (VD1 or VD2) must switch above VTHARM for proper
switching of VG1 and VG2 outputs. This can be easily achieved by powering up the VDD from the output of the
LLC or switching the LLC first before REG pin voltage reaches VREGON threshold.
Copyright © 2022 Texas Instruments Incorporated
20
Submit Document Feedback
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
UCC24624 is a high performance synchronous rectifier controller used to replace output diode rectifiers in an
LLC converter with synchronous rectifier (SR) MOSFETs. The SR-MOSFETs can achieve very low conduction
loss compared to that of diode rectifiers, significantly improving the efficiency and thermal performance of the
converter.
9.2 Typical Application
The UCC24624EVM-015 was used to replace rectifier diodes in a 120-W LLC converter using the UCC256302
LLC controller. The power converter had an input voltage (VIN) range of 340 V to 410 V with a typical input of
390 V, with a regulated 12-V output. More details about this power stage can be found in UCC256301 LLC
Evaluation Module. More information regarding designing PFC and LLC stages can be found on these training
topics (LLC Design Principles and Optimization for Transient Response, A new way to PFC and an even better
way to LLC, and PFC for not dummies).
The schematic of the UCC24624EVM-15 is shown in 图9-1.
图9-1. Schematic of UCC24624EVM-15
The top and bottom view of UCC24624EVM-015 are shown in 图11-2 and 图11-3.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
21
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
9.2.1 Design Requirements
The overall system requirements are summarized in 表9-1.
表9-1. UCC24624EVM-015 LLC Power Stage Specifications
PARAMETER
INPUT CHARACTERISTICS
DC voltage range
TEST CONDITION
MIN
TYP
390
12
MAX
UNITS
340
410
VDC
OUTPUT CHARACTERISTICS
Output Voltage
No load to full load = 10 A
340-V to 41-V VDC
VDC
A
Output Current
10
SYSTEM CHARACTERISTICS
Switching frequency
Peak efficiency
53
160
kHz
390 VDC, load = 10 A
96.5%
9.2.2 Detailed Design Procedure
9.2.2.1 MOSFET Selection
In this UCC256302-based LLC resonant converter, the transformer secondary side is a center-tap structure. The
SR MOSFET voltage stress, without considering the ringing voltages, must be twice of the output voltage. Given
the 12-V output, this determines the SR steady state voltage stress of 24 V. However, due to the switching
noises at MOSFET turn off, there is always extra voltage stress. To ensure enough design margin, 60-V rating
MOSFETs were selected.
The selection of the MOSFET on-state resistance is the trade-off among performance at full load, light load, as
well as cost. The lower on-state resistance gives lower conduction loss at heavy load while increases the
switching loss at lighter load. It is also higher cost. Generally, the on-state resistance must be selected so that
the 35-mV proportional gate drive threshold doesn't get activated until last 25% of the overall conduction time.
The SR MOSFET on-state resistance can be selected as 方程式 3. A 2.5-mΩ MOSFET was selected as the
synchronous rectifier.
2 2 × 35I8
¾
4&5KJ
=
= 3.15I3
è × +KQP _I=T
(3)
9.2.2.2 Snubber Design
It may be required to adjust snubbing components C3, C4, R2 and R5 to dampen noise.
To adjust these components requires knowing the LLC transformers secondary leakage inductance (Lslk) and
measuring the secondary resonant ring frequency (fr) in circuit at minimal load of 10% or less. TI also
recommends that the SR is not engaged while doing this and capacitors C3 and C4 are removed from the
evaluation module. ConnectTP6 to ground to disable the gate driver.
The secondary winding capacitance (Cs) then needs to be calculated based on 方程式 4. Note that for a
transformer with a secondary winding leakage inductance of 3.8 µH and a ring frequency of 2 MHz, the parasitic
capacitance would be 1.7 nF.
1
1
%O =
=
= 1.7J(
(2 × è × B )2 × .OHG (2 × è × 2/*V)2 × 3.8ä*
N
(4)
Based on the calculated Cs, Lslk and fr the snubber resistors R2 and R5 can be set to critically dampen the
ringing on the secondary, which requires setting the Q of the circuit equal to 1.
Copyright © 2022 Texas Instruments Incorporated
22
Submit Document Feedback
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
1
.OHG 1 3.8ä*
¨
¨
42 = 45 =
=
N 47 3
3
%O
1 1.7J(
(5)
Capacitors C3 and C5 are used to limit the time the snubber resistor is applied to the aux winding during the
switching cycle. It is recommended to set the snubber capacitor C3 with 方程式 6 based on the LLC converters
minimum switching frequency (fSW). For an LLC converter with a minimum switching at 85 kHz in the example
would require a C3 and C4 would be roughly 497 pF.
0.01
0.01
%3 = %4 =
=
N 497L(
5 × BOS × 43 5 × 85G*V × 47.3×
(6)
Note that the calculations for R2, R5, C3, and C4 are just starting points and must be adjusted based on
individual preference, performance and efficiency requirements.
9.2.3 Application Curves
The typical operation waveforms, as well as the efficiency performance are summarized in following sections.
• CH1 = VG1(TP4), CH3 = Q1 drain (TP2), CH2 = VG2(TP5), CH4 = Q1 drain (TP3)
图9-2. VIN = 340 V, IOUT = 0 A, No Gate Drive Under 图9-3. VIN = 340 V, IOUT = 0.3 A, LLC is Operating In
Light Load (VG1, VG2)
Burst Mode
图9-4. VIN = 340 V, IOUT = 10 A Full Load
图9-5. VIN = 390 V, IOUT = 0 A, No Gate Drive Under
Light Load (VG1, VG2)
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
23
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
图9-6. VIN = 390 V, IOUT = 0.3 A, LLC is Operating In
图9-7. VIN = 390 V, IOUT = 10 A Full Load
Burst Mode
图9-8. VIN = 410 V, IOUT = 0 A, No Gate Drive Under 图9-9. VIN = 410 V, IOUT = 0.3 A, LLC is Operating In
Light Load (VG1, VG2)
Burst Mode
0.97
0.96
0.95
0.94
0.93
0.92
0.91
0
1
2
3
4
5
6
Load Current (A)
7
8
9
10
D007
图9-11. VIN = 390 V, Power Converter System
图9-10. VIN = 410 V, IOUT = 10 A Full Load
Efficiency Using SR FETs
Copyright © 2022 Texas Instruments Incorporated
24
Submit Document Feedback
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
10 Power Supply Recommendations
UCC24624 internal circuits are powered from REG pin only. There is an internal linear regulator between VDD
pin and REG pin to provide a well-regulated REG pin voltage when VDD voltage is above 11 V. This allows the
device to have better bypassing and better gate driver performance.
It is important to keep the sufficient bypass cap on REG pin. A minimum of 1-μF bypass capacitor is required.
When the gate charge current is higher than 5 mA, it is required to have at least 2.2-μF bypass capacitor on
REG pin.
VDD pin is the main power source of the device. Keep the voltage on VDD pin between 4.25 V and 26 V for
normal operation. Refer to 节 7.5 for the tolerances on the REG pin UVLO ON and OFF levels. It is
recommended to power up the VDD from the output of LLC as shown in 图 8-1. It will make sure one of the
drain-to-source voltages (VD1 or VD2) will switch above VTHARM before REG pin voltage reaches VREGON
threshold for the proper switching of VG1 and VG2. Other power up methods are also possible (图10-1).
For the applications where LLC output voltage is higher than 24.75 V, an external resistor between LLC output
voltage and UCC24624 can be used to allow internal clamp circuit keeping the VDD voltage below its
recommended maximum voltage rating, as shown in 图8-3. The series resistor can be calculated as in 方程式7.
In 方程式 7, VOUT(max) is the maximum output voltage of LLC converter, including its transient conditions,
VCLAMP(min) is the minimum clamping voltage considering tolerance, and ILIM is the maximum current allowed by
the clamping circuit of 15 mA.
:
;
8176 max F 8%.#/2 (min)
4.+/
=
15I#
(7)
After the resistor is inserted, calculate the minimum voltage on VDD to ensure sufficient voltage on VDD for the
SR driving. The voltage on VDD based on RLIM can be calculated as 方程式 8. The VDD voltage under this
condition must be higher than desired minimum SR driving voltage. In this equation, VOUT is the nominal output
voltage, RLIM is the current limiting resistor value. Qg is the SR gate charge for each SR MOSFET and fSW is the
maximum switching frequency of LLC converter.
8
8&&(min) = 8176 F4.+/ ×(2×3C ×B ++8&&470)
59
(8)
If the output voltage is higher than 36 V, or no suitable current limit resistor RLIM can be selected or incase, the
auxiliary winding can be used to power up the UCC24624. The circuit diagram of powering UCC24624 using
auxiliary winding is shown in 图 10-1. Other option would be to use a linear regulator to create bias power from
the output voltage directly. But this is a less efficient solution.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
25
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
Q1
Lr
Vout
Vin
Cr
Q2
UCC24624
S1
S2
VG1
VG2
VDD
VD2
VSS
PGND
REG
VD1
图10-1. Powering UCC24624 Using Auxiliary Winding
Copyright © 2022 Texas Instruments Incorporated
26
Submit Document Feedback
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
The printed circuit board (PCB) requires careful layout to minimize current loop areas and track lengths,
especially when using single-sided PCBs.
• Place a ceramic MLCC bypass capacitor as close as possible to REG and GND.
• Avoid connecting VD1 or VD2 and VSS sense points at locations where stray inductance is added to the SR
MOSFET package inductance, as this tends to turn off the SR prematurely.
• Run a trace from the VD1 or VD2 pin directly to the MOSFET drain pad to avoid sensing voltage across the
stray inductance in the SR drain current path.
• Run a trace from the VSS pin directly to the MOSFET source pad to avoid sensing voltage across the stray
inductance in the SR source current path. Because this trace shares both the gate driver path and the
MOSFET voltage sensing path, TI recommends making this trace as short as possible.
• Run parallel traces from VG1 or VG2 and PGND to the SR MOSFET. Include a series gate resistance to
dampen ringing if it is needed.
11.2 Layout Example
To LLC Transformer
SR2
SR1
RG1
CREG
1
2
3
4
8
RG2
7
6
UCC24624
Top Layer
Bottom Layer
Via
5
CVDD
图11-1. UCC24624 Layout Example
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
27
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
图11-2. UCC24624EVM-015 (Top View)
图11-3. UCC24624EVM-015 (Bottom View)
Copyright © 2022 Texas Instruments Incorporated
28
Submit Document Feedback
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the UCC24624 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
12.4 Trademarks
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
29
UCC24624
ZHCSIL2C –JULY 2018 –REVISED MARCH 2022
www.ti.com.cn
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
30
Submit Document Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC24624DR
UCC24624DT
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
U24624
U24624
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC24624DR
UCC24624DT
SOIC
SOIC
D
D
8
8
2500
250
330.0
180.0
12.4
12.4
6.4
6.4
5.2
5.2
2.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UCC24624DR
UCC24624DT
SOIC
SOIC
D
D
8
8
2500
250
356.0
210.0
356.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
UCC24630
同步整流Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC24630DBVR
具有超低待机电流的同步整流器控制器 | DBV | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC24630DBVT
具有超低待机电流的同步整流器控制器 | DBV | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC24636
具有超低待机电流的同步整流器控制器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC24636DBVR
具有超低待机电流的同步整流器控制器 | DBV | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC24636DBVT
具有超低待机电流的同步整流器控制器 | DBV | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC24650
用于快速瞬态初级侧调节的 200V 唤醒监控器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC24650DBVR
用于快速瞬态初级侧调节的 200V 唤醒监控器 | DBV | 5 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC24650DBVT
用于快速瞬态初级侧调节的 200V 唤醒监控器 | DBV | 5 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC25230
12-V to 100-V Input, 0.2-A Output Switching ConverterWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC25230DRMR
12-V to 100-V Input, 0.2-A Output Switching ConverterWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC25230DRMT
12-V to 100-V Input, 0.2-A Output Switching ConverterWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
©2020 ICPDF网 联系我们和版权申明