UCC27212A-Q1 [TI]
具有 5V UVLO 的汽车类 4A、120V 半桥栅极驱动器;
| 型号： | UCC27212A-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 5V UVLO 的汽车类 4A、120V 半桥栅极驱动器 栅极驱动 驱动器 |
| 文件： | 总30页 (文件大小：1724K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
UCC27212A-Q1
ZHCSGD6 –JULY 2017
UCC27212A-Q1 汽车120V 自举 4A 峰值电流高频高侧
和低侧驱动器
1 特性
3 说明
1
•
符合汽车应用 要求
具有符合 AECA-Q100 标准的下列特性：
UCC27212A-Q1 驱动器是基于常用的 UCC27211
MOSFET 驱动器设计的。此外，UCC27212A-Q1 具
有更宽的工作电压范围，可低至 5V，有助于降低功率
损耗。
•
–
–
–
器件温度等级 –40°C 至 +140°C
器件 HBM 分类等级 2
器件 CDM 分类等级 C6
峰值输出上拉和下拉电流分别为 4A 拉电流和 4A 灌电
流，而且上拉和下拉电阻均为 0.9Ω。这使得该器件能
够驱动大功率 MOSFET，减少由于 MOSFET 的米勒
平台导致的开关损耗。
•
•
5V 关断欠压锁定 (UVLO)
通过独立输入驱动高侧和低侧配置中的两个 N 沟道
MOSFET
•
•
•
•
最大引导电压 120V 直流
4A 拉电流，4A灌电流能力
0.9Ω 上拉和下拉电阻
输入结构可直接处理 -10V 电压，这提高了器件的鲁棒
性，并且无需使用整流二极管即可实现与栅极驱动变压
器直接连接。此外，输入还独立于电源电压，且具有
20V 的最大额定值。
输入引脚能够耐受 –10V 至 +20V 的电压，并且与
电源电压范围无关
•
•
•
TTL 兼容输入
UCC27212A-Q1 的开关节点（HS 引脚）最高可处理
-18V 电压，从而保护高侧通道不受寄生电感和杂散电
容所固有的负电压影响。UCC27212A-Q1 具有更高的
迟滞，因而支持连接至具有增强型抗噪性能的模拟或数
字 PWM 控制器。
5V 至 17V VDD 工作范围，（最大绝对值 20V）
7.2ns 上升时间和 5.5ns 下降时间（采用 1000pF
负载）
•
•
•
快速传播延迟时间（典型值 20ns）
4ns 典型延迟匹配
低侧和高侧栅极驱动器是独立控制的，且彼此的开通和
采用 SOIC8(Powerpad) 封装
关断时间均为 4ns。
2 应用
由于使用了一个额定电压为 100V 的片上自举二极管，
因此无需采用外部分立式二极管。高侧和低侧驱动器均
配有欠压锁定功能，可提供对称的开通和关断行为，并
且能够在驱动电压低于额定阈值时将输出强拉至低电
平。
•
•
•
•
•
•
汽车应用中的 电源
半桥和全桥转换器
高电压同步降压转换器
双开关正向转换器
推挽式和有源钳位正向转换器
D 类音频放大器
器件信息(1)
器件型号
封装
封装尺寸（标称值）
UCC27212A-Q1
SOIC8(Powerpad)
5.0mm x 6.0mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSCZ8
UCC27212A-Q1
ZHCSGD6 –JULY 2017
www.ti.com.cn
典型应用图
传播延迟与电源电压间的关系 (T = 25°C)
12 V
VDD
100 V
32
28
24
20
16
12
8
TDLRR
TDLFF
TDHRR
TDHFF
HB
SECONDARY
SIDE
CIRCUIT
HO
HS
LO
HI
DRIVE
HI
PWM
CONTROLLER
LI
DRIVE
LO
UCC27212-Q1
4
ISOLATION
AND
FEEDBACK
0
8
12
16
20
Supply Voltage (V)
D001
Copyright © 2017, Texas Instruments Incorporated
2
版权 © 2017, Texas Instruments Incorporated
UCC27212A-Q1
www.ti.com.cn
ZHCSGD6 –JULY 2017
目录
7.4 Device Functional Modes........................................ 16
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application ................................................. 17
Power Supply Recommendations...................... 21
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 4
Pin Configuration and Functions......................... 5
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings ............................................................ 6
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information.................................................. 7
6.5 Electrical Characteristics........................................... 7
6.6 Switching Characteristics.......................................... 8
6.7 Typical Characteristics............................................ 11
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 15
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 23
11 器件和文档支持 ..................................................... 24
11.1 文档支持 ............................................................... 24
11.2 接收文档更新通知 ................................................. 24
11.3 社区资源................................................................ 24
11.4 商标....................................................................... 24
11.5 静电放电警告......................................................... 24
11.6 Glossary................................................................ 24
12 机械、封装和可订购信息....................................... 24
7
版权 © 2017, Texas Instruments Incorporated
3
UCC27212A-Q1
ZHCSGD6 –JULY 2017
www.ti.com.cn
4 修订历史记录
日期
修订版本
说明
2017 年 7 月
*
初始发行版。
4
Copyright © 2017, Texas Instruments Incorporated
UCC27212A-Q1
www.ti.com.cn
ZHCSGD6 –JULY 2017
5 Pin Configuration and Functions
DDA Package
8-Pin SO-PowerPAD
Top View
VDD
HB
1
2
3
4
8
7
6
5
LO
VSS
LI
HO
HS
HI
Thermal pad
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is
required. Connect positive side of the bootstrap capacitor to this pin. Typical range of HB bypass
capacitor is 0.022 µF to 0.1 µF. The capacitor value is dependant on the gate charge of the high-
side MOSFET and must also be selected based on speed and ripple criteria.
2
HB
P
5
3
HI
I
High-side input.(1)
HO
O
High-side output. Connect to the gate of the high-side power MOSFET.
High-side source connection. Connect to source of high-side power MOSFET. Connect the
negative side of bootstrap capacitor to this pin.
4
HS
P
6
8
LI
I
Low-side input.(1)
LO
O
Low-side output. Connect to the gate of the low-side power MOSFET.
Positive supply to the lower-gate driver. De-couple this pin to VSS (GND). Typical decoupling
capacitor range is 0.22 µF to 4.7 µF (See (2)).
1
7
VDD
VSS
P
—
—
Negative supply terminal for the device that is generally grounded.
Thermal
pad(3)
Electrically referenced to VSS (GND). Connect to a large thermal mass trace or GND plane to
dramatically improve thermal performance.
Pad
(1) HI or LI input is assumed to connect to a low impedance source signal. The source output impedance is assumed less than 100 Ω. If the
source impedance is greater than 100 Ω, add a bypassing capacitor, each, between HI and VSS and between LI and VSS. The added
capacitor value depends on the noise levels presented on the pins, typically from 1 nF to 10 nF should be effective to eliminate the
possible noise effect. When noise is present on two pins, HI or LI, the effect is to cause HO and LO malfunctions to have wrong logic
outputs.
(2) For cold temperature applications TI recommends the upper capacitance range. Follow the for PCB layout.
(3) The thermal pad is not directly connected to any leads of the package; however, it is electrically and thermally connected to the
substrate which is the ground of the device.
Copyright © 2017, Texas Instruments Incorporated
5
UCC27212A-Q1
ZHCSGD6 –JULY 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–10
MAX
20
UNIT
V
VDD(2), VHB – VHS
VLI, VHI
Supply voltage range
Input voltages on LI and HI
20
V
DC
–0.3
VDD + 0.3
VDD + 0.3
VHB + 0.3
VHB + 0.3
100
V
V
V
V
V
V
VLO
VHO
VHS
Output voltage on LO
Output voltage on HO
Repetitive pulse < 100
ns(3)
–2
VHS – 0.3
VHS – 2
–1
DC
Repetitive pulse < 100
ns(3)
DC
Voltage on HS
Voltage on HB
Repetitive pulse < 100
ns(3)
–(24 V –
VDD)
115
VHB
–0.3
–40
–65
120
150
150
V
TJ
Operating virtual junction temperature range
°C
°C
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to VSS unless otherwise noted. Currents are positive into and negative out of the specified terminal.
(3) Verified at bench characterization. VDD is the value used in an application design.
6.2 ESD Ratings
VALUE
±2000
±1500
UNIT
Human-body model (HBM), per AEC Q100-002
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
6
Copyright © 2017, Texas Instruments Incorporated
UCC27212A-Q1
www.ti.com.cn
ZHCSGD6 –JULY 2017
6.3 Recommended Operating Conditions
over operating free-air temperature range, all voltages are with respect to VSS; currents are positive into and negative out of
the specified terminal. –40°C < TJ = TA < 140°C (unless otherwise noted)
MIN
NOM
MAX
17
UNIT
V
VDD
VHS
VHS
VHB
Supply voltage range, VHB – VHS
Voltage on HS
7
–1
12
100
110
115
50
V
Voltage on HS (repetitive pulse < 100 ns)
Voltage on HB
–(20 V – VDD)
VHS + 8
V
V
Voltage slew rate on HS
Operating junction temperature
V/ns
°C
–40
140
6.4 Thermal Information
UCC27212A-Q1
DDA (SOIC8
Powerpad)
THERMAL METRIC(1)
UNIT
8 PINS
37.7
47.2
9.6
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.8
ψJB
9.4
RθJC(bot)
3.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range, VHS = VSS = 0 V, no load on LO or HO, TA = TJ = –40°C to +140°C, (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENTS, VDD = VHB = 12 V
IDD
VDD quiescent current
V(LI) = V(HI) = 0 V
0.05
2.1
0.085
2.5
0.17
6.5
0.1
5.1
1
mA
mA
mA
mA
µA
IDDO
IHB
VDD operating current
f = 500 kHz, CLOAD = 0
V(LI) = V(HI) = 0 V
Boot voltage quiescent current
Boot voltage operating current
HB to VSS quiescent current
HB to VSS operating current
0.015
1.5
0.065
2.5
IHBO
IHBS
IHBSO
f = 500 kHz, CLOAD = 0
V(HS) = V(HB) = 115 V
f = 500 kHz, CLOAD = 0
0.0005
0.07
1.2
mA
SUPPLY CURRENTS, VDD = VHB = 6.8 V
IDD
VDD quiescent current
V(LI) = V(HI) = 0 V
0.02
0.7
0.065
1.4
0.14
6.5
0.08
5.1
1
mA
mA
mA
mA
µA
IDDO
IHB
VDD operating current
f = 500 kHz, CLOAD = 0
V(LI) = V(HI) = 0 V
Boot voltage quiescent current
Boot voltage operating current
HB to VSS quiescent current
HB to VSS operating current
0.01
0.5
0.04
IHBO
IHBS
IHBSO
f = 500 kHz, CLOAD = 0
V(HS) = V(HB) = 115 V
f = 500 kHz, CLOAD = 0
1.23
0.0005
0.07
1.2
mA
INPUT, VDD = VHB = 12 V
VHIT
VLIT
VIHYS
RIN
Input voltage threshold
1.7
1.2
2.3
1.6
700
68
2.55
1.9
V
V
Input voltage threshold
Input voltage hysteresis
Input pulldown resistance
mV
kΩ
INPUT, VDD = VHB = 6.8 V
VHIT
Input voltage threshold
1.6
2.0
2.6
V
Copyright © 2017, Texas Instruments Incorporated
7
UCC27212A-Q1
ZHCSGD6 –JULY 2017
www.ti.com.cn
Electrical Characteristics (continued)
over operating free-air temperature range, VHS = VSS = 0 V, no load on LO or HO, TA = TJ = –40°C to +140°C, (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.5
MAX
UNIT
V
VLIT
VIHYS
RIN
Input voltage threshold
Input voltage hysteresis
Input pulldown resistance
1.1
2.1
500
68
mV
kΩ
UNDER-VOLTAGE LOCKOUT (UVLO), VDD = VHB = 12 V
VDDR
VDD turnon threshold
Hysteresis
4.9
5.7
0.4
5.3
0.3
6.4
6.3
V
V
V
V
VDDHYS
VHBR
VHB turnon threshold
Hysteresis
4.35
VHBHYS
BOOTSTRAP DIODE, VDD = VHB = 12 V
VF
Low-current forward voltage
High-current forward voltage
Dynamic resistance, ΔVF/ΔI
IVDD-HB = 100 µA
0.65
0.85
0.5
0.8
0.95
0.85
V
V
Ω
VFI
RD
IVDD-HB = 100 mA
IVDD-HB = 100 mA and 80 mA
0.3
0.3
BOOTSTRAP DIODE, VDD = VHB = 6.8 V
VF
Low-current forward voltage
High-current forward voltage
Dynamic resistance, ΔVF/ΔI
IVDD-HB = 100 µA
0.65
0.85
0.5
0.8
0.95
0.85
V
V
Ω
VFI
RD
IVDD-HB = 100 mA
IVDD-HB = 100 mA and 80 mA
LO GATE DRIVER, VDD = VHB = 12 V
VLOL
VLOH
Low-level output voltage
High level output voltage
Peak pullup current(1)
0.05
0.1
0.1
0.16
3.7
0.19
0.29
V
V
A
A
(1)
Peak pulldown current
4.5
LO GATE DRIVER, VDD = VHB = 6.8 V
VLOL
VLOH
Low-level output voltage
High level output voltage
Peak pullup current
ILO = 100 mA
0.04
0.12
0.13
0.23
1.3
0.35
0.42
V
V
A
A
ILO = –100 mA, VLOH = VDD – VLO
VLO = 0 V
Peak pulldown current
VLO = 12 V for VDD = 6.8V
1.7
HO GATE DRIVER, VDD = VHB = 12 V
VHOL
VHOH
Low-level output voltage
0.05
0.1
0.1
0.16
3.7
0.19
0.29
V
V
A
A
High-level output voltage
(1)
Peak pullup current
(1)
Peak pulldown current
4.5
HO GATE DRIVER, VDD = VHB = 6.8 V
VLOL
VLOH
Low-level output voltage
High level output voltage
Peak pullup current
IHO = 100 mA
0.04
0.12
0.13
0.23
1.3
0.35
0.42
V
V
A
A
IHO = –100 mA, VHOH = VHB – VHO
VHO = 0 V
Peak pulldown current
VHO = 12 V for VDD = 6.8V
1.7
(1) Ensured by design.
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PROPAGATION DELAYS, VDD = VHB = 12 V
TDLFF
TDHFF
TDLRR
VLI falling to VLO falling
VHI falling to VHO falling
VLI rising to VLO rising
CLOAD = 0
CLOAD = 0
CLOAD = 0
10
10
10
16
16
20
30
30
42
ns
ns
ns
8
Copyright © 2017, Texas Instruments Incorporated
UCC27212A-Q1
www.ti.com.cn
ZHCSGD6 –JULY 2017
Switching Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TDHRR
VHI rising to VHO rising
CLOAD = 0
10
20
42
ns
PROPAGATION DELAYS, VDD = VHB = 6.8 V
TDLFF
TDHFF
TDLRR
TDHRR
VLI falling to VLO falling
VHI falling to VHO falling
VLI rising to VLO rising
VHI rising to VHO rising
CLOAD = 0
CLOAD = 0
CLOAD = 0
CLOAD = 0
10
10
13
13
24
24
28
28
50
50
57
57
ns
ns
ns
ns
DELAY MATCHING, VDD = VHB = 12 V
TJ = 25°C
4
4
4
4
9.5
17
ns
ns
ns
ns
TMON
From HO OFF to LO ON
From LO OFF to HO ON
TJ = –40°C to +140°C
TJ = 25°C
9.5
17
TMOFF
TJ = –40°C to +140°C
DELAY MATCHING, VDD = VHB = 6.8 V
TJ = 25°C
8
8
6
6
ns
ns
ns
ns
TMON
From HO OFF to LO ON
From LO OFF to HO ON
TJ = –40°C to +140°C
TJ = 25°C
18
18
TMOFF
TJ = –40°C to +140°C
OUTPUT RISE AND FALL TIME, VDD = VHB = 12 V
tR
tR
tF
tF
tR
tF
LO rise time
HO rise time
LO fall time
HO fall time
LO, HO
CLOAD = 1000 pF, from 10% to 90%
CLOAD = 1000 pF, from 10% to 90%
CLOAD = 1000 pF, from 90% to 10%
CLOAD = 1000 pF, from 90% to 10%
CLOAD = 0.1 µF, (3 V to 9 V)
7.8
7.8
ns
ns
ns
ns
µs
µs
6.0
6.0
0.36
0.20
0.6
0.4
LO, HO
CLOAD = 0.1 µF, (9 V to 3 V)
OUTPUT RISE AND FALL TIME, VDD = VHB = 6.8 V
tR
tR
tF
tF
tR
tF
LO rise time
HO rise time
LO fall time
HO fall time
LO, HO
CLOAD = 1000 pF, from 10% to 90%
CLOAD = 1000 pF, from 10% to 90%
CLOAD = 1000 pF, from 90% to 10%
CLOAD = 1000 pF, from 90% to 10%
CLOAD = 0.1 µF, (30% to 70%)
9.5
13.0
9.5
ns
ns
ns
ns
µs
µs
13.0
0.45
0.2
0.7
0.5
LO, HO
CLOAD = 0.1 µF, (70% to 30%)
MISCELLANEOUS
Minimum input pulse width that changes the
output
100
ns
ns
(1)(2)
(3)
Bootstrap diode turnoff time
IF = 20 mA, IREV = 0.5 A
20
when VDD = VHB = 6.8 V, VHS =
100 V, and input pulse width is 100
ns
Extended output pulse
250
ns
(1) Ensured by design.
(2) IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode.
(3) Typical values for TA = 25°C.
版权 © 2017, Texas Instruments Incorporated
9
UCC27212A-Q1
ZHCSGD6 –JULY 2017
www.ti.com.cn
LI
Input
(HI, LI)
HI
TDLRR, TDHRR
LO
Output
(HO, LO)
TDLFF, TDHFF
HO
图 1. Timing Diagram
10
版权 © 2017, Texas Instruments Incorporated
UCC27212A-Q1
www.ti.com.cn
ZHCSGD6 –JULY 2017
6.7 Typical Characteristics
100
80
60
40
20
0
100
10
1
CL = 0 pF, T = −40°C
CL = 0 pF, T = 25°C
0.1
0.01
CL = 0 pF, T = 140°C
CL = 1000 pF, T = 25°C
CL = 1000 pF, T = 140°C
CL = 4700 pF, T = 140°C
IDD
IHB
0
2
4
6
8
10
12
14
16
18
20
10
100
Frequency (kHz)
1000
Supply Voltage (V)
G002
T = 25°C
VDD = 12 V
图 2. Quiescent Current vs Supply Voltage
图 3. IDD Operating Current vs Frequency
100
10
100
10
1
1
CL = 0 pF, T = −40°C
CL = 0 pF, T = 25°C
CL = 0 pF, T = −40°C
CL = 0 pF, T = 25°C
0.1
0.01
CL = 0 pF, T = 140°C
CL = 1000 pF, T = 25°C
CL = 1000 pF, T = 140°C
CL = 4700 pF, T = 140°C
0.1
0.01
CL = 0 pF, T = 140°C
CL = 1000 pF, T = 25°C
CL = 1000 pF, T = 140°C
CL = 4700 pF, T = 140°C
10
100
Frequency (kHz)
1000
10
100
Frequency (kHz)
1000
VDD = 12 V
VHB – VHS = 12 V
图 4. IDD Operating Current vs Frequency
图 5. Boot Voltage Operating Current vs
Frequency (HB To HS)
6
5
6
5
4
4
3
3
2
2
1
1
0
0
Rising
Falling
Rising
Falling
−1
−1
−40 −20
0
20
40
60
Temperature (°C)
80
100 120 140
8
12
16
20
Supply Voltage (V)
VDD = 12 V
图 7. Input Thresholds vs Temperature
T = 25°C
图 6. Input Threshold vs Supply Voltage
版权 © 2017, Texas Instruments Incorporated
11
UCC27212A-Q1
ZHCSGD6 –JULY 2017
www.ti.com.cn
Typical Characteristics (接下页)
0.32
0.28
0.24
0.2
0.2
0.16
0.12
0.08
0.04
0
0.16
0.12
0.08
0.04
0
VDD = VHB = 8 V
VDD = VHB = 12 V
VDD = VHB = 16 V
VDD = VHB = 20 V
VDD = VHB = 8 V
VDD = VHB = 12 V
VDD = VHB = 16 V
VDD = VHB = 20 V
−40 −20
0
20
40
Temperature (°C)
60
80
100 120 140
−40 −20
0
20
40
Temperature (°C)
60
80
100 120 140
IHO = ILO = 100 mA
IHO = ILO = 100 mA
图 8. LO and HO High-Level Output Voltage
图 9. LO and HO Low-Level Output Voltage
vs Temperature
vs Temperature
8
7.6
7.2
6.8
6.4
6
1.5
1.2
0.9
0.6
0.3
0
5.6
5.2
VDD Rising Threshold
HB Rising Threshold
VDD UVLO Hysteresis
HB UVLO Hysteresis
−40 −20
0
20
40
60
80
100 120 140
−40 −20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
G009
G010
图 10. Undervoltage Lockout Threshold
图 11. Undervoltage Lockout Threshold Hysteresis
vs Temperature
vs Temperature
40
36
32
28
24
20
16
12
8
32
24
16
8
TDLRR
TDLRR
TDLFF
TDHRR
TDHFF
TDLFF
TDHRR
TDHFF
4
0
0
−40 −20
0
20
40
Temperature (°C)
60
80
100 120 140
−40 −20
0
20
40
Temperature (°C)
60
80
100 120 140
VDD = VHB = 12 V
图 12. Propagation Delays vs Temperature
VDD = VHB = 12 V
图 13. Propagation Delays vs Temperature
12
版权 © 2017, Texas Instruments Incorporated
UCC27212A-Q1
www.ti.com.cn
ZHCSGD6 –JULY 2017
Typical Characteristics (接下页)
32
28
24
20
16
12
8
32
28
24
20
16
12
8
TDLRR
TDLFF
TDHRR
TDHFF
TDLRR
TDLFF
TDHRR
TDHFF
4
4
0
0
8
12
16
Supply Voltage (V)
20
8
12
16
20
Supply Voltage (V)
T = 25°C
T = 25°C
图 14. Propagation Delays vs Supply Voltage
(VDD = VHB
图 15. Propagation Delays vs Supply Voltage
(VDD = VHB
)
)
10
8
5
4
3
2
1
0
Pulldown Current
Pullup Current
6
4
2
0
TMON
TMOFF
−2
−40 −20
0
20
40
60
Temperature (°C)
80
100 120 140
0
2
4
6
8
10
12
Output Voltage (V)
G016
VDD = VHB = 12 V
VDD = VHB = 12 V
图 16. Delay Matching vs Temperature
图 17. Output Current vs Output Voltage
100
10
1
0.1
0.01
0.001
500
550
600
650
700
750
800
850
Diode Voltage (mV)
G017
图 18. Diode Current vs Diode Voltage
版权 © 2017, Texas Instruments Incorporated
13
UCC27212A-Q1
ZHCSGD6 –JULY 2017
www.ti.com.cn
7 Detailed Description
7.1 Overview
The UCC27212A-Q1 device represents Texas Instruments’ latest generation of high-voltage gate drivers, which
are designed to drive both the high-side and low-side of N-Channel MOSFETs in a half- and full-bridge or
synchronous-buck configuration. The floating high-side driver can operate with supply voltages of up to 120 V,
which allows for N-Channel MOSFET control in half-bridge, full-bridge, push-pull, two-switch forward, and active
clamp forward converters.
The UCC27212A-Q1 device feature 4-A source and sink capability, industry best-in-class switching
characteristics and a host of other features listed in 表 1. These features combine to ensure efficient, robust and
reliable operation in high-frequency switching power circuits.
表 1. UCC27212A-Q1 Highlights
FEATURE
BENEFIT
High peak current ideal for driving large power MOSFETs with
minimal power loss (fast-drive capability at Miller plateau)
4-A source and sink current with 0.9-Ω output resistance
Increased robustness and ability to handle undershoot and
overshoot can interface directly to gate-drive transformers without
having to use rectification diodes.
Input pins (HI and LI) can directly handle –10 VDC up to 20 VDC
120-V internal boot diode
Provides voltage margin to meet telecom 100-V surge requirements
Allows the high-side channel to have extra protection from inherent
negative voltages caused by parasitic inductance and stray
capacitance
Switch node (HS pin) able to handle –18 V maximum for 100 ns
Robust ESD circuitry to handle voltage spikes
Excellent immunity to large dV/dT conditions
Best-in-class switching characteristics and extremely low-pulse
transmission distortion
18-ns propagation delay with 7.2-ns rise time and 5.5-ns fall time
2-ns (typical) delay matching between channels
Symmetrical UVLO circuit
Avoids transformer volt-second offset in bridge
Ensures high-side and low-side shut down at the same time
Complementary to analog or digital PWM controllers; increased
hysteresis offers added noise immunity
TTL optimized thresholds with increased hysteresis
In the UCC27212A-Q1 device, the high side and low side each have independent inputs that allow maximum
flexibility of input control signals in the application. The boot diode for the high-side driver bias supply is internal
to the UCC27212A-Q1. The UCC27212A-Q1 is the TTL or logic compatible version. The high-side driver is
referenced to the switch node (HS), which is typically the source pin of the high-side MOSFET and drain pin of
the low-side MOSFET. The low-side driver is referenced to VSS, which is typically ground. The UCC27212A-Q1
functions are divided into the input stages, UVLO protection, level shift, boot diode, and output driver stages.
14
版权 © 2017, Texas Instruments Incorporated
UCC27212A-Q1
www.ti.com.cn
ZHCSGD6 –JULY 2017
7.2 Functional Block Diagram
2
I.
UVLO
3
4
Ih
I{
LEVEL
SHIFT
5
IL
1
6
ëꢀꢀ
UVLO
[h
8
7
ë{{
[L
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Input Stages
The input stages provide the interface to the PWM output signals. The input stages of the UCC27212A-Q1
device have impedance of 70-kΩ nominal and input capacitance is approximately 2 pF. Pulldown resistance to
VSS (ground) is 70 kΩ. The logic level compatible input provides a rising threshold of 2.3 V and a falling threshold
of 1.6 V. There is enough input hysteresis to avoid noise related jitter issues on the input.
7.3.2 Undervoltage Lockout (UVLO)
The bias supplies for the high-side and low-side drivers have UVLO protection. VDD as well as VHB to VHS
differential voltages are monitored. The VDD UVLO disables both drivers when VDD is below the specified
threshold. The rising VDD threshold is 5.7 V with 0.4-V hysteresis. The VHB UVLO disables only the high-side
driver when the VHB to VHS differential voltage is below the specified threshold. The VHB UVLO rising threshold is
5.3 V with 0.4 V hysteresis.
版权 © 2017, Texas Instruments Incorporated
15
UCC27212A-Q1
ZHCSGD6 –JULY 2017
www.ti.com.cn
Feature Description (接下页)
7.3.3 Level Shift
The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to
the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides
excellent delay matching with the low-side driver.
7.3.4 Boot Diode
The boot diode necessary to generate the high-side bias is included in the UCC27212A-Q1 family of drivers. The
diode anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and the
HS pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The boot
diode provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and
reliable operation.
7.3.5 Output Stages
The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance and
high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The low-
side output stage is referenced from VDD to VSS and the high side is referenced from VHB to VHS
.
7.4 Device Functional Modes
The device operates in normal mode and UVLO mode. See the Undervoltage Lockout (UVLO) section for
information on UVLO operation mode. In the normal mode the output state is dependent on states of the HI and
LI pins. 表 2 lists the output states for different input pin combinations.
表 2. Device Logic Table
HI PIN
LI PIN
HO(1)
LO(2)
L
L
L
H
L
L
L
L
H
L
H
H
H
H
H
H
(1) HO is measured with respect to HS.
(2) LO is measured with respect to VSS.
16
版权 © 2017, Texas Instruments Incorporated
UCC27212A-Q1
www.ti.com.cn
ZHCSGD6 –JULY 2017
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
To affect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is
employed between the PWM output of controllers and the gates of the power semiconductor devices. Also, gate
drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching
devices. With the advent of digital power, this situation will be often encountered because the PWM signal from
the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shifting
circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the
power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar
transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power
because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive
functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by
locating the high-current driver physically close to the power switch, driving gate-drive transformers, and
controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving
gate charge power losses from the controller into the driver.
Finally, emerging wide band-gap power device technologies such as GaN based switches, which are capable of
supporting very high switching frequency operation, are driving very special requirements in terms of gate drive
capability. These requirements include operation at low VDD voltages (5 V or lower), low propagation delays and
availability in compact, low-inductance packages with good thermal capability. Gate-driver devices are extremely
important components in switching power, and they combine the benefits of high-performance, low-cost
component count and board-space reduction as well as simplified system design.
8.2 Typical Application
12 V
100 V
VDD
HB
SECONDARY
SIDE
CIRCUIT
HO
HI
LI
DRIVE
HI
HS
LO
PWM
CONTROLLER
DRIVE
LO
UCC27212-Q1
ISOLATION
AND
FEEDBACK
Copyright © 2017, Texas Instruments Incorporated
图 19. UCC27212A-Q1 Typical Application
版权 © 2017, Texas Instruments Incorporated
17
UCC27212A-Q1
ZHCSGD6 –JULY 2017
www.ti.com.cn
Typical Application (接下页)
8.2.1 Design Requirements
For this design example, use the parameters listed in 表 3.
表 3. Design Specifications
DESIGN PARAMETER
Supply voltage, VDD
Voltage on HS, VHS
Voltage on HB, VHB
Output current rating, IO
Operating frequency
EXAMPLE VALUE
12 V
0 V to 100 V
12 V to 112 V
–4 A to 4 A
500 kHz
18
版权 © 2017, Texas Instruments Incorporated
UCC27212A-Q1
www.ti.com.cn
ZHCSGD6 –JULY 2017
8.2.2 Detailed Design Procedure
8.2.2.1 Power Dissipation
Power dissipation of the gate driver has two portions as shown in 公式 1.
PDISS = PDC + PSW
(1)
(2)
Use 公式 2 to calculate the DC portion of the power dissipation (PDC).
PDC = IQ × VDD
where
•
IQ is the quiescent current for the driver.
The quiescent current is the current consumed by the device to bias all internal circuits such as input stage,
reference voltage, logic circuits, protections, and also any current associated with switching of internal devices
when the driver output changes state (such as charging and discharging of parasitic capacitances, parasitic
shoot-through, and so forth). The UCC27212A-Q1 features very low quiescent currents (less than 0.17 mA, refer
to the table and contain internal logic to eliminate any shoot-through in the output driver stage. Thus the effect of
the PDC on the total power dissipation within the gate driver can be safely assumed to be negligible. The power
dissipated in the gate-driver package during switching (PSW) depends on the following factors:
•
Gate charge required of the power device (usually a function of the drive voltage VG, which is very close to
input bias supply voltage VDD)
•
•
Switching frequency
Use of external gate resistors. When a driver device is tested with a discrete, capacitive load calculating the
power that is required from the bias supply is fairly simple. The energy that must be transferred from the bias
supply to charge the capacitor is given by 公式 3.
2
EG = ½CLOAD × VDD
where
•
•
CLOAD is load capacitor
VDD is bias voltage feeding the driver
(3)
There is an equal amount of energy dissipated when the capacitor is charged and when it is discharged. This
leads to a total power loss given by 公式 4.
PG = CLOAD × VDD2 × fSW
where
•
fSW is the switching frequency
(4)
The switching load presented by a power MOSFET/IGBT is converted to an equivalent capacitance by examining
the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus
the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF
states. Most manufacturers provide specifications of typical and maximum gate charge, in nC, to switch the
device under specified conditions. Using the gate charge Qg, determine the power that must be dissipated when
switching a capacitor which is calculated using the equation QG = CLOAD × VDD to provide 公式 5 for power.
PG = CLOAD × VDD2 × fSW = QG × VDD × fSW
(5)
This power PG is dissipated in the resistive elements of the circuit when the MOSFET/IGBT is being turned on
and off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other half
is dissipated when the load capacitor is discharged during turnoff. When no external gate resistor is employed
between the driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the
use of external gate-drive resistors, the power dissipation is shared between the internal resistance of driver and
external gate resistor.
版权 © 2017, Texas Instruments Incorporated
19
UCC27212A-Q1
ZHCSGD6 –JULY 2017
www.ti.com.cn
8.2.3 Application Curves
图 20. Negative 10-V Input
图 21. Step Input
图 22. Symmetrical UVLO
20
版权 © 2017, Texas Instruments Incorporated
UCC27212A-Q1
www.ti.com.cn
ZHCSGD6 –JULY 2017
9 Power Supply Recommendations
The bias supply voltage range for which the UCC27212A-Q1 device is recommended to operate is from 7 V to
17 V. The lower end of this range is governed by the internal undervoltage-lockout (UVLO) protection feature on
the VDD pin supply circuit blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below
the V(ON) supply start threshold, this feature holds the output low, regardless of the status of the inputs. The
upper end of this range is driven by the 20-V absolute maximum voltage rating of the VDD pin of the device
(which is a stress rating). Keeping a 3-V margin to allow for transient voltage spikes, the maximum
recommended voltage for the VDD pin is 17 V. The UVLO protection feature also involves a hysteresis function,
which means that when the VDD pin bias voltage has exceeded the threshold voltage and device begins to
operate, and if the voltage drops, then the device continues to deliver normal functionality unless the voltage
drop exceeds the hysteresis specification VDD(hys). Therefore, ensuring that, while operating at or near the 7 V
range, the voltage ripple on the auxiliary power supply output is smaller than the hysteresis specification of the
device is important to avoid triggering device shutdown. During system shutdown, the device operation continues
until the VDD pin voltage has dropped below the V(OFF) threshold, which must be accounted for while evaluating
system shutdown timing design requirements. Likewise, at system start-up the device does not begin operation
until the VDD pin voltage has exceeded the V(ON) threshold.
The quiescent current consumed by the internal circuit blocks of the device is supplied through the VDD pin.
Although this fact is well known, it is important to recognize that the charge for source current pulses delivered by
the HO pin is also supplied through the same VDD pin. As a result, every time a current is sourced out of the HO
pin, a corresponding current pulse is delivered into the device through the VDD pin. Thus, ensure that a local
bypass capacitor is provided between the VDD and GND pins and located as close to the device as possible for
the purpose of decoupling is important. A low-ESR, ceramic surface-mount capacitor is required. TI recommends
using a capacitor in the range 0.22 µF to 4.7 µF between VDD and GND. In a similar manner, the current pulses
delivered by the HO pin are sourced from the HB pin. Therefore a 0.022-µF to 0.1-µF local decoupling capacitor
is recommended between the HB and HS pins.
版权 © 2017, Texas Instruments Incorporated
21
UCC27212A-Q1
ZHCSGD6 –JULY 2017
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
To improve the switching characteristics and efficiency of a design, the following layout rules must be followed.
•
•
•
Locate the driver as close as possible to the MOSFETs.
Locate the VDD – VSS and VHB-VHS (bootstrap) capacitors as close as possible to the device (see ).
Pay close attention to the GND trace. Use the thermal pad of the package as GND by connecting it to the
VSS pin (GND). The GND trace from the driver goes directly to the source of the MOSFET, but must not be
in the high current path of the MOSFET drain or source current.
•
•
Use similar rules for the HS node as for GND for the high-side driver.
For systems using multiple UCC27212A-Q1 devices, TI recommends that dedicated decoupling capacitors be
located at VDD–VSS for each device.
•
•
Care must be taken to avoid placing VDD traces close to LO, HS, and HO signals.
Use wide traces for LO and HO closely following the associated GND or HS traces. A width of 60 to 100 mils
is preferable where possible.
•
•
Use as least two or more vias if the driver outputs or SW node must be routed from one layer to another. For
GND, the number of vias must be a consideration of the thermal pad requirements as well as parasitic
inductance.
Avoid LI and HI (driver input) going close to the HS node or any other high dV/dT traces that can induce
significant noise into the relatively high impedance leads.
A poor layout can cause a significant drop in efficiency or system malfunction, and it can even lead to decreased
reliability of the whole system.
22
版权 © 2017, Texas Instruments Incorporated
UCC27212A-Q1
www.ti.com.cn
ZHCSGD6 –JULY 2017
10.2 Layout Example
HB Bypassing Cap
(Bottom Layer)
Ground plane
(Bottom Layer)
VDD Bypassing Cap
Ext. Gate
Resistance
(LO)
Ext. Gate
Resistance
(HO)
To LO
Load
To HO
Load
图 23. UCC27212A-Q1 Layout Example
10.2.1 Thermal Considerations
The useful range of a driver is greatly affected by the drive-power requirements of the load and the thermal
characteristics of the package. For a gate driver to be useful over a particular temperature range, the package
must allow for efficient removal of the heat produced while keeping the junction temperature within rated limits.
The thermal metrics for the driver package are listed in . For detailed information regarding the table, refer to the
Application Note from Texas Instruments entitled Semiconductor and IC Package Thermal Metrics (SPRA953).
The UCC27212A-Q1 device is offered in SOIC (8) and VSON (8). The section lists the thermal performance
metrics related to the SOT-23 package.
版权 © 2017, Texas Instruments Incorporated
23
UCC27212A-Q1
ZHCSGD6 –JULY 2017
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
•
•
《PowerPAD™ 散热增强型封装》，应用报告
《PowerPAD™ 速成》，应用报告
11.2 接收文档更新通知
要接收文档更新通知，请转至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品信
息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。
24
版权 © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC27212AQDDARQ1
ACTIVE SO PowerPAD
DDA
8
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 140
27212Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
DDA 8
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
©2020 ICPDF网 联系我们和版权申明