UCC27511AQDBVRQ1 [TI]
Single-Channel High-Speed Low-Side Gate Driver With 4-A Peak Source and 8-A Peak Sink;
| 型号： | UCC27511AQDBVRQ1 |
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TEXAS INSTRUMENTS |
| 描述： | Single-Channel High-Speed Low-Side Gate Driver With 4-A Peak Source and 8-A Peak Sink 栅 驱动 光电二极管 接口集成电路 |
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UCC27511A-Q1
SLVSCO2A –AUGUST 2014–REVISED SEPTEMBER 2014
UCC27511A-Q1 Single-Channel High-Speed Low-Side Gate Driver
With 4-A Peak Source and 8-A Peak Sink
1 Features
•
Input Pins Capable of Withstanding –5-V DC
Below GND pin
1
•
•
Qualified for Automotive Applications
•
•
Operating Temperature Range of –40°C to 140°C
6-Pin DBV (SOT-23) Package Option
AEC-Q100 Qualified With the Following Results:
–
Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
2 Applications
–
–
Device HBM ESD Classification Level 2
Device CDM ESD Classification Level C4B
•
•
•
Switch-Mode Power Supplies
DC-to-DC Converters
•
•
•
•
Low-Cost Gate-Driver Device Offering Superior
Replacement of NPN and PNP Discrete Solutions
Companion Gate-Driver Devices for Digital Power
Controllers
4-A Peak Source and 8-A Peak Sink
Asymmetrical Drive
•
•
Solar Power, Motor Control, UPS
Gate Driver for Emerging Wide Band-Gap Power
Devices (such as GaN)
Strong Sink Current Offers Enhanced Immunity
Against Miller Turnon
Split Output Configuration (Allows Easy and
Independent Adjustment of Turnon and Turnoff
Speeds) in the UCC27511A-Q1
3 Description
The UCC27511A-Q1 device is a compact gate driver
that offers superior replacement of NPN and PNP
discrete driver (buffer circuit) solutions. The
UCC27511A-Q1 device is an automotive-grade
single-channel low-side, high-speed gate driver rated
for MOSFETs, IGBTs, and emerging wide-bandgap
power devices such as GaN. The device features fast
rise times, fall times, and propagation delays, making
the UCD27511A-Q1 device suitable for high-speed
applications. The device features 4-A peak source
and 8-A peak sink currents with asymmetrical drive,
boosting immunity against parasitic Miller turnon
effect. The split output configuration enables easy
and independent adjustment of rise and fall times
using only two resistors and eliminating the need for
an external diode.
•
•
•
•
Fast Propagation Delays (13-ns typical)
Fast Rise and Fall Times (9-ns and 7-ns typical)
4.5 to 18-V Single Supply Range
Outputs Held Low During VDD UVLO (Ensures
Glitch-Free Operation at Power Up and Power
Down)
•
•
•
TTL and CMOS Compatible Input-Logic Threshold
(Independent of Supply Voltage)
Hysteretic-Logic Thresholds for High-Noise
Immunity
Dual-Input Design (Choice of an Inverting (IN–
Pin) or Non-Inverting (IN+ Pin) Driver
Configuration)
Device Information(1)
–
Unused Input Pin can be Used for Enable or
Disable Function
PART NUMBER
PACKAGE
BODY SIZE (NOM)
UCC27511A-Q1
SOT-23 (6)
2.90 mm × 1.60 mm
•
•
Output Held Low when Input Pins are Floating
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Input Pin Absolute Maximum Voltage Levels Not
Restricted by VDD Pin Bias Supply Voltage
4 Typical Application Diagrams
Non-Inverting Input
Inverting Input
VDD
VDD
V(SOURCE)
C2
4.5 V to18 V
C2
V(SOURCE)
4.5 V to 18 V
L1
UCC27511A-Q1
L1
D1
UCC27511A-Q1
V(IN+)
6
5
4
IN+
VDD
OUTH
OUTL
1
2
3
VO
D1
Q1
6
5
4
IN+
VDD
1
VO
R1
R2
Q1
IN–
R1
R2
+
V(IN–)
–
IN
OUTH
OUTL
2
3
C1
+
GND
C1
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC27511A-Q1
SLVSCO2A –AUGUST 2014–REVISED SEPTEMBER 2014
www.ti.com
Table of Contents
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 17
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application ................................................. 18
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Typical Application Diagrams .............................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 Handling Ratings....................................................... 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Switching Characteristics.......................................... 6
7.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
9
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 24
12 Device and Documentation Support ................. 24
12.1 Trademarks........................................................... 24
12.2 Electrostatic Discharge Caution............................ 24
12.3 Glossary................................................................ 24
13 Mechanical, Packaging, and Orderable
8
Information ........................................................... 24
5 Revision History
Changes from Original (August 2014) to Revision A
Page
•
•
Changed the device status From: Product Preview To Production ....................................................................................... 1
Changed the ESD HBM Values From: MIN = -2000 V, MAX = 2000 V To: MIN = -4000 V, MAX = 4000 V ....................... 4
2
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SLVSCO2A –AUGUST 2014–REVISED SEPTEMBER 2014
6 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
VDD
1
6
IN+
IN–
OUTH
OUTL
2
3
5
4
GND
Pin Functions
PIN
NAME
I/O
FUNCTION
NO.
1
VDD
I
Bias supply input.
Sourcing current output of driver. Connect a resistor between the OUTH pin and the gate of the power-
switching device to adjust turnon speed.
2
OUTH
O
Sinking current output of driver. Connect a resistor between the OUTL pin and the gate of the power-
switching device to adjust turnoff speed.
3
4
5
OUTL
GND
IN–
O
—
I
Ground. All signals referenced to this pin.
Inverting input. When the driver is used in non-inverting configuration, connect the IN– pin to GND in
order to enable output. The OUTx pin is held low if the IN– pin is unbiased or floating.
Non-inverting input. When the driver is used in inverting configuration, connect the IN+ pin to VDD in
order to enable output. The OUTx pin is held low if the IN+ pin is unbiased or floating.
6
IN+
I
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7 Specifications
7.1 Absolute Maximum Ratings(1)(2)(3)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–6
MAX
20
UNIT
Supply voltage
Input voltage
VDD
IN+, IN–(4)
20
VDD
0.3
+
OUTH
OUTL
–0.3
V
Output voltage
DC
–0.3
–2
20
20
Repetitive pulse less than 200 ns(5)
IO_DC (source)
IO_DC (sink)
0.3
0.6
4
Output continuous current
(OUTH source current and OUTL sink current)
A
IO_pulsed(source)
IO_pulsed(sink)
Output pulsed current (0.5 µs)
(OUTH source current and OUTL sink current)
8
Operating virtual junction temperature range, TJ
Lead temperature
–40
150
300
260
Soldering, 10 sec.
Reflow
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND unless otherwise noted. Currents are positive into and negative out of the specified terminal. See
the Thermal Information section for thermal limitations and considerations of packages.
(3) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
(4) Maximum voltage on input pins is not restricted by the voltage on the VDD pin.
(5) Values are verified by characterization on bench.
7.2 Handling Ratings
MIN
–65
MAX
150
UNIT
Tstg
Storage temperature range
°C
Human body model (HBM), per AEC Q100-002(1)
–4000
–1000
4000
1000
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per AEC Q100-011
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
–5
NOM
12
MAX UNIT
VDD
VI
Supply voltage
18
18
V
V
Input voltage, IN+ and IN–
Operating junction temperature range
TA
–40
140
°C
7.4 Thermal Information
DBV
THERMAL METRIC(1)
UNIT
6 PINS
217.8
97.6
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
72.2
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
8.6
ψJB
71.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
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7.5 Electrical Characteristics
VDD = 12 V, TA = TJ = –40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the
specified terminal.
PARAMETER
BIAS CURRENTS
TEST CONDITIONS
MIN
TYP
MAX UNIT
IN+ = VDD, IN– = GND
40
25
20
100
75
160
I(START)
Startup current
VDD = 3.4 V
TA = 25°C
IN+ = IN– = GND or IN+ = IN– = VDD
IN+ = GND, IN– = VDD
145
115
µA
60
UNDERVOLTAGE LOCKOUT (UVLO)
3.91
3.7
4.2
4.2
4.5
V(ON)
Supply start threshold
TA = –40°C to 140°C
4.65
V
Minimum operating voltage
after supply start
V(OFF)
3.45
0.2
3.9
0.3
4.35
0.5
VDD(hys)
Supply voltage hysteresis
INPUTS (IN+, IN–)
Output high for IN+ pin,
Output low for IN– pin
VIH(IN)
Input signal high threshold
2.2
2.4
Output low for IN+ pin,
Output high for IN– pin
V
VIL(IN)
Input signal low threshold
Input signal hysteresis
1.0
1.2
1
Vhys(IN)
SOURCE AND SINK CURRENT
IP(SRC)
IP(SNK)
Source peak current(1)
Sink peak current(1)
C(LOAD) = 0.22 µF, ƒS = 1 kHz
C(LOAD) = 0.22 µF, ƒS = 1 kHz
–4
8
A
A
OUTPUTS (OUTH, OUTL, OUT)
VDD = 12 V
I(OUTH) = –10 mA
50
60
90
130
6.5
VOH
High output voltage
VDD = 4.5 V
I(OUTH) = –10 mA
mV
VDD = 12
I(OUTL) = 10 mA
5
VOL
Low output voltage
VDD = 4.5 V
5.5
5
10
I(OUTL) = 10 mA
VDD = 12 V
I(OUTH) = –10 mA
7.5
RO(H)
Output pullup resistance(2)
Output pulldown resistance
VDD = 4.5 V
I(OUTH) = –10 mA
5
11
Ω
VDD = 12 V
I(OUTL) = 10 mA
0.375
0.45
0.65
0.75
RO(L)
VDD = 4.5 V
I(OUTL) = 10 mA
(1) Ensured by Design.
(2) RO(H) represents the on-resistance of P-channel MOSFET in pullup structure of the output stage of the UCC27511A-Q1 device.
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7.6 Switching Characteristics
VDD = 12 V, TA = TJ = –40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the
specified terminal. See Figure 1, Figure 2, Figure 3, and Figure 4
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 12 V
C(LOAD) = 1.8 nF, connected to
OUTH and OUTL pins tied together
8
12
tr
Rise time(1)
ns
VDD = 4.5 V
C(LOAD) = 1.8 nF
16
7
22
11
11
VDD = 12 V
C(LOAD) = 1.8 nF, connected to
OUTH and OUTL pins tied together
tf
Fall time(1)
ns
ns
VDD = 4.5 V
C(LOAD) = 1.8 nF
7
VDD = 12 V
5-V input pulse C(LOAD) = 1.8 nF,
connected to OUTH and OUTL pins
tied together
4
4
13
15
23
26
td(1)
IN+ to output propagation delay(1)
VDD = 4.5 V
5-V input pulse C(LOAD) = 1.8 nF,
connected to OUTH and OUTL pins
tied together
VDD = 12 V
C(LOAD) = 1.8 nF, connected to
OUTH and OUTL pins tied together
4
4
13
19
23
30
td(2)
IN– to output propagation delay(1)
ns
VDD = 4.5 V
C(LOAD) = 1.8 nF, connected to
OUTH and OUTL pins tied together
(1) See timing diagrams in Figure 1, Figure 2, Figure 3, and Figure 4.
High
INPUT
(IN+ pin)
Low
High
IN– pin
Low
90%
OUTPUT
10%
td(1) tr
td(1) tr
Figure 1. Non-Inverting Configuration
(PWM Input to IN+ pin (IN– Pin Tied to GND),
Output Represents OUTH and OUTL Pins Tied Together in the UCC27511A-Q1)
6
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High
INPUT
(IN– pin)
Low
High
IN+ pin
Low
90%
OUTPUT
10%
td(2) tr
td(2) tr
Figure 2. Inverting Configuration
(PWM Input to IN– Pin (IN+ Pin Tied to VDD),
Output Represents OUTH and OUTL Pins Tied Together in the UCC27511A-Q1)
High
INPUT
(IN– pin)
Low
High
ENABLE
(IN+ pin)
Low
90%
OUTPUT
10%
td(1) tr
td(1) tr
Figure 3. Enable And Disable Function Using IN+ Pin
(Enable and Disable Signal Applied to IN+ Pin, PWM Input to IN– Pin,
Output Represents OUTH and OUTL Pins Tied Together in the UCC27511A-Q1)
High
INPUT
(IN+ pin)
Low
High
ENABLE
(IN– pin)
Low
90%
OUTPUT
10%
td(2) tr
td(2) tr
Figure 4. Enable and Disable Function Using IN– Pin
(Enable and Disable Signal Applied to IN– Pin, PWM Input to IN+ Pin,
Output Represents OUTH and OUTL Pins Tied Together in the UCC27511A-Q1)
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7.7 Typical Characteristics
0.12
4
3.5
3
IN+ = High, IN– = Low
IN+ = Low, IN– = Low
0.11
0.1
0.09
0.08
0.07
0.06
0.05
2.5
2
−50
0
50
Temperature (°C)
100
150
−50
0
50
Temperature (°C)
100
150
G001
G013
VDD = 3.4 V
VDD = 12 V
C(LOAD) = 500 pF
ƒS = 500 kHz
Figure 5. Startup Current vs Temperature
Figure 6. Operating Supply Current vs Temperature (Output
Switching)
0.5
0.4
0.3
0.2
0.1
4.6
IN+ = High, IN– = Low
IN+ = Low, IN– = Low
UVLO Rising
UVLO Falling
4.4
4.2
4
3.8
3.6
−50
0
50
Temperature (°C)
100
150
−50
0
50
Temperature (°C)
100
150
G002
G003
VDD = 12 V
Figure 7. Supply Current vs Temperature (Output in DC On
or Off Condition)
Figure 8. UVLO Threshold Voltage vs Temperature
8
7
6
5
4
3.5
Turn−Off
RO(H)
Turn−On
3
2.5
2
1.5
1
−50
0
50
Temperature (°C)
100
150
−50
0
50
Temperature (°C)
100
150
G014
G004
VDD = 12 V
C(LOAD) = 1.8 nF
VDD = 12 V
IO = 10 mA
Figure 9. Input Threshold vs Temperature
Figure 10. Output Pullup Resistance vs Temperature
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Typical Characteristics (continued)
0.8
8
7
6
5
4
RO(L)
0.7
0.5
0.3
0.1
−50
0
50
Temperature (°C)
100
150
−50
0
50
Temperature (°C)
100
150
G005
G000
VDD = 12 V
IO = 10 mA
VDD = 12 V
C(LOAD) = 1.8 nF
Figure 11. Output Pull-Down Resistance vs Temperature
Figure 12. Rise Time vs Temperature
10
20
15
10
5
Turn−Off
Turn−On
9
8
7
6
−50
0
50
Temperature (°C)
100
150
−50
0
50
Temperature (°C)
100
150
G000
G006
VDD = 12 V
C(LOAD) = 1.8 nF
VDD = 12 V
Figure 13. Fall Time vs Temperature
Figure 14. Input to Output Propagation Delay vs
Temperature
20
18
16
14
12
10
8
20
18
16
14
12
10
8
VDD = 15 V
VDD = 12 V
VDD = 4.5 V
6
4
Turn−Off
Turn−On
2
0
6
0
100
200
300 400
Frequency (kHz)
500
600
700
0
4
8 12
Supply Voltage (V)
16
20
G010
G007
C(LOAD) = 1.8 nF
Figure 15. Operating Supply Current vs Frequency
Figure 16. Propagation Delays vs Supply Voltage
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Typical Characteristics (continued)
20
10
8
15
10
5
6
4
2
0
4
8 12
Supply Voltage (V)
16
20
0
4
8 12
Supply Voltage (V)
16
20
G008
G009
Figure 17. Rise Time vs Supply Voltage
Figure 18. Fall Time vs Supply Voltage
10
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8 Detailed Description
8.1 Overview
The UCC27511A-Q1 single-channel high-speed low-side gate-driver device is capable of effectively driving
MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, the
UCC27511A-Q1 device is capable of sourcing and sinking high peak-current pulses into capacitive loads offering
rail-to-rail drive capability and extremely small propagation delay of 13 ns (typical).
The UCC27511A-Q1 device provides 4-A source, 8-A sink (asymmetrical drive) peak-drive current capability.
Strong sink capability in asymmetrical drive boosts immunity against parasitic, Miller turnon effect. The
UCC27511A-Q1 device also features a unique split output configuration where the gate-drive current is sourced
through the OUTH pin and sunk through the OUTL pin. This unique pin arrangement allows the user to apply
independent turnon and turnoff resistors to the OUTH and OUTL pins (respectively) and easily control the
switching slew rates.
Alternatively the OUTH and OUTL pins can be tied together, which results in a typical gate driver output
configuration where the source and sink currents are delivered from the same pin. In case of UCC27511A-Q1
device, the state of the device's output is simply determined by the combined states of the OUTH and OUTL pins
when tied together. Output high implies that OUTH pin is pulled close to VDD pin bias voltage while OUTL pin is
in high-impedance state. Similarly output low implies that OUTL pin is pulled close to the GND pin while OUTH
pin is in high-impedance state. OUTH pulled to VDD, while OUTL pulled to GND pin simultaneously is not a valid
state for the device.
The UCC27511A-Q1 device is designed to operate over a wide VDD range of 4.5 to 18 V and wide temperature
range of –40°C to 140°C. Internal undervoltage lockout (UVLO) circuitry on the VDD pin holds the output low
outside VDD operating range. The capability to operate at low voltage levels, such as below 5 V, along with best-
in-class switching characteristics, is especially suited for driving emerging wide band-gap power-switching
devices such as GaN power-semiconductor devices.
The UCC27511A-Q1 device features a dual-input design which offers flexibility of implementing both inverting
(IN– pin) and non-inverting (IN+ pin) configuration with the same device. Either the IN+ or IN– pin can be used to
control the state of the driver output. The unused input pin can be used for enable and disable functions. For
system robustness, internal pullup and pulldown resistors on the input pins ensure that outputs are held low
when the input pins are in floating condition. Therefore the unused input pin is not left floating and must be
properly biased to ensure that driver output is in enabled for normal operation.
The input pin threshold of the UCC27511A-Q1 device is based on TTL and CMOS-compatible low-voltage logic
which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds
offers excellent noise immunity.
Table 1. UCC27511A-Q1 Device Summary
PART NUMBER
PACKAGE
PEAK CURRENT (SOURCE,
SINK)
INPUT THRESHOLD LOGIC
UCC27511A-Q1DBV
SOT-23, 6 pin
CMOS/TTL-Compatible
(low voltage, independent of VDD
bias voltage)
4-A, 8-A
(Asymmetrical Drive)
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Table 2. UCC27511A-Q1 Features and Benefits
FEATURE
BENEFIT
High current capability offers flexibility in employing UCC2751x
family of devices to drive a variety of power switching devices at
varying speeds
High source and sink current capability
4 A and 8 A (Asymmetrical) – UCC27511A-Q1 device
best-in-class 13-ns (typ) propagation delay
Extremely low pulse-transmission distortion
Expanded VDD Operating range of 4.5 V to 18 V
Flexibility in system design
Low VDD operation ensures compatibility with emerging wide band-
gap power devices such as GaN
Expanded operating temperature range of –40°C to 140°C
(See the Electrical Characteristics table)
Outputs are held low in UVLO condition, which ensures predictable
glitch-free operation at power up and power down
VDD UVLO Protection
Enables the device to pass abnormal-condition system tests and
delivers robust operation
Outputs held low when input pins (INx) in floating condition
Ability of input pins (and enable pin in UCC27518/9) to handle
voltage levels not restricted by VDD pin bias voltage
System simplification, especially related to auxiliary bias supply
architecture
Split output structure in the UCC27511A-Q1 device (OUTH, OUTL)
Allows independent optimization of turnon and turnoff speeds
Strong sink current (8 A) and low pulldown impedance (0.375 Ω) in
the UCC27511A-Q1 device
High immunity to C x dV/dt Miller turnon events
Enhanced noise immunity, while retaining compatibility with
microcontroller logic-level input signals (3.3 V, 5 V) optimized for
digital power
CMOS/TTL compatible input-threshold logic with wide hysteresis in
the UCC27511A-Q1 device
8.2 Functional Block Diagram
VDD
IN+
6
1
2
3
VDD
VDD
230 kΩ
200 kΩ
IN
–
5
4
OUTH
OUTL
VDD
GND
UVLO
8.3 Feature Description
In the following sections, the term output, or OUT refers to the combined state that results when the OUTH pin is
tied directly to the OUTL pin. As stated earlier, output high, or OUT high refers to the state when the OUTH pin is
pulled close to VDD pin bias voltage while the OUTL pin is in high-impedance state. Similarly output low or OUT
low implies that the OUTL pin is pulled close to the GND pin while the OUTH pin is in high-impedance state.
8.3.1 VDD and Undervoltage Lockout
The UCC27511A-Q1 device has and internal undervoltage-lockout (UVLO) protection feature on the VDD pin
supply circuit blocks. Whenever the driver is in UVLO condition (for example when the VDD voltage is less than
V(ON) during power up and when the VDD voltage is less than V(OFF) during power down), this circuit holds all
outputs low, regardless of the status of the inputs. The UVLO is typically 4.2 V with 300-mV typical hysteresis.
This hysteresis prevents chatter when low VDD supply voltages have noise from the power supply and also when
there are droops in the VDD bias voltage when the system commences switching and a sudden increase in IDD
occurs. The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching
characteristics, is especially suited for driving emerging GaN wide band-gap power-semiconductor devices.
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Feature Description (continued)
For example, at power up, the UCC27511A-Q1 driver output remains LOW until the VDD voltage reaches the
UVLO threshold. The magnitude of the OUT signal rises with VDD until steady-state VDD is reached. In the non-
inverting operation (PWM signal applied to IN+ pin) shown in Figure 19, the output remains LOW until the UVLO
threshold is reached, and then the output is IN–phase with the input. In the inverting operation (PWM signal
applied to IN– pin) shown in Figure 20 the output remains low until the UVLO threshold is reached, and then the
output is out-phase with the input. In both cases, the unused input pin must be properly biased to enable the
output. Note that in these devices the output turns to high state only if the IN+ pin is high and the IN– pin is low
after the UVLO threshold is reached.
Because the driver draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit
performance, two VDD-bypass capacitors are recommended to prevent noise problems. The use of surface-
mount components is highly recommended. A 0.1-μF ceramic capacitor should be located as close as possible to
the VDD to GND pins of the gate driver. In addition, to help deliver the high-current peaks required by the load, a
larger capacitor (such as one with a value of 1 μF) with relatively low ESR should be connected in parallel and
close proximity. The parallel combination of capacitors should present a low impedance characteristic for the
expected current levels and switching frequencies in the application.
VDD Threshold
VDD
VDD Threshold
IN+
IN–
IN–
IN+
OUTx
OUTx
Figure 19. Power-Up (Non-Inverting Drive)
8.3.2 Operating Supply Current
Figure 20. Power-Up (Inverting Drive)
The UCC27511A-Q1 device features very low quiescent IDD currents. The typical operating-supply current in
undervoltage-lockout (UVLO) state and fully-on state (under static and switching conditions) are summarized in
Figure 5, Figure 6 and Figure 7. The IDD current when the device is fully on and outputs are in a static state (DC
high or DC low, refer Figure 7) represents lowest quiescent IDD current when all the internal logic circuits of the
device are fully operational. The total supply current is the sum of the quiescent IDD current, the average IO
current because of switching, and finally any current related to pullup resistors on the unused input pin. For
example, when the inverting input pin is pulled low additional current is drawn from the VDD supply through the
pullup resistors (see the Functional Block Diagram). Knowing the operating frequency (ƒS) and the MOSFET gate
(QG) charge at the drive voltage being used, the average IO current can be calculated as product of QG and ƒS.
A complete characterization of the IDD current as a function of switching frequency at different VDD bias voltages
under 1.8-nF switching load is provided in Figure 15. The strikingly linear variation and close correlation with the
theoretical value of the average IO indicates negligible shoot-through inside the gate-driver device attesting to the
high-speed characteristics.
8.3.3 Input Stage
The input pins of the UCC27511A-Q1 device is based on a TTL and CMOS compatible input-threshold logic that
is independent of the VDD supply voltage. With a typicalyl high threshold of 2.2 V and a typically low threshold of
1.2 V, the logic-level thresholds can be conveniently driven with PWM control signals derived from 3.3-V and 5-V
digital-power controllers. Wider hysteresis (1 V typical) offers enhanced noise immunity compared to traditional
TTL-logic implementations, where the hysteresis is typically less than 0.5 V. This device also feature tight control
of the input-pin threshold-voltage levels which eases system design considerations and ensures stable operation
across temperature. The very-low input capacitance on these pins reduces loading and increases switching
speed.
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Feature Description (continued)
Whenever any of the input pins are in a floating condition, the output of the respective channel is held in the low
state. This function is achieved using VDD-pullup resistors on all the inverting inputs (IN– pin) or GND-pulldown
resistors on all the non-inverting input pins (IN+ pin), (see the Functional Block Diagram).
The device also features a dual-input configuration with two input pins available to control the state of the output.
The user has the flexibility to drive the device using either a non-inverting input pin (IN+) or an inverting input pin
(IN–). The state of the output pin is dependent on the bias on both the IN+ and IN– pins. For additional
clarification, refer to the I/O-logic truth table (Table 3) and the typical application diagrams, (Figure 22 and
Figure 23).
When an input pin is selected for PWM drive, the other input pin (the unused input pin) must be properly biased
in order to enable the output. As previously stated, the unused input pin cannot remain in a floating condition
because whenever any input pin is left in a floating condition the output is disabled. Alternatively, the unused
input pin can effectively be used to implement an enable or disable function. The following explains this function:
•
•
•
In order to drive the device in a non-inverting configuration, apply the PWM-control input signal to IN+ pin. In
this case, the unused input pin, IN–, must be biased low (such as tied to GND) in order to enable the output.
–
Alternately, the IN– pin is used to implement the enable or disable function using an external logic signal.
OUT is disabled when IN– is biased high and OUT is enabled when IN– is biased low.
In order to drive the device in an inverting configuration, apply the PWM-control input signal to IN– pin. In this
case, the unused input pin, IN+, must be biased high (such as tied to VDD) in order to enable the output.
–
Alternately, the IN+ pin is used to implement the enable or disable function using an external logic signal.
OUT is disabled when IN+ is biased low and OUT is enabled when IN+ is biased high.
Finally, note that the output pin can be driven into a high state only when the IN+ pin is biased high and the
IN– input is biased low.
The input stage of the driver is preferably driven by a signal with a short rise or fall time. Use caution whenever
the driver is used with slowly varying input signals, especially in situations where the device is located in a
mechanical socket or PCB layout that is not optimal:
•
High dI/dt current from the driver output coupled with board layout parasitics can cause ground bounce. The
differential voltage between input pins and GND is modified and triggers an unintended change of output
state because of fast 13-ns propagation delay which can ultimately result in high-frequency oscillations that
increase power dissipation and pose a risk of damage to the device.
•
•
A 1-V input-threshold hysteresis boosts noise immunity compared to most other industry standard drivers.
In the worst case, when a slow input signal is used and PCB layout is not optimal, adding a small capacitor (1
nF) between the input pin and GND pin very close to the driver device may be necessary which helps to
convert the differential mode noise with respect to the input-logic circuitry into common-mode noise and avoid
unintended change of output state.
If limiting the rise or fall times to the power device is the primary goal, then an external resistance is highly
recommended between the output of the driver and the power device instead of adding delays on the input
signal. This external resistor has the additional benefit of reducing part of the gate-charge related power
dissipation in the gate-driver device package and transferring the power dissipation into the external resistor.
8.3.4 Enable Function
As mentioned earlier, an enable and disable function is easily implemented in UCC27511A-Q1 device using the
unused input pin. When the IN+ pin is pulled down to GND or the IN– pin is pulled down to VDD, the output is
disabled. Thus the IN+ pin can be used like an enable pin that is based on active-high logic, while the IN– pin
can be used like an enable pin that is based on active-low logic.
8.3.5 Output Stage
Figure 21 shows the output stage of the UCC27511A-Q1 device. The UCC27511A-Q1 device features a unique
architecture on the output stage which delivers the highest peak-source current when the peak source current is
most needed during the Miller plateau region of the power switch turnon transition (when the power-switch drain
or collector voltage experiences dV/dt). The device output stage features a hybrid pullup structure using a
parallel arrangement of N-channel and P-channel MOSFET devices. By turning on the N-channel MOSFET
during a narrow instant when the output changes state from low to high, the gate-driver device is able to deliver a
brief boost in the peak-sourcing current enabling fast turnon.
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Feature Description (continued)
V
DD
R
O(H)
Pullup
R
(NMOS)
Gate
voltage
boost
OUTH
OUTL
Anti shoot-
through
circuitry
Input signal
Narrow pulse at
each turn on
R
O(L)
Figure 21. UCC27511A-Q1 Gate Driver Output Structure
The RO(H) parameter (see the Electrical Characteristics table) is a DC measurement and is representative of the
on-resistance of the P-channel device only, because the N-Channel device is turned on only during output
change of state from low to high. Thus the effective resistance of the hybrid pullup stage is much lower than what
is represented by RO(H) parameter. The pulldown structure is composed of a N-channel MOSFET only. The RO(L)
parameter (see the Electrical Characteristics table), which is also a DC measurement, is representative of true
impedance of the pulldown stage in the device. In the UCC27511A-Q1 device, the effective resistance of the
hybrid pullup structure is approximately 2.7 × RO(L)
.
The UCC27511A-Q1 device features a unique split output configuration where the gate-drive current is sourced
through the OUTH pin and sunk through the OUTL pin. This unique pin arrangement allows users to apply
independent turnon and turnoff resistors to the OUTH and OUTL pins respectively and easily control the turnon
and turnoff switching dV/dt. This pin arrangement, along with the low pulldown impedance of the output driver
stage, is especially useful in applications where a high C × dV/dt Miller turnon immunity is needed (such as with
GaN power switches, SR MOSFETs and other applications) and the OUTL pin can be directly tied to the gate of
the power device.
VDD
V(SOURCE)
C2
4.5 V to18 V
L1
UCC27511A-Q1
D1
V(IN+)
6
5
4
IN+
VDD
OUTH
OUTL
1
2
3
VO
Q1
R1
R2
IN–
+
C1
GND
Figure 22. Using Non-Inverting Input (IN– Is Grounded To Enable Output)
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Feature Description (continued)
VDD
C2
V(SOURCE)
4.5 V to 18 V
L1
UCC27511A-Q1
D1
6
IN+
VDD
1
VO
Q1
R1
R2
V(IN–)
–
5
4
IN
OUTH
OUTL
2
3
+
C1
GND
Figure 23. Using Inverting Input (IN+ Is Tied To VDD Enable Output)
The UCC27511A-Q1 device is capable of delivering 4-A source, 8-A sink (asymmetrical drive) at VDD equal to 12
V. Strong sink capability in asymmetrical drive results in a very-low pulldown impedance in the driver output
stage which boosts immunity against parasitic, Miller turnon (C × dV/dt turnon) effect, especially where the low
gate-charge MOSFETs or emerging wide band-gap GaN-power switches are used.
An example of a situation where the Miller turnon effect is a concern is synchronous rectification (SR). In an SR
application, the dV/dt occurs on the MOSFET drain when the MOSFET is already held in off state by the gate
driver. The current discharging the C(GD) Miller capacitance during this dV/dt is shunted by the pulldown stage of
the driver. If the pulldown impedance is not low enough then a voltage spike can result in the VGS of the
MOSFET, which can result in spurious turnon. This phenomenon is shown in Figure 24. The UCC27511A-Q1
device offers a best-in-class, 0.375-Ω (typ) pulldown impedance boosting immunity against Miller turnon.
V
DS
(of MOSFET)
Miller Turn-On Spike in V
GS
C
(GD)
Gate Driver
V
TH
R
V
of
G
GS
MOSFET
C
ON
OFF
(OSS)
I
(SNK)
OUTL
C
(GS)
V
I
R
O(L)
V
of
DS
MOSFET
Figure 24. Very-Low Pulldown Impedance in UCC27511A-Q1, 4-A and 8-A Asymmetrical Drive
(Output Stage Mitigates Miller Turnon Effect)
The driver-output voltage swings between the VDD and GND pins which provides rail-to-rail operation as a result
of the MOS-output stage which delivers very-low dropout. The presence of the MOSFET-body diodes also offers
low impedance to switching overshoots and undershoots. In many cases, external Schottky diode clamps are
eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current without either
damage to the device or logic malfunction.
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Feature Description (continued)
8.3.6 Low Propagation Delays
The UCC27511A-Q1 driver device features best-in-class input-to-output propagation delay of 13 ns (typical) at
VDD equal to 12 V, which promises the lowest level of pulse transmission distortion available from industry-
standard gate-driver devices for high-frequency switching applications. As shown in Figure 14, very little variation
in propagation delay occurs with temperature and supply voltage, offering typically less than 20-ns propagation
delays across the entire range of application conditions.
8.4 Device Functional Modes
The device operates in normal mode and UVLO mode. See the VDD and Undervoltage Lockout section for
information on UVLO operation mode. In the normal mode the output state is dependent on states of the IN+ and
IN– pins. Table 3 lists the output states for different input pin combinations.
Table 3. Device Logic Table
OUT
(OUTH AND OUTL PINS
TIED TOGETHER IN THE
UCC27511A-Q1)
IN+ PIN
IN– PIN
OUTH PIN
OUTL PIN
L
L
L
H
High impedance
High impedance
H
L
L
L
H
L
L
L
L
H
L
High impedance
H
x(1)
H
High impedance
High impedance
High impedance
L
L
L
Any
x(1)
Any
(1) x = Floating Condition
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9 Application and Implementation
9.1 Application Information
High-current gate-driver devices are required in switching-power applications for a variety of reasons. In order to
effect fast switching of power devices and reduce associated switching power losses, a powerful gate driver
employs between the PWM output of controllers and the gates of the power-semiconductor devices. Further,
gate drivers are indispensable when having the PWM controller directly drive the gates of the switching devices
is impossible. With the advent of digital power, this situation will be encountered often encountered because the
PWM signal from the digital controller is often a 3.3-V logic signal which is not capable of effectively turning on a
power switch.
A level-shifting circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to
fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN and
PNP bipolar transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with
digital power because these circuits lack level-shifting capability. Gate drivers effectively combine both the level-
shifting and buffer-drive functions. Gate drivers also satisfy other needs such as minimizing the effect of high-
frequency switching noise by locating the high-current driver physically close to the power switch, driving gate-
drive transformers and controlling floating power-device gates, reducing power dissipation and thermal stress in
controllers by moving gate charge power losses into the controller.
Finally, emerging wide bandgap power device technologies, such as GaN based switches, which are capable of
supporting very high switching frequency operation, are driving very special requirements in terms of gate drive
capability. These requirements include operation at low VDD voltages (5 V or lower), low propagation delays and
availability in compact, low-inductance packages with good thermal capability. In summary gate-driver devices
are extremely important components in switching power combining benefits of high-performance low-cost
component count and board-space reduction and simplified system design.
9.2 Typical Application
Figure 25 shows the typical application of UCC27511A-Q1 device when used as a gate driver for the power
MOSFET in a boost-converter application (for example, AC-DC power factor correction in AC-DC chargers for
electric vehicles). In this application the UCC27511 device is used in the non-inverting input configuration.
L1
D1
Rectified AC input
V
(LINE)
V
O
V
(BIAS)
4.5 to 18 V
C
UCC27511A-Q1
V
6
5
IN+
VDD
1
2
I
C
Q1
(OUT)
R1
R2
IN±
OUTH
OUTL
4
GND
3
Figure 25. Typical Application in PFC Power Stage
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Typical Application (continued)
9.2.1 Design Requirements
When selecting the proper gate driver device for an end application, some design considerations must be
evaluated first in order to make the most appropriate selection. Among these considerations are input-to-output
configuration, the input threshold type, bias supply voltage levels, peak source and sink currents, availability of
independent enable and disable functions, propagation delay, power dissipation, and package type.
9.2.2 Detailed Design Procedure
9.2.2.1 Input-to-Output Logic
The design should specify which type of input-to-output configuration should be used. If turning on the power
MOSFET or IGBT when the input signal is in high state is preferred, then the non-inverting configuration must be
selected. If turning off the power MOSFET or IGBT when the input signal is in high state is preferred, the
inverting configuration must be chosen. The UCC27511A-Q1 device can be configured in either an inverting or
non-inverting input-to-output configuration using the IN– or IN+ pins respectively. To configure the device for use
in inverting mode, tie the IN+ pin to VDD and apply the input signal to the IN– pin. For the non-inverting
configuration, tie the IN– pin to GND and apply the input signal to the IN+ pin.
9.2.2.2 Input Threshold type
The type of Input voltage threshold determines the type of controller that can be used with the gate driver device.
The UCC27511A-Q1 device features a TTL and CMOS-compatible input threshold logic, with wide hysteresis.
The threshold voltage levels are low voltage and independent of the VDD supply voltage, which allows
compatibility with both logic-level input signals from microcontrollers as well as higher-voltage input signals from
analog controllers. See the Electrical Characteristics table for the actual input threshold voltage levels and
hysteresis specifications for the UCC27511A-Q1 device.
9.2.2.3 VDD Bias Supply Voltage
The bias supply voltage to be applied to the VDD pin of the device should never exceed the values listed in the
Recommended Operating Conditions table. However, different power switches demand different voltage levels to
be applied at the gate terminals for effective turnon and turnoff. With certain power switches, a positive gate
voltage may be required for turnon and a negative gate voltage may be required for turnoff, in which case the
VDD bias supply equals the voltage differential. With a wide operating range from 4.5 V to 18 V, the UCC27511A-
Q1 device can be used to drive a variety of power switches, such as Si MOSFETs (for example, VGS = 4.5 V, 10
V, 12 V), IGBTs (VGE = 15 V, 18 V), and wide-bandgap power semiconductors (such as GaN, certain types of
which allow no higher than 6 V to be applied to the gate terminals).
9.2.2.4 Peak Source and Sink Currents
Generally, switching the speed of the power switch during turnon and turnoff should be as fast as possible in
order to minimize switching power losses. The gate driver device must be able to provide the required peak
current for achieving the targeted switching speeds for the targeted power MOSFET.
Using the example of a power MOSFET, the system requirement for the switching speed is typically described in
terms of the slew rate of the drain-to-source voltage of the power MOSFET (such as dVDS/dt). For example, the
system requirement might state that a SPP20N60C3 power MOSFET must be turned-on with a dVDS/dt of 20
V/ns or higher under a DC bus voltage of 400 V in a continuous-conduction-mode (CCM) boost PFC-converter
application. This type of application is an inductive hard-switching application and reducing switching power
losses is critical. This requirement means that the entire drain-to-source voltage swing during power MOSFET
turn-on event (from 400 V in the OFF state to VDS(on) in on state) must be completed in approximately 20 ns or
less. When the drain-to-source voltage swing occurs, the Miller charge of the power MOSFET (QGD parameter in
SPP20N60C3 power MOSFET data sheet = 33 nC typical) is supplied by the peak current of gate driver.
According to power MOSFET inductive switching mechanism, the gate-to-source voltage of the power MOSFET
at this time is the Miller plateau voltage, which is typically a few volts higher than the threshold voltage of the
power MOSFET, VGS(TH)
.
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Typical Application (continued)
In order to achieve the targeted dVDS/dt, the gate driver must be capable of providing the QGD charge in 20 ns or
less. In other words a peak current of 1.65 A (= 33 nC / 20 ns) or higher must be provided by the gate driver. The
UCC27511-Q1 gate driver is capable of providing 4-A peak sourcing current which clearly exceeds the design
requirement and has the capability to meet the switching speed needed. The 2.4x overdrive capability provides
an extra margin against part-to-part variations in the QGD parameter of the power MOSFET along with additional
flexibility to insert external gate resistors and fine tune the switching speed for efficiency versus EMI
optimizations.
However, in practical designs the parasitic trace inductance in the gate drive circuit of the PCB will have a
definitive role to play on the power MOSFET switching speed. The effect of this trace inductance is to limit the
dI/dt of the output current pulse of the gate driver. In order to illustrate this, consider output current pulse
waveform from the gate driver to be approximated to a triangular profile, where the area under the triangle (½ ×
IPEAK × time) would equal the total gate charge of the power MOSFET (QG parameter in SPP20N60C3 power
MOSFET datasheet = 87 nC typical). If the parasitic trace inductance limits the dI/dt then a situation may occur in
which the full peak current capability of the gate driver is not fully achieved in the time required to deliver the QG
required for the power MOSFET switching. In other words the time parameter in the equation would dominate
and the IPEAK value of the current pulse would be much less than the true peak current capability of the device,
while the required QG is still delivered. Because of this, the desired switching speed may not be realized, even
when theoretical calculations indicate the gate driver is capable of achieving the targeted switching speed. Thus,
placing the gate driver device very close to the power MOSFET and designing a tight gate drive-loop with
minimal PCB trace inductance is important to realize the full peak-current capability of the gate driver.
9.2.2.5 Enable and Disable Function
Certain applications demand independent control of the output state of the driver without involving the input
signal. A pin which offers an enable and disable function achieves this requirement. The UCC27511A-Q1 device
offers 2 input pins, IN+ and IN–, both of which control the state of the output as listed in Table 3. Based on
whether an inverting or non-inverting input signal is provided to the driver, the appropriate input pin can be
selected as the primary input for controlling the gate driver. The other unused input pin can be conveniently used
for the enable and disable functionality. If the design does not require an enable function, the unused input pin
can be tied to either the VDD pin (in case IN+ is the unused pin), or GND (in case IN– is unused pin) in order to
ensure it does not affect the output status.
9.2.2.6 Propagation delay
The acceptable propagation delay from the gate driver is dependent on the switching frequency at which it is
used and the acceptable level of pulse distortion to the system. The UCC27511A-Q1 device features industry
best-in-class 13-ns (typical) propagation delays which ensures very little pulse distortion and allows operation at
very high-frequencies. See the Switching Characteristics table for the propagation and switching characteristics
of the UCC27511A-Q1 device.
9.2.2.7 Thermal Information
The useful range of a driver is greatly affected by the drive-power requirements of the load and the thermal
characteristics of the package. In order for a gate driver to be useful over a particular temperature range the
package must allow for the efficient removal of the heat produced while keeping the junction temperature within
rated limits. The thermal metrics for the driver package is listed in the Thermal Information table. For detailed
information regarding the Thermal Information table, please refer to the Application Note from Texas Instruments
entitled IC Package Thermal Metrics (SPRA953).
The UCC27511A-Q1 device is offered in a SOT-23, 6-pin package (DBV). The Thermal Information section lists
the thermal performance metrics related to SOT-23 package. The ψJT and ψJB metrics are used when estimating
the die temperature during actual application measurements.
Heat removal occurs primarily through the leads of the device and the PCB traces connected to the leads.
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Typical Application (continued)
9.2.2.8 Power Dissipation
Power dissipation of the gate driver has two portions as shown in Equation 1.
P = P
+ P
D
D(DC)
D(SW)
where
•
•
•
PD is the power dissipation
PD(DC) is the DC portion of the power dissipation
PD(SW) is the power dissipated in the gate-driver package during switching
(1)
(2)
Use Equation 2 to calculate the DC portion of the power dissipation.
PP(DC) = IQ ´ VDD
where
•
IQ is the quiescent current for the driver
The quiescent current is the current consumed by the device to bias all internal circuits such as input stage,
reference voltage, logic circuits, protections, and also any current associated with switching of internal devices
when the driver output changes state (such as charging and discharging of parasitic capacitances, parasitic
shoot-through, and others). The UCC27511A-Q1 device features very low quiescent currents (less than 1 mA,
see Figure 7) and contains internal logic to eliminate any shoot-through in the output driver stage. Thus the effect
of the PD(DC) on the total power dissipation within the gate driver can be assumed to be negligible.
The power dissipated in the gate-driver package during switching (PD(SW)) depends on the following factors:
•
The gate charge required of the power device (usually a function of the drive voltage VG, which is very close
to input bias supply voltage VDD because of low VO(H) drop-out).
•
•
The switching frequency (ƒS)
Use of external gate resistors (R(GATE)
)
When a driver device is tested with a discrete, capacitive load calculating the power that is required from the bias
supply is fairly simple. The energy to charge the capacitor is given by Equation 3.
1
2
EG
=
C(LOAD) ´ VDD
Where
•
•
•
C(LOAD) is load capacitor
VDD is bias voltage feeding the driver
EG is the energy stored in the capacitor when it is charged to VDD
(3)
An equal amount of energy dissipates when the capacitor is charged which leads to a total power loss given by
Equation 4.
2
P
= C
´ V
´ ƒ
S
tot
(LOAD)
DD
where
•
•
Ptot is the total power loss
ƒS is the switching frequency
(4)
The switching load presented by a power MOSFET or IGBT is converted to an equivalent capacitance by
examining the gate charge required to switch the device. This gate charge includes the effects of the input
capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between
the ON and OFF states. Most manufacturers provide specifications of typical and maximum gate charge, in nC,
to switch the device under specified conditions. Using the gate charge, QG, determine the power that must be
dissipated when charging a capacitor (calculated using Equation 5, to provide Equation 6).
QG = C(LOAD) ´ VDD
(5)
2
P
= C
´ V
´ ƒ = Q ´ V ´ ƒ
S
tot
(LOAD)
DD
S
G
DD
(6)
21
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Typical Application (continued)
This power, Ptot, is dissipated in the resistive elements of the circuit when the MOSFET or IGBT is being turned
on or off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other
half is dissipated when the load capacitor is discharged during turnoff. When no external gate resistor is
employed between the driver and MOSFET or IGBT, this power is completely dissipated inside the driver
package. With the use of external gate-drive resistors, the power dissipation is shared between the internal
resistance of driver and external gate resistor in accordance to the ratio of the resistance (more power dissipated
in the higher resistance component). Based on this simplified analysis, the driver power dissipation during
switching is calculated in Equation 7.
æ
ç
ç
è
ö
÷
÷
ø
R(OFF)
R(ON)
PD(SW) = 0.5 ´ QG ´ VDD ´ ƒS
´
+
R(OFF) + R(GATE) R(ON) + R(GATE)
where
•
•
R(OFF) = RO(L)
R(ON) (effective resistance of pullup structure) = 2.7 × RO(L)
(7)
9.2.3 Application Curves
Figure 26 and Figure 27 show the typical switching characteristics of the UCC27511A-Q1 device.
VDD = 10 V
C(LOAD) = 1 nF
VDD = 10 V
C(LOAD) = 1 nF
Figure 26. Typical Turnon Waveform
Figure 27. Typical Turnoff Waveform
10 Power Supply Recommendations
The bias supply voltage range for which the UCC27511A-Q1 device is rated to operate is from 4.5 V to 18 V.
The lower end of this range is governed by the internal undervoltage-lockout (UVLO) protection feature on the
VDD pin supply circuit blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the
V(ON) supply start threshold, this feature holds the output low, regardless of the status of the inputs. The upper
end of this range is driven by the 20-V absolute maximum voltage rating of the VDD pin of the device (which is a
stress rating). Keeping a 2-V margin to allow for transient voltage spikes, the maximum recommended voltage for
the VDD pin is 18 V.
The UVLO protection feature also involves a hysteresis function. This means that when the VDD pin bias voltage
has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device
continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification VDD(hys)
.
Therefore, ensuring that, while operating at or near the 4.5V range, the voltage ripple on the auxiliary power
supply output is smaller than the hysteresis specification of the device is important to avoid triggering device
shutdown.
22
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During system shutdown, the device operation continues until the VDD pin voltage has dropped below the V(OFF)
threshold which must be accounted for while evaluating system shutdown timing design requirements. Likewise,
at system startup, the device does not begin operation until the VDD pin voltage has exceeded above the V(ON)
threshold.
The quiescent current consumed by the internal circuit blocks of the device is supplied through the VDD pin.
Although this fact is well known, recognizing that the charge for source current pulses delivered by the OUTH pin
is also supplied through the same VDD pin is important. As a result, every time a current is sourced out of the
output pins (OUTH), a corresponding current pulse is delivered into the device through the VDD pin. Thus
ensuring that local bypass capacitors are provided between the VDD and GND pins and located as close to the
device as possible for the purpose of decoupling is important. A low ESR, ceramic surface mount capacitor is a
must. TI recommends to have 2 capacitors; a 100-nF ceramic surface-mount capacitor which can be nudged
very close to the pins of the device and another surface-mount capacitor of few microfarads added in parallel.
11 Layout
11.1 Layout Guidelines
Proper PCB layout is extremely important in a high-current fast-switching circuit to provide appropriate device
operation and design robustness. The UCC27511A-Q1 gate driver incorporates short-propagation delays and
powerful output stages capable of delivering large current peaks with very fast rise and fall times at the gate of
power switch to facilitate voltage transitions very quickly. At higher VDD voltages, the peak-current capability is
even higher (4-A/8-A peak current is at VDD equal to 12 V). Very high di/dt causes unacceptable ringing if the
trace lengths and impedances are not well controlled. The following circuit-layout guidelines are strongly
recommended when designing with these high-speed drivers.
•
Place the driver device as close as possible to power device in order to minimize the length of high-current
traces between the output pins and the gate of the power device.
•
Place the VDD-bypass capacitors between the VDD pin and GND as close as possible to the driver with
minimal trace length to improve the noise filtering. These capacitors support high-peak current being drawn
from VDD during turnon of power MOSFET. The use of low inductance surface-mount components such as
chip resistors and chip capacitors is highly recommended.
•
The turnon and turnoff current-loop paths (driver device, power MOSFET, and VDD bypass capacitor) should
be minimized as much as possible in order to keep the stray inductance to a minimum. High dI/dt is
established in these loops at two instances – during turnon and turnoff transients, which will induce significant
voltage transients on the output pin of the driver device and gate of the power switch.
•
•
•
Wherever possible, parallel the source and return traces, taking advantage of flux cancellation.
Separate power traces and signal traces, such as the output and input signals.
Minimize noise coupling from one current loop to another with star-point grounding or other techniques. The
GND of the driver should be connected to the other circuit nodes such as source of power switch, ground of
PWM controller, and others at one single point. The connected paths should be as short as possible to
reduce inductance and be as wide as possible to reduce resistance.
•
•
Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals
during transition. The ground plane must not be a conduction path for any current loop. Instead the ground
plane must be connected to the star-point with one single trace to establish the ground potential. In addition
to noise shielding, the ground plane can help in power dissipation as well.
In noisy environments, tying the unused Input pin of UCC27511A-Q1 device to the VDD (in case of IN+) pin or
GND (in case of IN–) using short traces in order to ensure that the output is enabled and to prevent noise
from causing malfunction in the output may be necessary.
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11.2 Layout Example
Figure 28. UCC27511A-Q1 Layout Example
12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Aug-2014
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
UCC27511AQDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
EAKQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Aug-2014
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Aug-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC27511AQDBVRQ1 SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Aug-2014
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBV
SPQ
Length (mm) Width (mm) Height (mm)
180.0 180.0 18.0
UCC27511AQDBVRQ1
6
3000
Pack Materials-Page 2
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