UCC27512DRSR_技术文档

UCC27511

UCC27512

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SLUSAW9D –FEBRUARY 2012–REVISED MAY 2013

Single-Channel High-Speed Low-Side Gate Driver

(with 4-A Peak Source and 8-A Peak Sink)

Check for Samples: UCC27511, UCC27512

1

FEATURES

APPLICATIONS

•

Low-Cost Gate-Driver Device Offering Superior

Replacement of NPN and PNP Discrete

Solutions

•

Switch-Mode Power Supplies

DC-to-DC Converters

Companion Gate-Driver Devices for Digital

Power Controllers

•

4-A Peak Source and 8-A Peak Sink

Asymmetrical Drive

•

Solar Power, Motor Control, UPS

Strong Sink Current Offers Enhanced

Immunity Against Miller Turnon

Gate Driver for Emerging Wide Band-Gap

Power Devices (such as GaN)

Split Output Configuration (allows easy and

independent adjustment of turnon and turnoff

speeds) in the UCC27511

DESCRIPTION

The UCC27511 and UCC27512 single-channel high-

speed low-side gate-driver device is capable of

effectively driving MOSFET and IGBT power

switches. Using a design that inherently minimizes

shoot-through current, UCC27511 and UCC27512

are capable of sourcing and sinking high peak-current

pulses into capacitive loads offering rail-to-rail drive

capability and extremely small propagation delay

typically 13 ns.

•

Fast Propagation Delays (13-ns typical)

Fast Rise and Fall Times (9-ns and 7-ns

typical)

•

4.5 to 18-V Single Supply Range

Outputs Held Low During VDD UVLO (ensures

glitch-free operation at power up and power

down)

•

TTL and CMOS Compatible Input-Logic

Threshold, (independent of supply voltage)

The UCC27511 and UCC27512 provides 4-A source,

8-A sink (asymmetrical drive) peak-drive current

capability. Strong sink capability in asymmetrical drive

boosts immunity against parasitic, Miller turnon effect.

The UCC27511 device also features a unique split

output configuration where the gate-drive current is

sourced through OUTH pin and sunk through OUTL

pin. This unique pin arrangement allows the user to

apply independent turnon and turnoff resistors to the

OUTH and OUTL pins respectively and easily control

the switching slew rates.

Hysteretic-Logic Thresholds for High-Noise

Immunity

Dual-Input Design (choice of an inverting (IN-

pin) or non-inverting (IN+ pin) driver

configuration)

–

Unused Input Pin can be Used for Enable

or Disable Function

•

Output Held Low when Input Pins are Floating

UCC27511 and UCC27512 are designed to operate

over a wide VDD range of 4.5 to 18 V and wide

temperature range of –40°C to +140°C. Internal

Undervoltage Lockout (UVLO) circuitry on VDD pin

holds output low outside VDD operating range. The

capability to operate at low voltage levels such as

Input Pin Absolute Maximum Voltage Levels

Not Restricted by VDD Pin Bias Supply

Voltage

•

Operating Temperature Range of –40°C to

+140°C

below

5 V, along with best-in-class switching

6-Pin DBV (SOT-23) and 6-Pin DRS (3mm × 3

mm WSON with exposed thermal pad)

Package Options

characteristics, is especially suited for driving

emerging wide band-gap power-switching devices

such as GaN power-semiconductor devices.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

UCC27511

UCC27512

SLUSAW9D –FEBRUARY 2012–REVISED MAY 2013

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TYPICAL APPLICATION DIAGRAMS

Non-Inverting Input

V+

4.5 V to 18 V

VSOURCE

C2

L1

UCC27511

VDD

UCC27512

D1

IN+

6

5

4

IN+

IN-

1

2

3

VOUT

IN+

1

2

3

IN+

IN-

GND

OUT

6

5

4

VOUT

Q1

R1

OUTH

OUTL

GND

VDD

+

4.5 V to 18 V

C1

R2

R3

GND

V+

C2

Inverting Input

V+

VSOURCE

C2

4.5 V to 18 V

L1

UCC27512

UCC27511

VDD

D1

1

2

3

IN+

IN-

GND

OUT

6

5

4

IN-

R3

6

5

4

IN+

IN-

1

2

3

VOUT

Q1

R1

GND

VDD

IN-

OUTH

OUTL

4.5 V to 18 V

V+

+

C1

R2

GND

C2

DESCRIPTION (CONTINUED)

UCC27511 features a dual-input design which offers flexibility of implementing both inverting (IN- pin) and non-

inverting (IN+ pin) configuration with the same device. Either IN+ or IN- pin can be used to control the state of

the driver output. The unused input pin can be used for enable and disable functions. For safety purpose, internal

pullup and pulldown resistors on the input pins ensure that outputs are held low when input pins are in floating

condition. Hence the unused input pin is not left floating and must be properly biased to ensure that driver output

is in enabled for normal operation.

The input pin threshold of the UCC27511 device is based on TTL and CMOS-compatible low-voltage logic which

is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers

excellent noise immunity.

2

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

Table 1. ORDERING INFORMATION⁽¹⁾⁽²⁾

OPERATING

TEMPERATURE RANGE,

T_A

PEAK CURRENT

(SOURCE/SINK)

INPUT THRESHOLD

LOGIC

PART NUMBER

UCC27511DBV

UCC27512DRS

PACKAGE

CMOS/TTL-Compatible

(low voltage, independent

of VDD bias voltage)

4-A/8-A

(Asymmetrical Drive)

SOT-23 6 pin

-40°C to 140°C

CMOS/TTL-Compatible

(low voltage, independent

of VDD bias voltage)

3 mm x 3 mm WSON, 6

4-A/8-A

(Asymmetrical Drive)

(1) For the most current package and ordering information, see Package Option Addendum at the end of this document.

(2) All packages use Pb-Free lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C peak reflow temperature to be

compatible with either lead free or Sn/Pb soldering operations. DRS package is rated MSL level 2.

Table 2. UCC2751x Product Family Summary

PART NUMBER

PACKAGE

PEAK CURRENT

(SOURCE/SINK)

INPUT THRESHOLD LOGIC

UCC27511DBV

UCC27512DRS

SOT-23, 6 pin

3 mm x 3 mm WSON, 6 pin

SOT-23, 5 pin

4-A/8-A

(Asymmetrical Drive)

CMOS/TTL-Compatible

(low voltage, independent of VDD

bias voltage)

(1)

UCC27516DRS

UCC27517DBV

UCC27518DBV

UCC27519DBV

4-A/4-A

(Symmetrical Drive)

(1)

SOT-23, 5 pin

CMOS

(follows VDD bias voltage)

SOT-23, 5 pin

(1) Visit www.ti.com for the latest product datasheet.

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ABSOLUTE MAXIMUM RATINGS^(1)(2)(3)

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

Supply voltage range

VDD

-0.3

20

OUTH voltage, (UCC27511)

OUTL voltage, (UCC27511)

-0.3 VDD + 0.3

-0.3 20

V

DC

-0.3 VDD + 0.3

OUT voltage, (UCC27512)

Repetitive pulse less than 200 ns⁽⁴⁾

I_{OUT_DC}(source)

I_{OUT_DC}(sink)

-2 VDD + 0.3

0.3

0.6

4

Output continuous current

(OUTH source current and OUTL sink current)

A

V

I_{OUT_pulsed}(source)

I_{OUT_pulsed}(sink)

Output pulsed current (0.5 µs)

(OUTH source current and OUTL sink current)

8

IN+, IN-⁽⁵⁾

-0.3

20

4000

1000

150

Human Body Model, HBM

ESD

Charged Device Model, CDM

Operating virtual junction temperature range, T_J

Storage temperature range, T_STG

-40

-65

150

°C

Soldering, 10 sec.

Reflow

300

Lead temperature

260

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND unless otherwise noted. Currents are positive into and negative out of the specified terminal. See

Packaging Section of the datasheet for thermal limitations and considerations of packages.

(3) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.

(4) Values are verified by characterization on bench.

(5) Maximum voltage on input pins is not restricted by the voltage on the VDD pin.

4

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RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

-40

0

TYP

MAX

18

UNIT

V

Supply voltage range, VDD

12

Operating junction temperature range

Input voltage, IN+ and IN-

140

18

°C

V

THERMAL INFORMATION

UCC27511

UCC27512

THERMAL METRIC

SOT-23 (DBV)

6 PINS

217.8

97.6

⁽¹⁾WSON

6 PINS

85.6

UNITS

θ_JA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

θ_JCtop

θ_JB

100.1

58.6

72.2

°C/W

ψ_JT

8.6

7.5

ψ_JB

71.6

58.7

θ_JCbot

n/a

23.7

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

NOTE

Under identical power dissipation conditions, the DRS package will allow to maintain a

lower die temperature than the DBV. θ_JAmetric should be used for comparison of power

dissipation capability between different packages (Refer to the APPLICATION

INFORMATION Section).

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ELECTRICAL CHARACTERISTICS

VDD = 12 V, T_A= T_J= -40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the

specified terminal.

PARAMETER

BIAS Currents

TEST CONDITION

VDD = 3.4 V

T_A= 25°C

MIN

TYP

MAX UNITS

IN+ = VDD, IN- = GND

40

25

20

100

75

160

I_DD(off)

Startup current

IN+ = IN- = GND or IN+ = IN- = VDD

IN+ = GND, IN- = VDD

145

115

µA

60

Under Voltage Lockout (UVLO)

3.91

3.70

4.20

4.5

V_ON

Supply start threshold

T_A= -40°C to 140°C

4.65

V

Minimum operating

voltage after supply start

V_OFF

3.45

0.2

3.9

0.3

4.35

0.5

V_{DD_H}

Supply voltage hysteresis

Inputs (IN+, IN-)

Input signal high

Output high for IN+ pin,

Output low for IN- pin

V_{IN_H}

2.2

2.4

threshold

Output low for IN+ pin,

Output high for IN- pin

V

A

V_{IN_L}

Input signal low threshold

1.0

1.2

1.0

V_{IN_HYS}Input signal hysteresis

Source/Sink Current

Source/sink peak

I_SRC/SNK

C_LOAD= 0.22 µF, F_SW= 1 kHz

-4/+8

current⁽¹⁾

Outputs (OUTH, OUTL, OUT)

VDD = 12 V

I_OUTH= -10 mA

50

60

90

130

V_DD

V_OH

-

High output voltage

Low output voltage

VDD = 4.5 V

I_OUTH= -10 mA

mV

VDD = 12

I_OUTL= 10 mA

5

6.5

V_OL

VDD = 4.5 V

I_OUTL= 10 mA

5.5

10

VDD = 12 V

I_OUTH= -10 mA

5.0

7.5

Output pull-up

resistance⁽²⁾

R_OH

VDD = 4.5 V

I_OUTH= -10 mA

5.0

11.0

0.650

0.750

Ω

VDD = 12 V

I_OUTL= 10 mA

0.375

0.45

Output pull-down

resistance

R_OL

VDD = 4.5 V

I_OUTL= 10 mA

(1) Ensured by Design.

(2) R_OHrepresents on-resistance of P-Channel MOSFET in pull-up structure of the UCC27511 and UCC27512's output stage.

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ELECTRICAL CHARACTERISTICS (continued)

VDD = 12 V, T_A= T_J= -40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the

specified terminal.

PARAMETER

TEST CONDITION

MIN

TYP

MAX UNITS

Switching Time

VDD = 12 V

C_LOAD= 1.8 nF, connected to OUTH and OUTL pins tied

together

8

16

7

12

22

11

t_R

Rise time⁽³⁾

VDD = 4.5 V

C_LOAD= 1.8 nF

VDD = 12 V

C_LOAD= 1.8 nF, connected to OUTH and OUTL pins tied

together

t_F

Fall time⁽³⁾

VDD=4.5V

C_LOAD= 1.8 nF

7

VDD = 12 V

ns

23

5-V input pulse C_LOAD= 1.8 nF, connected to OUTH and

OUTL pins tied together

4

13

IN+ to output propagation

delay⁽³⁾

t_D1

VDD = 4.5 V

5-V input pulse C_LOAD= 1.8 nF, connected to OUTH and

OUTL pins tied together

15

13

19

26

23

30

VDD = 12 V

C_LOAD= 1.8 nF, connected to OUTH and OUTL pins tied

together

IN- to output propagation

delay⁽³⁾

t_D2

VDD = 4.5 V

C_LOAD= 1.8 nF, connected to OUTH and OUTL pins tied

together

(3) See timing diagrams in Figure 1, Figure 2, Figure 3 and Figure 4.

High

INPUT

(IN+ pin)

Low

High

IN- pin

Low

90%

OUTPUT

10%

t_D1t_r

t_D1t_f

Figure 1. Non-Inverting Configuration

(PWM Input To IN+ pin (IN- Pin Tied To GND),

Output Represents OUTH And OUTL Pins Tied Together In The UCC27511)

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High

INPUT

(IN- pin)

Low

High

IN+ pin

Low

90%

OUTPUT

10%

t_D2t_f

t_D2t_r

Figure 2. Inverting Configuration

(PWM Input to IN- Pin (IN+ Pin Tied To VDD),

Output Represents OUTH And OUTL Pins Tied Together In The UCC27511)

High

INPUT

(IN- pin)

Low

High

ENABLE

(IN+ pin)

Low

90%

OUTPUT

10%

t_D1t_r

t_D1t_f

Figure 3. Enable And Disable Function Using IN+ Pin

(Enable And Disable Signal Applied To IN+ Pin, PWM Input To IN- Pin,

Output Represents OUTH And OUTL Pins Tied Together In The UCC27511)

High

INPUT

(IN+ pin)

Low

High

ENABLE

(IN- pin)

Low

90%

OUTPUT

10%

t_D2t_f

t_D2t_r

Figure 4. Enable And Disable Function Using IN- Pin

(Enable And Disable Signal Applied To IN- Pin, PWM Input To IN+ Pin,

Output Represents OUTH And OUTL Pins Tied Together In The UCC27511)

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DEVICE INFORMATION

UCC27511 Functional Block Diagram

VDD

IN+

6

1

2

3

VDD

200 kW

230 kW

IN-

5

4

OUTH

OUTL

VDD

GND

UVLO

UCC27512 Functional Block Diagram

VDD

IN+

1

3

VDD

OUT

GND

VDD

200 kW

230 kW

IN-

6

2

4

5

VDD

GND

UVLO

SOT-23 DBV

(Top View)

VDD

1

6

IN+

OUTH

OUTL

2

3

5

IN-

GND

4

DRS Package

(Top View)

IN+

GND

VDD

1

2

3

6

5

4

IN-

GND

OUT

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Table 3. UCC27511 TERMINAL FUNCTIONS

TERMINAL

PIN NUMBER

I/O

FUNCTION

NAME

1

VDD

I

Bias supply input.

Sourcing current output of driver. Connect resistor between OUTH and Gate of

power-switching device to adjust turnon speed.

2

OUTH

O

Sinking current output of driver. Connect resistor between OUTL and Gate of

power-switching device to adjust turnoff speed.

3

4

5

OUTL

GND

IN-

O

-

Ground: All signals referenced to this pin.

Inverting input: When the driver is used in non-inverting configuration, connect IN-

to GND in order to enable output, OUT held LOW if IN- is unbiased or floating

I

Non-inverting input: When the driver is used in inverting configuration, connect IN+

to VDD in order to enable output, OUT held LOW if IN+ is unbiased or floating

6

IN+

I

Table 4. UCC27512 TERMINAL FUNCTIONS

TERMINAL

I/O

FUNCTION

PIN NUMBER

NAME

1

IN+

I

Non-inverting input: When the driver is used in inverting configuration, connect IN+

to VDD in order to enable output, OUT held LOW if IN+ is unbiased or floating.

2, 5

GND

-

Ground: All signals referenced to this pin. TI recommends to connect pin 2 and pin 5

on PCB as close to the device as possible.

3

4

6

VDD

OUT

IN-

I

O

I

Bias supply input.

Sourcing/sinking current output of driver.

Inverting input: When the driver is used in non-inverting configuration, connect IN-

to GND in order to enable output, OUT held LOW if IN- is unbiased or floating.

Table 5. Device Logic Table

IN+ PIN

IN- PIN

OUTH PIN

OUTL PIN

OUT

(OUTH and OUTL pins

tied together in the

UCC27511)

L

H

High impedance

H

L

H

L

H

L

High impedance

H

x⁽¹⁾

H

High impedance

L

Any

x⁽¹⁾

Any

(1) x = Floating Condition

10

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TYPICAL CHARACTERISTICS

START-UP CURRENT

vs

OPERATING SUPPLY CURRENT

vs

TEMPERATURE (Output Switching)

TEMPERATURE

0.12

0.11

0.1

4

3.5

3

IN+=Low,IN−=Low

IN+=High, IN−=Low

0.09

0.08

0.07

0.06

0.05

V_DD= 12 V

C_Load= 500 pF

f_sw= 500 kHz

2.5

2

V_DD= 3.4 V

−50

0

50

100

150

−50

0

50

100

150

Temperature (°C)

G001

G013

Figure 5.

Figure 6.

SUPPLY CURRENT

vs

TEMPERATURE (Output in DC On/Off condition)

UVLO THRESHOLD VOLTAGE

vs

TEMPERATURE

0.5

0.4

0.3

0.2

0.1

4.6

4.4

4.2

4

IN+=Low,IN−=Low

IN+=High, IN−=Low

UVLO Rising

UVLO Falling

3.8

3.6

V_DD= 12 V

−50

0

50

100

150

−50

0

50

100

150

Temperature (°C)

G002

G003

Figure 7.

Figure 8.

INPUT THRESHOLD

vs

TEMPERATURE

OUTPUT PULL-UP RESISTANCE

vs

TEMPERATURE

3.5

3

8

7

6

5

4

V_DD= 12 V

C_Load= 1.8 nF

Turn−On

Turn−Off

RoH

2.5

2

V_DD= 12 V

I_out= 10 mA

1.5

1

−50

0

50

100

150

−50

0

50

100

150

Temperature (°C)

G014

G004

Figure 9.

Figure 10.

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TYPICAL CHARACTERISTICS (continued)

OUTPUT PULL-DOWN RESISTANCE

RISE TIME

vs

TEMPERATURE

0.8

0.7

8

7

6

5

4

V_DD= 12 V

C_Load= 1.8 nF

ROL

0.5

0.3

0.1

V_DD= 12 V

I_out= 10 mA

−50

0

50

100

150

−50

0

50

100

150

Temperature (°C)

G005

G000

Figure 11.

Figure 12.

FALL TIME

vs

TEMPERATURE

INPUT TO OUTPUT PROPAGATION DELAY

vs

TEMPERATURE

10

9

20

15

10

5

V_DD= 12 V

C_Load= 1.8 nF

Turn−On

Turn−Off

8

7

V_DD= 12 V

6

−50

0

50

100

150

−50

0

50

100

150

Temperature (°C)

G000

G006

Figure 13.

Figure 14.

OPERATING SUPPLY CURRENT

PROPAGATION DELAYS

vs

FREQUENCY

SUPPLY VOLTAGE

20

18

16

14

12

10

8

20

18

16

14

12

10

8

VDD=4.5V

VDD=12V

VDD=15V

6

4

C_Load= 1.8 nF

Turn−On

Turn−Off

2

0

6

0

100

200

300

400

500

600

700

0

4

8

12

16

20

Frequency (kHz)

Supply Voltage (V)

G010

G007

Figure 15.

Figure 16.

12

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TYPICAL CHARACTERISTICS (continued)

RISE TIME

vs

FALL TIME

vs

SUPPLY VOLTAGE

20

15

10

5

10

8

6

4

2

0

4

8

12

16

20

0

4

8

12

16

20

Supply Voltage (V)

G008

G009

Figure 17.

Figure 18.

APPLICATION INFORMATION

Introduction

High-current gate-driver devices are required in switching-power applications for a variety of reasons. In order to

effect fast switching of power devices and reduce associated switching power losses, a powerful gate driver

employs between the PWM output of controllers and the gates of the power-semiconductor devices. Further,

gate drivers are indispensable when having the PWM controller directly drive the gates of the switching devices

is impossible. With advent of digital power, this situation will be often encountered since the PWM signal from the

digital controller is often a 3.3-V logic signal which is not capable of effectively turning on a power switch. A level-

shifting circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn

on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar

transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power

since they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive

functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by

locating the high-current driver physically close to the power switch, driving gate-drive transformers and

controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving

gate charge power losses into itself. Finally, emerging wide band-gap power device technologies such as GaN

based switches, which are capable of supporting very high switching frequency operation, are driving very

special requirements in terms of gate drive capability. These requirements include operation at low VDD voltages

(5 V or lower), low propagation delays and availability in compact, low-inductance packages with good thermal

capability. In summary gate-driver devices are extremely important components in switching power combining

benefits of high-performance low-cost component count and board-space reduction and simplified system design.

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UCC2751x Product Family

The UCC2751x family of gate-driver products (Table 6) represent Texas Instruments’ latest generation of single-

channel low-side high-speed gate-driver devices featuring high-source/sink current capability, industry best-in-

class switching characteristics and a host of other features (Table 7) all of which combine to ensure efficient,

robust and reliable operation in high-frequency switching power circuits.

Table 6. UCC2751x Product Family Summary

PART NUMBER

PACKAGE

PEAK CURRENT

(SOURCE/SINK)

INPUT THRESHOLD LOGIC

UCC27511DBV

UCC27512DRS

SOT-23, 6 pin

3 mm x 3 mm WSON, 6 pin

SOT-23, 5 pin

4-A/8-A

(Asymmetrical Drive)

CMOS/TTL-Compatible

(low voltage, independent of VDD

bias voltage)

(1)

UCC27516DRS

UCC27517DBV

UCC27518DBV

UCC27519DBV

(1)

4-A/4-A

(Symmetrical Drive)

SOT-23, 5 pin

CMOS

(follows VDD bias voltage)

SOT-23, 5 pin

(1) Visit www.ti.com for the latest product datasheet.

Table 7. UCC2751x Features and Benefits

FEATURE

BENEFIT

High Source and Sink Current Capability

4 A and 8 A (Asymmetrical) – UCC27511 and UCC27512

4 A and 4 A (Symmetrical) – UCC27511 and UCC27512

High current capability offers flexibility in employing UCC2751x

family of devices to drive a variety of power switching devices at

varying speeds

Best-in-class 13-ns (typ) Propagation delay

Extremely low pulse-transmission distortion

Expanded VDD Operating range of 4.5 V to 18 V

Flexibility in system design

Low VDD operation ensures compatibility with emerging wide band-

gap power devices such as GaN

Expanded Operating Temperature range of -40°C to 140°C

(See ELECTRICAL CHARACTERISTICS table)

Outputs are held low in UVLO condition, which ensures predictable

glitch-free operation at power up and power down

VDD UVLO Protection

Safety feature, especially useful in passing abnormal condition tests

during safety certification

Outputs held low when input pins (INx) in floating condition

Ability of input pins (and enable pin in UCC27518/9) to handle

voltage levels not restricted by VDD pin bias voltage

System simplification, especially related to auxiliary bias supply

architecture

Split output structure in UCC27511 and UCC27512 (OUTH, OUTL)

Allows independent optimization of turnon and turnoff speeds

Strong sink current (8 A) and low pulldown impedance (0.375 Ω) in

UCC27511 and UCC27512

High immunity to C x dV/dt Miller turnon events

Enhanced noise immunity, while retaining compatibility with

microcontroller logic-level input signals (3.3 V, 5 V) optimized for

digital power

CMOS/TTL compatible input-threshold logic with wide hysteresis in

UCC27511, UCC27512, UCC27516 and UCC27517

CMOS input threshold logic in UCC27518/9 (VIN_H – 70% VDD,

VIN_L – 30% VDD)

Well suited for slow input-voltage signals, with flexibility to program

delay circuits (RCD)

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Typical Application Diagram

Typical application diagrams of UCC27511 and UCC27512 devices are shown below illustrating use in non-

inverting and inverting driver configurations. The UCC27511 device features a unique split output configuration

where the gate-drive current is sourced through OUTH pin and sunk through OUTL pin. This unique pin

arrangement allows user to apply independent turn-on and turn-off resistors to the OUTH and OUTL pins

respectively and easily control the turn-on and turn-off switching dV/dt. This pin arrangement, along with the low

pulldown impedance of the output driver stage, is especially handy in applications where a high C x dV/dt Miller

turnon immunity is needed (such as with GaN power switches, SR MOSFETs etc) and OUTL pin can be directly

tied to the gate of the power device.

V+

VSOURCE

C2

4.5 V to 18 V

L1

UCC27511

VDD

UCC27512

D1

IN+

6

5

4

IN+

IN-

1

2

3

VOUT

IN+

1

2

3

IN+

IN-

GND

OUT

6

5

4

VOUT

Q1

R1

OUTH

OUTL

GND

VDD

+

4.5 V to 18 V

R2

C1

R3

C1

GND

V+

C2

Figure 19. Using Non-Inverting Input (IN- Is Grounded To Enable Output)

V+

VSOURCE

C2

4.5 V to 18 V

L1

UCC27512

UCC27511

VDD

D1

1

2

3

IN+

IN-

GND

OUT

6

5

4

IN-

R3

6

5

4

IN+

IN-

1

VOUT

Q1

R1

GND

VDD

4.5 V to 18 V

V+

IN-

OUTH

OUTL

2

3

+

C1

R2

C1

GND

C2

Figure 20. Using Inverting Input (IN+ Is Tied To VDD Enable Output)

NOTE

The UCC27516 features two ground pins, pin 2 and pin 5. TI recommends to tie both pins

together using PCB trace as close as possible to the device.

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VDD and Undervoltage Lockout

The UCC2751X devices have internal Undervoltage LockOut (UVLO) protection feature on the VDD pin supply

circuit blocks. Whenever the driver is in UVLO condition (for example when V_DDvoltage less than V_ONduring

power up and when V_DDvoltage is less than V_OFFduring power down), this circuit holds all outputs LOW,

regardless of the status of the inputs. The UVLO is typically 4.2 V with 300-mV typical hysteresis. This hysteresis

prevents chatter when low V_DDsupply voltages have noise from the power supply and also when there are

droops in the VDD bias voltage when the system commences switching and there is a sudden increase in I_DD

.

The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching

characteristics, is especially suited for driving emerging GaN wide band-gap power-semiconductor devices.

For example, at power up, the UCC2751X driver output remains LOW until the V_DDvoltage reaches the UVLO

threshold. The magnitude of the OUT signal rises with V_DDuntil steady-state V_DDis reached. In the non-inverting

operation (PWM signal applied to IN+ pin) shown in Figure 21, the output remains LOW until the UVLO threshold

is reached, and then the output is in-phase with the input. In the inverting operation (PWM signal applied to IN-

pin) shown in Figure 22 the output remains LOW until the UVLO threshold is reached, and then the output is out-

phase with the input. In both cases, the unused input pin must be properly biased to enable the output. Note that

in these devices the output turns to high state only if IN+ pin is high and IN- pin is low after the UVLO threshold

is reached.

Since the driver draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit

performance, two VDD-bypass capacitors are recommended to prevent noise problems. The use of surface-

mount components is highly recommended. A 0.1-μF ceramic capacitor should be located as close as possible to

the VDD to GND pins of the gate driver. In addition, a larger capacitor (such as 1 μF) with relatively low ESR

should be connected in parallel and close proximity, in order to help deliver the high-current peaks required by

the load. The parallel combination of capacitors should present a low impedance characteristic for the expected

current levels and switching frequencies in the application.

VDD Threshold

VDD

IN-

VDD Threshold

IN+

IN-

IN+

OUT

Figure 21. Power-Up (Non-Inverting Drive)

Operating Supply Current

Figure 22. Power-Up (Inverting Drive)

The UCC27511 and UCC27512 feature very low quiescent I_DDcurrents. The typical operating-supply current in

Undervoltage LockOut (UVLO) state and fully-on state (under static and switching conditions) are summarized in

Figure 5, Figure 6 and Figure 7. The I_DDcurrent when the device is fully on and outputs are in a static state (DC

high or DC low, refer Figure 7) represents lowest quiescent I_DDcurrent when all the internal logic circuits of the

device are fully operational. The total supply current is the sum of the quiescent I_DDcurrent, the average I_OUT

current due to switching, and finally any current related to pullup resistors on the unused input pin. For example,

when the inverting input pin is pulled low additional current is drawn from VDD supply through the pullup

resistors (refer to DEVICE INFORMATION for the device Block Diagram). Knowing the operating frequency (f_SW

and the MOSFET gate (Q_G) charge at the drive voltage being used, the average I_OUTcurrent can be calculated

as product of Q_Gand f_SW

)

.

A complete characterization of the IDD current as a function of switching frequency at different VDD bias

voltages under 1.8-nF switching load is provided in Figure 15. The strikingly linear variation and close correlation

with theoretical value of average I_OUTindicates negligible shoot-through inside the gate-driver device attesting to

its high-speed characteristics.

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Input Stage

The input pins of the UCC27511 and UCC27512 devices are based on a TTL/CMOS compatible input-threshold

logic that is independent of the VDD supply voltage. With typically high threshold = 2.2 V and typically low

threshold = 1.2 V, the logic-level thresholds can be conveniently driven with PWM control signals derived from

3.3-V and 5-V digital-power controllers. Wider hysteresis (typ 1 V) offers enhanced noise immunity compared to

traditional TTL-logic implementations, where the hysteresis is typically less than 0.5 V. These devices also

feature tight control of the input-pin threshold-voltage levels which eases system design considerations and

ensures stable operation across temperature. The very low input capacitance on these pins reduces loading and

increases switching speed.

The device features an important safety function wherein, whenever any of the input pins are in a floating

condition, the output of the respective channel is held in the low state. This is achieved using VDD-pullup

resistors on all the inverting inputs (IN- pin) or GND-pulldown resistors on all the non-inverting input pins (IN+

pin), (refer to DEVICE INFORMATION for the device Block Diagram).

The device also features a dual-input configuration with two input pins available to control the state of the output.

The user has the flexibility to drive the device using either a non-inverting input pin (IN+) or an inverting input pin

(IN-). The state of the output pin is dependent on the bias on both the IN+ and IN- pins. Refer to the input/output

logic truth table (Table 5) and the Typical Application Diagrams, (Figure 19 and Figure 20), for additional

clarification.

When an input pin has been chosen for PWM drive, the other input pin (the unused input pin) must be properly

biased in order to enable the output. As mentioned earlier, the unused input pin cannot remain in a floating

condition because whenever any input pin is left in a floating condition the output is disabled for safety purposes.

Alternatively, the unused input pin can effectively be used to implement an enable/disable function, as explained

below.

•

In order to drive the device in a non-inverting configuration, apply the PWM-control input signal to IN+ pin. In

this case, the unused input pin, IN-, must be biased low (such as tied to GND) in order to enable the output.

–

Alternately, the IN- pin is used to implement the enable/disable function using an external logic signal.

OUT is disabled when IN- is biased high and OUT is enabled when IN- is biased low.

In order to drive the device in an inverting configuration, apply the PWM-control input signal to IN- pin. In this

case, the unused input pin, IN+, must be biased high (such as tied to VDD) in order to enable the output.

–

Alternately, the IN+ pin is used to implement the enable/disable function using an external logic signal.

OUT is disabled when IN+ is biased low and OUT is enabled when IN+ is biased high.

Finally, note that the output pin can be driven into a high state ONLY when IN+ pin is biased high and IN-

input is biased low.

The input stage of the driver is preferably driven by a signal with a short rise or fall time. Caution must be

exercised whenever the driver is used with slowly varying input signals, especially in situations where the device

is located in a mechanical socket or PCB layout is not optimal:

•

High dI/dt current from the driver output coupled with board layout parasitics can cause ground bounce. The

differential voltage between input pins and GND is modified and triggers an unintended change of output

state because of fast 13-ns propagation delay, this can ultimately result in high-frequency oscillations, which

increases power dissipation and poses risk of damage.

•

1-V input-threshold hysteresis boosts noise immunity compared to most other industry standard drivers.

In the worst case, when a slow input signal is used and PCB layout is not optimal, adding a small capacitor (1

nF) between input pin and ground very close to the driver device may be necessary which helps to convert

the differential mode noise with respect to the input-logic circuitry into common-mode noise and avoid

unintended change of output state.

If limiting the rise or fall times to the power device is the primary goal, then an external resistance is highly

recommended between the output of the driver and the power device instead of adding delays on the input

signal. This external resistor has the additional benefit of reducing part of the gate charge related power

dissipation in the gate-driver device package and transferring it into the external resistor.

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Enable Function

As mentioned earlier, an enable/disable function is easily implemented in UCC27511 and UCC27512 using the

unused input pin. When IN+ is pulled down to GND or IN- is pulled down to VDD, the output is disabled. Thus

IN+ pin can be used like an enable pin that is based on active-high logic, while IN- can be used like an enable

pin that is based on active-low logic.

Output Stage

The output stage of the UCC27511 and UCC27512 devices are illustrated in Figure 23. OUTH and OUTL are

internally connected and pinned out as OUT pin in the UCC27512 . The UCC27511 and UCC27512 devices

feature a unique architecture on the output stage which delivers the highest peak-source current when it is most

needed during the Miller plateau region of the power switch turnon transition (when the power switch

drain/collector voltage experiences dV/dt). The device output stage features a hybrid pullup structure using a

parallel arrangement of N-Channel and P-Channel MOSFET devices. By turning on the N-Channel MOSFET

during a narrow instant when the output changes state from low to high, the gate-driver device is able to deliver a

brief boost in the peak-sourcing current enabling fast turn on.

VCC

R_OH

R_NMOS, Pull Up

Gate

Voltage

Boost

OUTH

OUTL

Anti Shoot-

Through

Circuitry

Input Signal

Narrow Pulse at

each Turn On

R_OL

Figure 23. UCC2751X Gate Driver Output Structure

The R_OHparameter (see ELECTRICAL CHARACTERISTICS) is a DC measurement and it is representative of

the on-resistance of the P-Channel device only, since the N-Channel device is turned on only during output

change of state from low to high. Thus the effective resistance of the hybrid pullup stage is much lower than what

is represented by R_OHparameter. The pulldown structure is composed of a N-Channel MOSFET only. The R_OL

parameter (see ELECTRICAL CHARACTERISTICS), which is also a DC measurement, is representative of true

impedance of the pull-down stage in the device. In UCC27511 and UCC27512, the effective resistance of the

hybrid pullup structure is approximately 2.7 x R_OL

.

The UCC27511 and UCC27512 are capable of delivering 4-A source, 8-A sink (asymmetrical drive) at VDD = 12

V. Strong sink capability in asymmetrical drive results in a very low pulldown impedance in the driver output

stage which boosts immunity against parasitic, Miller turnon (C x dV/dt turn on) effect, especially where low gate-

charge MOSFETs or emerging wide band-gap GaN-power switches are used.

An example of a situation where Miller turnon is a concern is synchronous rectification (SR). In SR application,

the dV/dt occurs on MOSFET drain when the MOSFET is already held in off state by the gate driver. The current

discharging the C_GDMiller capacitance during this dV/dt is shunted by the pulldown stage of the driver. If the

pulldown impedance is not low enough then a voltage spike can result in the V_GSof the MOSFET, which can

result in spurious turnon. This phenomenon is illustrated in Figure 24. UCC27511 and UCC27512 offers a best-

in-class, 0.375-Ω (typ) pulldown impedance boosting immunity against Miller turnon.

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V_DS

V_IN

Miller Turn-On Spike in V_GS

C_GD

Gate Driver

V_TH

V_GSof

MOSFET

R_G

C_OSS

I_SNK

ON OFF

OUTL

C_GS

V_IN

R_OL

V_DSof

MOSFET

Figure 24. Very Low Pull-Down Impedance In UCC27511, 4-A/8-A Asymmetrical Drive

(Output Stage Mitigates Miller Turnon Effect)

Figure 25 and Figure 26 illustrate typical switching characteristics of UCC27511.

Figure 25. Typical Turnon Waveform

(VDD = 10 V, C_L= 1 nF)

Figure 26. Typical Turnoff Waveform

(VDD = 10 V, C_L= 1 nF)

The driver-output voltage swings between VDD and GND providing rail-to-rail operation, thanks to the MOS-

output stage which delivers very low dropout. The presence of the MOSFET-body diodes also offers low

impedance to switching overshoots and undershoots. In many cases, external Schottky diode clamps are

eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current without either

damage to the device or logic malfunction.

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Power Dissipation

Power dissipation of the gate driver has two portions as shown in Equation 1.

P

= P + P

DC SW

DISS

(1)

The DC portion of the power dissipation is P_DC= I_Qx VDD where I_Qis the quiescent current for the driver. The

quiescent current is the current consumed by the device to bias all internal circuits such as input stage, reference

voltage, logic circuits, protections, and also any current associated with switching of internal devices when the

driver output changes state (such as charging and discharging of parasitic capacitances, parasitic shoot-through

etc). The UCC27511 and UCC27512 features very low quiescent currents (less than 1 mA, refer Figure 7) and

contains internal logic to eliminate any shoot-through in the output driver stage. Thus the effect of the P_DCon the

total power dissipation within the gate driver can be safely assumed to be negligible.

The power dissipated in the gate-driver package during switching (P_SW) depends on the following factors:

•

Gate charge required of the power device (usually a function of the drive voltage V_G, which is very close to

input bias supply voltage VDD due to low V_OHdrop-out).

•

Switching frequency.

Use of external gate resistors.

When a driver device is tested with a discrete, capacitive load calculating the power that is required from the bias

supply is fairly simple. The energy that must be transferred from the bias supply to charge the capacitor is given

by Equation 2.

1

2

E_G

=

C_LOADV_DD

2

Where

•

C_LOADis load capacitor

V_DDis bias voltage feeding the driver

(2)

There is an equal amount of energy dissipated when the capacitor is charged. This leads to a total power loss

given by Equation 3.

2

LOAD DD SW

P

= C

V

f

G

where

•

ƒ_SWis the switching frequency

(3)

The switching load presented by a power MOSFET/IGBT is converted to an equivalent capacitance by examining

the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus

the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF

states. Most manufacturers provide specifications of typical and maximum gate charge, in nC, to switch the

device under specified conditions. Using the gate charge Qg, determine the power that must be dissipated when

charging a capacitor which is calculated using the equation, Q_G= C_LOADx V_DD, to provide Equation 4 for power.

2

P

= C

V

f

= Q V f

g DD SW

G

LOAD DD SW

(4)

This power P_Gis dissipated in the resistive elements of the circuit when the MOSFET/IGBT is being turned on or

off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other half is

dissipated when the load capacitor is discharged during turnoff. When no external gate resistor is employed

between the driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the

use of external gate-drive resistors, the power dissipation is shared between the internal resistance of driver and

external gate resistor in accordance to the ratio of the resistances (more power dissipated in the higher

resistance component). Based on this simplified analysis, the driver power dissipation during switching is

calculated in Equation 5.

æ

ç

è

ö

R_OFF

R_ON

P_SW= 0.5´Q_G´ VDD´ f_SW

´

+

÷

R_OFF+ R_GATER_ON+ R_{GATE ø}

where

•

R_OFF= R_OL

R_ON(effective resistance of pull-up structure) = 2.7 x R_OL

(5)

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Low Propagation Delays

The UCC27511 and UCC27512 driver devices feature best-in-class input-to-output propagation delay of 13 ns

(typ) at VDD = 12 V, which promises the lowest level of pulse transmission distortion available from industry-

standard gate-driver devices for high-frequency switching applications. As seen in Figure 14, there is very little

variation of the propagation delay with temperature and supply voltage as well, offering typically less than 20-ns

propagation delays across the entire range of application conditions.

Thermal Information

The useful range of a driver is greatly affected by the drive-power requirements of the load and the thermal

characteristics of the package. In order for a gate driver to be useful over a particular temperature range the

package must allow for the efficient removal of the heat produced while keeping the junction temperature within

rated limits. The thermal metrics for the driver package is summarized in the section of the datasheet. For

detailed information regarding the table, please refer to the Application Note from Texas Instruments entitled IC

Package Thermal Metrics (SPRA953).

The UCC27511 and UCC27512 devices are offered in SOT-23, 6-pin package (DBV) and 3 mm × 3 mm, WSON

6-pin package with exposed thermal pad (DRS), respectively. The thermal information table summarizes the

thermal performance metrics related to the two packages. θ_JAmetric should be used for comparison of power

dissipation between different packages. Under identical power-dissipation conditions, the DRS package will

maintain a lower die temperature than the DBV. The ψ_JTand ψ_JBmetrics are used when estimating the die

temperature during actual application measurements.

The DRS is a better thermal package overall because it has the exposed thermal pad and is able to sink heat to

the PCB better than the DBV. The thermal pad in DRS package provides designers with an ability to create an

excellent heat removal sub-system from the vicinity of the device, thus helping to maintain a lower junction

temperature. This pad should be soldered to the copper on the printed circuit board directly underneath the

device package. Then a printed circuit board designed with thermal lands and thermal vias completes a very

efficient heat-removal subsystem. In such a design, the heat is extracted from the semiconductor junction

through the thermal pad, which is then efficiently conducted away from the location of the device on the PCB

through the thermal network. This helps to maintain a lower board temperature near the vicinity of the device

leading to an overall lower device-junction temperature.

In comparison, for the DBV package, heat removal occurs primarily through the leads of the device and the PCB

traces connected to the leads.

Note that the exposed pad in DRS package is not directly connected to any leads of the package, but is

electrically and thermally connected to the substrate of the device which is the ground of the device. TI

recommends to externally connect the exposed pads to GND in PCB layout for better EMI immunity.

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PCB Layout

Proper PCB layout is extremely important in a high-current fast-switching circuit to provide appropriate device

operation and design robustness. The UCC27511 and UCC27512 gate driver incorporates short-propagation

delays and powerful output stages capable of delivering large current peaks with very fast rise and fall times at

the gate of power switch to facilitate voltage transitions very quickly. At higher VDD voltages, the peak-current

capability is even higher (4-A/8-A peak current is at VDD = 12 V). Very high di/dt causes unacceptable ringing if

the trace lengths and impedances are not well controlled. The following circuit-layout guidelines are strongly

recommended when designing with these high-speed drivers.

•

Locate the driver device as close as possible to power device in order to minimize the length of high-current

traces between the output pins and the gate of the power device.

•

Locate the VDD-bypass capacitors between VDD and GND as close as possible to the driver with minimal

trace length to improve the noise filtering. These capacitors support high-peak current being drawn from VDD

during turnon of power MOSFET. The use of low inductance SMD components such as chip resistors and

chip capacitors is highly recommended.

•

The turnon and turnoff current-loop paths (driver device, power MOSFET and VDD bypass capacitor) should

be minimized as much as possible in order to keep the stray inductance to a minimum. High dI/dt is

established in these loops at two instances – during turnon and turnoff transients, which will induce significant

voltage transients on the output pin of the driver device and gate of the power switch.

•

Wherever possible, parallel the source and return traces, taking advantage of flux cancellation.

Separate power traces and signal traces, such as output and input signals.

Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of

the driver should be connected to the other circuit nodes such as source of power switch, ground of PWM

controller etc at one, single point. The connected paths should be as short as possible to reduce inductance

and be as wide as possible to reduce resistance.

•

Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals

during transition. The ground plane must not be a conduction path for any current loop. Instead the ground

plane must be connected to the star-point with one single trace to establish the ground potential. In addition

to noise shielding, the ground plane can help in power dissipation as well.

•

In noisy environments, tying the unused Input pin of UCC27511 and UCC27512 to VDD (in case of IN+) or

GND (in case of IN-) using short traces in order to ensure that the output is enabled and to prevent noise

from causing malfunction in the output may be necessary.

The UCC27512 device offers two ground pins, pin 2 and pin 5. Shorting the two pins together using the PCB

trace is extremely important. The shortest trace should be located as close as possible to the device.

22

Submit Documentation Feedback

Product Folder Links: UCC27511 UCC27512

UCC27511

UCC27512

www.ti.com

SLUSAW9D –FEBRUARY 2012–REVISED MAY 2013

REVISION HISTORY

Changes from Revision C (June 2012) to Revision D

Page

•

Added 0.05 to P_SWequation in the Power Dissipation section. .......................................................................................... 20

Changes from Revision B (March, 2012) to Revision C

Page

•

Added UCC27512 device throughout. .................................................................................................................................. 1

Added 6-Pin DRS package feature. ...................................................................................................................................... 1

Added UCC27512DRS ordering information. ....................................................................................................................... 3

Added OUT voltage ab max ratings for the UCC27512. ...................................................................................................... 4

Changed ESD ratings of Human Body Model, HBM from 2000 V to 4000 V. ...................................................................... 4

Changed ESD ratings of Charged Device Model, CDM SOT-23 from 500 V to 1000 V. ..................................................... 4

(1)

Added

............................................................................................................................................................................... 4

Added UCC27512 Thermal Information. .............................................................................................................................. 5

Added power dissipation conditions note to Thermal Information section. .......................................................................... 5

Added UCC27512 Functional Block Diagram. ...................................................................................................................... 9

Added DRS pinout for the UCC27512. ................................................................................................................................. 9

Added UCC27512 TERMINAL FUNCTIONS table. ............................................................................................................ 10

Added UCC27512 application diagrams. ............................................................................................................................ 15

Added Typical Application Diagram note. ........................................................................................................................... 15

Added Output stage text. .................................................................................................................................................... 18

Added Thermal Information description. ............................................................................................................................. 21

Added PCB layout bullet. .................................................................................................................................................... 22

(1) Values are verified by characterization on bench.

Submit Documentation Feedback

23

Product Folder Links: UCC27511 UCC27512

PACKAGE MATERIALS INFORMATION

www.ti.com

29-May-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UCC27511DBVR

UCC27511DBVT

UCC27512DRSR

UCC27512DRST

SOT-23

SON

DBV

DRS

6

3000

250

179.0

330.0

180.0

8.4

3.2

3.3

3.2

3.3

1.4

1.1

4.0

8.0

Q3

Q2

3000

250

12.4

12.0

SON

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

29-May-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

UCC27511DBVR

UCC27511DBVT

UCC27512DRSR

UCC27512DRST

SOT-23

SON

DBV

DRS

6

3000

250

203.0

367.0

210.0

203.0

367.0

185.0

35.0

3000

250

SON

Pack Materials-Page 2

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型号：	UCC27512DRSR
厂家：	TEXAS INSTRUMENTS
描述：	Single-Channel High-Speed Low-Side Gate Driver (with 4-A Peak Source and 8-A Peak Sink) 单通道高速低侧栅极驱动器（具有4 -A峰值源和8 -A峰汇）驱动器栅极栅极驱动
文件：	总33页 (文件大小：1615K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC27512DRSR [TI]

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