UCC28064ADR [TI]

具有高轻负载效率的 Natural Interleaving™ 转换模式 PFC 控制器 | D | 16 | -40 to 125;


型号：	UCC28064ADR
厂家：	TEXAS INSTRUMENTS
描述：	具有高轻负载效率的 Natural Interleaving™ 转换模式 PFC 控制器 \| D \| 16 \| -40 to 125 控制器功率因数校正
文件：	总56页 (文件大小：5034K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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UCC28064A

ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

具有较高的轻负载效率的 UCC28064A Natural Interleaving™ 转换模式

PFC 控制器

1 特性

3 说明

•

降低了输入滤波器和输出电容器纹波电流

与之前的同类产品相比，UCC28064A 交错式 PFC 控

制器具有更高的功率额定值。该器件采用了 Natural

Interleaving™ 技术。两个通道均作为主通道运行（即

没有从通道），而且这两个通道同步至同一频率。这种

方法可以实现更快的响应、出色的相间导通时间匹配以

及每个通道的转换模式。该器件具有突发模式功能，可

获得较高的轻负载效率。由于具有突发模式，因此在轻

负载运行期间无需关闭 PFC 即可实现待机功率目标。

而且，由于具有该模式，在与 UCC25630x LLC 控制

器和 UCC24624 同步整流器控制器配对使用时，该器

件无需使用辅助反激式转换器。

–

为了实现更高系统可靠性和更小大容量电容器而

减少的电流纹波

–

缩小的电磁干扰 (EMI) 滤波器尺寸

•

高轻负载效率

–

具有输入电压补偿功能的用户可调节相位管理

具有可调突发阈值的突发模式

有助于符合 EUP Lot6 Tier II、CoC Tier II 和

DOE Level VI 标准

•

无传感器电流整形简化了电路板布局并提升了效率

输入线路前馈可实现快速线路瞬态响应

浪涌安全电流限制：

器件信息⁽¹⁾

–

在浪涌期间防止 MOSFET 导通

器件型号

UCC28064A

封装

封装尺寸（标称值）

消除输出整流器中的 CCM 操作和反向恢复事件

SOIC (16)

9.90mm x 3.91mm

•

采用 16 引脚 SOIC 封装，工作温度范围为 –40°C

至 +125°C

使用 UCC28064A 及其 WEBENCH^®电源设计器创

建定制设计

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

P_OUT= 600 W

V_OUT= 40 V

1-phase TM

2 应用

•

高清、超高清和 LED 电视

1-phase CCM

一体式计算机

游戏

适配器

2-phase TM Interleaved

家用音频系统

120

170

220

270

Input Voltage (V)

简化应用

UCC28064A

R_ZCDB

R_ZCDA

ZCD_B

ZCD_A

VREF

GDA

VOUT

L_B

L_A

VSENSE

TSET

PHB Threshold

PHB

PGND

VCC

VSENSE

HVSEN

VCC

COMP

GDB

VINAC

HVSEN

AGND

VRECT

R_CS

HVSEN

BRST

Burst Threshold

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSC60

UCC28064A

ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）.............................................................. 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 5

7.6 Typical Characteristics.............................................. 9

Detailed Description ............................................ 13

8.1 Overview ................................................................. 13

8.2 Functional Block Diagram ....................................... 14

8.3 Feature Description................................................. 15

8.4 Device Functional Modes........................................ 36

Application and Implementation ........................ 37

9.1 Application Information............................................ 37

9.2 Typical Application .................................................. 37

10 Power Supply Recommendations ..................... 45

11 Layout................................................................... 46

11.1 Layout Guidelines ................................................. 46

11.2 Layout Example .................................................... 47

11.3 Package Option Addendum .................................. 48

12 器件和文档支持 ..................................................... 49

12.1 器件支持................................................................ 49

12.2 文档支持................................................................ 49

12.3 接收文档更新通知 ................................................. 49

12.4 社区资源................................................................ 49

12.5 商标....................................................................... 49

12.6 静电放电警告......................................................... 49

12.7 Glossary................................................................ 49

13 机械、封装和可订购信息....................................... 50

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision A (October 2018) to Revision B

Page

•

已更改更改了“简化应用”示意图.............................................................................................................................................. 1

UCC28064A

www.ti.com.cn

ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

5 说明（续）

扩展的系统级保护特性包括输入欠压和压降恢复、输出过压、开环、过载、软启动、相位故障检测以及热关断保

护。附加的失效防护过压保护 (OVP) 特性可防止到一个中间电压的短路，如果没有检测到此短路的话，有可能导致

非常严重的器件故障。该器件具有高级非线性增益，可针对线路和负载瞬态事件提供快速而平滑的响应。特殊的线

路压降处理可避免严重的电流中断。在突发模式期间，不发生切换时偏置电流会大幅降低，从而提高了待机性能。

6 Pin Configuration and Functions

D Package

16-Pin SOIC

Top View

ZCD_B

VSENSE

TSET

ZCD_A

VREF

GDA

PHB

PGND

VCC

COMP

AGND

VINAC

HVSEN

GDB

BRST

Pin Functions

I/O

DESCRIPTION

NAME

AGND

BRST

COMP

NO.

Analog ground

Burst mode threshold input

Error amplifier output

Current sense input

GDA

Phase A gate driver output

Phase B gate driver output

High voltage output sense

Power ground

GDB

HVSEN

PGND

PHB

Phase B enable disable threshold input

Timing set

TSET

VCC

Bias supply input

VINAC

VSENSE

VREF

ZCDA

ZCDB

Input AC voltage sense

Error amplifier input

Voltage reference output

Phase A zero current detection input

Phase B zero current detection input

UCC28064A

ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

All voltages are with respect to GND, −40°C < T_J= T_A< 125°C, currents are positive into and negative out of the specified

terminal, unless otherwise noted.

MIN

−0.5

–0.5

MAX UNIT

VCC⁽¹⁾

COMP⁽²⁾, PHB, HVSEN⁽³⁾, VINAC⁽³⁾, VSENSE⁽³⁾, TSET, BRST

Continuous input voltage

Continuous input current

ZCDA, ZCDB

CS⁽⁴⁾

GDA, GDB⁽⁵⁾

VCC + 0.3

VCC

±5

ZCDA, ZCDB

GDA, GDB⁽⁵⁾

VREF

–25

–2

Peak input current

–30

–40

°C

T_J

Operating junction temperature

Soldering 10 s

125

260

150

T_SOL

T_stg

Storage temperature

–65

(1) Voltage on VCC is internally clamped. VCC may exceed the continuous absolute maximum input voltage rating if the source is current

limited below the absolute maximum continuous VCC input current level.

(2) In normal use, COMP is connected to capacitors and resistors and is internally limited in voltage swing.

(3) In normal use, VINAC, VSENSE, and HVSEN are connected to high-value resistors and are internally limited in negative-voltage swing.

Although not recommended for extended use, VINAC, VSENSE, and HVSEN can survive input currents as high as -10mA from negative

voltage sources, and input currents as high as +0.5mA from positive voltage sources.

(4) In normal use, CS is connected to a series resistor to limit peak input current during brief system line-inrush conditions. In these

situations, negative voltage on CS may exceed the continuous absolute maximum rating.

(5) No GDA or GDB current limiting is required when driving a power MOSFET gate. However, a small series resistor may be required to

damp resonant ringing due to stray inductance.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

UCC28064A

www.ti.com.cn

ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

7.3 Recommended Operating Conditions

All voltages are with respect to GND, −40°C < T_J= T_A< 125°C, currents are positive into and negative out of the specified

terminal, unless otherwise noted.

MIN

MAX

UNIT

VCC input voltage from a low-impedance source

VCC input current from a high-impedance source

VINAC input voltage

VREF load current

–2

kΩ

ZCDA, ZCDB series resistor

66.5

0.8

TSET resistor to program PWM on-time

HVSEN input voltage

400

4.5

PHB Phase management threshold voltage

BRST Burst mode threshold voltage

V_PHB- 0.6 V

7.4 Thermal Information

UCC28064A

SOIC (D)

16 PINS

91.6

THERMAL METRIC

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance⁽¹⁾

Junction-to-case (top) thermal resistance⁽²⁾

Junction-to-board thermal resistance⁽³⁾

Junction-to-top characterization parameter⁽⁴⁾

Junction-to-board characterization parameter⁽⁵⁾

°C/W

52.1

48.6

14.9

ψ_JB

48.3

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard

test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(4) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(5) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

7.5 Electrical Characteristics

At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 0V, BRST = 0V, R_TSET= 133 kΩ,

all voltages are with respect to GND, all outputs unloaded, −40°C < T_J= T_A< 125°C, and currents are positive into and

negative out of the specified terminal, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VCC BIAS SUPPLY

VCC_SHUNT

I_VCC(UVLO)

I_VCC(stby)

I_VCC(on)

VCC shunt voltage⁽¹⁾

VCC current, UVLO

VCC current, disabled

VCC current, enabled

I_VCC= 10 mA

125

150

200

210

VCC = 9.3 V prior to turn on

VSENSE = 0 V

µA

VSENSE = 2 V

VCC current burst mode no

switching

I_VCC(BURST)

V_COMP< V_BURST

650

850

µA

UNDERVOLTAGE LOCKOUT (UVLO)

VCC_ON

VCC turnon threshold

VCC turnoff threshold

UVLO Hysteresis

VCC rising

9.45

8.8

10.35

9.6

11.1

10.7

0.9

VCC_OFF

VCC falling

ΔVCC_UVLO

REFERENCE

VCC_ON- VCC_OFF

0.68

0.8

(1) Excessive VCC input voltage and current will damage the device. This clamp will not protect the device from an unregulated bias supply.

If an unregulated bias supply is used, a series-connected Fixed Positive-Voltage Regulator such as the UA78L15A is recommended.

See the Absolute Maximum Ratings table for the limits on VCC voltage, current, and junction temperature.

UCC28064A

ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

Electrical Characteristics (continued)

At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 0V, BRST = 0V, R_TSET= 133 kΩ,

all voltages are with respect to GND, all outputs unloaded, −40°C < T_J= T_A< 125°C, and currents are positive into and

negative out of the specified terminal, unless otherwise noted.

PARAMETER

TEST CONDITIONS

I_VREF= 0 mA

MIN

5.82

-6

TYP

6.00

-1

MAX

UNIT

V_REF

VREF output voltage, no load

VREF change with load

VREF change with VCC

6.18

ΔV_{REF_LOAD}

ΔV_{REF_VCC}

ERROR AMPLIFIER

0 mA ≤ I_VREF≤ −2 mA

12 V ≤ VCC ≤ 20 V

VSENSE input regulation

voltage

VSENSEreg25

T_A= 25°C

5.85

6.15

VSENSE input regulation

voltage

VSENSEreg

I_VSENSE

5.82

100

6.18

150

VSENSE input bias current

In regulation

VSENSE enable threshold,

rising

V_ENAB

1.15

1.25

1.35

VSENSE enable hysteresis

COMP high voltage, clamped

COMP low voltage, saturated

VSENSE to COMP

0.02

4.70

0.07

4.95

0.03

0.15

5.10

V_{COMP_CLMP}

V_{COMP_SAT}

VSENSE = VSENSEreg – 0.3 V

VSENSE = VSENSEreg + 0.3 V

0.99(VSENSEreg) < VSENSE <

0.125

g_M1

µS

transconductance, small signal 1.01(VSENSEreg), COMP = 3 V

VSENSE high-going threshold

to enable COMP large signal

gain, percent

V_{SENSE_gM2_SIN}

Relative to VSENSEreg, COMP = 3 V

3.25

6.75

VSENSE low-going threshold to

enable COMP large signal gain, Relative to VSENSEreg, COMP = 3 V

percent

V_{SENSE_gM2_SO}

URCE

–6.75

−5

−3.25

VSENSE to COMP

transconductance, large signal

VSENSE = VSENSEreg – 0.4 V , COMP =

3 V

g_{M2_SOURCE}

g_{M2_SINK}

I_{COMP_SOURCE_}

210

290

370

µS

VSENSE to COMP

transconductance, large signal

VSENSE = VSENSEreg + 0.4 V, COMP =

3 V

COMP maximum source current VSENSE = 5 V, COMP = 3 V

-170

1.6

-125

-80

2.4

4.8

µA

kΩ

µA

MAX

R_COMPDCHG

COMP discharge resistance

HVSEN = 5.2 V, COMP = 3 V

COMP discharge current during VSENSE = 5 V, VINAC = 0.3 V, COMP =

Dropout

I_DODCHG

V_{LOW_OV}

3.2

VSENSE overvoltage threshold,

rising

Relative to VSENSEreg

6.5

-3

-2

9.5

-1.5

12.7

ΔV_{LOW_OV_HYS}

VSENSE overvoltage hysteresis Relative to V_{LOW_OV}

VSENSE 2nd overvoltage

Relative to VSENSEreg

threshold, rising

V_{HIGH_OV}

9.3

SOFT START

V_SSTHR

COMP Soft-Start threshold,

VSENSE = 1.5 V

falling

I_SS,FAST

I_SS,SLOW

COMP Soft-Start current, fast

COMP Soft-Start current, slow

SS-state, V_ENAB< VSENSE < VREF/2

-170

-20

-125

-16

-80

µA

SS-state, VREF/2 < VSENSE < 0.88VREF

-11.5

VSENSE End-of-Soft-Start

threshold factor

K_EOSS

Percent of VSENSEreg

96.5%

98.3%

99.8%

OUTPUT MONITORING

HVSEN threshold to

overvoltage fault

V_{HV_OV_FLT}

HVSEN rising

HVSEN falling

4.64

4.45

4.87

4.67

5.1

4.8

HVSEN threshold to

overvoltage clear

V_{HV_OV_CLR}

GATE DRIVE

UCC28064A

www.ti.com.cn

ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

Electrical Characteristics (continued)

At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 0V, BRST = 0V, R_TSET= 133 kΩ,

all voltages are with respect to GND, all outputs unloaded, −40°C < T_J= T_A< 125°C, and currents are positive into and

negative out of the specified terminal, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

12.4

8.8

MAX

UNIT

V_{GDx_H}

R_{GDx_H}

V_{GDx_L}

R_{GDx_L}

GDA, GDB output voltage, high I_GDA, I_GDB= −100 mA

GDA, GDB on-resistance, high I_GDA, I_GDB= −100 mA

10.7

16.7

0.32

3.2

GDA, GDB output voltage, low

GDA, GDB on-resistance, low

I_GDA, I_GDB= 100 mA

0.18

GDA, GDB output voltage high,

clamped

V_{GDx_H_VCCH}

V_{GDx_H_VCCL}

V_{GDx_L_UVLO}

VCC = 20 V, I_GDA, I_GDB= −5 mA

VCC = 12 V, I_GDA, I_GDB= −5 mA

VCC = 3.0 V, I_GDA, I_GDB= 2.5 mA

11.8

13.5

10.5

100

11.5

200

GDA, GDB output voltage high,

low VCC

GDA, GDB output voltage,

UVLO

t_{GDx_RISE}

t_{GDx_FALL}

Rise time

Fall time

1 V to 9 V, C_LOAD= 1 nF

9 V to 1 V, C_LOAD= 1 nF

ZERO CURRENT DETECTOR

ZCDA, ZCDB voltage threshold,

V_{ZCDx_TRIG}

0.8

1.5

1.2

1.9

falling

ZCDA, ZCDB voltage threshold,

rising

V_{ZCDx_ARM}

1.7

V_{ZCDx_CLMP_H}

V_{ZCDx_CLMP_L}

I_ZCDx

ZCDA, ZCDB clamp, high

ZCDA, ZCDB clamp, low

I_ZCDA= +2 mA, I_ZCDB= +2 mA

2.6

-0.40

-0.5

−0.2

3.4

I_ZCDA= −2 mA, I_ZCDB= −2 mA

ZCDA, ZCDB input bias current ZCDA = 1.4 V, ZCDB = 1.4 V

0.5

µA

ZCDA, ZCDB delay to GDA,

GDB outputs

From ZCDx input falling to 1 V to

respective gate drive output rising 10%

t_{ZCDx_DEL}

100

t_{ZCDx_BLNK}

ZCDA, ZCDB blanking time

From GDx rising to GDx falling

100

CURRENT SENSE

CS input bias current, dual-

phase

I_CS

At rising threshold

-200

-0.22

-166

-0.2

-120

-0.18

-0.149

-0.002

100

µA

CS current-limit rising threshold,

dual-phase

V_{CS_DPh}

V_{CS_SPh}

V_{CS_RST}

t_{CS_DEL}

CS current-limit rising threshold,

single-phase

PHB = 6 V

-0.183

-0.025

-0.166

–0.015

CS current-limit reset falling

threshold

From CS exceeding threshold−0.05 V to

GDx dropping 10%

CS current-limit response time

CS blanking time

t_{CS_BLNK}

From GDx rising and falling edges

100

VINAC INPUT

VINAC input bias current,

above brownout

I_VINAC

VINAC = 2 V

-0.5

1.33

500

1.45

640

0.5

1.6

µA

V_BOTHR

t_BODLY

VINAC brownout threshold

VINAC below the brownout threshold for

the brownout filter time

VINAC brownout filter time

810

VINAC above the brownout threshold for

the brownout reset time after Brown out

event

t_BORST

VINAC brownout reset time

300

450

600

VINAC brownout hysteresis

current

I_BOHYS

V_DODET

t_DODLY

VINAC = 1 V for > t_BODLY

VINAC falling

1.6

0.310

3.5

1.95

0.35

2.25

0.38

µA

VINAC dropout detection

threshold

VINAC below the dropout detection

threshold for the dropout filter time

VINAC dropout filter time

UCC28064A

ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

Electrical Characteristics (continued)

At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 0V, BRST = 0V, R_TSET= 133 kΩ,

all voltages are with respect to GND, all outputs unloaded, −40°C < T_J= T_A< 125°C, and currents are positive into and

negative out of the specified terminal, unless otherwise noted.

PARAMETER

TEST CONDITIONS

VINAC rising

MIN

TYP

MAX

UNIT

V_DOCLR

VINAC dropout clear threshold

0.67

0.71

0.75

PULSE-WIDTH MODULATOR

On-time factor, two phases

operating, low VINAC_PK

K_TL

VINAC=1.6V, VCOMP=4V⁽²⁾

3.0

0.36

6.1

4.15

0.43

8.3

5.3

0.5

µs/V

µs

On-time factor, two phases

operating, high VINAC_PK

K_TH

VINAC= 5V, VCOMP = 4V⁽²⁾

On-time factor, single-phase

operating, low VINAC_PK

K_TSL

K_TSH

t_{ZCC_I}

t_{ZCC_II}

VINAC=1.6V, VCOMP = 1.5V, PHB = 2V⁽²⁾

VINAC= 5V, VCOMP = 1.5V, PHB=2V⁽²⁾

COMP = 0.5 V, VINAC = 0.1 V

COMP = 0.5 V, VINAC = 1.6 V

10.5

1.01

32.2

1.5

On-time factor, single-phase

operating, high VINAC_PK

0.73

0.87

23.6

1.1

Zero-crossing distortion

correction additional on time

Zero-crossing distortion

correction additional on time

0.7

µs

R_TSET= 133 kΩ, VCOMP = 0.3, VINAC = 3

t_MIN

Minimum Switching period

PWM restart time

1.9

160

2.7

210

3.5

265

µs

V⁽²⁾

t_START

t_{ONMAX_L}

ZCDA = ZCDB = 2 V⁽³⁾

Maximum FET on time at low

VINAC

VSENSE = 5.8 V, VINAC=1.6V

15.1

20.4

26.2

Maximum FET on time at High

VINAC

t_{ONMAX_H}

VSENSE = 5.8 V, VINAC= 5V

VSENSE = 5.8V, VINAC=1.6V, PHB = 6V

VSENSE = 5.8V, VINAC=5 V, PHB = 6V

VSENSE = 5.8 V, VINAC=1.6V

VSENSE = 5.8 V, VINAC= 5V

BRST = 1V, VINAC = 1.5 V

PHB = 3V, VINAC = 2.5 V

1.5

11.8

1.37

–6

2.4

20.2

1.95

µs

Maximum FET on time at low

VINAC, Single Phase operation.

t_{ONMAX_SL}

Maximum FET on time at hgih

VINAC, single phase operation

t_{ONMAX_SH}

1.66

Phase B to phase A on-time

matching error

Δt_{ONMAX_AB_L}

Δt_{ONMAX_AB_H}

ΔV_{BRST_HYST}

ΔV_{PHB_HYST}

I_{PHB_RANGE}

I_{BRST_RANGE}

Phase B to phase A on-time

matching error

-6

BRST Hysteresis, COMP

voltage rising

150

µA

PHB Hysteresis COMP voltage

rising

210

4.1

3.3

400

PHB pin sourced current when

high input voltage

VINAC = 3.75V, PHB = 2V

BRST pin sourced current when

high input voltage

VINAC = 3.75V, BRST = 2V

PHB = 2V, BRST = 2V

V_{VINAC _}

RANGE_THF

VINAC range falling threshold

2.95

300

3.15

350

VINAC range Hysteresis at

rising edge

ΔV_{INAC_RANGE}

PHB = 2V, BRST=2V

THERMAL SHUTDOWN

T_J

Thermal shutdown temperature Temperature rising⁽⁴⁾

160

140

°C

Thermal restart temperature

Temperature falling⁽⁴⁾

(2) Gate drive on-time is proportional to (VCOMP – 0.125 V). The on-time proportionality factor, KT, scales linearly with the value of RTSET

and is different in two-phase and single-phase modes. The minimum switching period is proportional to RTSET.

(3) An output on-time is generated at both GDA and GDB if both ZCDA and ZCDB negative-going edges are not detected for the restart

time. In single-phase mode, the restart time applies for the ZCDA input and the GDA output.

(4) Thermal shutdown occurs at temperatures higher than the normal operating range. Device performance above the normal operating

temperature is not specified or assured.

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7.6 Typical Characteristics

V_VCC= 16 V, V_AGND= V_PGND= 0 V, V_VINAC= 3 V, V_VSENSE= 6 V, V_HVSEN= 3 V, V_PHB= 0 V, R_TSET= 133 kΩ; all voltages are

with respect to GND, all outputs unloaded, T_J= 25°C, and currents are positive into and negative out of the specified terminal,

unless otherwise noted.

1.5

1.49

1.48

1.47

1.46

1.45

1.44

1.43

1.42

1.41

1.4

66.5kW

130kW

266kW

1.39

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7

VINAC (V)

-40

-20

T_j-Temperature (°C)

100 120 140

D100

D101

图 1. RTSET Resistance and Zero-Crossing Distortion

图 2. VINAC Brownout Detection Threshold

Correction Additional On Time

6.05

6.04

6.03

6.02

6.01

1.9475

VREF (V)

VREF_LOAD (V)

1.9425

1.9375

1.9325

1.9275

1.9225

1.9175

1.9125

1.9075

1.9025

1.8975

5.99

5.98

5.97

5.96

5.95

-40

-20

T_j-Temperature (°C)

100 120 140

-40

-20

T_j-Temperature (°C)

100 120 140

D102

D103

图 3. VINAC Brownout Hysteresis Current

图 4. VREF Output Voltage

10.8

10.6

10.4

10.2

0.85

0.84

0.83

0.82

0.81

0.8

VCCON (V)

VCCOFF (V)

9.8

0.79

0.78

0.77

0.76

0.75

9.6

9.4

9.2

-40

-20

T_j-Temperature (°C)

100 120 140

-40

-20

T_j-Temperature (°C)

100 120 140

D104

D105

图 5. UVLO On Off Thresholds

图 6. UVLO Hysteresis

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Typical Characteristics (接下页)

V_VCC= 16 V, V_AGND= V_PGND= 0 V, V_VINAC= 3 V, V_VSENSE= 6 V, V_HVSEN= 3 V, V_PHB= 0 V, R_TSET= 133 kΩ; all voltages are

with respect to GND, all outputs unloaded, T_J= 25°C, and currents are positive into and negative out of the specified terminal,

unless otherwise noted.

150

Low OV

Clear

100

Low OV

Trigger

Transconduction

55 ꢀS

0.1

œ50

œ100

œ150

I_VCC(ON)

I_VCC(BURST)

I_VCC(UVLO)

0.01

5.0 5.2 5.4 5.6 6.8 6.0 6.2 6.4 6.6 6.8 7.0

-40

-20

T_j-Temperature(°C)

100 120 140

VSENSE Input Voltage (V)

D106

Soft-start period completed

图 7. VCC Bias Supply Current

图 8. Error Amplifier Output Current vs Input Voltage

300

250

200

150

100

5.9 V < V_VSENSE< 6.1 V

5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0

−40

−20

100

120

V_VSENSE− Input Voltage (V)

T_J− Temperature (°C)

G005

G006

图 9. Error Amplifier Transconductance vs VSENSE

图 10. Error Amplifier Transconductance vs Temperature

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Typical Characteristics (接下页)

V_VCC= 16 V, V_AGND= V_PGND= 0 V, V_VINAC= 3 V, V_VSENSE= 6 V, V_HVSEN= 3 V, V_PHB= 0 V, R_TSET= 133 kΩ; all voltages are

with respect to GND, all outputs unloaded, T_J= 25°C, and currents are positive into and negative out of the specified terminal,

unless otherwise noted.

3.0

2.5

2.0

1.5

1.0

0.5

V_VSENSE= 6.2 V

GD Voltage:

V_CC= 20 V

V_VSENSE= 6.1 V

GD Source Current:

V_CC= 20 V

V_CC= 12 V

V_VSENSE= 5.9 V

−5

V_VSENSE= 5.8 V

−10

−15

−20

-0.5

-1.0

-2

100

150

200

250

300

350

V_COMP− Output Voltage (V)

Time (ns)

G007

C_LOAD= 4.7 nF

图 11. Error Amplifier Output Current vs Output Voltage

图 12. Gate Drive Rising vs Time

3.0

2.5

2.0

1.5

1.0

0.5

GD Output:

T_J= –40°C

GD Sink Current:

V_CC= 20 V

T_J= +25°C

V_CC= 12 V

T_J= +125°C

GD Voltage:

V_CC= 20 V

-0.5

-1.0

ZCD Input Voltage

V_CC= 12 V

-2

-1

-2

100

120 140

-25

100

150

200

250

300

Time (ns)

C_LOAD= 4.7 nF

图 13. Gate Drive Falling vs Time

C_LOAD= 4.7 nF

图 14. Gate Drive Rising and Delay From ZCD Input vs Time

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Typical Characteristics (接下页)

V_VCC= 16 V, V_AGND= V_PGND= 0 V, V_VINAC= 3 V, V_VSENSE= 6 V, V_HVSEN= 3 V, V_PHB= 0 V, R_TSET= 133 kΩ; all voltages are

with respect to GND, all outputs unloaded, T_J= 25°C, and currents are positive into and negative out of the specified terminal,

unless otherwise noted.

500

400

300

200

100

CS Input

Voltage

GD Output:

T_J= -40°C

T_J= +25°C

T_J= +125°C

-100

-200

-300

-2

-25

100

150

200

250

300

Time (ns)

C_LOAD= 4.7 nF

图 15. Gate Drive Falling and Delay From CS Input vs Time

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8 Detailed Description

8.1 Overview

Transition mode (TM) control is a popular choice for the boost power factor correction topology at lower power

levels. Some advantages of this control method are its lower complexity in achieving high power factor and

because lower cost boost diode with higher reverse recovery current specification may be used. In TM control

MOSFET is turned on always when no current is flowing into diode. Interleaved Transition Mode Control retains

this benefit and generally extends the applicability up to much higher power levels while simultaneously

conferring the interleaving benefits of reduced input and output ripple current and system thermal optimization.

In UCC28064A, burst mode was introduced respect its predecessor (UCC28063) to achieve higher efficiency in

light load conditions. Input voltage feed-forward and threshold adjustment is also available to ensure the user can

optimize performance across line and load conditions. When operating single phase on time of the switching

phase is doubled with the purpose of compensating the missing power from the not switching phase. In this way

for the same COMP value the converter should provide the same output power regardless if operating single

phase mode or dual phase mode. Unfortunately this is not always the case. Component variations and

MOSFETs turn-off delay can lead to big differences (for the same COMP voltage) in the output power delivery.

The Phase Management and Light-Load Operation section will discuss some ways to deal with the variations.

Line voltage feed-forward compensation provides several benefits: it maintains constant bandwidth of the control

loop versus line voltage variation, avoids high current in the MOSFETs, inductors, and line filter when line

transitions from low to high happens, and helps to keep simple Phase Management control because the COMP

pin voltage is almost proportional to Load. Burst Mode enables high efficiency at light load and soft-on and soft-

off in burst mode reduces risk of audible noise. The optimal load current at which the converter should enter

burst mode can be different for different input voltages. These thresholds can be customized by the user.

Interleaving control and phase management facilitates high efficiency 80+ and Energy Star designs with reduced

input and output ripple. The Natural Interleaving method allows TM operation and achieves 180 degrees between

the phases by On-time management. Moreover Natural interleaving method does not rely on tight tolerance

requirements on the inductors. Negative current sensing is implemented on the total input current instead of just

the MOSFET current which prevents MOSFET switching during inrush surges or in any mode where the inductor

current may enter in continuous conduction mode (CCM). This prevents reverse recovery conduction events

between the MOSFET and output rectifier.

Independent output voltage sense circuits with their separate fault management behaviors provide a high degree

of redundancy against PFC stage over-voltage. Brownout, over voltage protection on HVSEN pin (HVSENSE

OV), under voltage lockout (UVLO), and device over-temperature faults will all cause a complete Soft-Start cycle.

Other faults such as short duration AC Drop-Out, minor over-voltage or cycle-by-cycle over-current cause a live

recovery process to initiate by pulling down the COMP pin or by terminating the pulses early.

The error amplifier transconductance is designed to allow smaller compensation components and optimum

transient response for large changes in line or load. The Soft-Start process is carefully optimized. A complete

Soft-Start is implemented. It is dependent on the output voltage sense to speed up start-up from low AC line and

to minimize the effect of excessive capacitance on the COMP pin during start-up into no-load. If some faults

events are triggered COMP pin is fast pulled down to zero. This complete discharge of COMP aids with

preventing excessive currents on recovery from an AC Brown-Out event.

UCC28064A

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8.2 Functional Block Diagram

CS_OPEN

VCC_ON/

VCCO_FF

Overcurrent

UVLO

OPEN

100ns

Blanking

VCC

167mV

Hyst. 15mV

TSD

CS_OPEN

TSET_FAULT

UVLO

HVSEN_OV

BROWNOUT

200mV

Hyst. 15mV

COMP_DSCHG

PHB_OFF

DISCH_RST

Brownout

t_BODLY

V_BOTHR

VINAC

BROWNOUT

5ms

Delay

DROPOU

VAC_PK

0.7V /

0.35V

2ꢀA

t_BORST

PHB_OFF

PEAK

DETECT

COMP_DSCHG

VREF

STOP_GDB

HIGH_OV

VAC_PK

STOP_GDA

VFF_ITSET

TSET

VFF

12.4V

Max

TSET

ZCDA

ZCDB

PHB_OFF

STOP_GDA

TSET_FAULT

Phase A

On Time Control

t_ON

VFF_ITSET

V_{COMP_II}

1.7V /

SW_EN

GDA

100ns

Blankin

Modulation

TRIGGE

ZCA

Crossove

PGND

Notch

Reductio

Interleaving

Control

VINAC

1.7V /

12.4V Max

100ns

Blanking

TRIGGE

ZCB

t_ONModulation

SW_E

GDB

V_{COMP_II}

Phase B

On Time Control

STOP_GDB

VFF_ITSET

PGND

20mV /

40mV

3ꢀA

DISCH_RST

HLN

3.15V

2.8V

4ꢀ

BRST

V_{COMP_II}

PHB_OFF_F

SW_EN

HIGH_OV

LOW_OV

Burst Mode

Managment

2kW

6.67V

V_COMP

LOW_OV

COMP_DISCH

6.48V

1.25V

HVSEN

HVSEN_OV

4.87V /

4.67V

EA gain control for

Soft Start

And Dropout

DIS_HIGH_GAIN

DIS_EA

COMP_DISC

VREF

PHB_OFF_F

3ꢀA

VSENSE

HLN

Double Gain

Error Amplifier

100nA

V_COMP

Phase

Managment

PHB_OFF

PHB

AGND

COMP

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8.3 Feature Description

8.3.1 Principles of Operation

The UCC28064A device contains the control circuits for two parallel-connected boost pulse-width modulated

(PWM) power converters. The boost PWM power converters ramp current in the boost inductors for a time period

proportional to the voltage on the error amplifier output (COMP pin). Each power converter then turns off the

power MOSFET until current in the boost inductor decays to zero (as sensed on the zero current detection

inputs, ZCDA and ZCDB). After the inductor demagnetizes, the power converter starts another cycle. This cycle

process produces a triangular waveform of current, with peak current set by the on-time and the instantaneous

power mains input voltage, V_IN(t) value, as shown in 公式 1.

V × t_ON

I_PEAK

(1)

The average line current is exactly equal to half of the peak line current, as shown in 公式 2.

V × t_ON

I_PEAK

2 × L

(2)

When the t_ONand L values are essentially constant during an AC-line period, the resulting triangular current

waveform during each switching cycle has an average value proportional to the instantaneous value of the

rectified AC-line voltage. This architecture results in a resistive input impedance characteristic at the line

frequency and a near-unity power factor.

8.3.2 Natural Interleaving

Under normal operating conditions, the UCC28064A device regulates the relative phasing of the channel A and

channel B inductor currents to be approximately 180°. This greatly reduces the switching-frequency ripple

currents seen at the line-filter and output capacitors, compared to the ripple current of each individual converter.

This design allows a reduction in the size and cost of input and output filtering. The phase-control function

differentially modulates the on-times of the A and B channels based on their phase and frequency relationship.

The Natural Interleaving method allows the converter to achieve 180° phase-shift and transition-mode operation

for both phases without tight requirements on boost inductor tolerance.

Ideally, the best current-sharing is achieved when both inductors are exactly the same value. Typically the

inductances are not the same, so the current-sharing of the A and B channels is proportional to the inductor

tolerance. Also, switching delays and resonances of each channel typically differ slightly, and the controller

allows some necessary phase-error deviation from 180° to maintain equal switching frequencies. Optimal phase

balance occurs if the individual power stages and the on-times are well matched. Mismatches in inductor values

do not affect the phase relationship.

Interleaving may not be ideal under all conditions. In particular a loss of interleaving may be experienced at light

loads near the zero crossings. In some cases there may be insufficient current to trigger a large enough signal to

trip the zero crossing detectors. In addition the turn off delay in the MOSFET may dominate the overall on-time at

very light loads. This creates a very limited ability for the controller to correct for phase errors in the system.

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Feature Description (接下页)

8.3.3 On-Time Control, Maximum Frequency Limiting, Restart Timer and Input Voltage Feed-Forward

compensation

Gate-drive on-time varies proportionately with the error-amplifier output voltage (V_COMP) and inversely

proportional to the squared value of the peak of the rectified input voltage sensed through VINAC pin as stated

by equation (3). In equation (3) it is shown that the on-time is inversely proportionally to the value of resistor

R_TSETconnected between pin TSET and pin AGND. In order to calculate on-time, Equation (4) can be used.

Parameter K_Tis function of the rectified peak input voltage sensed by pin VINAC as reported in graph of 图 16.

In this graph 3 curves are reported for three different values of R_TSET. Two values of parameter K_Tare reported

in the electrical specs table for two values of VINAC: K_TLand K_THcorresponding at the VINAC = 1.6V and

VINAC = 5V and R_TSET= 133kΩ. Because voltage on VINAC is proportional to the line rectified voltage, for t_ON

calculation purposes we refer to the peak value of this voltage that is obtained through an internal peak detect.

K_Tis inversely proportional to the squared value of VINAC peak value so it is the t_ONtime realizing the so called

voltage feed-forward compensation. The Voltage Feed-forward function modifies the MOSFET on time according

to line voltage so, ideally output power delivered does not change if line voltage changes. When operating in

single phase mode K_Tis called K_TSand its value is doubled.

;

V_COMPF 125 mV

t_ON=ß

× R_TSET

INAC

(3)

The COMP pin voltage value is clamped at 4.95 V, so the maximum on time can be calculated by 公式 4.

;

t_ON= V_COMPF 125 mV × K_TV

;

INAC

(4)

图 16 shows the values of K_Tversus the peak voltage value on VINAC pin.

The maximum switching frequency of each phase is limited by minimum-period timers. If the inductor current

decays to zero before the minimum-period timer elapses, the next turn on will be delayed, resulting in

discontinuous phase current.

A restart timer ensures starting under all circumstances by restarting both phases if the ZCD input of either

phase has not transitioned from high-to-low within approximately 210 µs.

The minimum switching period, T_(MIN), is inversely proportional to the time-setting resistor R_TSET(the resistor from

the TSET pin to ground).

K_Tvs V_{INAC, PK}

R_TSET

66 kW

133 kW

266 kW

0.7

0.5

0.3

0.2

0.1

1.5

2.5

3.5 4

V_INAC,PK(V)

4.5

5.5

D012

图 16. K_Tvs Peak Voltage

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Feature Description (接下页)

8.3.4 Distortion Reduction

Due to the parasitic resonance between the drain-source capacitance of the switching MOSFET and the boost

inductor, conventional transition-mode PFC circuits may not be able to absorb power from the input line when the

input voltage is near zero. This limitation increases total harmonic distortion as a result of ac-line current

waveform distortion in the form of flat spots. To help reduce line-current distortion, the UCC28064A increases

switching MOSFET on-time when the input voltage is near 0 V to improve the power absorption capability and

compensate for this effect.

图 1 in the Typical Characteristics section shows the increase in on-time with respect to VINAC voltage.

Excessive filtering of the VINAC signal will nullify this function. In cases where small inductances are used (< 250

µH) the increased MOSFET on time can be excessive, increasing distortion instead of decreasing. If this is the

case the external circuit shown in 图 17 can help limit this effect.

VREF

100kΩ

1N4148

VINAC

R_U

1N4148

AGND

R_D

R_S

图 17. External Circuit to improve THD in case of Low inductance

8.3.5 Zero-Current Detection and Valley Switching

In transition-mode PFC circuits, the MOSFET turns on when the boost inductor current reaches zero. Because of

the resonance between the boost inductor and the parasitic capacitance at the MOSFET drain node, part of the

energy stored in the MOSFET junction capacitor can be recovered, reducing switching losses. Furthermore,

when the rectified input voltage is less than half of the output voltage, all the energy stored in the MOSFET

junction capacitor can be recovered and zero-voltage switching (ZVS) can be realized. By adding an appropriate

delay, the MOSFET can be turned on at the valley of its resonating drain voltage (valley-switching). In this way,

the energy recovery can be maximized and switching loss is minimized.

The optimal time delay is generally derived empirically, but a good starting point is a value equal to 25% of the

resonant period of the drain circuit. The delay can be realized by a simple RC filter, as shown in 图 18, but the

delay time increases slightly as the input voltage nears the output voltage. Because the ZCD pin is internally

clamped, a more accurate delay can also be realized by using the circuit shown in 图 19.

ZCD

图 18. Simple RC Delay Circuit

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Feature Description (接下页)

R₁

D₁

ZCD

C_T

C₁

R₂

图 19. More Accurate Time Delay Circuit

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Feature Description (接下页)

8.3.6 Phase Management and Light-Load Operation

It is challenging to maintain high efficiency under all loading conditions. When operating in light-load, switching

losses may dominate over conduction losses and the efficiency may be improved if one phase is turned off.

Turning off a phase at light load is especially valuable for meeting light-load efficiency standards. This is a major

benefit of interleaved PFC and it is especially valuable for meeting 80+ design requirements.

In order to ensure smooth operation when removing or adding a phase, some additional considerations are

required. When the number of phases operating is changed from 2 to 1 the overall switching frequency is

reduced by a factor of 2. If everything else is held constant this will also reduce the energy delivered to the load

by a factor of 2. In order to maintain the same power delivery to the output, it is necessary to increase the on-

time when performing such a transition. A similar situation exists when a phase is added. In other words, when

going from 1 phase to 2 phases, the on-time should decrease in order to have smooth continuous power

delivery. If everything is ideal, the amount by which the system has to increase/decrease the on-time is a factor

of 2. Since 1 phase needs to deliver twice the energy as each phase when both phases are operating, doubling

the on-time would seem to make the most sense (or cutting it in half if going from 1 phase to 2 phases). While

this works well in many cases there are real world examples where this fails to provide a sufficiently smooth

phase shedding/adding operation. In order to resolve this conflict the circuit in 图 20 can be utilized to program a

custom on-time for both 1 phase and 2 phase operation. The circuit operates by monitoring the gate drive of

phase 2 (GDB). When this signal is active the resistor R_TSETconfigures the on-time. When the gate drive is

absent the on-time is configured by the parallel combination of R_TSETand R_{TSET_II}. The capacitors C_FILand C_HOLD

can be adjusted to set up custom delays in the phase shedding/adding process.

TSET

VREF

GDB

R_{TSET_II}

900 lQ

R_{PULL_UP}

100 lQ

330 Q

1N4148

R_TSET

160 lQ

C_FIL

1 nF

R_DISCH

120 lQ

C_HOLD

4.7 nF

图 20. External circuit for Enhanced Phase Shedding

In the case where the 2x factor is sufficient, the UCC28064A can manage this phase shedding/adding process

without the need of the circuit in 图 20.The PHB input can be used to set the load value when the UCC28064A

has to operate in single-phase mode. The UCC28064A internally compares the voltage fed to PHB pin with the

COMP pin voltage. If COMP is below PHB channel B will stop switching and the channel A on-time will

automatically double to compensate the missing power from channel B. When operating in single phase mode in

order to avoid risk of inductor saturation an internal clamp ensures the on time never can exceed the maximum

on-time you will have when operating in dual phase mode. The device will resume dual-phase mode when the

COMP pin voltage exceeds PHB voltage plus the PHB hysteresis. In order to avoid voltage ripple on the COMP

pin causing the system to oscillate between one and two phases a time delay filter is present. In order to change

from normal operation to single phase mode the COMP voltage should stay below PHB pin voltage for 14 line

half cycles. The filter does not apply for the opposite transition. When the COMP pin voltage exceeds PHB pin

voltage plus the hysteresis, channel B is immediately turned on and the channel A on-time is halved.

At start up, the output voltage can be very close to the peak line voltage. The inductor current value during the

off time will decrease very slowly and it is possible systems will operate in CCM for a few switching cycles. In

order to avoid high current, during soft start, the system is forced to work with both phases on even if the COMP

pin voltage is below PHB pin voltage. In two phase mode the on-time of each phase is one half of the on time of

phase A when Phase B is off so this mitigates the risk of high CCM currents.

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Feature Description (接下页)

图 21. Phase Management Block Diagram

图 22. Phase Management Time Diagram

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Feature Description (接下页)

The voltage on the PHB pin can be set using a simple resistor divider connected to the V_REFpin. Another

important feature, that allows optimization of phase management is that it is possible to set different thresholds

wether the PFC input voltage is in the range of 90 to 132 V_RMS(US mains) or in the range of 180 to 265 V_RMS

(European mains). If the peak voltage sensed by the V_INACpin exceeds 3.5V the converter assumes that the

input voltage is in the range of 180 to 265 V_RMSand starts sourcing from PHB a small current (3µA typically) that

increases the voltage on PHB pin.

图 23. Change Phase Management Thresholds

Use 公式 5 and 公式 6 to calculate PHB thresholds.

R_D

V_{PHB _LR}

× V_REF

R_U+ R_D

(5)

(6)

R_D

R_D× R_U

R_U+ R_D

V_{PHB _HR}

× V_REF

× I_{PHB _RANGE}

R_U+ R_D

The load value at which the system moves between single phase and dual phase modes of operation is part of

the system specification. The formulas to calculate resistor divider resistance values that allows us to get the

desired thresholds are reported below.

¿V_PHB× V_REF

R_U=

V_{PHB _LR}× I_{PHB _RANGE}

(7)

¿V_PHB× V_REF

R_D=

(V_REFF V_{PHB _LR}) × I_{PHB _RANGE}

where

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Feature Description (接下页)

•

R_Dis the lower resistor of the resistor divider that provides voltage to PHB pin that is supplied by V_REF

R_Uis the upper resistor of the resistor divider.

(8)

(9)

¿V_PHB= V_{PHB _HR}F V_{PHB _LR}

PHB thresholds are selected by the user according to the load value where they want to turn off Phase B. So

assuming we want to turn off Phase B when the load goes below P_{OUT_PHB}we can calculate the threshold using

equation (10). We can use the same equation in order to calculate the two thresholds V_{PHB_HR}and V_{PHB_LR}once

provided the two different load values, for US range and EU range where Phase B has to be turned off. Of

course main EU range PHB_OFF load value has to be greater than main US range PHB_OFF load value. A

reasonable range of load values is from 20% to 30% of converter rated power.

;

P_{OUT (PHB )}

4.825 V

V_PHB

+ 125 mV

V_REF

P_{OUT (MAX )}

(10)

When the COMP voltage goes below the burst mode threshold the device is forced to work in single phase mode

so if the COMP pin voltage drops below the burst threshold it is possible that the time delay filtering is not

respected. Moreover it is recommended that PHB pin voltage is at least 600mV higher than BRST pin voltage.

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Feature Description (接下页)

8.3.7 Burst Mode Operation

To further improve light load efficiency burst mode operation can be used. In this case the burst mode threshold

is fed to BRST pin by an external source that could be a simple resistor divider connected to the V_REFpin. If

COMP pin voltage goes below the BRST pin voltage the converter stops switching. When the COMP voltage

exceeds BRST pin voltage plus hysteresis, the converter restarts switching.

In order to have a smooth transition between switching and not switching and vice-versa burst soft-on and burst

soft-off features are added. So when the COMP voltage goes below BRST voltage switching is not stopped

immediately, but there will be eight additional switching cycles where FET on time is decreased gradually. In

similar way when COMP voltage exceeds BRST voltage plus hysteresis a soft-on period occurs where the on

time is increased gradually to a value that corresponds to the present COMP voltage in eight switching cycles.

When the load decreases the device is intended to operate in single phase mode starting from 35% to 15% of

rated load and goes to burst mode at lower load values when single phase operation is activated. If the PHB

threshold is lower than the Burst mode threshold, single phase operation is forced during soft-on and soft-off

periods of burst mode.

Similar to the PHB feature the burst mode threshold has two different levels depending if the PFC input voltage is

in the range of 90 to 132 V_RMS(US main) or in the range of 180 to 265 V_RMS(European main). If the peak

voltage on VINAC pin peak voltage exceeds 3.5 V (typ.) a small current (3 µA typically) is provided from BRST

pin. If a resistor divider is used to set the BRST pin voltage this current will raise the voltage.

Use 公式 11 and 公式 12 to calculate the resistor divider that sets the Burst Mode thresholds. These equations

are identical to the equations used to calculate the PHB resistor divider.

R_Uand R_Dare the upper and the lower resistence of the resistor divider connected to VREF pin.

¿V_PHB× V_REF

R_U=

V_{PHB _LR}× I_{PHB _RANGE}

(11)

¿V_BRST× V_REF

R_D=

(V_REFF V_{BRST (LR)}) × I_{BRST (RANGE )}

(12)

8.3.8 External Disable

The UCC28064A can be externally disabled by pulling the VSENSE pin to ground with an open-drain or open-

collector driver. When disabled, the device supply current drops significantly and COMP is actively pulled low.

This disable method forces the device into standby mode and minimizes its power consumption. When VSENSE

is released, the device enters soft-start mode.

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Feature Description (接下页)

8.3.9 Improved Error Amplifier

The voltage error amplifier is a transconductance amplifier. Voltage-loop compensation is connected from the

error amplifier output, COMP, to analog ground, AGND. The recommended Type-II compensation network is

shown in 图 24. For loop-stability purposes, the compensation network values are calculated based on small-

signal perturbations of the output voltage using the nominal transconductance (gain) of 55 µS.

VREF

COMP

g_M

VSENSE

C_Z

C_P

4.95V

R_Z

图 24. Transconductance Error Amplifier With Typical Compensation Network

To improve the transient response to large perturbations, the error amplifier gain increases by a factor of around

5X when the error amplifier input deviates more than ±5% from the nominal regulation voltage, VSENSEreg. This

increase allows faster charging and discharging of the compensation components following sudden load-current

increases or decreases.

I_EA

V_SENSE

V_REF

Basic voltage error amplifier transconductance curve showing small-signal and large-signal gain sections, with

maximum current limitations.

图 25. Basic Voltage-Error Amplifier Transconductance Curve

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Feature Description (接下页)

8.3.10 Soft Start

Soft-start is a process for boosting the output voltage of the PFC converter from the peak of the ac-line input

voltage to the desired regulation voltage under controlled conditions. Instead of a dedicated soft-start pin, the

UCC28064A uses the voltage error amplifier as a controlled current source to increase the PWM duty-cycle by

way of increasing the COMP voltage. To avoid excessive start-up time-delay when the ac-line voltage is low, a

higher current is applied until VSENSE exceeds 3 V at which point the current is reduced to minimize the

tendency for excess COMP voltage at no-load start-up.

The PWM gradually ramps from zero on-time to normal on-time as the compensation capacitor from COMP to

AGND charges from zero to near its final value. This process implements a soft-start, with timing set by the

output current of the error amplifier and the value of the compensation capacitors. Soft-start ends when VSENSE

pin voltage exceeds 95% of VSENSEreg. During soft-start the device will operate with both phases on and even

if the COMP voltage is below the BRST pin voltage the device will not stop switching. In the event of a HVSEN

failsafe OVP, brownout, external-disable, UVLO fault, or other protection faults, COMP is actively discharged and

the UCC28064A will soft-start after the triggering event is cleared. Even if a fault event happens very briefly, the

fault is latched into the soft-start state and soft-start is delayed until COMP is fully discharged to 20 mV and the

fault is cleared. See 图 26 for details on the COMP current. See 图 27 which illustrates an example of typical

system behavior during soft-start.

I_COMP

OVP1 trigger. 2k pull-down

applied to COMP.

+63μA

OVP1 reset. 2k pull-down

removed from COMP .

+15μA

-15μA

1.0

2.0

3.0

4.0

5.0

6.0

7.0

VSENSE

COMP current limit

during Soft-Start only

(high-gain disabled )

-111 μA

Expanded COMP output current curve including voltage error amplifier transconductance and modifications applicable

to soft-start and overvoltage conditions.

图 26. Expanded COMP pin Output Current Curve

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Feature Description (接下页)

OVERSHOOT

VSENSE_REG

V_ENDofSS

VSENSE

V_COMPCLMP

COMP

V_SSTHR

I_AC-LINE

I_COMP

I_SS,SLOW

I_SS,FAST

HIGH GAIN ENABLED

SOFTSTART

图 27. Soft-Start Timing with System Behavior

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Feature Description (接下页)

8.3.11 Brownout Protection

As the power line RMS voltage decreases, RMS input current must increase to maintain a constant output

voltage for a specific load. Brownout protection helps prevent excess system thermal stress (due to the higher

RMS input current) from exceeding a safe operating level. Power-line voltage is sensed at VINAC pin. When the

VINAC fails to exceed the brownout threshold for the brownout filter time (t_BODLY), a brownout condition is

detected and both gate drive outputs are turned off. During brownout, COMP is actively pulled low and soft-start

condition is initiated. When VINAC rises above the brownout threshold, the power stage soft-starts as COMP

rises with controlled current.

The brownout threshold and its hysteresis are set by the voltage-divider ratio and resistor values. Brownout

protection is based on VINAC peak voltage; the threshold and hysteresis are also based on the line peak

voltage. Hysteresis is provided by a 2-μA current-sink (I_BOHYS) enabled whenever Brownout protection is

activated. As soon as the Brownout protection is activated an additional timer is started that counts the t_BORST

time. During this time the device is forced to stay in a Brownout condition. So, during t_BORSTtime, the device is

not allowed to switch, COMP is pulled low and the 2-uA current sink (I_BOHYS) is active regardless of the voltage

on VINAC pin. After t_BORSTis elapsed the device can exit from Brownout condition only if VINAC pin exceeds

V_BOTHRthreshold. When the device operates in burst mode, several blocks inside the IC are turned off to reduce

IC current consumption. The Brownout management block is also turned off. Each time the system stops

switching, because of burst mode, the Brownout filter timer is reset. So if the system is operating in burst mode,

the Brownout protection, generally is not triggered. The main purpose of Brownout is to avoid excess system

thermal stress. When the system is operating in burst-mode the load is low enough to avoid thermal stress. The

peak VINAC voltage can be easily translated into an RMS value. Example resistor values for the voltage divider

are 8.61 MΩ ±1% from the rectified input voltage to VINAC and 133 kΩ ±1% from VINAC to ground. These

resistors set the typical thresholds for RMS line voltages, as shown in 表 1.

表 1. Brownout Thresholds (For Conditions Stated in the Text)

THRESHOLD

Falling

AC-LINE VOLTAGE (RMS)

67 V

81 V

Rising

公式 13 and 公式 14 can be used to calculate the VINAC divider-resistors values based on desired brownout and

brown-in voltage levels. V_{AC_OK}is the desired RMS turnon voltage, V_{AC_BO}is the desired RMS turnoff brownout

voltage, and V_LOSSis total series voltage drop due to wiring, EMI-filter, and bridge-rectifier impedances at V_{AC_BO}

V_BOTHR, and I_BOHYSare found in the data-tables of this datasheet.

2 × kV

F V_AC_BOo

R_A= H

I_BOHYS

(13)

R_A

F V_LOSS

V_BOTHR

R_B=

2 × V

F 1G

(14)

When standard values for the VINAC divider-resistors R_Aand R_Bare selected, the actual turn-on and brownout

threshold RMS voltages for the ac-line can be back-calculated with 公式 15 and 公式 16:

R_A

V_AC

× dl1 + p × V_BOTHR+ V_LOSS

R_B

(15)

(16)

R_B+ R_A

V_AC

× d

× V_BOTHR+ R_A× I_BOHYSh

R_B

An example of the timing for the brownout function is illustrated in 图 28.

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8.3.12 Line Dropout Detection

It is often the case that the AC-line voltage momentarily drops to zero or nearly zero, due to transient abnormal

events affecting the local AC-power distribution network. Referred to as AC-line dropouts (or sometimes as line-

dips) the duration of such events usually extends to only 1 or 2 line cycles. During a dropout, the down-stream

power conversion stages depend on sufficient energy storage in the PFC output capacitance, which is sized to

provide the ride-through energy for a specified hold-up time. Typically while the PFC output voltage is falling, the

voltage-loop error amplifier output rises in an attempt to maintain regulation. As a consequence, excess duty-

cycle is commanded when the AC-line voltage returns and high peak current surges may saturate the boost

inductors with possible overstress and audible noise.

The UCC28064A incorporates a dropout detection feature which suspends the action of the error amplifier for the

duration of the dropout. If the VINAC voltage falls below 0.35 V for longer than 5 ms, a dropout condition is

detected and the error amplifier output is turned off. In addition, a 4-μA pull down current is applied to COMP to

gently discharge the compensation network capacitors. In this way, when the AC-line voltage returns, the COMP

voltage (and corresponding duty-cycle setting) remains very near or even slightly below the level it was before

the dropout occurred. Current surges due to excess duty-cycle, and their undesired attendant effects, are

avoided. The dropout condition is cancelled and the error amplifier resumes normal operation when VINAC rises

above 0.71 V.

Based on the VINAC divider-resistor values calculated for Brownout in the previous section, the input RMS

voltage thresholds for dropout detection V_{AC_DO}and dropout clearing V_{DO_CLR}can be determined using 公式 17

and 公式 18, below.

+1 + V

DODET

LOSS

AC _DO

(17)

(18)

+1 + V

DOCLR

LOSS

DO _CLR

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Avoid excessive filtering of the VINAC signal, or dropout detection may be delayed or defeated. An RC time-

constant of ≤ 100 s. should provide good performance. 图 29 shows an example of the timing for the dropout

function.

6 V

VSENSE

3 V

COMP

switching

no switching

switching

Brownout

Detect

VINAC_PK

V_BOTHR

VINAC

t_BODLY

t_BORST

图 28. AC-Line Brownout Timing and System Behavior

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V_SENSE

VINAC

COMP

V_DOCLR

V_DODET

DROPOUT

t_DODLY

图 29. AC-Line Dropout Timing With Illustrative System Behavior

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8.3.13 VREF

VREF is an output which supplies a well-regulated reference voltage to circuits within the device as well as

serving as a limited source for external circuits. This output must be bypassed to GND with a low-impedance 0.1-

μF or larger capacitor placed as close to the VREF and GND pins as possible. Current draw by external circuits

should not exceed 2mA and should not be pulsing.

The VREF output is disabled under the following conditions: when VCC is in UVLO, or when VSENSE is below

the Enable threshold. This output can only source current and is unable to accept current into the pin.

8.3.14 VCC

VCC is usually connected to a bias supply of between 14 V and 21 V. To minimize switching ripple voltage on

VCC, it should be bypassed with a low-impedance capacitor as close to the VCC and GND pins as possible. The

capacitance should be sized to adequately decouple the peak currents due to gate-drive switching at the highest

operating frequency. When powered from a poorly-regulated low-impedance supply, an external zener diode is

recommended to prevent excessive current into VCC.

The undervoltage-lockout (UVLO) condition is when VCC voltage has not yet reached the turn-on threshold or

has fallen below the turn-off threshold, having already been turned on. While in UVLO, the VREF output and

most circuits within the device are disabled and VCC current falls significantly below the normal operating level.

The same situation applies when VSENSE is below its Enable threshold. This helps minimize power loss during

pre-power up and standby conditions.

8.3.15 System Level Protections

8.3.15.1 Failsafe OVP - Output Over-voltage Protection

Failsafe OVP prevents any single failure from allowing the output to boost above safe levels. Redundant paths

for output voltage sensing provide additional protection against output over-voltage. Over-voltage protection is

implemented through two independent paths: VSENSE and HVSEN.

VSENSE pin voltage is compared with two levels of over-voltage. If the lower one, V_{LOW_OV},is exceeded the

COMP pin is discharged by an internal 2-kΩ resistance until the output voltage falls below V_{LOW_OV}reduced of

2% to provide hysteresis (ΔV_{LOW_OV_HYST}). If also the higher over-voltage threshold is exceeded in addition to

activate the 2-kΩ pull down switching is soon disabled. In order to re-enable the switching the sensed voltage

has to fall below V_{LOW_OV}reduced of 2%. Additional over-voltage protection can be implemented on HVSEN pin

through a separate resistor divider to monitor output voltage. An over-voltage is detected if HVSEN pin voltage

exceeds V_{HV_OV_FLT}an as consequence device stops switching and the 2-kΩ pull down is activated. The pull

down 2-kΩ pull down is removed only if HVSEN pin goes below V_{HV_OV_CLR}threshold and the COMP pin is fully

discharged to 20 mV. Both conditions needs to be true before the soft-start can begin.

The converter shuts down if either input senses a severe over-voltage condition. The output voltage can still

remain below a safe limit if either sense path fails. The device is re-enabled when both sense inputs fall back into

their normal ranges. At that time, the gate drive outputs will resume switching under PWM control. A low-level

over-voltage on VSENSE does not trigger soft-start, an higher-level over voltage on VSENSE additionally shuts

off the gate-drive outputs until the OV clears, but still does not trigger a soft-start. However, an over-voltage

detected on HVSEN does trigger a full soft-start and the COMP pin is fully discharged to 20 mV before the soft-

start can begin.

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8.3.15.2 Overcurrent Protection

Under certain conditions (such as inrush, brownout-recovery, and output over-load) the PFC power stage sees

large currents. It is critical that the power devices be protected from switching during these conditions.

The conventional current-sensing method uses a shunt resistor in series with each MOSFET source leg to sense

the converter currents, resulting in multiple ground points and high power dissipation. Furthermore, since no

current information is available when the MOSFETs are off, the source-resistor current-sensing method results in

repeated turn-on of the MOSFETs during overcurrent (OC) conditions. Consequently, the converter may

temporarily operate in continuous conduction mode (CCM) and may experience failures induced by excessive

reverse-recovery currents in the boost diodes or other abnormal stresses.

The UCC28064A uses a single resistor to continuously sense the combined total inductor (input) current. This

way, turn-on of the MOSFETs is completely avoided when the inductor currents are excessive. The gate drive to

the MOSFETs is inhibited until total inductor current drops to near zero, precluding reverse-recovery-induced

failures (these failures are most likely to occur when the AC-line recovers from a brownout condition).

The nominal OC threshold voltage during two-phase operation is -200 mV, which helps minimize losses. This

threshold is automatically reduced to -166 mV during single-phase operation, either by detection of a phase

failure or because COMP is below PHB.

An OC condition immediately turns off both gate-drive outputs, but does not trigger a soft-start and does not

modify the error amplifier operation. The overcurrent condition is cleared when the total inductor current-sense

voltage falls below the OC-clear threshold (–15 mV).

Following an overcurrent condition, both MOSFETs are turned on simultaneously once the input current drops to

near zero. Because the two phase currents are temporarily operating in-phase, the current-sense resistance

should be chosen so that OC protection is not triggered with twice the maximum current peak value of either

phase to allow quick return to normal operation after an overcurrent event. Automatic phase-shift control will re-

establish interleaving within a few switching cycles.

8.3.15.3 Open-Loop Protection

If the feedback loop is disconnected from the device, a 100-nA current source internal to the UCC28064A pulls

the VSENSE pin voltage towards ground. When VSENSE falls below 1.20 V, the device becomes disabled.

When disabled, the bias supply current decreases, both gate-drive outputs and COMP are actively pulled low,

and a soft-start condition is initiated. The device is re-enabled when VSENSE rises above 1.25 V. At that time,

the gate drive outputs will begin switching under soft-start PWM control.

If the resistor connected from AGND pin and VSENSE pin (Low resistor of the resistor divider used to sense

output voltage from VSENSE pin) opens, the VSENSE voltage will be pulled high. When VSENSE rises above

the 2nd-level over-voltage protection threshold, both gate drive outputs are shut off and COMP is actively pulled

low. The device is re-enabled when VSENSE falls below the OV-clear threshold. The VSENSE input can tolerate

a limited amount of current into the device under abnormally high input voltage conditions. Refer to the Absolute

Maximum Ratings table near the beginning of this datasheet for details.

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8.3.15.4 VCC Undervoltage Lock-Out (UVLO) Protection

VCC must rise above the turn-on threshold for the controller to begin functioning. If VCC drops below the UVLO

threshold during operation, both gate-drive outputs are actively pulled low, COMP is actively pulled low, and a

soft-start condition is triggered. VCC must again rise above the turn-on threshold for the PWM function to restart

in soft-start mode.

8.3.15.5 Phase-Fail Protection

The UCC28064A detects failure of either of the phases by monitoring the sequence of ZCD pulses. During

normal two-phase operation, if one ZCD input remains idle for longer than approximately 400 µs while the other

ZCD input switches normally, the over-current threshold is reduced to the value used for single phase operation

(V_{CS_SPh}). During normal single-phase operation, phase failure is not monitored. Phase failure is also not

monitored when COMP is below approximately 250 mV.

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8.3.15.6 CS - Open, TSET - Open and Short Protection

In the event that CS input becomes open-circuited, the UCC28064A detects this condition and will shutdown the

outputs and trigger a full soft start condition. In the event that TSET input becomes either open-circuited or short-

circuited to GND, the UCC28064A detects these conditions and will shutdown the outputs and trigger a full-soft-

start condition. Normal operation will resume (with a soft start) when the fault clears.

8.3.15.7 Thermal Shutdown Protection

Overloading of the gate-drive outputs, VREF, or both can dissipate excess power within the device which may

raise the internal temperature of the circuits beyond a safe level. Even normal power dissipation can generate

excess heat if the thermal impedance is too high or the ambient temperature is too high. When the UCC28064A

detects an internal over-temperature condition it will shutdown the outputs and trigger a full soft-start condition.

When the internal device junction temperature has cooled below the thermal hysteresis temperature, operation

will resume under soft-start control.

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8.3.15.8 Fault Logic Diagram

图 30 depicts the fault-handling logic involving VSENSE, COMP, and several internal states. It should be noted

that recovery from any fault except OC if the soft start is not triggered, will result in single phase soft-on

operation (8 switching cycles).

图 30. Fault Logic With VSENSE Detections and Error Amplifier Control

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8.4 Device Functional Modes

The controller is primarily intended for set up as a dual phase interleaved PFC which utilizes inductor

demagnetization information based on inductor sense winding voltages which are routed to ZCDA and ZCDB to

trigger the start of a switching cycle.

The functionality may be extended in a couple of ways:

Phase-B Enable and Disable: When the voltage on COMP is below the voltage on the PHB pin, Phase B and

the Phase Fail Detector will be disabled. The on-time for Phase-A will be doubled to compensate

the Phase-B missing power. When the voltage on COMP is greater than the PHB pin voltage, two

phase mode is enabled. Connect PHB to a resistor divider sourced by VREF to set a threshold for

COMP pin and obtain an automatic light load efficiency management feature. Because when PHB

voltage is higher then COMP voltage, the on-time is doubled, in order to avoid risk of inductor

saturation an internal clamp ensures the on-time never can exceed dual phase mode maximum on-

time.

PFC Stage Enable and Disable Control: Controller operation is enabled when VSENSE voltage exceeds the

1.25-V enable threshold. The primary disable method should be by pulling VSENSE low by an open

drain or open collector logic output. This will disable the outputs and significantly reduce VCC

current. Releasing VSENSE will initiate a soft-start. Avoid any PCB traces which would couple any

noise into this node.

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9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

This control device is generally applicable to the control of AC-DC power supplies which require Active Power

Factor Correction off Universal AC line. Applications using this device generally meet the Class-D equipment

input current harmonics standards per EN61000-3-2. This standard applies to equipment with rated Powers

higher than 75W. The device brings two phase interleaved control capability to the Transition Mode Boost and

hence will be generally a very good choice for cost optimized applications in the 150W to 800W space, or to

even lower powers that wish to leverage on the interleaving benefits of reduced filtering component size, lower

profile solutions and distributed thermal management.

9.2 Typical Application

图 31 shows an example of the UCC28064A PFC controller in a two-phase interleaved, transition-mode PFC pre-

regulator.

L_A

L_B

C_ZA

C_B

220nF

PHB THRESHOLD

C_OUT

ZCD_B

VSENSE

TSET

ZCD_A

VREF

GDA

PGND

VCC

VSENSE

HVSEN

PHB THRESHOLD

PHB

VSENSE

C_Z

R_Z

COMP

AGND

VINAC

HVSEN

GDB

HVSEN

BRST

图 31. Typical Interleaved Transition-Mode PFC Preregulator

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Typical Application (接下页)

9.2.1 Design Requirements

The specifications for this design were chosen based on the power requirements of a typical 300-W LCD TV. 表

2 lists these specifications.

表 2. Design Specifications

DESIGN PARAMETER

RMS input voltage

MIN

TYP

MAX

UNIT

V_IN

265

(VIN_MAX)

VRMS

(VIN_MIN)

V_OUT

f_LINE

Output voltage

390

AC-line frequency

Power factor at maximum load

0.90

P_OUT

300

Full-load efficiency

92%

f_MIN

Minimum switching frequency

kHz

9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the UCC28064A device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

UCC28064A

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ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

9.2.2.2 Inductor Selection

The boost inductor is selected based on the minimum switching requirements. Operating at the boundary

between DCM and CCM the minimum switching frequency will be at maximum power and at the peak of the line.

It is possible that the minimum switching frequency can occur at minimum line or at maximum line. 公式 20.

0.92ì(264V )²ì(390 - 2 ì264V)

27kHz ì390V ì300W

ìV_{IN _ MAX}ì(V_OUT- 2 ìV_{IN _ MAX}

)

L_H=

= 338

f_MINìV_OUTì P

OUT _ MAX

(19)

0.92ì(85V )²ì(390 - 2 ì85V )

27kHz ì390V ì300W

ìV_{IN _ MIN}ì(V_OUT- 2 ìV_{IN _ MIN}

)

L_L=

= 568

f_MINìV_OUTì P

OUT _ MAX

(20)

In order to be sure that converters operates always above the desired (f_MIN) we will select the minimum value

between L_Hthat would be the value we have if we consider the minimum occurs at maximum input voltage and

L_Lthat would be the value we have if we consider that minimum switching frequency occurs at minimum Line

voltage. For this design example, f_MINis set to 27 kHz in order to be always above the audible range. For a 2-

phase interleaved design, L1 and L2 are determined by minimum between L_Hand L_Las stated in formula (19)

here below公式 21.

L1= L2 = min(L L ) @ 340

H ,

(21)

The inductor for this design would have a peak current (I_LPEAK) of 5.4 A, as shown in 公式 22, and an RMS

current (I_LRMS) of 2.2 A, as shown in 公式 23.

P_OUT

300W 2

I_LPEAK

» 5.4Apk

V_{IN_MIN}´ h 85V ´ 0.92

(22)

(23)

5.4A

LPEAK

» 2.2Arms

LRMS

This converter uses constant on time (T_ON) and zero-current detection (ZCD) to set up the converter timing.

Auxiliary windings on L1 and L2 detect when the inductor currents are zero. Selecting the turns ratio using 公式

24 ensures that there will be at least 2 V at the peak of high line to reset the ZCD comparator after every

switching cycle.

The turns-ratio of each auxiliary winding is:

V_OUT- V

N_P

N_s

390V - 265V 2

IN_MAX

» 8

(24)

9.2.2.3 ZCD Resistor Selection R_ZA, R_ZB

The minimum value of the ZCD resistors is selected based on the internal clamps maximum current ratings of 3

mA, as shown in 公式 25.

390V

OUT

= R

N ´ 3mA 8´3mA

» 16.3kW

(25)

(26)

In this design the ZCD resistors are set to 20 kΩ, as shown in 公式 26.

= R = 20kW

9.2.2.4 HVSEN

According to R_Eand R_Fresistor values, the Failsafe OVP threshold will be set according to 公式 27

4.87V R + R

(

4.87V 8.22MW + 82.5kW

(

82.5kW

)

» 490V

OV _FAILSAFE

(27)

UCC28064A

ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

9.2.2.5 Output Capacitor Selection

The output capacitor ( C_OUT) is selected based on holdup requirements, as shown in 公式 28.

P_OUT

300W

h f_LINE

V_OUT²- (V_{OUT _MIN}

0.92 47Hz

390V²- (252V)²

C_OUT

» 156mF

)

(28)

(29)

Two 100-μF capacitors were used in parallel for the output capacitor.

= 200mF

OUT

For this size capacitor, the low-frequency peak-to-peak output voltage ripple (V_RIPPLE) is approximately 14 V, as

shown in 公式 30:

2´P

2´300W

OUT

» 14Vppk

RIPPLE

´ 4p´ f

´ C

OUT

0.92´ 390V ´ 4p´ 47Hz ´ 200mF

OUT

LINE

(30)

In addition to holdup requirements, a capacitor must be selected so that it can withstand the low-frequency RMS

current (I_{COUT_100Hz}) and the high-frequency RMS current (I_{COUT_HF}); see 公式 31 to 公式 33. High-voltage

electrolytic capacitors generally have both a low- and a high-frequency RMS current ratings on the product data

sheets.

P_OUT

300W

I_{COUT _100Hz}

= 0.591 Arms

_OUT´ h´ 2 390V ´ 0.92´ 2

(31)

ö²

4 2V

P_OUT2 2

2´ h´ V

IN_MIN

I_{COUT _HF}

- I

(

COUT _100Hz

)

9pV_OUT

IN_MIN

(32)

(33)

300W ´ 2 2 4 2 ´85V

2´ 0.92´85V 9p´390V

)

- 0.591A » 0.966Arms

(

COUT _HF

UCC28064A

www.ti.com.cn

ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

9.2.2.6 Selecting R_SFor Peak Current Limiting

The UCC28064A peak limit comparator senses the total input current and is used to protect the MOSFETs

during inrush and over-load conditions. For reliability, the peak current limit (I_PEAK) threshold in this design is set

for 120% of the nominal maximum current that will be observed during power up, as shown in 公式 34.

2P_OUT2(1.2)

2´300W 2 ´1.2

0.92´85V

I_PEAK

» 13A

h´ V

IN_MIN

(34)

A standard 15-mΩ metal-film current-sense resistor will be used for current sensing, as shown in 公式 35. The

estimated power loss of the current-sense resistor (P_RS) is less than 0.25 W during normal operation, as shown

in 图 8.

200mV 200mV

R_S=

» 15mΩ

I_PEAK

13A

(35)

ö²

P_OUT

_{IN_MIN}´ h

ö²

300W

85V ´0.92

P =

R =

´15mW » 0.22 W

(36)

The most critical parameter in selecting a current-sense resistor is the surge rating. The resistor needs to

withstand a short-circuit current larger than the current required to open the fuse (F1). I²t (ampere-squared-

seconds) is a measure of thermal energy resulting from current flow required to melt the fuse, where I²t is equal

to RMS current squared times the duration of the current flow in seconds. A 4-A fuse with an I²t of 14 A²s was

chosen to protect the design from a short-circuit condition. To ensure the current-sense resistor has high-enough

surge protection, a 15-mΩ, 500-mW, metal-strip resistor was chosen for the design. The resistor has a 2.5-W

surge rating for 5 seconds. This result translates into 833 A²s and has a high-enough I²t rating to survive a short-

circuit before the fuse opens, as described in 公式 37.

2.5W

I t =

´ 5s = 833A s

0.015W

(37)

9.2.2.7 Power Semiconductor Selection (Q1, Q2, D1, D2)

The selection of Q1, Q2, D1, and D2 are based on the power requirements of the design. For an explanation of

how to select power semiconductor components for transition-mode PFC preregulators, refer to UCC38050 100-

W Critical Conduction Power Factor Corrected (PFC) Pre-regulator.

The MOSFET (Q1, Q2) pulsed-drain maximum current is shown in 公式 38:

I_DM³ I_PEAK= 13A

(38)

The MOSFET (Q1, Q2) RMS current calculation is shown in 公式 39:

4 2 V

I_PEAK

13A 1 4 2 ´85V

IN_MIN

I_DS

» 2.3A

9p´ V_OUT

9p´390V

(39)

(40)

To meet the power requirements of the design, IRFB11N50A 500-V MOSFETs were chosen for Q1 and Q2.

The boost diode (D1, D2) RMS current is shown in 公式 40:

4 2 ´ V

13A 4 2 ´85V

IN_MIN

PEAK

» 1.4A

9p´ V

9p´ 390V

OUT

To meet the power requirements of the design, MURS360T3, 600-V diodes were chosen for D1 and D2.

UCC28064A

ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

9.2.2.8 Brownout Protection

Resistor R_Aand R_Bare selected to activate brownout protection at ~75% of the specified minimum-operating

input voltage. Resistor R_Aprograms the brownout hysteresis comparator, which is selected to provide 17 V (~12

V_RMS) of hysteresis. Calculations for R_Aand R_Bare shown in 公式 41 through 公式 44.

Hysteresis 17V

= 8.5MW

2mA

(41)

(42)

(43)

(44)

To meet voltage requirements, three 2.87-MΩ resistors were used in series for R_A.

= 3´ 2.87MW = 8.61MW

1.4V ´R

1.4V ´8.61MW

´ 0.75 2 -1.4V 85V ´0.75 2 -1.4V

= 135.8kW

IN_MIN

Select a standard value for R_B.

= 133kW

In this design example, brownout becomes active (shuts down PFC) when the input drops below 67 V_RMSfor

longer than 680 ms and deactivates (restarts with a full soft start) if, after that the t_BORSTtime is elapsed, the input

reaches 81 V_RMS

9.2.2.9 Converter Timing

The MOSFET on-time T_ONdepends on value of the selected inductance on load value, represented by COMP

pin voltage and by the converter AC input voltage 公式 45. To ensure proper operation, the timing must be set

based on the highest boost inductance (L1_MAX) and output power (P_OUT) at minimum operating AC input Voltage.

Because the input voltage is sensed by VINAC pin the on time setting needs to take into account of the selected

resistor divider that provide voltage at VINAC pin. In this design example, the boost inductor could be as high as

390 µH.

Let's call K_BOthe ratio:公式 49.

R_A+ R_B8.61MW +133kW

K_BO

= 65.74

R_B

133kW

(45)

the Maximum on time at full load (P_OUT= 300W) and minimum input voltage (85V_AC) is given by formula;

; :

3009 × 340ä*

;

2₁₇₆× .

ß × k8_{+0_/+0}o²

P_{10_/#:}

= 15.34äO

0.92 × 858

;

(46)

The value of the resistor R_Tconnected to TSET pin to set the on time timers is the minimum of R_THand R_TL

provided by formulas (46) and (47)

R = min(R ,R )

(47)

(48)

(49)

K_{TH _ MIN}ì(5V )²ì(133kW)ì(4.825V )

R_TH

≈

’

2 ìV_{IN _ MIN}

K_BO

ìt_{ON _ MAX}

∆

◊

K_{TL _ MIN}ì(1.6V )²ì(133kW)ì(4.825V)

R_TL=

≈

’

2 ìV_{IN _ MIN}

K_BO

ìt_{ON _ MAX}

∆

◊

Where the values of K_{TL_min}and K_{TH_min}are the minimum values of K_TLand K_THparameters reported on the

electrical characteristic table at page 7 of this datasheet.

The selected value for R_Tis 115 kΩ.

UCC28064A

www.ti.com.cn

ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

9.2.2.10 Programming V_OUT

Resistor R_Cis selected to minimize loading on the power line when the PFC is disabled. Construct resistor R_C

from two or more resistors in series to meet high-voltage requirements. Resistor R_Dis then calculated based on

R_C, the reference voltage, V_REF, and the required output voltage, V_OUT. Based on the values shown in 公式 50 to

公式 53, the primary output overvoltage protection threshold should be as shown in 公式 54:

= 2.74MW + 2.74MW + 3.01MW = 8.49MW

(50)

(51)

= 6 V

REF

´R

6V ´ 8.49MW

390V - 6V

REF

= 132.7kW

- V

REF

OUT

(52)

Select a standard value for R_D.

= 133kW

(53)

(54)

+ R

8.49MW +133kW

133kW

= 6.48V

= 420.1V

OVP

9.2.2.11 Voltage Loop Compensation

Resistor R_Zis sized to attenuate low-frequency ripple to less than 2% of the voltage amplifier output range. This

value ensures good power factor and low harmonic distortion on the input current. The voltage on the COMP pin

needs to stay above 250 mV to maintain normal operation. If COMP falls below this threshold switching will stop.

The transconductance amplifier small-signal gain is shown in 公式 55:

= 50mS

(55)

(56)

(57)

The voltage-divider feedback gain is shown in 公式 56:

REF

H =

» 0.015

390V

OUT

The value of R_Zis calculated as shown in 公式 57:

100mV

= 9.52 kW

´H´ g

14V ´0.015´50mS

RIPPLE

C_Zis then set to add 45° phase margin at 1/5th of the line frequency, as shown in 公式 58:

f_LINE

C_Z

= 1.78mF

47Hz

2p´

´ 9.52kW

2p´

´R_Z

(58)

(59)

C_Pis sized to attenuate high-frequency switching noise, as shown in 公式 59:

f_MIN

45kHz

C_p=

= 770pF

2p´

´ 9.52kW

2p´

´R_Z

Standard values should be chosen for R_Z, C_Zand C_P, as shown in 公式 60 to 公式 62.

= 9.53kW

= 2.2mF

= 820pF

(60)

(61)

(62)

UCC28064A

ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

9.2.3 Application Curves

9.2.3.1 Input Ripple Current Cancellation with Natural Interleaving

图 32 through 图 34 show the input current (CH2), Inductor Ripple Currents (CH3, CH4) versus rectified line

voltage. From these graphs, it can be observed that natural interleaving reduces the overall magnitude of input

(and output) ripple current caused by the individual inductor current ripples.

CH3 = Phase A Inductor

Current

CH3 = Phase A Inductor

Current

CH2 = Input Current

CH4 = Phase B Inductor

Current

CH4 = Phase B Inductor

Current

图 32. Inductor and Input Ripple Current at 85 V_RMSat

图 33. Inductor and Input Ripple Current at 265 V_RMSInput

Peak of Line Voltage

at Peak Line Voltage

CH2 = Input Current

CH3 = Phase A Inductor Current

CH4 = Phase B Inductor Current

图 34. Inductor and Input Ripple Current at V_IN= 85 V_RMS, P_OUT= 300 W

UCC28064A

www.ti.com.cn

ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

9.2.3.2 Brownout Protection

The UCC28064A has a brownout protection that shuts down both gate drives (GDA and GDB) when the VINAC

pin detects that the RMS input voltage is too low. 图 35.

CH1 = V_GDA

CH3 = V_OUT

CH2 = V_GDB

CH3 = V_IN

图 35. UCC28064A Response to a Line Brownout Event at 115 V_RMS

10 Power Supply Recommendations

The device receives all of its power through the VCC pin. This voltage should be as well regulated as possible

through all of the operating conditions of the PFC stage. Consider creating the steady state bias for this stage

from a downstream DC:DC stage which will in general be able to provide a bias winding with very well regulated

voltage. This strategy will enhance the overall efficiency of the bias generation. A lower efficiency alternative will

be to consider a series-connected fixed positive-voltage regulator such as the UA78L15A.

For all normal and abnormal operating conditions it is critically important that VCC remains within the

recommended operating range for both Voltage and Input Current. VCC overvoltage may cause excessive power

dissipation in the internal voltage clamp and undervoltage may cause inadequate drive levels for power

MOSFETs, UVLO events (causing interrupted PFC operation) or inadequate headroom for the various on-chip

linear regulators and references.

Note also that the high RMS and peak currents required for the MOSFET gate drives are provided through the

device 13.5-V linear regulator, which does not have provision for the addition of external decoupling capacitance.

For higher Powers, very high Q_Gpower MOSFETs or high switching frequencies, consider using external driver

transistors, local to the power MOSFETs. These will reduce the device operating temperature and ensure that

the VCC maximum input current rating is not exceeded.

Use decoupling capacitances between VREF and AGND and between VCC and PGND which are as local as

possible to the device. These should have some ceramic capacitance which will provide very low ESR. PGND

and AGND should ideally be star connected at the control device so that there is negligible DC or high frequency

AC voltage difference between PGND and AGND. Use values for decoupling capacitors similar to or a little larger

than those used in the EVM.

Pay close attention to start-up and shutdown VCC bias bootstrap arrangements so that these provide adequate

regulated bias power as early as possible during power application and as late as possible during power

removal. Ensure that these start-up bias bootstrap circuits do not cause unnecessary steady-state power drain.

UCC28064A

ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

Interleaved transition-mode PFC system architecture dramatically reduces input and output ripple current,

allowing the circuit to use smaller and less expensive filters. To maximize the benefits of interleaving, the input

and output filter capacitors should be located after the two phase currents are combined together. Similar to

other power management devices, when laying out the printed circuit board (PCB) it is important to use star

grounding techniques and keep filter capacitors as close to device ground as possible. To minimize the

interference caused by capacitive coupling from the boost inductor, the device should be located at least 1 in

(25.4 mm) away from the boost inductor. It is also recommended that the device not be placed underneath

magnetic elements. Because of the precise timing requirement, timing-setting resistor R_Tshould be placed as

close as possible to the TSET pin and returned to the analog ground pin with the shortest possible path. 图 36

shows a recommended component placement and layout.

UCC28064A

www.ti.com.cn

ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

11.2 Layout Example

Dotted line could be or a wire mounted on the top of the board or Top layer traces, assuming device and other traces

are in the bottom layer.

图 36. Recommended PCB Layout

UCC28064A

ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

11.3 Package Option Addendum

11.3.1 Packaging Information

Package

Drawing

Lead/Ball

Finish⁽³⁾

Device

(1)

(2)

(4)

Orderable Device

Status

Package Type

Pins

Qty

Eco Plan

MSL Peak Temp

Op Temp (°C)

Marking⁽⁵⁾⁽⁶⁾

UCC28064ADT

UCC28064ADR

ACTIVE

SOIC

250

Green (RoHS & no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125

UCC28064A

2500

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

space

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest

availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the

requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified

lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used

between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by

weight in homogeneous material)

space

(3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the

finish value exceeds the maximum column width.

space

(4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

space

(5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device

space

(6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief

on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third

parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for

release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

UCC28064A

www.ti.com.cn

ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

12 器件和文档支持

12.1 器件支持

12.1.1 开发支持

12.1.1.1 使用 WEBENCH® 工具创建定制设计

单击此处，使用 UCC28064 器件及其 WEBENCH® 电源设计器创建定制设计。

1. 首先输入输入电压 (V_IN)、输出电压 (V_OUT) 和输出电流 (I_OUT) 要求。

2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。

3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。

WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。

在多数情况下，可执行以下操作：

•

运行电气仿真，观察重要波形以及电路性能

运行热性能仿真，了解电路板热性能

将定制原理图和布局方案以常用 CAD 格式导出

打印设计方案的 PDF 报告并与同事共享

有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。

12.2 文档支持

12.2.1 相关文档

请参阅如下相关文档：

•

《UCC28064AEVM 300W 交错式 PFC 前置稳压器》

《UCC38050 100W 临界导通功率因数校正 (PFC) 前置稳压器》

12.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 社区资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.5 商标

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

UCC28064A

ZHCSIB2B –DECEMBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

UCC28064ADR

UCC28064ADT

ACTIVE

SOIC

2500 RoHS & Green

250 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

UCC28064A

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Dec-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UCC28064ADR

UCC28064ADT

SOIC

2500

250

330.0

16.4

6.5

10.3

2.1

8.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Dec-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

UCC28064ADR

UCC28064ADT

SOIC

2500

250

340.5

336.1

32.0

Pack Materials-Page 2

重要声明和免责声明

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保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

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TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

UCC28064ADR [TI]

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