UCC28180D [TI]
Programmable Frequency, Continuous Conduction Mode (CCM), Boost Power Factor Correction (PFC) Controller; 可编程频率,连续导通模式( CCM )升压功率因数校正(PFC )控制器型号: | UCC28180D |
厂家: | TEXAS INSTRUMENTS |
描述: | Programmable Frequency, Continuous Conduction Mode (CCM), Boost Power Factor Correction (PFC) Controller |
文件: | 总48页 (文件大小:1765K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
UCC28180
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SLUSBQ5A –NOVEMBER 2013–REVISED NOVEMBER 2013
Programmable Frequency, Continuous Conduction Mode (CCM), Boost Power Factor
Correction (PFC) Controller
Check for Samples: UCC28180
1
FEATURES
DESCRIPTION
The UCC28180 is a flexible and easy-to-use, 8-pin,
active Power Factor Correction (PFC) controller that
operates under Continuous Conduction Mode (CCM)
to achieve high Power Factor, low current distortion
and excellent voltage regulation of boost pre-
regulators in AC - DC front-ends. The controller is
suitable for universal AC input systems operating in
100-W to few-kW range with the switching frequency
programmable between 18 kHz to 250 kHz, to
conveniently support both power MOSFET and IGBT
switches. An integrated 1.5-A and 2-A (SRC-SNK)
peak gate drive output, clamped internally at 15.2 V
(typical), enables fast turn-on, turn-off and easy
management of the external power switch without the
need for buffer circuits.
•
•
8-pin Solution (no AC line sensing needed)
Wide Range Programmable Switching
Frequency (18 kHz to 250 kHz for MOSFET and
IGBT based PFC converters)
•
•
Trimmed Current Loop Circuits for Low iTHD
Reduced Current Sense Threshold (minimizes
power dissipation in shunt)
•
•
Average Current-Mode Control
Soft Over Current and Cycle-by-Cycle Peak
Current Limit Protection
•
Output Over-Voltage Protection with
Hysteresis Recovery
•
•
•
Audible Noise Minimization Circuitry
Open Loop Detection
Low-distortion wave shaping of the input current
using average current mode control is achieved
without input line sensing, reducing the external
component count. In addition, the controller features
reduced current sense thresholds to facilitate the use
of small value shunt resistors for reduced power
dissipation, especially important in high power
systems. To enable low current distortion, the
controller also features trimmed internal current loop
regulation circuits for eliminating associated
inaccuracies.
Enhance Dynamic Response During Output
Over and Under-Voltage Conditions
•
•
•
Maximum Duty Cycle of 96% (typical)
Burst Mode for No Load Regulation
VCC UVLO, Low ICC Start-Up (<75 µA)
APPLICATIONS
•
Universal AC Input, CCM Boost PFC
converters in 100-W to Few-kW range
•
•
Server and Desktop Power Supplies
White Good Appliances (Air Conditioners,
Refrigerators)
•
•
Industrial Power Supplies (DIN Rail)
Flat Panel TV (PDP, LCD and LED) TVs
Typical Application
VOUT
EMI Filter
LINE
INPUT
Bridge
Rectifier
–
+
GND
GATE
VCC
1
2
3
4
8
7
6
5
Auxilary
Supply
ICOMP
ISENSE VSENSE
FREQ VCOMP
Rload
UCC28180
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
UCC28180
SLUSBQ5A –NOVEMBER 2013–REVISED NOVEMBER 2013
www.ti.com
DESCRIPTION (CONT.)
Simple external networks allow for flexible compensation of the current and voltage control loops. In addition,
UCC28180 offers an enhanced dynamic response circuit that is based on the voltage feedback signal to deliver
improved response under fast load transients, both for output over-voltage and under-voltage conditions. An
unique VCOMP discharge circuit provided in UCC28180 is activated whenever the voltage feedback signal
exceeds VOVP_L thus allowing a chance for the control loop to stabilize quickly and avoid encountering the over-
voltage protection function when PWM shut-off can often cause audible noise. Controlled soft start gradually
regulates the input current during start-up and reduces stress on the power switches. Numerous system-level
protection features available in the controller include VCC UVLO, peak current limit, soft over-current, output
open-loop detection, output over-voltage protection and open-pin detection (VISNS). A trimmed internal reference
provides accurate protection thresholds and regulation set-point. The user can control low power standby mode
by pulling the VSENSE pin below 0.82 V.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE, TA
UCC28180D
SOIC 8-Pin (D) Lead (Pb)-Free/Green(1) Lead
(Pb)-Free/Green
–40°C to 125°C
(1) SOIC (D) package is available taped and reeled by adding “R” to the above part number. Reeled quantities are 2,500 devices per reel.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, all voltages are with respect to GND (unless otherwise noted). Currents are
positive into and negative out of the specified terminal.
VALUE
MIN
–0.3
–0.3
–24
UNIT
MAX
22
7
Input voltage range
VCC, GATE
V
FREQ, VSENSE, VCOMP, ICOMP
ISENSE
7
Input current range
VSENSE, ISENSE
Operating
–1
1
mA
°C
°C
°C
kV
V
–55
150
150
300
2
Junction temperature, TJ
Lead temperature, TSOL
Storage
–65
Soldering, 10 s
Human Body Model (HBM)
Charged Device Model (CDM)
Electrostatic Discharge (ESD)
Protection
500
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those included under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.
2
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
VCCOFF + 1V
–40
MAX UNIT
VCC input voltage from a low-impedance source
Operating junction temperature, TJ
Operating frequency
21
V
125
°C
18
250 kHz
THERMAL INFORMATION
UCC28180
SOIC (D)
8 PINS
116.1
62.2
THERMAL METRIC(1)
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
56.4
°C/W
ψJT
14.4
ψJB
55.9
θJCbot
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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ELECTRICAL CHARACTERISTICS
Unless otherwise noted, VCC=15Vdc, 0.1µF from VCC to GND, –40°C ≤ TJ = TA ≤ +125°C. All voltages are with respect to
GND. Currents are positive into and negative out of the specified terminal.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
VCC Bias Supply
ICCPRESTART
ICCSTBY
ICC Pre-start current
ICC Standby current
ICC Operating current
VCC = VCCOFF – 0.2 V
75
2.95
8.8
µA
mA
mA
VSENSE = 0.5 V
1.80
5.8
2.40
7.0
ICCON_load
VSENSE = 4.0 V, CGATE = 4.7 nF
Under Voltage LockOut (UVLO)
VCCON
VCC Turn on threshold
10.8
9.1
11.5
9.5
12.1
10.3
2.0
V
V
V
VCCOFF
VCC Turn off threshold
UVLO Hysteresis
1.6
1.7
Variable Frequency
Minimum switching frequency
RFREQ = 130 kΩ
RFREQ = 32.7 kΩ
RFREQ = 8.2 kΩ
TA = 25°C
16.3
61.75
225
18.0
65.00
250
19.8
68.25
275
kHz
kHz
kHz
V
fSW
Typical switching frequency
Maximum switching frequency
Voltage at FREQ pin
VFREQ
PWM
DMIN
1.43
1.50
1.56
Minimum duty cycle
Maximum duty cycle
Minimum off time
VSENSE = 5.1 V, ISENSE = –0.25 V
VSENSE = 4.0 V, RFREQ = 32.7 Ω
VSENSE = 3 V, ICOMP = 0.72 V
0%
DMAX
94.8% 96.5% 98.0%
450 570 690
tOFF(min)
ns
System Protection
VSOC
VPCL
ISENSE threshold, soft over current (SOC)
–0.259 –0.295 –0.312
V
V
ISENSE threshold, peak current limit (PCL)
–0.345
–0.4 –0.438
ISENSE bias current, ISENSE open-pin protection
(ISOP)
IISOP
ISENSE = 0 V
–2.30
–2.95
µA
ISENSE threshold, ISENSE open-pin protection
(ISOP)
VISOP
VOLP
ISENSE = open pin
0.085
16.5
100
0.14
17.6
325
V
%VREF
nA
VSENSE threshold, open loop protection (OLP)
ICOMP = 1 V, ISENSE = 0 V
VSENSE = 0.5 V
15.6
Open loop protection (OLP) Internal pull-down
current
VSENSE threshold, output under-voltage detection
(UVD) used for enhanced dynamic response(1)
VUVD
VOVD
93.25
95.00
97.00
%VREF
%VREF
VSENSE threshold, output over-voltage detection
(OVD) used for Enhanced dynamic response(1)
103.00 105.00 106.75
Output over-voltage protection low threshold,
VCOMP is discharged by a 4kΩ resistor when
VSENSE > VOVP_L
VOVP_L
105
107
100
107
109
109
111
%VREF
%VREF
Output over-voltage protection high threshold, PWM
shuts off when VSENSE > VOVP_H
VOVP_H
Output over-voltage protection (VOVP_H) reset
threshold, PWM turns on when VSENSE <
VOVP_H(RST)
VOVP_H(RST)
102
104
%VREF
%VREF
ICOMP threshold, external overload protection
0.20
0.25
Current Loop
gmi
Transconductance gain
0.75
2.7
0.95
±50
3.0
1.10
3.3
mS
µA
V
(1)
Output linear range
ICOMP voltage during OLP
VSENSE = 0 V
(1) Not production tested. Characterized by design
4
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ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted, VCC=15Vdc, 0.1µF from VCC to GND, –40°C ≤ TJ = TA ≤ +125°C. All voltages are with respect to
GND. Currents are positive into and negative out of the specified terminal.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Voltage Loop
VREF
Reference voltage
TA = 25°C
4.93
4.87
–40
–230
23
5.00
5.00
–56
–280
40
5.07
5.15
–70
V
V
–40°C ≤ TA ≤ +125°C
gmv
Transconductance gain without EDR
Transconductance gain under EDR
Maximum sink current under normal operation
Source current under soft start
Maximum current under EDR operation
VSENSE input bias current
µS
µS
µA
µA
µA
nA
V
gmv-EDR
–340
57
VSENSE = 5 V, VCOMP = 4 V
VSENSE = 4 V, VCOMP = 4 V
VSENSE = 4 V, VCOMP = 2.5 V
VSENSE = 5 V
–29
–40
–200
100
0.04
0.37
1.5
–52
–241
250
20
VCOMP voltage during OLP
VSENSE = 0.5 V, IVCOMP= 0.5 mA
VCOMP = 2 V, VCC = floating
IVCOMP = –100 µA, VSENSE = 4 V
VCOMP = 0 V
0.00
0.10
VCOMP rapid discharge current
VCOMP precharge voltage
mA
V
VPRECHARGE
IPRECHARGE
VCOMP precharge current
–1
mA
%VREF
VSENSE threshold, end-of-soft-start
Initial Start-up
98
Gate Driver
GATE current, peak, sinking(2)
GATE current, peak, sourcing(2)
GATE rise time
CGATE = 4.7 nF
2.0
–1.5
40
A
A
CGATE = 4.7 nF
CGATE = 4.7 nF, GATE = 2 V to 8 V
CGATE = 4.7 nF, GATE = 8 V to 2 V
IGATE = 0 A
8
8
60
40
ns
ns
V
GATE fall time
25
GATE low voltage, no load
GATE low voltage, sinking
GATE low voltage, sourcing
GATE low voltage, sinking, OFF
GATE low voltage, sinking, OFF
GATE high voltage
0.00
0.04
–0.04
0.20
0.8
0.01
0.06
–0.06
0.31
1.4
IGATE = 20 mA
V
IGATE = -20 mA
V
VCC = 5 V, IGATE = 5 mA
VCC = 5 V, IGATE = 20 mA
VCC = 20 V, CGATE = 4.7 nF
VCC = 12.2 V, CGATE = 4.7 nF
0.10
0.4
V
V
14.5
10.8
15.2
11.2
16.1
12
V
GATE high voltage
V
VCC = VCCOFF + 0.2 V,
CGATE = 4.7 nF
GATE high voltage
8.2
9.0
10.1
V
(2) Not production tested. Characterized by design
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DEVICE INFORMATION
SOIC (TOP VIEW)
GND
GATE
VCC
1
2
3
4
8
7
6
5
ICOMP
ISENSE VSENSE
FREQ
VCOMP
PIN FUNCTIONS
NAME
GATE
I/O
PIN #
FUNCTION
Gate Drive: Integrated push-pull gate driver for one or more external power MOSFETs. Typical 2.0-A sink
and 1.5-A source capability. Output voltage is typically clamped at 15.2 V (typical).
O
8
1
GND
Ground: device ground reference.
Current Loop Compensation: Transconductance current amplifier output. A capacitor connected to GND
provides compensation and averaging of the current sense signal in the current control loop. The controller is
disabled if the voltage on ICOMP is less than 0.2 V, (ICOMPP protection function).
ICOMP
O
I
2
Inductor Current Sense: Input for the voltage across the external current sense resistor, which represents
the instantaneous current through the PFC boost inductor. This voltage is averaged by the current amplifier to
eliminate the effects of ripple and noise. Soft Over Current (SOC) limits the average inductor current. Cycle-
by-cycle peak current limit (PCL) immediately shuts off the GATE drive if the peak-limit voltage is exceeded.
An internal 2.3-µA current source pulls ISENSE above 0.085 V to shut down PFC operation if this pin
becomes open-circuited, (ISOP protection function). Use a 220-Ω resistor between this pin and the current
sense resistor to limit inrush-surge currents into this pin.
ISENSE
VCC
3
Device Supply: External bias supply input. Under-Voltage Lockout (UVLO) disables the controller until VCC
exceeds a turn-on threshold of 11.5 V. Operation continues until VCC falls below the turn-off (UVLO)
threshold of 9.5 V. A ceramic by-pass capacitor of 0.1 µF minimum value should be connected from VCC to
GND as close to the device as possible for high-frequency filtering of the VCC voltage.
7
Voltage Loop Compensation: Transconductance voltage error amplifier output. A resistor-capacitor network
connected from this pin to GND provides compensation. VCOMP is held at GND until VCC, and VSENSE
exceed their threshold voltages. Once these conditions are satisfied, VCOMP is charged until the VSENSE
voltage reaches its nominal regulation level. When Enhanced Dynamic Response (EDR) is engaged, a higher
transconductance is applied to VCOMP to reduce the charge or discharge time for faster transient response.
Soft Start is programmed by the capacitance on this pin. VCOMP is pulled low when VCC UVLO,
OLP/Standby, ICOMPP and ISOP functions are activated.
VCOMP
FREQ
O
O
5
4
Switching Frequency Setting: This pin allows the setting of the operating switching frequency by connecting
a resistor to ground. The programmable frequency range is from 18 kHz to 250 kHz.
Output Voltage Sense: An external resistor-divider network connected from this pin to the PFC output
voltage provides feedback sensing for regulation to the internal 5-V reference voltage. A small capacitor from
this pin to GND filters high-frequency noise. Standby disables the controller and discharges VCOMP when
the voltage at VSENSE drops below the Open-Loop Protection (OLP) threshold of 16.5%VREF (0.82 V). An
internal 100-nA current source pulls VSENSE to GND during pin disconnection. Enhanced Dynamic
Response (EDR) rapidly returns the output voltage to its normal regulation level when a system line or load
step causes VSENSE to rise above 105% or fall below 95% of the reference voltage. Two level Output Over-
Voltage Protection (OVP): a 4-kΩ resistor connects VCOMP to ground to rapidly discharge VCOMP when
VSENSE exceeds 107% (VOVP_L) of the reference voltage. If VSENSE exceeds 109% (VOVP_H) of the
reference voltage, GATE output will be disabled until VSENSE drops below 102% of the reference voltage.
VSENSE
I
6
6
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BLOCK DIAGRAM
EMI Filter
LBST
DBST
VOUT
LINE
INPUT
Bridge
Rectifier
–
+
RFB1
QBST
RGATE
CIN
COUT
RLOAD
RFB2
RSENSE
Auxiliary Supply
VCC
UCC28180 Block Diagram
+
+
7
Under voltage lockout
VCCON
11.5V
ICOMP Protection
Q
Q
S
R
CVCC
GND
0.2V
+
ICOMPP
VCCOFF
9.5V
1
UVLO
ICOMP
2
PWM
Comparator
KPC(s)
Current
Amplifier
Gate Driver
+
gmi
CICOMP
S
Q
Q
+
3V
PWM
RAMP
M2
R
FAULT
GAIN
M1, K1
GATE
O
V
P
|
O
L
P
I
OVP_H
Min Off Time
8
S
O
P
Oscillator
H
PCL
S
R
Q
Q
Pre-Drive and
Clamp Circuit
Clock
M2
M1
VCOMP
+
Q
S
OVP_H
RISENSEfilter
5.45V
5.10V
4k
Q
R
+
+
+
ISENSE
Peak Current Limit(PCL)
3
300ns
Leading Edge
Blanking
Over voltage protection
5.35V
1V
PCL
OVP_L
SOC
CISENSEfilter
+
+
-2.5X
EDR
EDR
5.25V
Soft Over Current(SOC)
0.72V
Over voltage detector
4.75V
+
+
SOC
ISOP
Under voltage detector
0.82V
+
OLP/STANDBY
ICOMPP
FREQ
100nA
Oscillator
Voltage Error
Amplifier
ISOP
UVLO
OLP
4
FAULT
5V
+
gmv
RFREQ
VSENSE
CVSENSE
6
5
gmv Enhancement
End of soft start detector
4.9V
+
END OF SS
VCOMP
RCV
Rapid Discharge
when
VCC < VCCOFF
EDR
UVLO
SS
Q
Q
S
R
END OF SS
FAULT
CCV2
FAULT
CCV1
VPRECHARGE
FAULT
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TYPICAL CHARACTERISTICS
0.99
0.97
0.95
0.93
0.91
0.89
0.87
0.85
VCC = 15 V
265
215
165
115
65
15
0
20
40
60
80
100
120
140
15 35 55 75 95 115 135 155 175 195 215 235 255
RFREQ (K)
FSW ± Switching Frequency (kHz)
C001
C002
Figure 1. Switching Frequency vs. Resistor
Figure 2. Maximum Duty Cycle vs. Switching Frequency
12.0
11.5
11.0
10.5
10.0
9.5
3.5
TJ = 25C
VSENSE = 3 V
No Gate Load
VCC Turn ON
3.0
FSW = 65 kHz
2.5
2.0
1.5
1.0
0.5
0.0
ICC Turn ON
VCC Turn OFF
ICC Turn OFF
9.0
8.5
8.0
10
60
110
±40
0
5
10
15
20
25
TJ ± Temperature (C)
VCC ± Bias Supply Voltage (V)
C003
C004
Figure 3. UVLO Threshold vs. Temperature
Figure 4. Supply Current vs. Bias Supply Voltage
8
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TYPICAL CHARACTERISTICS (continued)
9
8
7
6
5
4
3
2
1
0
70
65
60
55
50
45
40
35
30
VCC = 15 V
VCC = VCCON t 0.2 V
Operating, GATE Load = 4.7 nF
Pre-Start
Standby
10
60
110
10
60
TJ ± Temperature (C)
110
±40
±40
TJ ± Temperature (C)
C005
C006
Figure 5. Supply Current vs. Temperature
Figure 6. Pre-Start Supply Current vs. Temperature
75
73
71
69
67
65
63
61
59
57
55
75
73
71
69
67
65
63
61
59
57
55
VCC = 15 V
FSW = 65 kHz
TJ = 25C
FSW = 65 kHz
Switching Frequency
Switching Frequency
10
60
110
9
11
13
15
17
19
21
23
±40
TJ ± Temperature (C)
VCC ± Bias Supply Voltage (V)
C007
C008
Figure 7. Oscillator Frequency (65 kHz) vs. Temperature
Figure 8. Oscillator Frequency (65 kHz) vs. Bias Supply
Voltage
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TYPICAL CHARACTERISTICS (continued)
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
15.5
15.0
250.0
249.5
249.0
248.5
248.0
247.5
247.0
246.5
246.0
245.5
245.0
VCC = 15 V
VCC = 15 V
0
25
50
75
100
125
0
25
50
75
100
125
±50
±25
±50
±25
Temperature (C)
Temperature (C)
C006
C002
Figure 9. Oscillator Frequency (18 kHz) vs. Temperature
Figure 10. Oscillator Frequency (250 kHz) vs. Temperature
20.0
250.0
TJ = 25C
TJ = 25C
19.5
249.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
15.5
15.0
249.0
248.5
248.0
247.5
247.0
246.5
246.0
245.5
245.0
9
11
13
15
17
19
21
9
11
13
15
17
19
21
Bias Supply Voltage (V)
Bias Supply Voltage (V)
C003
C004
Figure 11. Oscillator Frequency (18 kHz) vs. Bias Voltage
Figure 12. Oscillator Frequency (250 kHz) vs. Bias Voltage
2.0
±45
VCC = 15 V
VCC = 15 V
1.8
1.6
1.4
1.2
1.0
±47
±49
±51
±53
±55
Gain, No EDR
0.8
0.6
0.4
0.2
0.0
±57
Gain
±59
±61
±63
±65
10
60
TJ ± Temperature (C)
110
10
60
110
±40
±40
T
J t Temperature (C)
C009
C010
Figure 13. Current Loop Gain vs. Temperature
Figure 14. Voltage Loop Gain vs. Temperature
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TYPICAL CHARACTERISTICS (continued)
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
0.00
±0.05
±0.10
±0.15
±0.20
±0.25
±0.30
±0.35
±0.40
±0.45
±0.50
VCC = 15 V
VCC = 15 V
Reference Voltage
Soft Over-Current Protection (SOC)
10
60
110
10
60
110
±40
±40
TJ ± Temperature (C)
TJ ± Temperature (C)
C011
C012
Figure 15. Reference Voltage vs. Temperature
Figure 16. ISENSE Threshold Soft Over Current (SOC) vs.
Temperature
2.0
115
110
105
100
95
VCC = 15 V
VCC = 15 V
1.8
1.6
1.4
1.2
VOVP_H
VOVP_L
VOVD
VOVP_H(RST
)
1.0
VOLP
0.8
0.6
0.4
0.2
0.0
VUVD
90
10
35
60
85
110
10
60
110
±40
±15
±40
T
J t Temperature (C)
TJ ± Temperature (C)
C013
C014
Figure 17. VSENSE Threshold vs. Temperature
Figure 18. VSENSE Threshold Open Loop vs. Temperature
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TYPICAL CHARACTERISTICS (continued)
650
630
610
590
570
550
530
510
490
470
450
50
45
40
35
30
25
20
15
10
5
VSENSE = 3 V
ICOMP = 0.72 V
FSW = 65 kHz
VCC = 15 V
CGATE = 4.7 nF
VGATE = 2 V-8 V
tOFF(min)
Rise Time
Fall Time
0
10
35
60
85
110
10
35
60
85
110
±40
±15
±40
±15
TJ ± Temperature (C)
TJ ± Temperature (C)
C015
C016
Figure 19. Minimum Off Time vs. Temperature
Figure 20. Gate Drive Rise/Fall Time vs. Temperature
50
45
40
35
30
25
20
15
10
5
2.0
TJ = 25C
CGATE = 4.7 nF
VGATE = 2 V-8 V
VCC = 15 V
IGATE = 20 mA
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Rise Time
Fall Time
VGATE
0
10
12
14
16
18
20
22
10
35
60
85
110
±40
±15
VCC ± Bias Supply Voltage (V)
TJ ± Temperature (C)
C017
C018
Figure 21. Gate Drive Rise/Fall Time vs. Bias Supply
Voltage
Figure 22. Gate Low Voltage vs. Temperature
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APPLICATION INFORMATION
UCC28180 Operation
The UCC28180 is a switch-mode controller used in boost converters for power factor correction operating at a
fixed frequency in continuous conduction mode. The UCC28180 requires few external components to operate as
an active PFC pre-regulator. The operating switching frequency can be programmed from 18 kHz to 250 kHz
simply by connecting the FREQ pin to ground through a resistor.
The internal 5-V reference voltage provides for accurate output voltage regulation over the typical world-wide 85-
VAC to 265-VAC mains input range from zero to full output load. The usable system load ranges from 100 W to
few kW.
Regulation is accomplished in two loops. The inner current loop shapes the average input current to match the
sinusoidal input voltage under continuous inductor current conditions. Under light-load conditions, depending on
the boost inductor value, the inductor current may go discontinuous but still meet Class-A/D requirements of IEC
61000-3-2 despite the higher harmonics. The outer voltage loop regulates the PFC output voltage by generating
a voltage on VCOMP (dependent upon the line and load conditions) which determines the internal gain
parameters for maintaining a low-distortion, steady-state, input-current wave shape.
Bias Supply
The UCC28180 operates from an external bias supply. It is recommended that the device be powered from a
regulated auxiliary supply. (This device is not intended to be used from a bootstrap bias supply. A bootstrap bias
supply is fed from the input high voltage through a resistor with sufficient capacitance on VCC to hold up the
voltage on VCC until current can be supplied from a bias winding on the boost inductor. For that reason, the
minimal hysteresis on VCC would require an unreasonable value of hold-up capacitance.)
During normal operation, when the output is regulated, current drawn by the device includes the nominal run
current plus the current supplied to the gate of the external boost switch. Decoupling of the bias supply must take
switching current into account in order to keep ripple voltage on VCC to a minimum. A ceramic capacitor of 0.1-
µF minimum value from VCC to GND with short, wide traces is recommended.
VCC
VCC(ON) 11.5V
VCC(
9.5V
OFF)
ICC
ICC(ON)
ICC(stby) < 2.95 mA
ICC(prestart) < 75 µA
Controller
State
Soft-
Start
UVLO
OFF
Run
Run
UVLO
OFF
Soft-Start
Fault/standby
OFF
PWM
State
Ramp
Regulated
Ramp Regulated
Figure 23. Device Supply States
The device's bias operates in several states. During startup, VCC Under-Voltage LockOut (UVLO) sets the
minimum operational DC input voltage of the controller. There are two UVLO thresholds. When the UVLO turn-on
threshold is exceeded, the PFC controller turns ON. If the VCC voltage falls below the UVLO turn-off threshold,
the PFC controller turns off. During UVLO, current drawn by the device is minimal. After the device turns on, Soft
Start (SS) is initiated and the boost inductor current is ramped up in a controlled manner to reduce the stress on
the external components and avoids output voltage overshoot. During soft start and after the output is in
regulation, the device draws its normal run current. If any of several fault conditions are encountered or if the
device is put in standby with an external signal, the device draws a reduced standby current.
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Soft Start
Soft-Start controls the rate of rise of VCOMP in order to obtain a linear control of the increasing duty cycle as a
function of time. VCOMP, the output of the voltage loop transconductance amplifier, is pulled low during UVLO,
ICOMPP, ISOP and OLP (Open-Loop Protection)/STANDBY. Once the fault condition is released, an initial pre-
charge source rapidly charges VCOMP to 1.5 V. After that point, a constant 40 µA of current is sourced into the
compensation components causing the voltage on this pin to ramp linearly until the output voltage reaches 85%
of its final value. At this point, the sourcing current decreases until the output voltage reaches its final rated
voltage. The soft-start time is controlled by the voltage error amplifier compensation capacitor values selected,
and is user programmable based on desired loop crossover frequency. Once the output voltage exceeds 98% of
rated voltage, soft start is over, the initial pre-charge source is disconnected, and EDR is no longer inhibited.
Soft-Start
5V
+
gmv
VCOMP
FAULT
VSENSE
VCOMP
ISS = -40uA
for VSENSE < 4.25V
during Soft-Start
FAULT
END OF SS
(LATCHED)
1.5V source for
rapid pre-charge
of VCOMP prior
to Soft-Start
+
Figure 24. Soft Start
System Protection
System-level protection features help keep the system within safe operating limits.
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VCC Under-Voltage LockOut (UVLO)
VCC
Auxiliary Supply
CDECOUPLE
GND
UVLO
Figure 25. UVLO
During startup, Under-Voltage LockOut (UVLO) keeps the device in the off state until VCC rises above the 11.5-
V enable threshold, VCCON. With a typical 1.7 V of hysteresis on UVLO to increase noise immunity, the device
turns off when VCC drops to the 9.5-V disable threshold, VCCOFF
.
If, during a brief AC-line dropout, the VCC voltage falls below the level necessary to bias the internal FAULT
circuitry, the UVLO condition enables a special rapid discharge circuit which continues to discharge the VCOMP
capacitors through a low impedance despite a complete lack of VCC. This helps to avoid an excessive current
surge should the AC-line return while there is still substantial voltage stored on the VCOMP capacitors. Typically,
these capacitors can be discharged to less than 1 V within 150 ms of loss of VCC.
Output Over-Voltage Protection (OVP)
There are two levels of OVP: When VSENSE exceeds 107% (VOVP_L) of the reference voltage, a 4-kΩ resistor
connects VCOMP to ground to rapidly discharge VCOMP. If VSENSE exceeds 109% (VOVP_H) of the reference
voltage, GATE output is disabled until VSENSE drops below 102% of the reference voltage.
Open Loop Protection/Standby (OLP/Standby)
If the output voltage feedback components were to fail and disconnect (open loop) the signal from the VSENSE
input, then it is likely that the voltage error amp would increase the GATE output to maximum duty cycle. To
prevent this, an internal pull-down forces VSENSE low. If the output voltage falls below 16.5% of its rated
voltage, causing VSENSE to fall below 0.82 V, the device is put in standby, a state where the PWM switching is
halted and the device is still on but draws standby current below 2.95 mA. This shutdown feature also gives the
designer the option of pulling VSENSE low with an external switch (standby function).
ISENSE Open-Pin Protection (ISOP)
If the current feedback components were to fail and disconnect (open loop) the signal to the ISENSE input, then
it is likely that the PWM stage would increase the GATE output to maximum duty cycle. To prevent this, an
internal pull-up source drives ISENSE above 0.085 V so that a detector forces a state where the PWM switching
is halted and the device is still on but draws standby current below 2.95 mA. This shutdown feature avoids
continual operation in OVP and severely distorted input current.
ICOMP Open-Pin Protection (ICOMPP)
If the ICOMP pin shorts to ground, then the GATE output increases to maximum duty cycle. To prevent this,
once ICOMP pin voltage falls below 0.2 V, the PWM switching is halted and the device is still on but draws
standby current below 2.95 mA .
FAULT Protection
VCC UVLO, OLP/Standby, ISOP and ICOMPP funtions constitute the fault protection feature in the UCC28180.
Under fault protection, VCOMP pin is pulled low and the device is in standby.
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Output Over-Voltage Detection (OVD), Under-Voltage Detection (UVD) and Enhanced Dynamic
Response (EDR)
During normal operation, small perturbations on the PFC output voltage rarely exceed ±5% deviation and the
normal voltage control loop gain drives the output back into regulation. For large changes in line or load, if the
output voltage perturbation exceeds ±5%, an output over-voltage (OVD) or under-voltage (UVD) is detected and
Enhanced Dynamic Response (EDR) acts to speed up the slow response of the low-bandwidth voltage loop.
During EDR, the transconductance of the voltage error amplifier is increased approximately five times to speed
charging or discharging the voltage-loop compensation capacitors to the level required for regulation. EDR is
disabled when 5.25 V > VSENSE > 4.75 V. The EDR feature is not activated until soft start is completed. The
UVD is disabled during soft over protection (SOC) condition (since UVD and SOC conflict with each other).
Over Voltage Protection
Enhanced Dynamic Response
Open Loop Protection/ Standby
Soft-Start Complete
+
OVP_L
5.35V
+
OVP_H
5.45V
S
R
Q
Q
OVERVOLTAGE
PROTECTION
+
5.10V
Output Voltage
Standby
EDR
EDR
+
+
RFB1
VSENSE
OVERVOLTAGE
DETECTION
5.25V
UNDERVOLTAGE
DETECTION
4.75V
4.9V
RFB2
Optional
END OF SS
SOFT-START COMPLETE
+
+
OPEN LOOP
PROTECTION/STANDBY
OLP/STANDBY
0.82V
Figure 26. OVP_H, OVP_L, EDR, OLP, Soft Start Complete
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Over-Current Protection
Inductor current is sensed by RISENSE, a low value resistor in the return path of input rectifier. The other side of
the resistor is tied to the system ground. The voltage is sensed on the rectifier side of the sense resistor and is
always negative. The voltage at ISENSE is buffered by a fixed gain of -2.5 to provide a positive internal signal to
the current functions. There are two over-current protection features; Soft Over-Current (SOC) protects against
an overload on the output and Peak Current Limit (PCL) protects against inductor saturation.
Soft Over Current (SOC)
0.72V
SOC
ISENSE Open-Pin
Protection (ISOP)
+
LINE
INPUT
–
+
IISOP
2µA
VOUT
VISOP
0.082V
ISOP
RISENSE
+
ISENSE
CISENSEfilter
RISENSEfilter
300ns
Leading Edge
Blanking
(Optional)
PCL
1V
+
+
-2.5x
Peak Current Limit (PCL)
Figure 27. Soft Over-Current/Peak-Current Limit
Soft Over-Current (SOC)
Soft Over-Current (SOC) limits the input current. SOC is activated when the current sense voltage on ISENSE
reaches -0.285 V. This is a soft control as it does not directly switch off the gate driver. Instead a 4-kΩ resistor
connects VCOMP to ground to discharges VCOMP and the control loop is adjusted to reduce the PWM duty
cycle. The under-voltage detection (UVD) is disabled during SOC.
Peak Current Limit (PCL)
Peak Current Limit (PCL) operates on a cycle-by-cycle basis. When the current sense voltage on ISENSE
reaches –0.4 V, PCL is activated, immediately terminating the active switch cycle. PCL is leading-edge blanked
to improve noise immunity against false triggering.
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Current Sense Resistor, RISENSE
The current sense resistor, RISENSE, is sized using the minimum threshold value of Soft Over Current (SOC),
VSOC(min) . To avoid triggering this threshold during normal operation, resulting in a decreased duty-cycle, the
resistor is sized for an overload current of 10% more than the peak inductor current,
VSOC(min)
RISENSE
£
1.1 IL _ PEAK(max)
(1)
Since RISENSE “sees” the average input current, worst-case power dissipation occurs at input low-line when input
current is at its maximum. Power dissipated by the sense resistor is given by:
PRISENSE = I
(
2 R
)
IN_RMS(max)
ISENSE
(2)
Peak current limit (PCL) protection turns off the output driver when the voltage across the sense resistor reaches
the PCL threshold, VPCL. The absolute maximum peak current, IPCL, is given by:
VPCL / 2.5
=
IPCL
RISENSE
(3)
Gate Driver
The GATE output is designed with a current-optimized structure to directly drive large values of total
MOSFET/IGBT gate capacitance at high turn-on and turn-off speeds. An internal clamp limits voltage on the
MOSFET gate to 15.2 V (typical). When VCC voltage is below the UVLO level, the GATE output is held in the off
state. An external gate drive resistor, RGATE, can be used to limit the rise and fall times and dampen ringing
caused by parasitic inductances and capacitances of the gate drive circuit and to reduce EMI. The final value of
the resistor depends upon the parasitic elements associated with the layout and other considerations. A 10-kΩ
resistor close to the gate of the MOSFET/IGBT, between the gate and ground, discharges stray gate capacitance
and helps protect against inadvertent dv/dt-triggered turn-on.
Gate Driver
VCC
7
PWM
FAULT
GATE
GND
OVP_H
8
1
PCL
S
R
Q
Q
Pre-Drive and
Clamp Circuit
Clock
Figure 28. Gate Driver
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Current Loop
The overall system current loop consists of the current averaging amplifier stage, the pulse width modulator
(PWM) stage, the external boost inductor stage and the external current sensing resistor.
ISENSE and ICOMP Functions
The negative polarity signal from the current sense resistor is buffered and inverted at the ISENSE input. The
internal positive signal is then averaged by the current amplifier (gmi), whose output is the ICOMP pin. The
voltage on ICOMP is proportional to the average inductor current. An external capacitor to GND is applied to the
ICOMP pin for current loop compensation and current ripple filtering. The gain of the averaging amplifier is
determined by the internal VCOMP voltage. This gain is non-linear to accommodate the world-wide AC-line
voltage range.
ICOMP is connected to 3-V internally whenever OVP_H, ISOP, or OLP is triggered.
Pulse Width Modulator
The PWM stage compares the ICOMP signal with a periodic ramp to generate a leading-edge-modulated output
signal which is high whenever the ramp voltage exceeds the ICOMP voltage. The slope of the ramp is defined by
a non-linear function of the internal VCOMP voltage.
The PWM output signal always starts low at the beginning of the cycle, triggered by the internal clock. The output
stays low for a minimum off-time, tOFF_min, after which the ramp rises linearly to intersect the ICOMP voltage. The
ramp-ICOMP intersection determines tOFF, and hence DOFF. Since DOFF = VIN/VOUT by the boost-topology
equation, and since VIN is sinusoidal in wave-shape, and since ICOMP is proportional to the inductor current, it
follows that the control loop forces the inductor current to follow the input voltage wave-shape to maintain boost
regulation. Therefore, the average input current is also sinusoidal in wave-shape.
PWM cycle
VICOMP
VRAMP = F(VCOMP
)
tON
tOFF
Figure 29. PWM Generation
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Control Logic
The output of the PWM comparator stage is conveyed to the GATE drive stage, subject to control by various
protection functions incorporated into the device. The GATE output duty-cycle may be as high as 98%, but
always has a minimum off-time tOFF_min. Normal duty-cycle operation can be interrupted directly by OVP_H and
PCL. UVLO, ISOP, ICOMMP and OLP/Standby also terminate the GATE output pulse, and further inhibit output
until the SS operation can begin.
Voltage Loop
The outer control loop of the PFC controller is the voltage loop. This loop consists of the PFC output sensing
stage, the voltage error amplifier stage, and the non-linear gain generation.
Output Sensing
A resistor-divider network from the PFC output voltage to GND forms the sensing block for the voltage control
loop. The resistor ratio is determined by the desired output voltage and the internal 5-V regulation reference
voltage.
The very low bias current at the VSENSE input allows the choice of the highest practicable resistor values for
lowest power dissipation and standby current. A small capacitor from VSENSE to GND serves to filter the signal
in a high-noise environment. This filter time constant should generally be less than 100 µs.
Voltage Error Amplifier
The transconductance error amplifier (gmv) generates an output current proportional to the difference between the
voltage feedback signal at VSENSE and the internal 5-V reference. This output current charges or discharges
the compensation network capacitors on the VCOMP pin to establish the proper VCOMP voltage for the system
operating conditions. Proper selection of the compensation network components leads to a stable PFC pre-
regulator over the entire AC-line range and 0% to 100% load range. The total capacitance also determines the
rate-of-rise of the VCOMP voltage at Soft Start, as discussed earlier.
The amplifier output VCOMP is pulled to GND during any fault or standby condition to discharge the
compensation capacitors to an initial zero state. Usually, the large capacitor has a series resistor which delays
complete discharge for their respective time constant (which may be several hundred milliseconds). If VCC bias
voltage is quickly removed after UVLO, the normal discharge transistor on VCOMP loses drive and the large
capacitor could be left with substantial voltage on it, negating the benefit of a subsequent Soft Start. The
UCC28180 incorporates a parallel discharge path which operates without VCC bias, to further discharge the
compensation network after VCC is removed.
If the output voltage perturbations exceed ±5%, and output over-voltage (OVD) or under-voltage (UVD) is
detected, the OVD or UVD function invokes EDR which immediately increases the voltage error amplifier
transconductance to about 280 µS. This higher gain facilitates faster charging or discharging the compensation
capacitors to the new operating level. When output voltage perturbations greater than 107%VREF appear at the
VSENSE input, a 4-kΩ resistor connects VCOMP to ground to quickly reduce VCOMP voltage. When output
voltage perturbations are greater than 109%VREF, the GATE output is shut off until VSENSE drops below 102%
of regulation.
Non-Linear Gain Generation
The voltage at VCOMP is used to set the current amplifier gain and the PWM ramp slope. This voltage is subject
to modification by the SOC function, as discussed earlier.
Together the current gain and the PWM slope adjust to the different system operating conditions (set by the AC-
line voltage and output load level) as VCOMP changes, to provide a low-distortion, high-power-factor, input-
current wave shape following that of the input voltage.
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Design Example
Design Goals
This example illustrates the design process and component selection for a continuous mode power factor
correction boost converter utilizing the UCC28180. The pertinent design equations are shown for a universal
input, 360-W PFC converter with an output voltage of 390 V.
Table 1. Design Goal Parameters
PARAMETER
Input Characteristics
TEST CONDITION
MIN
TYP
MAX
UNIT
VIN
Input voltage
85
47
265
VAC
Hz
fLINE
Input frequency
63
VIN = VIN(min)
IOUT = IOUT(max)
,
IIN(peak)
Peak input current
7
A
Output Characteristics
V
IN(min) ≤ VIN ≤ VIN(max)
fLINE(min) ≤ fLINE≤ fLINE(max)
OUT ≤ IOUT(max)
,
VOUT
Output voltage
Line Regulation
,
379
390
402
5%
5%
VDC
I
V
IN(min) ≤ VIN≤ VIN(max),
IOUT = IOUT(max)
VIN = 115 VAC,
fLINE = 60 Hz,
I
OUT(min) ≤ IOUT ≤ IOUT(max)
Load Regulation
VIN = 230 VAC,
fLINE = 60 Hz,
5%
I
OUT(min)≤ IOUT ≤ IOUT(max)
IN(min) ≤ VIN ≤ VIN(max)
fLINE(min) ≤ fLINE ≤ fLINE(max)
IN(min) ≤ VIN ≤ VIN(max)
LINE(min) ≤ fLINE ≤ fLINE(max)
V
IOUT
Output Load Current
Output Power
0
0
0.923
360
A
V
f
POUT
W
VIN = 115 VAC,
fLINE = 60 Hz
IOUT = IOUT(max)
2.5
2.5
3.9
3.9
VRIPPLE(SW High frequency
VP-P
Output voltage ripple
)
VIN = 230 VAC,
fLINE = 50 Hz
IOUT = IOUT(max)
VIN = 115 VAC,
fLINE = 60 Hz,
IOUT = IOUT(max)
11.6
13.3
19.5
19.5
VRIPPLE(f_LI Line frequency
VP-P
Output voltage ripple
NE)
VIN = 230 VAC,
fLINE = 50 Hz,
IOUT = IOUT(max)
Output over voltage
protection
VOUT(OVP)
VOUT(UVP)
425
370
V
Output under voltage
protection
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UNIT
Table 1. Design Goal Parameters (continued)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
Control Loop Characteristics
fSW
Switching frequency
TJ = 25°C
114
120
126
kHz
Hz
VIN = 162 VDC,
IOUT = 0.466 A
f(CO)
Voltage Loop Bandwidth
8
68
VIN = 162 VDC,
IOUT = 0.466 A
Voltage Loop Phase Margin
Power Factor
°
VIN = 115 VAC,
IOUT = IOUT(max)
PF
0.99
VIN = 115 VAC,
fLINE = 60 Hz,
IOUT = IOUT(max)
4.3%
4%
10%
10%
THD
Total harmonic distortion
VIN = 230 VAC,
fLINE = 50 Hz
IOUT = IOUT(max)
VIN = 115 VAC,
fLINE = 60 Hz,
IOUT = IOUT(max)
η
Full load efficiency
94%
25
Ambient temperature
°C
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The following procedure refers to the schematic shown in Figure 30.
+
-
Figure 30. Design Example Schematic
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Current Calculations
The input fuse, bridge rectifier, and input capacitor are selected based upon the input current calculations. First,
determine the maximum average output current, IOUT(max)
POUT(max)
IOUT(max) =
:
VOUT
(4)
(5)
360W
390 V
IOUT(max)
=
@ 0.923 A
The maximum input RMS line current, IIN_RMS(max), is calculated using the parameters from Table 1 and the
efficiency and power factor initial assumptions:
POUT(max)
I IN_ RMS(max)
=
hVIN(min)PF
(6)
(7)
360W
I IN_ RMS(max)
=
= 4.551A
0.94 ´85 V ´0.99
Based upon the calculated RMS value, the maximum input current, IIN (max), and the maximum average input
current, IIN_AVG(max), assuming the waveform is sinusoidal, can be determined.
I
=
2I
IN_ RMS(max)
IN(max)
(8)
(9)
I
=
2 ´ 4.551A = 6.436 A
IN(max)
2I
IN(max)
I
=
IN_ AVG(max)
p
(10)
(11)
2´ 6.436 A
I
=
= 4.097 A
IN_ AVG(max)
p
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The Switching Frequency
The UCC28180 switching frequency is user programmable with a single resistor on the FREQ pin to ground. For
this design, the switching frequency, fSW, was chosen to be 120 kHz. Figure 31 (same as Figure 1) could be
used to select the suitable resistor to program the switching frequency or the value can be calculated using
constant scaling values of fTYP and RTYP. In all cases, fTYP is a constant that is equal to 65 kHz, RINT is a constant
that is equal to 1 MΩ, and RTYP is a constant that is equal to 32.7 kΩ. Simply applying the calculation below
yields the appropriate resistor that should be placed between FREQ and GND:
f
TYP ´RTYP ´RINT
RFREQ
=
(fSW ´RINT ) + (RTYP ´ fSW ) - (RTYP ´ fTYP
65kHz ´32.7kW ´1MW
)
(12)
(13)
RFREQ
=
= 17.451kW
(120kHz ´1MW) + (32.7kW ´120kHz) - (32.7kW ´ 65kHz)
A typical value of 17.8 kΩ for the FREQ resistor results in a switching frequency of 118 kHz.
265
215
165
115
65
15
0
20
40
60
80
100
120
140
RFREQ (K)
C001
Figure 31. Frequency vs. RFREQ
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Bridge Rectifier
The input bridge rectifier must have an average current capability that exceeds the input average current.
Assuming a forward voltage drop, VF_BRIDGE, of 1 V across the rectifier diodes, BR1, the power loss in the input
bridge, PBRIDGE, can be calculated:
P
= 2VF _ BRIDGEIIN_ AVG(max)
BRIDGE
(14)
(15)
P
= 2´1V ´ 4.097 A = 8.195W
BRIDGE
Heat sinking will be required to maintain operation within the bridge rectifier’s safe operating area.
Inductor Ripple Current
The UCC28180 is a Continuous Conduction Mode (CCM) controller but if the chosen inductor allows relatively
high-ripple current, the converter will be forced to operate in Discontinuous Mode (DCM) at light loads and at the
higher input voltage range. High-inductor ripple current has an impact on the CCM/DCM boundary and results in
higher light-load THD, and also affects the choices for the input capacitor, RSENSE and CICOMP values. Allowing an
inductor ripple current, ΔIRIPPLE, of 20% or less will result in CCM operation over the majority of the operating
range but requires a boost inductor that has a higher inductance value and the inductor itself will be physically
large. As with all converter designs, decisions must be made at the onset in order to optimize performance with
size and cost. In this design example, the inductor is sized in such a way as to allow a greater amount of ripple
current in order to minimize space with the understanding that the converter operates in DCM at the higher input
voltages and at light loads but optimized for a nominal input voltage of 115 VAC at full load. Although specifically
defined as a CCM controller, the UCC28180 is shown in this application to meet the overall performance goals
while transitioning into DCM at high-line voltage, at a higher load level.
Input Capacitor
The input capacitor must be selected based upon the input ripple current and an acceptable high frequency input
voltage ripple. Allowing an inductor ripple current, ΔIRIPPLE, of 40% and a high frequency voltage ripple factor,
ΔVRIPPLE_IN, of 7%, the maximum input capacitor value, CIN, is calculated by first determining the input ripple
current, IRIPPLE, and the input voltage ripple, VIN_RIPPLE
:
I
RIPPLE= DIRIPPLEIIN(max)
(16)
(17)
(18)
(19)
(20)
DIRIPPLE = 0.4
RIPPLE= 0.4 ´ 6.436 A = 2.575 A
= DVRIPPLE _IN
I
V
V
IN_ RECTIFIED(min)
IN_ RIPPLE
DVRIPPLE _IN = 0.07
V
=
2V
IN
IN_ RECTIFIED
(21)
V
=
2 ´85 V = 120 V
IN_ RECTIFIED
(22)
(23)
V
= 0.07 ´120 V = 8.415 V
IN_ RIPPLE
The recommended value for the input x-capacitor can now be calculated:
I
RIPPLE
CIN
=
8fSW
V
IN_ RIPPLE
(24)
(25)
2.575 A
8 118kHz 8.415 V
CIN
=
= 0.324mF
A standard value 0.33-µF Y2/X2 film capacitor is used.
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Boost Inductor
Based upon the allowable inductor ripple current discussed above, the boost inductor, LBST, is selected after
determining the maximum inductor peak current, IL_PEAK
:
IRIPPLE
+
IL _ PEAK(max) = I
IN(max)
(26)
(27)
2.575 A
IL _ PEAK(max) = 6.436 A +
= 7.724 A
The minimum value of the boost inductor is calculated based upon the acceptable ripple current, IRIPPLE, at a
worst case duty cycle of 0.5:
VOUTD(1- D)
LBST(min)
³
fSWIRIPPLE
(28)
(29)
390 V ´0.5(1- 0.5)
118kHz 2.575 A
LBST(min)
³
³ 321mH
The recommended minimum value for the boost inductor assuming a 40% ripple current is 321 µH; the actual
value of the boost inductor that will be used is 327 µH. With this actual value used, the actual resultant inductor
current ripple will be:
LBST = 327mH
(30)
VOUTD(1- D)
IRIPPLE(actual)
=
fSWLBST
(31)
390 V ´0.5(1- 0.5)
118kHz ´327mH
IRIPPLE(actual)
=
= 2.527 A
(32)
(33)
2.527 A
IL _ PEAK(max) = 6.436 A +
= 7.7 A
The duty cycle is a function of the rectified input voltage and will be continuously changing over the half line
cycle. The duty cycle, DUTY(max), can be calculated at the peak of the minimum input voltage:
VOUT - V
=
IN_ RECTIFIED(min)
DUTY
(max)
VOUT
(34)
(35)
V
=
2 ´85 V = 120 V
IN_ RECTIFIED(min)
390 V -120 V
DUTY
=
= 0.692
(max)
390 V
(36)
Boost Diode
The diode losses are estimated based upon the forward voltage drop, VF, at 125°C and the reverse recovery
charge, QRR, of the diode. Using a silicon carbide Schottky diode, although more expensive, will essentially
eliminate the reverse recovery losses and result in less power dissipation:
PDIODE = VF _125CIOUT(max) + 0.5fSW VOUTQRR
(37)
(38)
(39)
VF _125°C = 1V
QRR = 0nC
PDIODE = 1V ´0.923 A + 0.5 ´119kHz ´390 V ´0nC = 0.923W
)
(
) (
(40)
This output diode should have a blocking voltage that exceeds the output over voltage of the converter and be
attached to an appropriately sized heat sink.
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Switching Element
The MOSFET/IGBT switch will be driven by a GATE output that is clamped at 15.2 V for VCC bias voltages
greater than 15.2 V. An external gate drive resistor is recommended to limit the rise time and to dampen any
ringing caused by the parasitic inductances and capacitances of the gate drive circuit; this will also help in
meeting any EMI requirements of the converter. The design example uses a 3.3-Ω resistor; the final value of any
design is dependent upon the parasitic elements associated with the layout of the design. To facilitate a fast turn
off, a standard 40-V, 1-A Schottky diode is placed anti-parallel with the gate drive resistor. A 10-kΩ resistor is
placed between the gate of the MOSFET/IGBT and ground to discharge the gate capacitance and protect from
inadvertent dv/dt triggered turn-on.
The conduction losses of the switch MOSFET, in this design are estimated using the RDS(on) at 125°C, found in
the device data sheet, and the calculated drain to source RMS current, IDS_RMS
:
PCOND = ID2S _ RMSRDS(on)125°C
(41)
(42)
RDS(on)125°C = 0.35W
POUT(max)
16V
IN_ RECTIFIED(min)
IDS _ RMS
=
2 -
V
3pVOUT
IN_ RECTIFIED(min)
(43)
360W
120 V
16 ´120 V
3p ´390 V
IDS _ RMS
=
2 -
= 3.639 A
(44)
(45)
PCOND = 3.639 A2 ´0.35W = 4.636W
The switching losses are estimated using the rise time, tr, and fall time, tf, of the MOSFET gate, and the output
capacitance losses.
tr = 5ns
tf = 4.5ns
COSS = 780pF
(46)
(tr + tf ) + 0.5COSSV2
OUT û
é
ù
PSW = fSW 0.5VOUT IN(max)
I
ë
(47)
(48)
é
ë
2 ù
û
PSW = 118kHz 0.5 ´390 V ´ 6.436A(5ns + 4.5ns) + 0.5´ 780pF´390 V = 8.407W
Total FET losses
PCOND + PSW = 4.636W + 8.407W = 13.042W
(49)
The MOSFET requires an appropriately sized heat sink.
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Sense Resistor
To accommodate the gain of the non-linear power limit, the sense resistor, RSENSE, is sized such that it triggers
the soft over current at 10% higher than the maximum peak inductor current using the minimum soft over current
threshold of the ISENSE pin, VSOC, of ISENSE equal to 0.265 V.
VSOC(min)
RSENSE
=
I
L _ PEAK(max) ´1.1
(50)
(51)
0.259 V
RSENSE
=
= 0.032W
7.7 A ´1.1
The power dissipated across the sense resistor, PRSENSE, must be calculated:
PRSENSE = II2N_ RMS(max)RSENSE
(52)
(53)
PRSENSE = 4.551A2 ´0.032W = 0.663W
The peak current limit, PCL, protection feature is triggered when current through the sense resistor results in the
voltage across RSENSE to be equal to the VPCL threshold. For a worst case analysis, the maximum VPCL threshold
is used:
VPCL(max)
IPCL
=
RSENSE
(54)
(55)
0.438 V
IPCL
=
= 13.688 A
0.032W
To protect the device from inrush current, a standard 220-Ω resistor, RISENSE, is placed in series with the ISENSE
pin. A 1000-pF capacitor is placed close to the device to improve noise immunity on the ISENSE pin.
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Output Capacitor
The output capacitor, COUT, is sized to meet holdup requirements of the converter. Assuming the downstream
converters require the output of the PFC stage to never fall below 300 V, VOUT_HOLDUP(min), during one line cycle,
tHOLDUP = 1/fLINE(min), the minimum calculated value for the capacitor is:
2POUT(max)tHOLDUP
VO2UT - VO2UT _ HOLDUP(min)
COUT(min)
³
(56)
(57)
2´360W ´ 21.28ms
390 V2 300 V2
COUT(min)
³
³ 247mF
It is advisable to de-rate this capacitor value by 10%; the actual capacitor used is 270 µF.
Verifying that the maximum peak-to-peak output ripple voltage will be less than 5% of the output voltage ensures
that the ripple voltage will not trigger the output over-voltage or output under-voltage protection features of the
controller. If the output ripple voltage is greater than 5% of the regulated output voltage, a larger output capacitor
is required. The maximum peak-to-peak ripple voltage, occurring at twice the line frequency, and the ripple
current of the output capacitor is calculated:
VOUT _ RIPPLE(pp) < 0.05 VOUT
(58)
VOUT _ RIPPLE(pp) < 0.05 ´390 V = 19.5 VPP
(59)
IOUT
VOUT _ RIPPLE(pp)
=
2p(2fLINE(min))COUT
(60)
(61)
0.923A
VOUT _ RIPPLE(pp)
=
= 5.789 V
2p(2´ 47Hz)´ 270mF
The required ripple current rating at twice the line frequency is equal to:
IOUT(max)
ICOUT _ 2fline
=
2
0.923 A
2
(62)
(63)
ICOUT _ 2fline
=
= 0.653 A
There is a high frequency ripple current through the output capacitor:
16 VOUT
ICOUT _ HF = IOUT(max)
-1.5
3pV
IN_ RECTIFIED(min)
(64)
(65)
16 ´390 V
3p ´120 V
ICOUT _ HF = 0.923 A
-1.5 = 1.848 A
The total ripple current in the output capacitor is the combination of both and the output capacitor must be
selected accordingly:
I
COUT _ RMS(total)= IC2OUT _ 2fline + IC2OUT _ HF
(66)
(67)
I COUT _ RMS(total)
=
0.653 A2 +1.848 A2 = 1.96 A
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Output Voltage Set Point
For low power dissipation and minimal contribution to the voltage set point, it is recommended to use 1 MΩ for
the top voltage feedback divider resistor, RFB1. Multiple resistors in series are used due to the maximum
allowable voltage across each. Using the internal 5-V reference, VREF, the bottom divider resistor, RFB2, is
selected to meet the output voltage design goals.
VREFRFB1
RFB2
=
VOUT - VREF
(68)
(69)
5 V ´1MW
RFB2
=
= 13.04kW
390 V - 5 V
A standard value 13-kΩ resistor for RFB2 results in a nominal output voltage set point of 391 V.
An output over voltage is detected when the output voltage exceeds its nominal set-point level by 5%, as
measured when the voltage at VSENSE is 105% of the reference voltage, VREF. At this threshold, the enhanced
dynamic response (EDR) is triggered and the non-linear gain to the voltage error amplifier will increase the
transconductance to VCOMP and quickly return the output to its normal regulated value. This EDR threshold
occurs when the output voltage reaches the VOUT(ovd) level:
VOVD = 1.05 VREF = 1.05 ´5 V = 5.25 V
(70)
æ
OVD ç
è
ö
÷
ø
RFB1 + RFB2
VOUT(ovd) = V
RFB2
(71)
(72)
æ
ç
è
ö
÷
ø
1MW +13kW
13kW
VOUT(ovd) = 5.25 V ´
= 410.7 V
In the event of an extreme output over voltage event, the GATE output will be disabled if the output voltage
exceeds its nominal set-point value by 9%. The output voltage, VOUT(ovp), at which this protection feature is
triggered is calculated as follows:
æ
REF ç
è
ö
÷
ø
RFB1 + RFB2
VOUT(ovp) = 1.09 ´ V
= 426.4 V
RFB2
(73)
An output under voltage is detected when the output voltage falls below 5% below its nominal set-point as
measured when the voltage at VSENSE is 95% of the reference voltage, VREF
:
VUVD = 0.95 VREF = 0.95 ´5 V = 4.75 V
(74)
æ
UVD ç
è
ö
÷
ø
RFB1 + RFB2
VOUT(uvp) = V
RFB2
(75)
(76)
æ
ç
è
ö
÷
ø
1MW +13kW
13kW
VOUT(uvp) = 4.75 V ´
= 371.6 V
A small capacitor on VSENSE must be added to filter out noise. Limit the value of the filter capacitor such that
the RC time constant is limited to approximately 10 µs so as not to significantly reduce the control response time
to output voltage deviations.
10ms
CVSENSE
=
= 769pF
RFB2
(77)
The closest standard value of 820 pF was used on VSENSE for a time constant of 10.66 µs.
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Loop Compensation
The current loop is compensated first by determining the product of the internal loop variables, M1M2, using the
internal controller constants K1 and KFQ. Compensation is optimized maximum load and nominal input voltage,
115 VAC is used for the nominal line voltage for this design:
IOUT(max)VO2UT 2.5RSENSEK1
M1M2 =
hVI2N_ RMSKFQ
(78)
1
KFQ
=
=
fSW
1
KFQ
= 8.475ms
118kHz
K1 = 7
(79)
(80)
0.923 A ´390 V2 ´ 2.5 ´0.032W ´ 7
0.92´115 V2 ´8.475ms
V
M1M2 =
= 0.751
ms
The VCOMP operating point is found on the following chart, M1M2 vs. VCOMP. Once the M1M2 result is
calculated above, find the resultant VCOMP voltage at that operating point to calculate the individual M1 and M2
components.
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VCOMP (V)
C007
Figure 32. M1M2 vs. VCOMP
For the given M1M2 of 0.751 V/µs, the VCOMP approximately equal to 3 V, as shown in Figure 32.
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The individual loop factors, M1 which is the current loop gain factor, and M2 which is the voltage loop PWM ramp
slope, are calculated using the following conditions:
The M1 non-linear current loop gain factor follows the following identities:
M1 = 0.068
if VCOMP < 1 V
(81)
(82)
(83)
(84)
M1 = 0.156 ´ VCOMP - 0.088
if 1 V < VCOMP < 2 V
if 2 V < VCOMP < 4.5 V
M1 = 0.313 ´ VCOMP - 0.401
M1 = 1.007
if 4.5 V < VCOMP < 5 V
In this example, according to the chart in Figure 32, VCOMP is approximately equal to 3 V, so M1 is calculated
to be approximately equal to 0.538:
M1 = 0.313 ´ 2.45 - 0.401= 0.366
(85)
The M2 non-linear PWM ramp slope will obey the following relationships:
V
M2 = 0
ms
if VCOMP ≤ 0.5 V
(86)
(87)
(88)
fSW
V
M2 =
M2 =
´0.1223 ´(VCOMP - 0.5)2
65kHz
fSW
ms
if 0.5 V ≤ VCOMP ≤ 4.6 V
V
´ 2.056
65kHz
ms
if 4.6 V ≤ VCOMP ≤ 5 V
In this example, with VCOMP approximately equal to 3 V, M2 equals 1.388 V/µs:
118kHz
V
V
M2 =
´0.1223 ´(3 - 0.5)2
= 1.388
65kHz
ms
ms
(89)
Verify that the product of the individual gain factors, M1 and M2, is approximately equal to the M1M2 factor
determined above, if not, iterate the VCOMP value and recalculate M1M2
V
V
M1 ´M2 = 0.538 ´1.388
= 0.747
ms
ms
(90)
The product of M1 and M2 is within 1% of the M1M2 factor previously calculated:
M1 ´M2 @ M1M2
(91)
(92)
V
V
0.747
@ 0.751
ms
ms
If more accuracy was desired, iteration results in a VCOMP value of 3.004 V where M1M2 and M1 x M2 are both
equal to 0.751 V/µs.
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The non-linear gain variable, M3, can now be calculated:
M3 = 0
if VCOMP < 5 V
(93)
(94)
(95)
(96)
fSW
65kHz ms
fSW
65kHz ms
fSW
65kHz ms
fSW
65kHz ms
M3 = 0
V
M3 =
M3 =
M3 =
M3 =
´
´(0.0166´ VCOMP - 0.0083)
if 0.5 V < VCOMP < 1 V
V
´
´(0.0572´ VCOMP2 - 0.0597´ VCOMP + 0.0155)
´(0.1148´ VCOMP2 - 0.1746´ VCOMP + 0.0586)
´(0.1148´ VCOMP2 - 0.1746´ VCOMP + 0.0586)
if 1 V < VCOMP < 2 V
if 2 V < VCOMP < 4.5 V
if 4.5 V < VCOMP < 4.6 V
V
´
V
´
(97)
(98)
if 4.6 V < VCOMP < 5 V
In this example, using 3.004 V for VCOMP for a more precise calculation, M3 calculates to 1.035 V/µs:
118kHz
V
V
M3 =
´
65kHz ms
´(0.1148´3.0042 - 0.1746´ 3.004 + 0.0586) = 1.035
ms
(99)
For designs that allow a high inductor ripple current, the current averaging pole, which functions to flatten out the
ripple current on the input of the PWM comparator, should be at least decade before the converter switching
frequency. Analysis on the completed converter may be needed to determine the ideal compensation pole for the
current averaging circuit as too large of a capacitor on ICOMP will add phase lag and increase iTHD where as too
small of an ICOMP capacitor will result in not enough averaging and an unstable current averaging loop. The
frequency of the current averaging pole, fIAVG, is chosen to be at approximately 5 kHz for this design as the
current ripple factor, ∆IRIPPLE, was chosen at the onset of the design process to be 40%, which is large enough to
force DCM operation and result in relatively high inductor ripple current. The required capacitor on ICOMP,
CICOMP, for this is determined using the transconductance gain, gmi, of the internal current amplifier:
g
mi ´M1
CICOMP
=
K12pf
IAVG
(100)
(101)
0.95mS´0.538
7 ´ 2´ p ´3kHz
CICOMP
=
= 2330pF
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A standard value 2700-pF capacitor for CICOMP results in a current averaging pole frequency of 4.314 kHz.
mi ´M1
K1 ´ 2´ p ´ 2700pF
g
f
=
= 4.314kHz
IAVG
(102)
The transfer function of the current loop can be plotted:
K12.5RSENSEVOUT
1
GCL(f) =
´
s(f)2K1CICOMP
KFQM1M2LBST
s(f) +
gmi ´M1
(103)
(104)
GCLdB(f) = 20log G (f)
(
CL
)
100
80
±80
Gain
±90
Phase
60
±100
±110
±120
±130
±140
±150
±160
±170
±180
40
20
0
±20
±40
±60
±80
±100
10
100
1k
10k
100k
1M
Frequency (Hz)
C005
Figure 33. Bode Plot of the Current Averaging Circuit
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The voltage transfer function, GVL(f) contains the product of the voltage feedback gain, GFB, and the gain from the
pulse width modulator to the power stage, GPWM_PS, which includes the pulse width modulator to power stage
pole, fPWM_PS. The plotted result is shown in Figure 33.
RFB2
GFB
=
R
FB1 + RFB2
13kW
GFB
=
= 0.013
1MW +13kW
(105)
1
fPWM _ PS
=
=
K12.5RSENSEVO3UTCOUT
2p
KFQM1M2V2
IN(nom)
1
fPWM _ PS
= 1.479Hz
7 ´ 2.5 ´0.032W ´390V3 ´ 270mF
2p
V
8.475ms ´0.539´1.392 ´115 V2
ms
(106)
M3VOUT
M1M2 ´1V
GPWM _ PS(f) =
s(f)
1+
2pfPWM_ PS
(107)
(108)
GVL(f) = GFBGPWM _ PS(f)
GVLdB(f) = 20log G (f)
(
VL
)
100
80
0
PWM to Power Stage Gain
Total Open Loop Gain
Total Open Loop Phase
±10
±20
±30
±40
±50
±60
±70
±80
±90
±100
60
40
20
0
±20
±40
±60
±80
±100
0.01
0.1
1
10
100
1000
Frequency (Hz)
C008
Figure 34. Bode Plot of the Open Voltage Loop without Error Amplifier
36
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The voltage error amplifier is compensated with a zero, fZERO, at the fPWM_PS pole and a pole, fPOLE, placed at 20
Hz to reject high frequency noise and roll off the gain amplitude. The overall voltage loop crossover, fV, is desired
to be at 10 Hz. The compensation components of the voltage error amplifier are selected accordingly.
1
fZERO
=
2pRVCOMPCVCOMP
(109)
(110)
1
fPOLE
=
RVCOMPCVCOMPCVCOMP _ P
2p
C
VCOMP + CVCOMP _ P
é
ù
ú
ú
ú
ú
ú
ê
ê
ê
ê
ê
1+ s(f)RVCOMPCVCOMP
GEA(f) = gmv
é
ù
ú
ú
û
æ
ç
ç
è
ö
÷
÷
ø
RVCOMPCVCOMPCVCOMP _ P
C
(
VCOMP + CVCOMP _ P s(f)ê1+ s(f)
)
CVCOMP + CVCOMP _ P
ê
ë
ê
ë
ú
û
(111)
From Figure 34, the gain of the voltage transfer function at 10 Hz is approximately 0.081 dB. Estimating that the
parallel capacitor, CVCOMP_P, is much smaller than the series capacitor, CVCOMP, the unity gain will be at fV, and
the zero will be at fPWM_PS, the series compensation capacitor is determined:
fV = 10Hz
(112)
fV
gmv
fPWM_ PS
(f)
CVCOMP
=
0-G
VLdB
20
10
´ 2pfV
(113)
(114)
10Hz
56ms ´
1.479Hz
CVCOMP
=
= 6.08mF
0-0.081dB
20
10
210Hz
The capacitor for VCOMP must have a voltage rating that is greater than the absolute maximum voltage rating of
the VCOMP pin, which is 7 V. The readily available standard value capacitor that is rated for at least 10 V in the
package size that would fit the application was 4.7 µF and this is the value used for CVCOMP in this design
example.
RVCOMP is calculated using the actual CVCOMP capacitor value.
CVCOMP = 4.7mF
(115)
1
RVCOMP
=
2pfZEROCVCOMP
(116)
(117)
1
RVCOMP
=
= 22.89kW
2´ p ´1.479Hz ´ 4.7mF
A 22.6-kΩ resistor is used for RVCOMP
.
CVCOMP
CVCOMP _ P
=
2pfPOLERVCOMPCVCOMP -1
(118)
(119)
4.7mF
CVCOMP _ P
=
= 0.381mF
2´ p ´ 20Hz ´ 22.6kkW ´ 4.7mF -1
A 0.47-µF capacitor is used for CVCOMP_P
.
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The total closed loop transfer function, GVL_total, contains the combined stages and is plotted in Figure 35.
GVL _ total(f) = GFB(f)GPWM _ PS(f)GEA(f)
(120)
(121)
GVL _ totaldB(f) = 20log G
(
(f)
)
VL _ total
100
100
80
60
40
20
0
50
0
±50
±100
±150
EA Gain
Total Closed Loop Gain
Total Closed Loop Phase Margin
0.01
0.1
1
10
100
1000
Frequency (Hz)
C001
Figure 35. Closed Loop Voltage Bode Plot
38
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SLUSBQ5A –NOVEMBER 2013–REVISED NOVEMBER 2013
Layout Guidelines
Layout Guidelines
As with all PWM controllers, the effectiveness of the filter capacitors on the signal pins depends upon the
integrity of the ground return. Separating the high di/dt induced noise on the power ground from the low current
quiet signal ground is required for adequate noise immunity. Even with a signal layer PCB design, the pin out of
the UCC28180 is ideally suited to minimize noise on the small signal traces. As shown in Figure 36, the
capacitors on VSENSE, VCOMP, ISENSE, ICOMP, and FREQ (if used) must be all be returned directly to the
portion of the ground plane that is the quiet signal GND and not in high-current return path of the converter,
shown as power GND. The trace from the FREQ pin to the frequency programming resistor should be as short
as possible. It is recommended that the compensation components on ICOMP and VCOMP are located as close
as possible to the UCC28180. Placement of these components should take precedence, paying close attention
to keeping their traces away from high noise areas. The bypass capacitors on VCC must be located physically
close the VCC and GND pins of the UCC28180 but should not be in the immediate path of the signal return.
Other layout considerations should include keeping the switch node as short as possible, with a wide trace to
reduce induced ringing caused by parasitic inductance. Every effort should be made to avoid noise from the
switch node from corrupting the small signal traces with adequate clearance and ground shielding. As some
compromises must be made due to limitation of PCB layers or space constraints, traces that must be made long,
such as the signal from the current sense resistor shown in Figure 36, should be as wide as possible, avoid long
narrow traces.
Table 2. Layout Component Description for Figure 36
LAYOUT COMPONENTS
REFERENCE DESIGNATOR
FUNCTION
Controller, UCC28180
U1
Q1
Main switch
D2
Boost diode
R5
RGATE
R7
Pull-down resistor on GATE
Turn-off diode on GATE
D1
C11, C12
C7
VCC bypass capacitors
ICOMP compensation, CICOMP
Placeholders for additional ICOMP compensation, if needed
ISENSE filter, CISENSE
R1, C6
C8
R2
ISENSE inrush current limiting resistor, RISENSE
Frequency programming resistor, RFREQ
Placeholder for FREQ filter, if needed
VCOMP compensation components, RVCOMP, CVCOMP_P, CVCOMP
VSENSE filter, CVSENSE
R3
C9
R6, C13, C14
C15
R11, R12
R13
RFB1 on VSENSE
RFB2 on VSENSE
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Figure 36. Recommended Layout for UCC28180
Additional References
References
These references, additional design tools, and links to additional references, including design software and
models may be found on the web at http://www.power.ti.com under Technical Documents.
User Guide, Using the UCC28180EVM-573, 360-W Power Factor Correction, Texas Instruments Literature No.
SLUUAT3
Design Spreadsheet, UCC28180 Design Calculator, Texas Instruments Literature No. SLUC506
40
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UCC28180
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SLUSBQ5A –NOVEMBER 2013–REVISED NOVEMBER 2013
REVISION HISTORY
Changes from Original (November 2013) to Revision A
Page
•
•
•
•
Added Features bullet, "Reduced Current Sense Threshold" . ............................................................................................ 1
Changed marketing status from Product Preview to Production Data. ................................................................................ 1
Added Figure 8 through Figure 13. ....................................................................................................................................... 8
Changed Figure 31 through Figure 35. .............................................................................................................................. 21
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Nov-2013
PACKAGING INFORMATION
Orderable Device
UCC28180D
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
D
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
U28180
U28180
UCC28180DR
ACTIVE
D
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Nov-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Nov-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC28180DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Nov-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
340.5 338.1 20.6
UCC28180DR
D
8
2500
Pack Materials-Page 2
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