UCC28501N_技术文档

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ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃꢄ ꢅꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

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used to keep input power constant with varying input

voltage. Generation of V is accomplished using I in

conjunction with an external single-pole filter. This not

only reduces external parts count, but also avoids the

use of high-voltage components, offering a lower-cost

solution. The multiplier then divides the line current by

FEATURES

FF

AC

D

Combines PFC and Downstream Converter

Controls

Controls Boost Preregulator to Near-Unity

Power Factor

the square of V

.

D

Accurate Power Limiting

FF

Improved Feedforward Line Regulation

The UCC2850x PFC section incorporates a low

offset-voltage amplifier with 7.5-V reference,

highly-linear multiplier capable of a wide current range,

a high-bandwidth, low offset-current amplifier, with a

a

Peak Current-Mode Control in Second Stage

Programmable Oscillator

Leading-Edge/Trailing-Edge Modulation for

Reduced Output Ripple

novel

noise-attenuation

configuration,

PWM

comparator and latch, and a high-current output driver.

Additional PFC features include over-voltage

protection, zero-power detection to turn off the output

when VAOUT is below 0.33 V and peak current and

power limiting.

D

Low Start-up Supply Current

D

Synchronized Second Stage Start-Up, with

Programmable Soft-start

D

Programmable Second Stage Shutdown

The dc-to-dc section relies on an error signal generated

on the secondary-side and processes it by performing

peak current mode control. The dc-to-dc section also

features current limiting, a controlled soft-start, preset

operating range with selectable options, and 50%

maximum duty cycle.

DESCRIPTION

The UCC2850x family provides all of the control

functions necessary for an active power-factor-

corrected preregulator and a second-stage dc-to- dc

converter. The controller achieves near-unity power

factor by shaping the ac input line current waveform to

correspond to the ac input-line voltage using average

current-mode control. The dc-to-dc converter uses

peak current-mode control to perform the step-down

power conversion.

The UCC28500 and UCC28502 have a wide UVLO

threshold (16.5 V/10 V) for bootstrap bias supply

operation. The UCC28501 and UCC28503 are

designed with a narrow UVLO range (10.5 V/10 V) more

suitable for fixed bias operation. The UCC28500 and

UCC28501 have a narrow UVLO threshold for PWM

stage (to allow operation down to 75% of nominal bulk

voltage), while the UCC28502 and UCC38503 are

configured for a much wider operation range for the

PWM stage (down to 50% of bulk nominal voltage).

The PFC stage is leading-edge modulated while the

second stage is trailing-edge synchronized to allow for

minimum overlap between the boost and PWM

switches. This reduces ripple current in the bulk-output

capacitor.In order to operate with over three-to-one

Available in 20-pin N and DW packages.

range of input-line voltages, a line feedforward (V ) is

FF

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Copyright  2001, Texas Instruments Incorporated

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ꢠ ꢤ ꢡ ꢠꢊ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ

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1

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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢅꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢇꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢂꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢈ

ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢅꢆ ꢀ ꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢂꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

†}

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V

Gate Drive Current

Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 A

Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 A

Input Voltage

ISENSE1, ISENSE2, MOUT, VSENSE, OVP/ENBL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V

CAI, MOUT, CT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V

PKLMT, VERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V

Input Current

RSET, RT, IAC, PKLMT, ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA

VCC (no switching) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Maximum Negative Voltage GT1, GT2, PKLMT, MOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W

Storage temperature T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

Junction temperature T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C

J

Lead temperature (soldering, 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and

considerations of packages. All voltages are referenced to GND.

‡

AVAILABLE OPTIONS

PFC THRESHOLD

PACKAGED DEVICES

UVLO2

HYSTERESIS

(V)

T

J

UVLO TURN−ON

THRESHOLD (V)

PLASTIC DIP SMALL OUTLINE

(N)

(DW)

16

10.5

16

1.2

3.0

1.2

3.0

UCC28500N

UCC28501N

UCC28502N

UCC28503N

UCC38500N

UCC38501N

UCC38502N

UCC38503N

UCC28500DW

UCC28501DW

UCC28502DW

UCC28503DW

UCC38500DW

UCC38501DW

UCC38502DW

UCC38503DW

–40°C to 85°C

0°C to 70°C

10.5

16

10.5

16

10.5

The DW package is available taped and reeled. Add TR suffix to device type (e.g. UCC38500DWTR)

to order quantities of 2000 devices per reel.

N PACKAGE

DW PACKAGE

(TOP VIEW)

VAOUT

RT

1

2

3

4

5

6

7

8

9

10

20 VREF

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

VAOUT

RT

VSENSE

OVP/ENBL

CT

VREF

VFF

IAC

MOUT

ISENSE1

CAOUT

PKLMT

SS2

19

18

17

16

15

14

13

12

11

VFF

VSENSE

OVP/ENBL

CT

IAC

MOUT

ISENSE1

CAOUT

PKLMT

SS2

GND

VERR

ISENSE2

VCC

VERR

ISENSE2

VCC

GT1

PWRGND

GT1

GT2

PWRGND

2

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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

electrical characteristics T = 0°C to 70°C for the UCC3850X, –40°C to 85°C for the UCC2850X,

A

T = T , VCC = 12 V, RT = 22 kΩ, CT = 330 pF (unless otherwise noted)

A

J

supply current

PARAMETER

TEST CONDITIONS

VCC turn-on threshold –300 mV

VCC = 12 V (no load on GT1 or GT2)

MIN

TYP

150

MAX

300

UNITS

µA

Supply current, off

Supply current, on

4

6

mA

undervoltage lockout

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VCC turn-on threshold (UCCx8500/502)

UVLO hysteresis (UCCx8500/502)

Shunt voltage (UCCx8500/502)

VCC turn-on threshold (UCCx8501/503)

VCC turn-off threshold

15.4

16

6.3

16.6

V

5.8

15.4

9.7

I

= 10 mA

16.2

10.2

9.7

17.0

10.8

VCC

9.4

UVLO hysteresis (UCCx8501/503)

0.3

0.5

voltage amplifier

PARAMETER

TEST CONDITIONS

0°C ≤ T ≤ 70°C

MIN

TYP

MAX

UNITS

7.387

7.35

7.500

7.50

50

7.613

7.65

200

V

A

Input voltage

–40°C ≤ T ≤ 85°C

A

V

bias current

nA

dB

V

SENSE

Open loop gain

VAOUT = 2 V to 5 V

50

5.3

90

High-level output voltage

Low-level output voltage

I

= –150 µA

= 150 µA

5.5

5.6

LOAD

0.00

0.05

0.15

V

LOAD

PFC overvoltage protection and enable

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VREF

Over voltage reference

V

+ 0.480 + 0.500 + 0.520

Hysteresis

300

1.7

0.1

500

1.9

0.2

600

2.1

0.3

mV

V

Enable threshold

Enable hysteresis

V

current amplifier

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

mV

nA

Input offset voltage

V

= 0 V,

V

= 3 V

–6

0

−50

25

6

−100

100

CM

CAOUT

Input bias current

V

= 0 V,

= 3 V

CM

Input offset current

= 3 V

nA

CM

Open loop gain

= 2 V to 5 V

= 3 V

90

dB

CM

Common−mode rejection ratio

High-level output voltage

Low-level output voltage

Gain bandwidth product

= 0 V to 1.5 V, V

dB

CM

I

= –120 µA

5.6

0.1

7.0

0.2

2.5

7.5

0.5

V

LOAD

= 1 mA

V

LOAD

See Note 1

MHz

NOTES: 1. Ensured by design. Not production tested.

2. See Figure 6 for reference variation.

3. See Figure 5 for reference variation for VCC < 10.8 V.

3

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ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢅꢆ ꢀ ꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢂꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

electrical characteristics T = 0°C to 70°C for the UCC3850X, –40°C to 85°C for the UCC2850X,

A

T = T , VCC = 12 V, RT = 22 kΩ, CT = 330 pF (unless otherwise noted)

A

J

voltage reference

PARAMETER

TEST CONDITIONS

= 0°C to 70°C

MIN

7.387

7.35

0

TYP

7.500

7.50

MAX

7.613

7.65

10

UNITS

V

T

A

Input voltage

T

A

= –40°C to 85°C

V

Load regulation

Line regulation

I

= −1 mA to −2 mA,

See Note 2

See Note 3

mV

mA

REF

VCC = 10.8 V to 15 V,

VREF = 0V

0

10

Short circuit current

−20

–25

−50

oscillator

PARAMETER

TEST CONDITIONS

MIN

85

TYP

MAX

115

1%

UNITS

Frequency, initial accuracy

Frequency, voltage stability

Frequency, total variation

Ramp peak voltage

T

A

= 25°C

100

kHz

VCC = 10.8 V to 15 V

Line, Temp

−1%

80

120

5.5

kHz

V

4.5

3.5

5

4

Ramp amplitude voltage (peak to peak)

4.5

V

peak current limit

PARAMETER

TEST CONDITIONS

MIN

–15

150

TYP

0

MAX

15

UNITS

mV

PKLMT reference voltage

PKLMT propagation delay

300

500

ns

multiplier

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

I

= 500 µA, VFF = 4.7 V, VAOUT = 1.25 V,

AC

I

, high-line low-power output current

0

–6

−20

−23

MOUT

0°C ≤ T ≤ 85°C

A

I

= 500 µA, VFF = 4.7 V, VAOUT = 1.25 V,

AC

–40°C ≤ T ≤ 85°C

MOUT

A

µA

I

, high-line high-power output current

, low-line low-power output current

, low-line high-power output current

, IAC-limited output current

I

= 500 µA, VFF = 4.7 V, VAOUT = 5 V

= 150 µA, VFF = 1.4 V, VAOUT = 1.25 V

= 150 µA, VFF = 1.4 V, VAOUT = 5 V

= 150 µA, VFF = 1.3 V, VAOUT = 5 V

= 300 µA, VFF = 2.8 V, VAOUT = 2.5 V

= 150 µA, VFF = 1.4 V, VAOUT = 0.25 V

= 500 µA, VFF = 4.7 V, VAOUT = 0.25 V

= 500 µA, VFF = 4.7 V, VAOUT = 0.5 V,

−70

−10

–90

–19

–300

1

−105

−50

−345

−400

1.5

MOUT

AC

−268

−250

0.5

Gain constant (K)

1/V

µA

0

–2

0

–2

I

, zero current

0

–3

MOUT

0°C ≤ T ≤ 85°C

A

I

= 500 µA, VFF = 4.7 V, VAOUT = 0.5 V,

AC

−40°C ≤ T ≤ 85°C

0

–3.5

µA

A

Power limit (I

MOUT

× V )

FF

I

= 150 µA, VFF = 1.4 V, VAOUT = 5 V

−375

–420

−485

µW

AC

zero power

PARAMETER

Zero power comparator threshold

TEST CONDITIONS

MIN

0.175

TYP

0.330

MAX

0.500

UNITS

Measured on VAOUT

V

NOTES: 1. Ensured by design. Not production tested.

2. See Figure 6 for reference variation.

3. See Figure 5 for reference variation for VCC < 10.8 V .

4

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ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢂ ꢆ ꢀꢁ ꢁꢂ ꢃꢄ ꢅꢈ

ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃꢄ ꢅꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

electrical characteristics T = 0°C to 70°C for the UCC3850X, –40°C to 85°C for the UCC2850X,

A

T = T , VCC = 12 V, RT = 22 kΩ, CT = 330 pF (unless otherwise noted)

A

J

PFC gate driver

PARAMETER

TEST CONDITIONS

from −100 mA to –200 mA

= 100 mA

MIN

TYP

MAX

12

UNITS

GT1 pull up resistance

I

5

2

Ω

OUT

GT1 pull down resistance

10

OUT

C

= 1 nF,

R

= 10 Ω

LOAD

from 0.7 V to 9.0 V

LOAD

GT1 output rise time

GT1 output fall time

25

50

ns

V

GT1

C

= 1 nF,

LOAD

from 9.0 V to 0.7 V

R

LOAD

10

50

V

GT1

Maximum duty cycle

93%

95%

100%

2%

Minimum controlled duty cycle

f = 100 kHZ

second stage undervoltage lockout (UVLO2)

PARAMETER

TEST CONDITIONS

MIN

6.30

TYP

MAX

7.30

1.44

7.30

3.6

UNITS

PWM turn-on reference (UCCx8500/501)

Hysteresis (UCCx8500/501)

6.75

1.20

6.75

3

V

0.96

6.30

2.4

PWM turn−on reference (UCCx8502/503)

Hysteresis (UCCx8502/503)

second stage soft-start

PARAMETER

TEST CONDITIONS

MIN

TYP

–10

MAX

–12.5

300

UNITS

µA

SS2 charge current

–7.3

Input voltage (VERR)

SS2 discharge current

I

= 2 mA,UVLO = Low

mV

VERR

ENBL = High, UVLO = Low, SS2 = 2.5 V

3

10

mA

second stage duty cycle clamp

PARAMETER

TEST CONDITIONS

MIN

44%

TYP

MAX

UNITS

Maximum duty cycle

50%

second stage pulse-by-pulse current sense

PARAMETER

TEST CONDITIONS

MIN

0.94

TYP

1.05

MAX

UNITS

Current sense comparator threshold

VERR = 2.5 V measured on ISENSE2

1.15

V

second stage overcurrent limit

PARAMETER

TEST CONDITIONS

MIN

1.15

TYP

1.30

50

MAX

UNITS

V

Peak current comparator threshold

Input bias current

1.45

nA

second stage gate driver

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

12

UNITS

GT2 pull up resistance

GT2 pull down resistance

GT2 output rise time

I

from −100 mA to –200 mA

= 100 mA

5

3

Ω

OUT

10

OUT

C

V

= 1 nF,R

= 10 Ω

LOAD

25

50

ns

LOAD

from 0.7 V to 9.0 V

GT2

GT2 output fall time

C

= 1 nF,R

= 10 Ω

LOAD

25

50

ns

LOAD

from 9.0 V to 0.7 V

V

GT2

NOTES: 1. Ensured by design. Not production tested.

2. See Figure 6 for reference variation.

3. See Figure 5 for reference variation for VCC < 10.8 V .

5

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ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢅꢆ ꢀ ꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢂꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

pin assignments

CAOUT: (current amplifier output) This is the output of a wide bandwidth operational amplifier that senses line

current and commands the PFC pulse width modulator (PWM) to force the correct duty cycle. This output can

swing close to GND, allowing the PWM to force zero duty cycle when necessary.

CT: (oscillator timing capacitor) A capacitor from CT to GND sets the oscillator frequency according to:

0.725

f +

ǒ

_TǓ

R C

T

GND: (ground) All voltages measured with respect to ground. VCC and VREF should be bypassed directly to

GND with a 0.1-µF or larger ceramic capacitor. The timing capacitor discharge current also returns to this pin,

so the lead from the oscillator timing capacitor to GND should be as short and direct as possible.

GT1: (gate drive) The output drive for the PFC stage is a totem pole MOSFET gate driver on GT1. Use a series

gate resistor of at least 10.5 Ω to prevent interaction between the gate impedance and the GT1 output driver

that might cause the GT1 to overshoot excessively. Some overshoot of the GT1 output is always expected when

driving a capacitive load. Refer to Figure 4 for gate drive resistor selections.

GT2: (gate drive) Same as output GT1 for the second stage output drive. Limited to 50% maximum duty cycle.

IAC: (input ac current) This input to the analog multiplier is a current. The multiplier is tailored for very low

distortion from this current input (I ) to MOUT, so this is the only multiplier input which should be used for

AC

sensing instantaneous line voltage. Recommended maximum I

is 500 µA.

AC

ISENSE1: (current sense) This is the non-inverting input to the current amplifier. This input and the inverting

input MOUT remain functional down to and below GND.

ISENSE2: (current sense) A resistor from the source of the lower FET to ground generates the input signal for

the peak limit control of the second stage. The oscillator ramp can also be summed into this pin, for slope

compensation.

MOUT: (multiplier output and current sense amplifier inverting input) The output of the analog multiplier and the

inverting input of the current amplifier are connected together at MOUT. As the multiplier output is a current, this

is a high impedance input so the amplifier can be configured as a differential amplifier to reject ground noise.

Multiplier output current is given by:

ǒ_VVAOUT_* 1.0Ǔ_I

IAC

I

+

MOUT

_Kǒ_VVFFǓ²

Connect current loop compensation components between MOUT and CAOUT.

OVP/ENBL:(over-voltage/enable) A window comparator input which disables the PFC output driver if the boost

output is 6.67% above nominal or disables both the PFC and second stage output drivers and reset SS2 if pulled

below 1.9 V. This input is also used to determine the active range of the second stage PWM.

PKLMT: (PFC peak current limit) The threshold for peak limit is 0 V. Use a resistor divider from the negative side

of the current sense resistor to VREF to level-shift this signal to a voltage corresponding to the desired

overcurrent threshold across the current sense resistor.

PWRGND: Ground for totem pole output drivers.

RT: (oscillator charging current) A resistor from RT to GND is used to program oscillator charging current. A

resistor between 10 kΩ and 100 kΩ is recommended. Nominal voltage on this pin is 3 V.

6

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ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃꢄ ꢅꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

pin assignments (continued)

SS2: (soft-start for PWM) SS2 is at ground for either enable low or OVP/ENBL below the UVLO2 threshold

conditions. When enabled, SS2 charges an external capacitor with a current source. This voltage is used as

the voltage error signal during start-up, enabling the PWM duty cycle to increase slowly. In the event of a disable

command or a UVLO2 dropout, SS2 quickly discharges to disable the PWM.

VAOUT: (voltage amplifier output) This is the output of the operational amplifier that regulates output voltage.

The voltage amplifier output is internally limited to approximately 5.5 V to prevent overshoot.

VCC: (positive supply voltage) Connect to a stable source of at least 20 mA between 12 V and 17 V for normal

operation. Bypass VCC directly to GND to absorb supply current spikes required to charge external MOSFET

gate capacitances. To prevent inadequate gate drive signals, the output devices are inhibited unless VCC

exceeds the upper under-voltage lockout threshold and remains above the lower threshold.

VERR: (voltage amp error signal for the second stage) The error signal is generated by an external amplifier

which drives this pin. This pin has an internal 4.5-V voltage clamp that limits GT2 to less than 50% duty cycle

to ensure transformer reset in the typical application.

VFF: (RMS feed forward signal) VFF signal is generated at this pin by mirroring one-half of I into a single pole

AC

external filter. At low line, the VFF voltage should be 1.4 V.

VSENSE: (voltage amplifier inverting input) This is normally connected to a compensation network and to the

boost converter output through a divider network.

VREF: (voltage reference output) VREF is the output of an accurate 7.5-V voltage reference. This output is

capable of delivering 10 mA to peripheral circuitry and is internally short-circuit current limited. VREF is disabled

and remains at 0 V when VCC is below the UVLO threshold. Bypass VREF to GND with a 0.1-µF or larger

ceramic capacitor for best stability.

7

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ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢇ

ꢆ

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢅꢆ ꢀ ꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢂꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ

ꢅ

ꢂ

ꢆ

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

block diagram

ISENSE2

8

SS2

13

VCC

9

GND

6

VERR

7

7.5 V

REFERENCE

SECOND STAGE

SOFT START

20 VREF

6.75 V

UVLO2

UVLO

16 V/10 V

10.5 V/10 V

VCC

OVP/ENBL

4

+

1.9 V

ENABLE

I_LIMIT

+

10

GT2

R

4.5 V

1.3 V

+

1.5 V

Q

S

PWM

+

CLK2

PWM 2ND STAGE

SECTION

PWM 2ND STAGE

SECTION

PFC SECTION

8.0 V

PFCOVP

+

PFC SECTION

VCC

ZERO

POWER

VAOUT

1

3

VOLTAGE

ERROR AMP

0.33 V

Q

PWM

+

OSC

CLK1

CLK2

S

+

PWM

LATCH

CURRENT

AMP

12 GT1

VSENSE

X

÷

X

MULT

+

R

+

7.5 V

11 PWRGND

14 PKLMT

2

VFF 19

CLK1

(V_FF

)

CLK2

I_LIMIT

OSCILLATOR

MIRROR

2:1

+

IAC 18

17

16

15

2

5

UDG−98189

MOUT ISENSE1 CAOUT

RT

CT

8

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ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃꢄ ꢅꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

TYPICAL CHARACTERISTICS

MULTIPLIER OUTPUT CURRENT

MULTIPLIER GAIN

vs.

VOLTAGE ERROR AMPLIFIER OUTPUT

1.5

1.3

1.1

350

300

250

IAC = 150

A

µ

IAC = 150

A

µ

200

150

IAC = 300

A

µ

0.9

0.7

0.5

IAC = 300

A

µ

IAC = 500

A

µ

100

50

0

A

µ

IAC = 500

4

1

2

3

4

5

0

1

2

3

5

VAOUT − Voltage Error Amplifier Output − V

Figure 1

Figure 2

RECOMMENDED MINIMUM GATE RESISTANCE

vs.

MULTIPLIER CONSTANT POWER PERFORMANCE

500

SUPPLY VOLTAGE

17

16

15

14

13

12

11

10

9

400

VAOUT = 5 V

300

VAOUT = 4 V

200

VAOUT = 3 V

100

VAOUT = 2 V

8

0

1

2

3

4

5

10

12

14

16

18

20

VCC − Supply Voltage − V

VFF − Feedforward Voltage − V

Figure 3

Figure 4

9

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ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢅꢆ ꢀ ꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢂꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

REFERENCE VOLTAGE

vs.

REFERENCE CURRENT

REFERENCE VOLTAGE

vs.

SUPPLY VOLTAGE

7.60

7.55

7.50

7.45

7.40

7.510

7.505

7.500

7.495

7.490

0

5

I

10

15

20

25

9

10

11

12

13

14

− Reference Current − mA

VCC − Supply Voltage − V

VREF

Figure 5

Figure 6

10

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ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃꢄ ꢅꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

TYPICAL APPLICATION

The UCC38500 series is designed to incorporate all the control functions required for a power factor correction

circuit and a second stage dc-to-dc converter. The PFC function is implemented as a full-feature,

average-current-mode controller integrated circuit. In addition, the input voltage feedforward function is

implemented in a simplified manner. Current from IAC input is mirrored over to the VFF pin. By simply adding

a resistor and capacitor (to attenuate 120-Hz ripple) a voltage is developed which is proportional to RMS line

voltage, eliminating the need for several components normally connected to the line.

The UCC3850x uses leading-edge modulation for the PFC stage and trailing-edge modulation for the dc-to-dc

stage. This reduces ripple current in the output capacitor by reducing the overlap in conduction time of the PFC

and dc-to-dc switches. Figures 7 and 8 depict the ripple current reduction in the boost switch. In addition to the

reduced ripple current, noise immunity is improved through the current error amplifier implementation. Please

refer to the UCC3817 datasheet (TI Literature No. SLUS395) for a detailed explanation of current error amplifier

implementation.

UDG−97130−1

Figure 7. Simplified Representation of a 2−Stage PFC Power Supply

i

CBST

i

= i − i

CBST D1 Q2

Figure 8. Timing Waveforms for Synchronization Scheme

11

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ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢅꢆ ꢀ ꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢂꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

TYPICAL APPLICATION

The UCC3850x is optimized to control a boost PFC stage operating in continuous conduction mode, followed

by a dc-to-dc converter (typically a forward topology). The dc-to-dc converter is transformer isolated and

therefore its error amplifier is located on the secondary side. For this reason the UCC3850x is configured without

an internal error amplifier for the second power stage. The externally generated error signal is fed into the VERR

pin typically through an opto coupler.

The UCC3850x can be configured for voltage-mode control or current-mode control of the second stage. The

application figure shows a typical current-mode configuration. For voltage-mode control, the ramp generated

by CT can be fed back into the ISENSE2 pin through a voltage divider.

One of the main system challenges in designing systems with a PFC front end is coordinating the turn-on and

turn-off on the dc-to-dc converter. If the dc-to-dc converter is allowed to turn on before the boost converter is

operational, it must operate at a much-reduced voltage and therefore represents a large current draw to the

boost converter. This start-up sequencing is handled internally by the UCC3850x. The UCC3850x monitors the

output voltage of the PFC converter and holds the dc-to-dc converter off until the output is within 10% of its

regulation point. Once the trip point is reached the dc-to-dc section goes through a soft start sequence for a

controlled, low stress start-up. Similarly, if the output voltage drops too low (two voltage options are available)

the dc-to-dc converter shuts down thereby preventing overstress of the converter. For the UCC38500 and

UCC38501, the dc-to-dc converter shuts down when the PFC output falls below 74% of its nominal value, while

for the UCC38502 and UCC38503, the threshold is lowered to 50%.

design example: an off-line, 100-W, power converter

The following design example shows how to implement the UCC38500 in an off-line 100-W power converter.

The system requires the converter to operate from a universal input of 85 V

to 265 V

with a 12-V, 100-W,

RMS

dc output. This design example is divided into two parts. The first part is the PFC stage design and the second

section is the dc-to-dc power stage design. The design goal of the system is to achieve an efficiency of

approximately 80%. This is accomplished by requiring the boost regulator to be designed for an efficiency of

95% and the dc-to-dc power stage to be designed for 85% efficiency. The efficiency of the boost converter is

designated by variable η1 and the efficiency of the dc-to-dc converter is designated by variable η2. Figure 9

shows the schematic of the typical application upon which this design example is based. The UCC38500 control

device is chosen for this design because of it’s self-biasing scheme and minimum input voltage requirements

of the dc-to-dc power stage.

12

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ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃꢄ ꢅꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

UDG−99138

Figure 9. Typical Application Circuit

13

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ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢅꢆ ꢀ ꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢂꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

TYPICAL APPLICATION

I. PFC Boost Power Stage

LBOOST (L1 in Figure 9)

The boost inductor value is determined by the following equations:

Ǹ

ǒ

Ǔ

P

0.25 2

OUT

h1 h2

DI +

,

V

IN (min)

(1)

(2)

(3)

Ǹ

V

2

IN (min)

D + 1 *

,

V

BOOST

Ǹ

V

2 D

IN (min)

L

+

BOOST

D I f

S

where ∆I, the inductor current ripple was set to approximately 25% of the peak inductor current.

In this design example ∆I is approximately 505 mA. Drepresents the duty cycle at the peak of low line voltage,

V

is the minimum RMS input voltage, and V

for this design is selected to be 385 V to ensure the PFC stage regulates for the full input voltage range.

is the controlled output voltage of the PFC stage.

IN(min)

BOOST

Variable f represent the switching frequency. The switching frequency was selected to be 100 kHz for this

design. The calculated boost inductor required for this design is approximately 1.7 mH.

S

CBOOST (C2 in Figure 9)

Two main criteria, the capacitance and the voltage rating, dictate the selection of the output capacitor. The value

of capacitance is determined by the holdup time required for supporting the load after the input ac voltage is

removed. Holdup is the amount of time that the output stays in regulation after the input has been removed. For

this circuit, the desired holdup time is approximately 16 ms. Expressing the capacitor value in terms of output

power, output voltage, and holdup time is described in equation (4):

2 P

D t

OUT

⁺ǒ_V_BOOSTǓ

C

BOOST

2

ǒ

_{BOOST (min)}Ǔ

* V

(4)

In practice, the calculated minimum capacitor value may be inadequate because output ripple voltage

specifications limit the amount of allowable output capacitor ESR. Attaining a sufficiently low value of ESR often

necessitates the use of a much larger capacitor value than calculated. The amount of output capacitor ESR

allowed is determined by dividing the maximum specified output ripple voltage by the capacitor ripple current.

In this design, holdup time is the dominant determining factor and a 100 µF, 450 V aluminum electrolytic

capacitor from Panasonic, part number ECOS2TB101BA, is used. The voltage rating and the low ESR of

0.663 Ω make it an ideal choice for this design.

14

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ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃꢄ ꢅꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

TYPICAL APPLICATION

power switch selection (Q3 in Figure 9)

As in any power supply design, tradeoffs between performance, cost and size are necessary. When selecting

a power switch, it is useful to calculate the total power dissipation in the switch for several different devices at

the switching frequencies being considered for the converter. Total power dissipation in the switch is the sum

of switching loss and conduction loss. Switching losses are the combination of the gate charge loss, drain

source capacitance of the MOSFET loss and turnon and turnoff losses:

P

+ Q

V

f

GATE

COSS

SW

GATE

S

(5)

_OSSǒ_V_OFFǓ²

C

1

2

+

f

S

(6)

(7)

1

2

_Iǒ_t

Ǔ

f

+

V

) t

OFF

L

ON

OFF

S

Where Q

is the total gate charge, V

is the gate drive voltage, f is the switching frequency, C

OSS

is

GATE

s

the drain source capacitance of the MOSFET, t

parameters R

and t

are the switching times (estimated using device

ON

OFF

, Q

and V ) and V

is the voltage across the switch during the off time, in this case V

GATE GD

TH

OFF OFF

= V

.

BOOST

Conduction loss is calculated as the product of the R

and the square of RMS current:

of the switch (at the worst case junction temperature)

(8)

DS(on)

_Kǒ_I_RMSǓ²

P

+ R

DS(on)

COND

where K is the temperature factor found in the manufacturer’s R

vs junction temperature curves.

DS(on)

Calculating these losses and plotting against frequency gives a curve that enables the designer to determine

either which manufacturer’s device has the best performance at the desired switching frequency, or which

switching frequency has the least total loss for a particular power switch. For this design example an IRFP450

HEXFET from International Rectifier is chosen because of its low R

and its V

rating. The IRFP450’s

DS(on)

DSS

R

of 400 mΩ and the maximum V

of 500 V makes it an ideal choice. A comprehensive review of this

DS(on)

DSS

procedure can be found in the Unitrode Power Supply Design Seminar SEM−1200, Topic 6, TI Literature No.

SLUP117.

More recently, faster switching insulated gate bipolar transistors (IGBTs) have become widely available.

Depending on the system power level (and the switching frequency), use of IGBTs may make sense for the

power switch.

boost diode selection (D3 in Figure 9)

In order to keep the switching losses to a minimum and meet the voltage and current requirements, a

HFA08TB60 fast recovery diode from International Rectifier is selected for the design. This diode is rated for

a maximum reverse voltage of 600 V and a maximum forward current of 8 A. The typical reverse recovery of

18 ns made this diode ideal for this design.

15

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ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢅꢆ ꢀ ꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢂꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

TYPICAL APPLICATION

peak current limit

Resistor divider R14 and R29 along with current sense resistor R5, devise the peak-limit comparator of the

UCC38500 and are used to protect the boost switch Q3 from excessive currents. Proper preparation of this

comparator requires that it not interfere with the boost converter’s power limit or the forward converter’s

pulse-by-pulse current limiting. For this design example the forward converter is selected to go into

pulse-by-pulse current limiting at approximately 130% of maximum output power. The power limit of the boost

converter is set at 140% of the maximum output power. The peak current limit for the boost stage was selected

to engage at 150% of the maximum output power to ensure circuit stability.

The following equation is used to select the current-sense resistor R5, where the current-sense resistor is

selected to operate over a 1-V dynamic range (V

). The current-sense resistor required for the design

DYNAMIC

needed to be approximately 0.43 Ω.

V

DYNAMIC

R5 + R

+

^ 0.43 W

SENSE

( )

) 0.5 DI

I

(9)

PK

The following equation is used to size resistor R14 properly by first selecting R29 to be a standard resistance

value. For this design resistor R29 was selected to be 10 kΩ. With a typical reference voltage (V

gives a calculated value of approximately 1.91 kΩ for resistor R14.

) of 7.5 V

REF

Ǹ

P

1.5 2

OUT

ǒ

) DI

Ǔ

R5 R29

V

h1 h2

IN (min)

R14 +

multiplier

V

REF

(10)

The output of the multiplier of the UCC38500 is a signal representing the desired input line current. It is an input

to the current amplifier, which programs the current loop to control the input current to give high power-factor

operation. As such, the proper functioning of the multiplier is key to the success of the design. The inputs to the

multiplier are V

and an input voltage feed forward signal, V

, the voltage amplifier output, I , a representation of the input rectified ac line voltage,

VAOUT

IAC

. The output of the multiplier, I

, can be expressed:

MOUT

VFF

ǒ_V

_Kǒ_V_VFFǓ²

_* 1Ǔ

VAOUT

I

IAC

I

+

MOUT

(11)

Where K is a constant typically equal to 1 / V.

The I signal is obtained through a high-value resistor connected between the rectified ac line and the IAC

IAC

pin of the UCC3850X. This resistor (R

) is sized to provide the maximum I

current at high line. For the

IAC

UCC3850X the maximum I

current is about 500 µA, and a higher current can drive the multiplier out of its

IAC

linear range. A smaller current level is functional, but noise can become an issue, especially at low input line.

Assuming a universal line operation of 85 V to 265 V gives a R value of 750 kΩ. Because of voltage

RMS

IAC

rating constraints of the standard 1/4-W resistor, this application requires a combination of lower value resistors

connected in series to give the required resistance and distribute the high voltage amongst the resistors. For

this design example two 383 kΩ resistors are used in series.

16

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ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃꢄ ꢅꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

TYPICAL APPLICATION

The current into the IAC pin is mirrored internally to the VFF pin where it is filtered to produce a voltage feed

forward signal proportional to line voltage. The VFF voltage is used to keep the power stage gain constant and

to providing input power limiting. Please refer to Texas instruments Application Note on Power Limiting with

Sinusoidal Input TI Literature No. SLUA196, for detailed explanation on how the VFF pin provides power

limiting. The following equation is used to determine the VFF resistor size (R

) to provide power limiting where

VFF

V

is the minimum RMS input voltage and R

is the total resistance connected between the IAC pin and

IN(min)

IAC

the rectified line voltage.

1.4 V

R

+

^ 28.7 kW

VFF

V

0.9

IN (min)

ǒ Ǔ

2 R

IAC

(12)

Because the VFF voltage is generated from line voltage it needs to be adequately filtered to reduce total

harmonic distortion caused by the 120-Hz rectified line voltage. Refer to Unitrode Power Supply Design

Seminar, SEM−700 Topic 7, Optimizing a High Power Factor Switching Preregulator, TI Literature No.

SLUP093. A single pole filter is adequate for this design. Assuming that an allocation of 1.5% total harmonic

distortion from this input is allowed, and that the second harmonic ripple is 66% of the input ac line voltage, the

amount of attenuation required by this filter is:

1.5%

66%

+ 0.022

(13)

With a ripple frequency (f ) of 120-Hz and an attenuation of 0.022 requires that the pole of the filter (f ) be placed

R

P

at:

f + 120 Hz 0.022 ^ 2.6 Hz

(14)

P

The following equation is used to select the filter capacitor (C

1

) required to produce the desired low pass filter.

VFF

C

+

^ 2.2 mF

VFF

2p R

f

VFF

P

(15)

This results in a single-pole filter, which adequately attenuates the harmonic distortion and provides power

limiting.

The R

resistor is sized to provide power limiting for the circuit. The power limit is set to 140% of the

MOUT

maximum output power. This is done so that the power limit of the PFC stage does not interfere with power

limiting of the dc-to-dc converter, which is set to 130% of the maximum output power. The following equations

are used to size the R

resistor, R19. In these equations P

is the maximum multiplier output current, I @V

is the power limit level, P

is the maximum

MOUT

LIMIT

OUT

output power. I

is the minimum current into

MOUT(max)

IAC

IN(min)

the IAC pin at low line and V

is the maximum voltage amplifier output voltage. For this design R19

VAOUT(max)

and R15 need to be approximately 3.57 kΩ.

P

1.4

OUT

P

+

LIMIT

h1 h2

(16)

(17)

ǒ_V

_{* 1 V}Ǔ

I

@ V

IAC

IN(min)

VAOUT(max)

I

+

MOUT(max)

_Kǒ_V_FFǓ²

17

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ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢅꢆ ꢀ ꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢂꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

TYPICAL APPLICATION

Ǹ

P

2 R

LIMIT

SENSE

V

IN (min)

R

+

MOUT

I

MOUT(max)

(18)

current loop

The UCC38500 current amplifier has the input from the multiplier applied to the inverting input. This change in

architecture from previous Texas Instruments PFC controllers improves noise immunity in the current amplifier.

It also adds a phase inversion into the control loop. The UCC38500 takes advantage of this phase inversion

to implement leading-edge duty cycle modulation. Please refer to Figure 10 for the typical configuration of the

current amplifier.

The following equation defines the gain of the power stage, where V is the voltage swing of the oscillator ramp,

P

4 V for the UCC38500.

V

R

BOOST

SENSE

G (s) +

ID

s L

V

BOOST

P

(19)

In order to have a good dynamic response the crossover frequency of the current loop was set to 10% of the

switching frequency. This can be achieved by setting the gain of the current amplifier (G ) to the inverse of

CA

the current loop power stage gain at the crossover frequency. This design requires that the current amplifier

have a gain of 2.581 at 10 kHz.

1

G

+

+ 2.581

CA

G (s)

ID

(20)

R is the R

resistor, previously calculated to be 3.57 kΩ (refer to Figure 10). The gain of the current amplifier

I

MOUT

is R /R , so multiplying R by G gives the value of R , in this case approximately 9.09 kΩ. Setting a zero at

F

I

EA

F

the crossover frequency and a pole at half the switching frequency to roll off the high-frequency gain completes

the current loop compensation.

1

C +

Z

2p R f

F

C

(21)

(22)

1

C +

P

f

s

ǒ Ǔ

2p R

F

2

18

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ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃꢄ ꢅꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

TYPICAL APPLICATION

C

P

C

R

Z

f

R

I

−

+

CAOUT

Figure 10. Current Loop Compensation

voltage loop

The second major source of harmonic distortion is the ripple on the output capacitor at the second harmonic

of the line frequency. This ripple is fed back through the error amplifier and appears as a 3rd harmonic ripple

at the input to the multiplier. The voltage loop must be compensated not just for stability but also to attenuate

the contribution of this ripple to the total harmonic distortion of the system (refer to Figure 11).

C

f

V

OUT

C

R

Z

f

R

IN

−

+

R

D

V

REF

Figure 11. Voltage Amplifier Configuration

The gain of the voltage amplifier, G , can be determined by first calculating the amount of peak ripple present

VA

on the output capacitor V

The peak value of the second harmonic voltage is given by equation (23), where

OPK.

f

is the frequency of the rectified line voltage. For this design f is equal to 120 Hz.

R

P

IN

⁺ǒ_{2 p f C}

_BOOSTǓ

V

OPK

V

R

BOOST

(23)

19

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ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢅꢆ ꢀ ꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢂꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

TYPICAL APPLICATION

In this example V

is equal to 4 V. Assuming an allowable contribution of 0.75% (1.5% peak-to-peak) from

OPK

the voltage loop to the total harmonic distortion budget sets the gain equal to:

ǒ_DV

Ǔ ₍

0.015

)

VAOUT

G

+

VA

2 V

OPK

(24)

Where ∆V

is the effective output voltage range of the error amplifier (5 V for the UCC38500). The network

VAOUT

needed to realize this filter is comprised of an input resistor, R , and feedback components C , C , and R . The

IN

F

Z

F

value of R is already determined because of its function as one-half of a resistor divider from V

feeding

IN

OUT

back to the voltage amplifier for output voltage regulation. In this case the value is 1.12 MΩ. This high value was

chosen to reduce power dissipation in the resistor. In practice, the resistor value would be realized by the use

of two 560-kΩ resistors in series because of the voltage rating constraints of most standard 1/4 W resistors. The

value of C is determined by the equation:

F

1

C

F

⁺ǒ_{2 p f}

_INǓ

G

R

VA

(25)

In this example C equals 150 nF. Resistor R and C generate a pole in the voltage amplifier feedback to reduce

F

total harmonic distortion (THD). The location of the pole is found by setting the gain of the loop equation to one

and solving for the crossover frequency. The frequency, expressed in terms of input power, is calculated by the

equation:

Ǹ_P

IN

f

+

VI

_2pǸ_DV

V

R C

C

BOOST

F

VAOUT

OUT

IN

(26)

f

for this converter is 10 Hz. A derivation of this equation can be found in the Unitrode Power Supply Design

VI

Seminar SEM−1000, Topic 1, Power Factor Correction Circuit, TI Literature No. SLUP106.

Solving for R becomes:

F

1

R

⁺ǒ_{2 p f}

_FǓ

F

C

VI

(27)

Or R equals approximately 118 kΩ.

F

Due to the low output impedance of the voltage amplifier, capacitor C is added to improve dc regulation. To

Z

maintain good phase margin, the zero from C is set to 10% of f . For this design, C is a 2.2-µF capacitor. The

Z

VI

Z

following equation is used to calculate C^Z.

1

C +

Z

f

VI

2p ǒ Ǔ R

F

10

(28)

20

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ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃꢄ ꢅꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

TYPICAL APPLICATION

II. Two Switch Forward DC−to−DC Power Stage

A two-switch forward converter topology was selected for the second stage of this design. The two-switch

forward power converter has two major advantages over a traditional forward converter, making it ideal for this

application. First, the FETs used in the two-switch forward required only one-half the maximum V

as

DS

compared to the traditional forward converter. Second, the transformer’s reset energy is returned to the input

through clamping diodes for higher efficiency.

transformer turns ratio

Equation (29) calculates the transformer turns ratio required for the two-switch forward power converter of this

design example. It can be derived from the dc transfer function of a forward converter. V

is the output voltage

OUT

of the forward converter and is 12-V for this design. V is the forward voltage drop of the secondary rectifier diode

F

and is set to 1V. V

is the minimum input voltage to the forward converter. The level of this voltage is

BOOST(min)

determined by where the control device forces the dc-to-dc converter into undervoltage lockout (UVLO). The

UCC38500 control device is configured to drive the dc-to-dc power stage into UVLO at approximately 74% of

the nominal boost converters output voltage. V

for this design is approximately 285 V. D

is 0.44

BOOST(min)

MAX

and is the guaranteed maximum duty cycle of the forward converter. For this design example the calculated

turns ratio is approximately 0.101.

V

) V

N

OUT

BOOST(min)

F

S

P

Transformer Turns +

+

V

D

MAX

(29)

output inductor

The following equations can be used to calculate the inductor required for this design example. First, the

minimum duty cycle D , which occurs at the maximum boost voltage, needs to be calculated. The maximum

MIN

boost voltage is limited by the OVP trip point, which is set to approximately 425 V. For this design D

is

MIN

approximately 31%. The output inductor ripple current (∆I ) for this design is given at 30% of the maximum load

L

current. Next calculate the output inductor (L), where the switching frequency (f ) is 100 kHz. The calculated

S

output inductor for this design is approximately 38 µH.

V

) V

F

N

OUT

P

S

D

+

MIN

V

BOOST(max)

(30)

(31)

P

0.3

OUT

V

DI +

L

OUT

ǒ_V

Ǔ ǒ

_MINǓ

) V 1 * D

OUT

F

L +

DI f

L

S

(32)

21

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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢅꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢇꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢂꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢈ

ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢅꢆ ꢀ ꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢂꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

TYPICAL APPLICATION

output capacitor

The following equations can be used to estimate the minimum output capacitance and the capacitor’s maximum

allowable equivalent series resistance (ESR), where C is the minimum output capacitance and t is the

OUT

S

period of the switching frequency. ∆V

is the maximum allowable output ripple voltage, selected as

OUT

approximately 1% of the output voltage. For this design, the minimum calculated output capacitance is 170 µF

and the maximum allowable ESR is 96 mΩ. A Panasonic HFQ 1800-µF electrolytic capacitor with an ESR of

0.048 Ω is used.

ǒ_V

Ǔ

ǒ Ǔ²

t

S

ǒ_D

Ǔ

) V

OUT

F

MAX

1

8

C

+

OUT

L DV

OUT

(33)

(34)

DV

OUT

ESR +

DI

L

R

SENSE2

The dc-to-dc power converter is designed for peak current mode control. R

is the resistor that senses

SENSE2

the current in the forward converter. The sense resistor in Figure 9 is referred to as R4. The following equations

can be used to calculate R . Where I is the magnetizing current of the transformer used in the step-down

SENSE2

M

converter and V

is the output voltage of the boost stage. D is the typical duty ratio of the forward converter.

BOOST

V

is the peak current sense comparator voltage that is typically 1.15 V. For this design example L

ISENSE2_peak

M

is approximately 8 mH and the R

is approximately 1 Ω.

SENSE2

V

BOOST

D

I

+

M

L

f

M

S

(35)

V

ISENSE2_peak

R

+

SENSE2

N

DI

S

P

L

ǒ

_1.3Ǔ

I

)

) I

OUT(max)

M

2

N

(36)

soft-start

The UCC38500 has soft-start circuitry to allow for a controlled ramp of the second stage’s duty cycle during

start-up. This is accomplished through the SS2 circuitry described earlier in this data sheet. Equation (37)

calculates the approximate capacitance needed based on the designer’s soft-start requirements. Where I

SS2

is the soft-start charging current, which is typically 10 µA. ∆t is the desired soft start time, which was selected

to be approximately 5 ms for this example. The calculated soft-start capacitor (C ) for this example is

SS

approximately 10 nF.

I

D t

ISS2

C

+

SS

4.5

slope compensation

(37)

When designing with peak current-mode control, slope compensation may be necessary to prevent instability.

In this design, the magnetizing current provided more than enough slope compensation. If slope compensation

is needed with external components, please refer to Unitrode/Texas Instruments Application Note, Practical

Considerations in Current Mode Power Supplies, TI Literature No. SLUA110.

22

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ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃꢄ ꢅꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

TYPICAL APPLICATION

control loop

Figure 12 shows the control block diagram for the typical application shown in Figure 9. G (s) is the

C

compensation network’s transfer function (TF), G

(s) is the opto-isolator TF, G (s) is the control-to-output

OPTO

CO

TF, and H(s) is the divider TF. The following equations can be used to estimate the frequency response of each

gain block, where f is the frequency, where the optoisolator is −3 dB from its dc operating point, and

OPTO_pole

V

is the reference voltage of the TL431 shunt regulator. R

represents the typical load impedance

REF_TL431

LOAD

for the design.

R13

R36

1

G

(s) +

OPTO

s

1 )

2p f

OPTO_pole

(38)

s R35 C14 ) 1

s C14 R31 1 ) s R35 C15

R13

R36

1

s

G (s) +

C

(

))

1 )

2p f

OPTO_pole

(39)

(40)

V

VREF_TL431

R27

R27 ) R31

H(s) +

+

V

OUT

_{1 )}ǒ_{s C}

Ǔ

ǒ

_ESRǓ

V

R

LOAD

N

OUT

P

G

(s) +

+

CO

V

R

N

s

_{1 )}ǒ_{s C}

Ǔ

ǒ

_LOADǓ

C

SENSE2

R

OUT

(41)

V

BOOST

V

C

V

OUT

V

REF_TL431

G (s)

C

G

(s)

CO

Σ

H(s)

Figure 12. UCC38500 Control Block

23

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ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢅꢆ ꢀ ꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢂꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

TYPICAL APPLICATION

Figure 13 shows the circuitry for the voltage feedback loop. D13 is a TL431 shunt regulator that functions as

an operational amplifier, providing feedback control.

V

BOOST

V

V = V

OUT

C

ERR

G

(s)

CO

G

CO(s)

Q5

V

REF

R36

R16

H11AV1

D14

6

5

R13

1

PGND2

R31

2

3

C14

R35

4

C15

U3

D13

SGND

R27

UDG−01091

Figure 13. UCC38500 Feedback Loop

Initially the designer must select the resistor values for the divider gain H(s). Equation (42) is used to determine

resistor size. Selecting R27 to be a standard value of 10-kΩ requires R31 to be approximately 38.3 kΩ.

_R27ǒ_V

_REFǓ

* V

OUT

R31 +

V

REF

(42)

It is important to correctly bias the TL431 and the optoisolator for proper operation. Zener diode D14 and a

depletion mode J-FET, Q5, supply the bias voltage for the TL431. Resistors R16 and R13 provide the minimum

bias currents for the TL431 and the optoisolator respectively and can be calculated with the following equations.

Where I

is the minimum optoisolation current, and V

is the maximum voltage seen at the VERR

OP(min)

VERR(max)

pin of the UCC38500. VERR has an internal clamp that limits this pin to 4.5 V. V is the typical forward voltage

of the diode in the opto isolator, and I

F

is the minimum cathode current of the TL431. For the

TL431(min)

components used in this design example R13 is calculated to be approximately 2.0 kΩ and R16 was calculated

to be approximately 680 Ω. The optoisolator is configured to have dc gain of approximately 20 dB and the

optoisolator −3 dB point is approximately 8 kHz. Figure 14 shows the frequency response of the optoisolator.

24

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ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃꢄ ꢅꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

TYPICAL APPLICATION

V

F

R16 +

R13 +

I

TL431 (min)

(43)

(44)

V

* V

REF

VERR (max)

I

OP (min)

To compensate the loop, it is necessary to estimate or measure the control-to-output gain’s frequency response

(s). The frequency response for G (s) was measured with a network analyzer and the measured

G

CO

frequency response is shown in Figure 15.

POWER STAGE CONTROL-TO-OUTPUT TRANSFER

OPTOISOLATOR TRANSFER FUNCTION

FUNCTION (GAIN AND PHASE)

(GAIN AND PHASE)

vs.

FREQUENCY

50

40

180

144

108

72

60

180

40

20

0

120

60

GAIN

30

20

GAIN

10

36

0

−10

−20

−36

−72

−60

−20

−120

PHASE

−30

−40

−50

−108

−144

−180

−40

−60

PHASE

−180

100

1 k

10 k

100 k

100

1 k

10 k

100 k

f − Frequency − Hz

Figure 14

Figure 15

After determining the frequency response of G (s) it is necessary to define some closed loop frequency

CO

response design goals. The following equation describes the frequency response of the loop gain (T(s) ) of

dB

the system in decibels. Typically, the loop is designed to crossover at a frequency below one-sixth of the

switching frequency. In order for this design example to have good transient response, the design goal is to have

the loop gain crossover at approximately 1 kHz, which is less than one-sixth of the switching frequency. The

gain crossover frequency for this design example is referenced as f .

C

T(s) dB + G (s) ) G (s) ) H(s)

C

CO

(45)

The compensation network that is used (G (s)) has three poles and one zero. One pole occurs at the origin,

C

and a second pole is caused by the limitations of the opto-isolator. The third pole is set to attenuate the

high-frequency gain and needs to be set to one-half of the switching frequency. The zero is set at the desired

crossover frequency.

The following equations can be used to select R35, C14 and C15, where G (s), G

(s), and H(s) are the

CO

OPTO

gains in decibels (dB) of each control block at the desired f . From the graphs in Figures 14 and 15 it can be

C

observed at the desired crossover frequency G (s) is approximately 0 dB and G

(s) is approximately

CO

OPTO

25

www.ti.com

ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢅꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢇꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢂꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢈ

ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢅꢆ ꢀ ꢁꢁ ꢈ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢂꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢈ

SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001

23 dB. Therefore the compensation circuitry needs to have a gain of −23 dB at the desired crossover frequency.

For this example R35 is calculated at approximately 18.2 kΩ. Capacitor C14 is estimated to be approximately

10 nF and C15 is calculated at approximately 180 pF.

V

REF

_{H(s) + 20log}ƪ ƫ

V

OUT

(46)

ǒ

Ǔ

*G_CO(s) dB)G_OPTO(s) dB)H(s) dB

R35 + R31 10

(47)

1

C14 +

ǒ

_CǓ

2p R35 f

(48)

1

C15 +

f

SW

2

ǒ

Ǔ

2p R35

(49)

Figure 16 shows the frequency response of the compensation network G (s) and Figure 17 shows the

C

measured frequency response of the loop gain T(s). The frequency response characteristics in Figure 17 show

that f is approximately 1.5 kHz with a phase margin of about 55 degrees. The gain margin is approximately

C

50 dB.

FEEDBACK CONTROL TRANSFER FUNCTION

TOTAL LOOP TRANSFER FUNCTION

(GAIN AND PHASE)

vs.

(GAIN AND PHASE)

vs.

FREQUENCY

60

180

60

180

COMPENSATION

PHASE

40

20

0

120

60

40

20

0

LOOP PHASE

120

60

0

COMPENSATION

GAIN

−60

−20

−60

LOOP GAIN

−120

−40

−60

−120

−40

−60

−180

100 k

100

1 k

10 k

100 k

100

1 k

10 k

f − Frequency − Hz

Figure 16

Figure 17

26

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

18-Feb-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

SOIC

PDIP

SOIC

PDIP

SOIC

PDIP

SOIC

PDIP

SOIC

PDIP

SOIC

PDIP

SOIC

PDIP

SOIC

PDIP

Drawing

DW

N

UCC28500DW

UCC28500DWTR

UCC28500N

ACTIVE

20

25

2000

20

None

CU SNPB

Level-2-220C-1 YEAR

Level-NA-NA-NA

UCC28501DW

UCC28501DWTR

UCC28501N

DW

N

25

Level-2-220C-1 YEAR

Level-NA-NA-NA

2000

20

UCC28502DW

UCC28502DWTR

UCC28502N

DW

N

25

Level-2-220C-1 YEAR

Level-NA-NA-NA

2000

20

UCC28503DW

UCC28503DWTR

UCC28503N

DW

N

25

Level-2-220C-1 YEAR

Level-NA-NA-NA

2000

20

UCC38500DW

UCC38500DWTR

UCC38500N

DW

N

25

Level-2-220C-1 YEAR

Level-NA-NA-NA

2000

20

UCC38501DW

UCC38501DWTR

UCC38501N

DW

N

25

Level-2-220C-1 YEAR

Level-NA-NA-NA

2000

20

UCC38502DW

UCC38502DWTR

UCC38502N

DW

N

25

Level-2-220C-1 YEAR

Level-NA-NA-NA

2000

20

UCC38503DW

UCC38503DWTR

UCC38503N

DW

N

25

Level-2-220C-1 YEAR

Level-NA-NA-NA

2000

20

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

18-Feb-2005

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for

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Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

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Amplifiers

amplifier.ti.com

www.ti.com/audio

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www.ti.com/digitalcontrol

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Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

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Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

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Post Office Box 655303 Dallas, Texas 75265


型号：	UCC28501N
厂家：	TEXAS INSTRUMENTS
描述：	BICMOS PFC/PWM COMBINATION CONTROLLER 的BiCMOS PFC / PWM组合控制器稳压器开关式稳压器或控制器电源电路开关式控制器功率因数校正光电二极管信息通信管理
文件：	总31页 (文件大小：561K)
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