UCC28722DBVT [TI]
具有初级侧调节功能、适用于双极性功率器件的低成本 CVCC 反激式控制器 | DBV | 6 | -40 to 125;
| 型号： | UCC28722DBVT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有初级侧调节功能、适用于双极性功率器件的低成本 CVCC 反激式控制器 | DBV | 6 | -40 to 125 控制器 光电二极管 |
| 文件： | 总35页 (文件大小：1945K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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UCC28722
ZHCSEK1B –DECEMBER 2013–REVISED OCTOBER 2015
UCC28722 具有一次侧稳压和 BJT 驱动功能的
恒压、恒流控制器
1 特性
3 说明
1
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•
•
•
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•
•
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低于 50mW 的无负载功耗
UCC28722 反激电源控制器无需使用光耦合器即可提
供单独输出的恒定电压 (CV) 和恒定电流 (CC) 输出稳
压。此器件处理来自一次侧电源开关和辅助反激式绕组
的信息，以对输出电压和电流进行精确控制。
一次侧稳压 (PSR) 免除了对光耦合器的需要
动态双极性结型晶体管 (BJT) 驱动
线路和负载具有 ±5% 电压调节和电流调节能力
80kHz 最大开关频率可实现高功率密度充电器设计
针对最高总体效率的准谐振谷值开关运行
宽 VDD 范围允许使用小型偏置电容器
输出过压、低线路和过流保护功能
可动态控制工作状态并定制调制配置文件，支持在所有
负载条件下高效运行，并且不会影响输出瞬态响应。
UCC28722 所采用的控制算法使得工作效率符合甚至
超过现行标准。输出驱动接口与双极型晶体管功率开关
相连实现了低成本转换器设计。带有谷值开关的断续导
通模式 (DCM) 减少了开关损耗，调制开关频率和一次
侧峰值电流振幅（FM 和 AM）可在整个负载和线路范
围内保持高转换效率。
可编程电缆补偿
小外形尺寸晶体管 (SOT) 23-6 封装
2 应用
•
用于消费类电子产品的 USB 兼容适配器和充电器
–
–
–
智能电话
平板电脑
摄像机
此控制器的最大开关频率为 80kHz，并且一直保持对
变压器内峰值一次侧电流的控制。输出过压和过流以及
输入欠压保护 特性 有助于抑制一次侧和二次侧应力分
量。此外，UCC28722 可通过设定外部电阻来补偿电
缆中的压降。
•
•
适用于电视和台式机的备用电源
白色家电
器件信息(1)
器件型号
UCC28722
封装
封装尺寸（标称值）
DBV (6)
2.90mm x 1.60mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
简化的应用示意图
VOUT
Np
Ns
VIN
Na
UCC28722
1
2
3
CBC
VDD
DRV
VS
GND
CS
6
5
4
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSBL7
UCC28722
ZHCSEK1B –DECEMBER 2013–REVISED OCTOBER 2015
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 16
Power Supply Recommendations...................... 22
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
8
9
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 23
11 器件和文档支持 ..................................................... 25
11.1 器件支持 ............................................................... 25
11.2 文档支持 ............................................................... 26
11.3 社区资源................................................................ 27
11.4 商标....................................................................... 27
11.5 静电放电警告......................................................... 27
11.6 Glossary................................................................ 27
12 机械、封装和可订购信息....................................... 27
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (January 2014) to Revision B
Page
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已添加ESD 额定值表，特性 说明部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文档
支持部分以及机械、封装和可订购信息部分 ........................................................................................................................... 1
Changes from Original (December 2013) to Revision A
Page
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已更改 简化应用示意图。 ....................................................................................................................................................... 1
Changed Supply current, fault values from 95 µA and 170 µA to 2.00 mA and 2.65 mA...................................................... 5
Changed Bias Supply Current vs VDD Voltage image........................................................................................................... 6
Changed Operating Current vs Junction Temperature image................................................................................................ 6
Changed Functional Block Diagram....................................................................................................................................... 8
Changed Simplified Flyback Convertor image. .................................................................................................................... 11
Changed CDD equation. ........................................................................................................................................................ 20
2
Copyright © 2013–2015, Texas Instruments Incorporated
UCC28722
www.ti.com.cn
ZHCSEK1B –DECEMBER 2013–REVISED OCTOBER 2015
5 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
VS
CBC
VDD
DRV
1
2
3
6
5
4
GND
CS
Pin Functions
PIN
I/O
DESCRIPTION
NAME
CBC
NO.
Cable compensation is a programming pin for compensation of cable voltage drop. Cable
compensation is programmed with a resistor to GND.
1
I
Current sense input connects to a ground-referenced current-sense resistor in series with the power
switch. The resulting voltage is used to monitor and control the peak primary current. A series resistor
can be added to this pin to compensate the peak switch current levels as the AC-mains input varies.
CS
4
3
5
I
DRV
GND
O
—
Drive is an output used to drive the base of an external high voltage NPN transistor.
The ground pin is both the reference pin for the controller and the low-side return for the drive output.
Special care should be taken to return all AC decoupling capacitors as close as possible to this pin and
avoid any common trace length with analog signal return paths.
VDD is the bias supply input pin to the controller. A carefully-placed bypass capacitor to GND is
required on this pin.
VDD
VS
2
6
I
I
Voltage sense is an input used to provide voltage and timing feedback to the controller. This pin is
connected to a voltage divider between an auxiliary winding and GND. The value of the upper resistor
of this divider is used to program the AC-mains run and stop thresholds and line compensation at the
CS pin.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
VVDD
IDRV
IDRV
IVS
Bias supply voltage, VDD
Continuous base current sink
Continuous base current source
Peak current, VS
38
50
mA
mA
mA
V
Self-limiting
–1.2
VDRV
Base drive voltage at DRV
–0.5
–0.75
–0.5
–55
Self-limiting
VS
Voltage
7
V
CS, CBC
5
V
TJ
Operating junction temperature
150
260
150
°C
°C
°C
Lead temperature 0.6 mm from case for 10 seconds
Storage temperature
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Copyright © 2013–2015, Texas Instruments Incorporated
3
UCC28722
ZHCSEK1B –DECEMBER 2013–REVISED OCTOBER 2015
www.ti.com.cn
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX
35
UNIT
V
VDD
CVDD
RCBC
IVS
Bias supply operating voltage
VDD bypass capacitor
9
1.0
10
10
µF
Cable-compensation resistance
VS pin current
kΩ
mA
°C
−1
TJ
Operating junction temperature
−40
125
6.4 Thermal Information
UCC28722
THERMAL METRIC(1)
DBV (SOT-23)
6 PINS
180.0
72.2
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
44.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
5.1
ψJB
43.8
RθJC(bot)
NA
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2013–2015, Texas Instruments Incorporated
UCC28722
www.ti.com.cn
ZHCSEK1B –DECEMBER 2013–REVISED OCTOBER 2015
6.5 Electrical Characteristics
over operating free-air temperature range, VVDD = 25 V, HV = open, RCBC = open, TA = -40°C to 125°C, TA = TJ
(unless otherwise noted)
PARAMETER
BIAS SUPPLY INPUT
TEST CONDITIONS
MIN
TYP
MAX UNIT
IRUN
Supply current, run
Supply current, wait
Supply current, start
Supply current, fault
IDRV = 0, run state
2.00
95
2.65
170
1.5
mA
µA
IWAIT
ISTART
IFAULT
IDRV = 0, wait state
IDRV = 0, VVDD = 18 V, start state, IHV = 0
IDRV = 0, fault state
1.0
µA
2.00
2.65
mA
UNDERVOLTAGE LOCKOUT
VVDD(on) VDD turnon threshold
VVDD(off) VDD turnoff threshold
VS INPUT
VVDD low to high
VVDD high to low
19
21
23
V
V
7.2
7.7
8.3
VVSR
Regulating level
Measured at no-load condition, TJ = 25°C(1)
IVS = –300 µA, volts below ground
VVS = 4 V
3.99
190
4.05
250
0
4.11
325
V
VVSNC
IVSB
Negative clamp level
Input bias current
mV
µA
–0.25
0.25
CS INPUT
VCST(max) Max CS threshold voltage
VCST(min) Min CS threshold voltage
VVS = 3.7 V
730
170
3.6
780
190
4.0
820
220
4.4
mV
mV
V/V
mV
A/A
ns
VVS = 4.35 V
KAM
AM control ratio
VCST(max) / VCST(min)
VCCR
KLC
Constant current regulating level
Line compensation current ratio
Leading-edge blanking time
CC regulation constant
IVSLS = –300 µA, IVSLS / current out of CS pin
DRV output duration, V CS = 1 V
314
24.0
230
330
25.0
290
347
28.6
355
TCSLEB
DRIVER
IDRS(max) Maximum DRV source current
IDRS(min) Minimum DRV source current
VDRV = 2 V, VVDD = 9 V, VVS = 3.85 V
VDRV = 2 V, VVDD = 9 V, VVS = 4.30 V
IDRV = 10 mA
31
15
37
19
1
42
23
2.4
7
mA
mA
Ω
RDRVLS
VDRCL
DRV low-side drive resistance
DRV clamp voltage
VVDD = 35 V
5.9
20
V
RDRVSS
TIMING
fSW(max)
fSW(min)
tZTO
DRV pulldown in start state
25
kΩ
Maximum switching frequency
Minimum switching frequency
Zero-crossing timeout delay
VVS = 3.7 V
72
570
2.4
80
650
3.1
89
750
3.7
kHz
Hz
µs
VVS = 4.35 V
PROTECTION
VOVP
Overvoltage threshold
At VS input, TJ = 25°C(1)
At CS input
4.49
1.4
4.60
1.5
4.75
1.6
V
V
VOCP
Overcurrent threshold
IVSL(run)
VS line-sense run current
Current out of VS pin increasing
Current out of VS pin decreasing
IVSL(run) / IVSL(stop)
188
70
225
80
277
100
3.05
µA
µA
A/A
°C
IVSL(stop) VS line-sense stop current
KVSL
VS line sense ratio
2.45
2.80
165
TJ(stop)
Thermal shutdown temperature
Internal junction temperature
CABLE COMPENSATION
Cable compensation maximum
VCBC(max)
Voltage at CBC at full load
2.9
–55
270
3.1
–15
320
3.5
25
V
voltage
VCBC = open, change in VS regulating level at full
load
VCVS(min) Minimum compensation at VS
VCVS(max) Maximum compensation at VS
mV
mV
VCBC = 0 V, change in VS regulating level at full
load
385
(1) The regulating level and over voltage at VS decreases with temperature by 0.8 mV/˚C. This compensation is included to reduce the
power supply output voltage variance over temperature.
Copyright © 2013–2015, Texas Instruments Incorporated
5
UCC28722
ZHCSEK1B –DECEMBER 2013–REVISED OCTOBER 2015
www.ti.com.cn
6.6 Typical Characteristics
VDD = 25 V, unless otherwise noted.
10
10
1
Run State
IRUN, VDD = 25 V
1
Wait State
0.1
IWAIT, VDD = 25 V
0.1
0.01
0.01
0.001
0.0001
VDD Turn−Off
Start State
VDD Turn−On
0.001
0.0001
ISTART, VDD = 18 V
0.00001
0
5
10
15
20
25
30
35
−25
0
25
50
75
100
125
VDD − Bias Supply Voltage (V)
TJ − Temperature (°C)
G001
G002
Figure 1. Bias Supply Current vs VDD Voltage
Figure 2. Operating Current vs Junction Temperature
250
4.2
Start
4.15
4.1
4.05
4
200
150
100
Stop
50
0
3.95
3.9
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Junction Temperature (°C)
C004
Junction Temperature (°C)
C003
Figure 4. VS Pin Start and Stop Thresholds
vs Junction Temperature
Figure 3. VS Pin Regulation Voltage
vs Junction Temperature
900
800
700
600
500
400
300
200
100
0
340
335
330
325
320
VVS = 3.7 V
VVS = 4.35 V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Junction Temperature (°C)
Junction Temperature (°C)
C005
C006
Figure 5. Current Sense Threshold
vs Temperature
Figure 6. Constant Current Regulation Level
vs Junction Temperature
6
Copyright © 2013–2015, Texas Instruments Incorporated
UCC28722
www.ti.com.cn
ZHCSEK1B –DECEMBER 2013–REVISED OCTOBER 2015
Typical Characteristics (continued)
VDD = 25 V, unless otherwise noted.
700
690
680
670
660
650
640
630
620
610
600
85
84
83
82
81
80
79
78
77
76
75
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Junction Temperature (°C)
Junction Temperature (°C)
C007
C012
Figure 7. Minimum Switching Frequency
vs Junction Temperature
Figure 8. Maximum Switching Frequency
vs Junction Temperature
40
35
30
25
20
15
10
1.6
1.5
1.4
1.3
1.2
1.1
1
VVS = 3.7 V
0.9
0.8
0.7
0.6
VVS = 4.35 V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Junction Temperature (°C)
Junction Temperature (°C)
C008
C009
Figure 9. Driver Output Source Current
vs Junction Temperature
Figure 10. Driver Pull Down Resistance
vs Junction Temperature
4.68
4.66
4.64
4.62
4.6
4.58
4.56
4.54
-50
-25
0
25
50
75
100
125
Junction Temperature (°C)
C010
Figure 11. Over Voltage Protection Threshold
vs Junction Temperature
Copyright © 2013–2015, Texas Instruments Incorporated
7
UCC28722
ZHCSEK1B –DECEMBER 2013–REVISED OCTOBER 2015
www.ti.com.cn
7 Detailed Description
7.1 Overview
The UCC28722 is a flyback power supply controller that provides accurate voltage and constant current
regulation with primary-side feedback, eliminating the need for opto-coupler feedback circuits. The controller
operates in discontinuous conduction mode with valley-switching to minimize switching losses. The modulation
scheme is a combination of frequency and primary peak current modulation to provide high conversion efficiency
across the load range. The control law provides a wide-dynamic operating range of output power, which allows
the power designer to achieve less than 75-mW of stand-by power.
During low-power operating ranges, the device has power-management features to reduce the device operating
current at operating frequencies below 28 kHz. Accurate voltage and constant current regulation, fast dynamic
response, and fault protection are achieved with primary-side control. A complete charger solution can be
realized with a straightforward design process, low cost and low component count.
7.2 Functional Block Diagram
OC FAULT
POWER
OV FAULT
UVLO
& FAULT
2
5
6
VDD
GND
VS
TSD/SD FAULT
LINE FAULT
21 V / 8 V
MANAGEMENT
VDD
5 V
4.05 V + VCVS
35mA
+
+
CONTROL
LAW
E/A
SAMPLER
3
DRV
6V
VCST
1 / fSW
20 kO
OV FAULT
VOVP
VALLEY
S
R
Q
Q
SWITCHING
4
+
CS
SECONDARY
TIMING
CURRENT
REGULATION
VCST
DETECT
LEB
IVSLS
LINE
SENSE
IVSLS
IVSLS / KLC
+
+
OC FAULT
LINE
10 kO
1.5 V
FAULT
2.2 V / 0.80 V
VCVS = ICBC x 3 kO
CABLE
0 V-3 V
COMPENSATION
+
ICBC
28 kO
1
CBC
8
Copyright © 2013–2015, Texas Instruments Incorporated
UCC28722
www.ti.com.cn
ZHCSEK1B –DECEMBER 2013–REVISED OCTOBER 2015
7.3 Feature Description
7.3.1 Device Bias Voltage Supply (VDD)
The VDD pin is connected to a bypass capacitor to ground. The VDD turnon UVLO threshold is 21 V and turnoff
UVLO threshold is 7.7 V, with an available operating range up to 35 V on VDD. The USB charging specification
requires the output current to operate in constant-current mode from 5 V to a minimum of 2 V, which is easily
achieved with a nominal VDD of approximately 22 V. The additional VDD headroom (up to 35 V) allows for VDD
to rise due to the leakage energy delivered to the VDD capacitor in high-load conditions.
NOTE
It is possible for the start-up resistor to supply more current to the VDD node than the IC
will consume at higher bulk input voltages. A Zener diode clamp is required on the VDD
pin to keep the VDD pin voltage within limits if this is the case.
7.3.2 Ground (GND)
There is one ground reference external to the device for the base drive current and analog signal reference. TI
recommends placing the VDD bypass capacitor close to GND and VDD with short traces to minimize noise on
the VS and CS signal pins.
7.3.3 Voltage-Sense (VS)
The VS pin is connected to a resistor divider from the auxiliary winding to ground. The output-voltage feedback
information is sampled at the end of the transformer secondary current demagnetization time to provide an
accurate representation of the output voltage. Timing information for achieving valley-switching and to control the
duty cycle of the secondary transformer current is determined by the waveform on the VS pin. Avoid placing a
filter capacitor on this input because it would interfere with accurate sensing of this waveform.
The VS pin also senses the bulk capacitor voltage to provide for AC-input run and stop thresholds, and to
compensate the current-sense threshold across the AC-input range. During the transistor on-time, the VS pin is
clamped to approximately 250 mV below GND and the current out of the VS pin is sensed. For the AC-input run
and stop function, the run threshold on VS is 225 µA and the stop threshold is 80 µA. The values for the auxiliary
voltage divider upper-resistor (RS1) and lower-resistor (RS2) can be determined by Equation 1 and Equation 2.
V
IN(run) ´ 2
RS1
=
NPA ´IVSL(run)
where
•
•
•
NPA is the transformer primary-to-auxiliary turns ratio.
VIN(run) is the AC RMS voltage to enable turnon of the controller (run).
IVSL(run) is the run-threshold for the current pulled out of the VS pin during the switch on-time (see Electrical
Characteristics).
(1)
RS1 ´ VVSR
RS2
=
NAS ´ V
(
+ VF - V
VSR
)
OCV
where
•
•
•
•
•
VOCV is the converter regulated output voltage.
VF is the output rectifier forward drop at near-zero current.
NAS is the transformer auxiliary to secondary turns ratio.
RS1 is the VS divider high-side resistance.
VVSR is the CV regulating level at the VS input (see Electrical Characteristics).
(2)
Copyright © 2013–2015, Texas Instruments Incorporated
9
UCC28722
ZHCSEK1B –DECEMBER 2013–REVISED OCTOBER 2015
www.ti.com.cn
Feature Description (continued)
7.3.4 Base Drive (DRV)
The DRV pin is connected to the NPN transistor base pin. The driver provides a base drive signal limited to 7 V.
The turn-on characteristic of the driver is a 19-mA to 37-mA current source that is scaled with the current sense
threshold dictated by the operating point in the control scheme. When the minimum current sense threshold is
being used, the base drive current is also at its minimum value. As the current sense threshold is increased to
the maximum, the base drive current scales linearly to its maximum of 35-mA typical. The turn-off current is
determined by the low-side driver RDS(on)
.
7.3.5 Current Sense (CS)
The current-sense pin is connected through a series resistor (RLC) to the current-sense resistor (RCS). The
current-sense threshold is 0.78 V for IPP(max) and 0.19 V for IPP(min). The series resistor RLC provides the function
of feedforward line compensation to eliminate change in IPP due to change in di/dt and the propagation delay of
the internal comparator and NPN transistor turn-off time. There is an internal leading-edge blanking time of
approximately 300 ns to eliminate sensitivity to the turnon current spike. It should not be necessary to place a
bypass capacitor on the CS pin. The value of RCS is determined by the target output current in constant current
(CC) regulation. The values of RCS and RLC can be determined by Equation 3 and Equation 4. The term ηXFMR is
intended to account for the energy stored in the transformer but not delivered to the secondary, which includes
transformer resistance and core loss, bias power, and primary-to-secondary leakage ratio.
7.3.5.1 Example
With a transformer core and winding loss of 5%, primary-to-secondary leakage inductance of 3.5%, and bias
power-to-output power ratio of 1.5%, the ηXFMR value is approximately: 1 – 0.05 – 0.035 – 0.015 = 0.9.
V
´N
CCR
PS
R
=
´ h
XFMR
CS
2I
OCC
where
•
•
•
•
VCCR is a current regulation constant (see Electrical Characteristics).
NPS is the transformer primary-to-secondary turns ratio (a ratio of 13 to 15 is recommended for 5-V output).
IOCC is the target output current in constant-current regulation.
ηXFMR is the transformer efficiency.
(3)
spacer
K
´R ´R ´ t ´N
LC
S1
CS
D
PA
R
=
LC
L
P
where
•
•
•
RS1 is the VS pin high-side resistor value.
RCS is the current-sense resistor value.
t D is the current-sense delay including NPN transistor turn-off delay, add approximately 50 ns to transistor
delay.
•
•
•
NPA is the transformer primary-to-auxiliary turns ratio.
LP is the transformer primary inductance.
KLC is a current-scaling constant (see Electrical Characteristics).
(4)
10
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Feature Description (continued)
7.3.6 Cable Compensation (CBC)
The cable compensation pin is connected to a resistor to ground to program the amount of output voltage
compensation to offset cable resistance. The cable compensation block provides a 0-V to 3-V voltage level on
the CBC pin corresponding to IOCC(max) output current. Connecting a resistance from CBC to GND programs a
current that is summed into the VS feedback divider, increasing the regulation voltage as IOUT increases. There is
an internal series resistance of 28 kΩ to the CBC pin that sets a maximum cable compensation of a 5-V output to
400 mV when CBC is shorted to ground. The CBC resistance value can be determined by Equation 5.
VCBC(max) ´ 3 kW ´ V
(
VVSR ´ VOCBC
+ VF
)
OCV
RCBC
=
- 28 kW
where
•
•
•
•
VOCV is the regulated output voltage.
VF is the diode forward voltage in V.
VOCBC is the target cable compensation voltage at the output terminals.
VCBC(max) is the maximum voltage at the cable compensation pin at the maximum converter output current (see
Electrical Characteristics).
•
VVSR is the CV regulating level at the VS input (see Electrical Characteristics).
(5)
7.4 Device Functional Modes
7.4.1 Primary-Side Voltage Regulation
Figure 12 illustrates a simplified flyback convertor with the main voltage regulation blocks of the device shown.
The power train operation is the same as any DCM flyback circuit but accurate output voltage and current
sensing is the key to primary-side control.
Bulk Voltage
Secondary
Winding
Primary Winding
VOUT
RLOAD
COUT
Timing
VCL
Aux
Winding
RS1
Control
Law
Discriminator
and
Sampler
GD
DRV
CS
VS
-
Minimum
Period
and Peak
Primary
Current
RS2
RCS
Zero Crossings
UDG-13093
The main voltage regulation blocks are shown.
Figure 12. Simplified Flyback Convertor
In primary-side control, the output voltage is sensed on the auxiliary winding during the transfer of transformer
energy to the secondary. As shown in Figure 13, it is clear there is a down slope representing a decreasing total
rectifier (VF) and resistance voltage drop (ISRS) as the secondary current decreases to zero. To achieve an
accurate representation of the secondary output voltage on the auxiliary winding, ensure that the discrimantor:
•
•
•
Reliably recognizes the leakage inductance reset, ringing, and ingores
Continuously samples the auxiliary voltage during the down slope after the ringing is diminished
Captures the error signal at the time the secondary winding reaches zero current
The internal reference on VS is 4.05 V. Temperature compensation on the VS reference voltage of –0.8-mV/°C
offsets the change in the output rectifier forward voltage with temperature. The resistor divider is selected as
outlined in the VS pin description.
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Device Functional Modes (continued)
VS Sample
V
(
+ VF + IS ´ RS ´ N
)
OUT
A
NS
0 V
- V
(
´ N
)
BLK
A
NP
Figure 13. Auxiliary Winding Voltage
The UCC28722 includes a VS signal sampler that uses discrimination methods to ensure an accurate sample of
the output voltage from the auxiliary winding. There are some conditions that must be met on the auxiliary
winding signal to ensure reliable operation. These conditions are the reset time of the leakage inductance and
the duration of any subsequent leakage inductance ring. Refer to Figure 14 for a detailed illustration of waveform
criteria to ensure a reliable sample on the VS pin. The first detail to examine is the duration of the leakage
inductance reset pedestal, tLK_RESET in Figure 14. Because this can mimic the waveform of the secondary current
decay followed by a sharp downslope, it is important to keep the leakage reset time less than 600 ns for IPRI
minimum, and less than 2.2 µs for IPRI maximum. The second detail is the amplitude of ringing on the VAUX
waveform following tLK_RESET. The peak-to-peak voltage at the VS pin should be less than approximately 100
mVp-p at least 200 ns before the end of the demagnetization time, tDM. If there is a concern with excessive
ringing, it usually occurs during light or no-load conditions, when tDM is at the minimum. The tolerable ripple on
VS scales up when measured at the auxiliary winding by RS1 and RS2, and is equal to 100 mV × (RS1 + RS2) /
RS2 when measured directly at the auxiliary winding.
tLK_RESET
tSMPL
VS Ring (p-p)
tDM
UDG-12202
Figure 14. Auxiliary Waveform Details
During voltage regulation, the controller operates in frequency modulation mode and amplitude modulation mode
as illustrated in Figure 15. The internal operating frequency limits of the device are 80 kHz, fSW(max) and 650 Hz,
fSW(min). The transformer primary inductance and primary peak current chosen sets the maximum operating
frequency of the converter. The output preload resistor and efficiency at low power determines the converter
minimum operating frequency. There is no stability compensation required for the UCC28722.
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Device Functional Modes (continued)
Control Law Profile in Constant Voltage (CV) Mode
80 kHz
fSW(max)
IPP(max)
IPP
fSW
IPP(max)/4
28 kHz
3.3 kHz
FM
AM
FM
fSW(min)
0.75 V 1.3 V
2.2 V
3.55 V
5 V
Control Voltage, E/A Output (VCL
)
UDG-13095
Figure 15. Frequency and Amplitude Modulation Modes During Voltage Regulation
7.4.2 Primary-Side Current Regulation
Timing information at the VS pin and current information at the CS pin allow accurate regulation of the secondary
average current. The control law dictates that as power is increased in CV regulation and approaching CC
regulation the primary-peak current is at IPP(max). Referring to Figure 16, the primary-peak current, turns ratio,
secondary demagnetization time (tDM), and switching period (tSW) determine the secondary average output
current. Ignoring leakage inductance effects, the average output current is given by Equation 6. When the
average output current reaches the regulation reference in the current control block, the controller operates in
frequency modulation mode to control the output current at any output voltage at or below the voltage regulation
target as long as the auxiliary winding can keep VDD above the UVLO turnoff threshold.
I
S ´ NS
IPP
NP
tON
tDM
tSW
UDG-12203
Figure 16. Transformer Currents
I
N
t
PP
P
´
DM
I
=
´
OUT
2
N
t
S
SW
(6)
13
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Device Functional Modes (continued)
VOCV
5.25 V
4.75 V
5
4
5ꢀ
3
2
1
IOCC
Output Current
UDG-12201
Figure 17. Typical Target Output V-I Characteristic
7.4.3 Valley Switching
The UCC28722 utilizes valley switching to reduce switching losses in the transistor, to reduce induced-EMI, and
to minimize the turnon current spike at the sense resistor. The controller operates in valley-switching in all load
conditions unless the collector voltage (VC) ringing has subsided.
Referring to Figure 18, the UCC28722 operates in a valley-skipping mode in most load conditions to maintain an
accurate voltage or current regulation point and still switch on the lowest available VC.
VC
VDRV
UDG-13091
Figure 18. Valley-Skipping Mode
7.4.4 Start-Up Operation
An external resistor connected from the bulk capacitor voltage (VBLK) to the VDD pin charges the VDD capacitor.
The amount of startup current that is available to charge the VDD capacitor is dependent on the value of this
external startup resistor. Larger values supply less current and increase startup time but at the expense of
increasing standby power and decreasing efficiency at high input voltage and light loading. When VDD reaches
the 21-V UVLO turnon threshold, the controller is enabled, the converter starts switching. The initial three cycles
are limited to IPP(min). After the initial three cycles at minimum IPP(min), the controller responds to the condition
dictated by the control law. The converter will remain in discontinuous mode during charging of the output
capacitors, maintaining a constant output current until the output voltage is in regulation.
14
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Device Functional Modes (continued)
NOTE
It is possible for the startup resistor to supply more current to the VDD node than the IC
will consume at higher bulk input voltages. A Zener diode clamp will be required on the
VDD pin to keep the VDD pin voltage within limits if this is the case.
7.4.5 Fault Protection
The UCC28722 provides comprehensive fault protection. Protection functions include the following:
•
•
•
•
•
•
Output over-voltage fault
Input under-voltage fault
Internal over-temperature fault
Primary over-current fault
CS pin fault
VS pin fault
A UVLO reset and restart sequence applies for all fault protection events.
The output over-voltage function is determined by the voltage feedback on the VS pin. If the voltage sample on
VS exceeds 115% of the nominal VOUT, the device stops switching and the internal current consumption is IFAULT
which discharges the VDD capacitor to the UVLO turnoff threshold. After that, the device returns to the start state
and a start-up sequence ensues.
The UCC28722 always operates with cycle-by-cycle primary peak current control. The normal operating range of
the CS pin is 0.78 V to 0.195 V. There is additional protection if the CS pin reaches 1.5 V. This results in a UVLO
reset and restart sequence.
The line input run and stop thresholds are determined by current information at the VS pin during the transistor
on-time. While the VS pin is clamped close to GND during the transistor on-time, the current through RS1 is
monitored to determine a sample of the bulk capacitor voltage. A wide separation of run and stop thresholds
allows clean start-up and shut-down of the power supply with the line voltage. The run current threshold is
225 µA and the stop current threshold is 80 µA.
The internal over-temperature protection threshold is 165°C. If the junction temperature reaches this threshold
the device initiates a UVLO reset cycle. If the temperature is still high at the end of the UVLO cycle, the
protection cycle repeats.
Protection is included in the event of component failures on the VS pin. If complete loss of feedback information
on the VS pin occurs, the controller stops switching and restarts.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The UCC28722 flyback power supply controller provides constant voltage (CV) and constant current (CC) output
regulation to help meet USB-compliant adaptors and charger requirements. This device uses the information
obtained from auxiliary winding sensing (VS) to control the output voltage and does not require optocoupler or
TL431 feedback circuitry. Not requiring optocoupler feedback reduces the component count and makes the
design more cost effective and efficient.
8.2 Typical Application
+ VF
-
VBLK
CB1
CB2
Np
RPL
VOUT
Ns
COUT
RST
VAC
- VFA
+
VAUX
RS1
Na
RCBC
RS2
1
2
3
CBC
VDD
DRV
VS
6
5
4
GND
CS
CDD
30V
RLC
RCS
Figure 19. Design Procedure Application Example
16
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Typical Application (continued)
8.2.1 Design Requirements
The design parameters are listed in Table 1.
Table 1. Design Parameters
PARAMETER
INPUT CHARACTERISTICS
TEST CONDITIONS
MIN
NOM
MAX UNIT
VIN
RMS Input Voltage
Line Frequency
100 (VIN(MIN)
)
115/230
50/60
70
240
64
V
Hz
V
fLINE
47
VIN(RUN)
Brownout Voltage
IOUT = Nom
OUTPUT CHARACTERISTICS
VOCV
VRIPPLE
IOUT
Output Voltage
VIN = Nom, IOUT = NOM
VIN = Nom, IO = Max
VIN = Min to Max
4.75
5
5.25
0.15
1.05
V
V
A
V
Output Voltage Ripple
Output Current
1
Output OVP
IOUT = Min to Max
5.75
Transient Response
(0.1 to 0.6 A) or (0.6 to 0.1 A)
VOΔ= 0.9 V for Calculations
Load Step (ITRAN = 0.6 A)
4.1
5
6
V
SYSTEMS CHARACTERISTICS
fMAX
Switching Frequency
70
kHz
Full Load Efficiency (115/230 V RMS
input)
IOUT = 1 A
75%
ƞ
8.2.2 Detailed Design Procedure
This procedure outlines the steps to design a constant-voltage, constant-current flyback converter using the
UCC28722 controller. Refer to Figure 19 for component names and network locations. The design procedure
equations use terms that are defined in Stand-by Power Estimate through Startup Resistance and Startup Time.
8.2.2.1 Stand-by Power Estimate
Assuming no-load stand-by power is a critical design parameter, determine estimated no-load power based on
target converter maximum switching frequency and output power rating.
The followingEquation 7 estimates the stand-by power of the converter.
POUT ´ fMIN
PSB _ CONV
=
2
hSB ´ KAM ´ fMAX
(7)
For a typical USB charger application, the bias power during no-load is approximately 2.5 mW. This is based on
25-V VDD and 100-µA bias current. The output preload resistor can be estimated by VOCV and the difference in
the converter stand-by power and the bias power. Equation 8 shows output preload resistance accounts for bias
power estimated at 2.5 mW.
2
VOCV
RPL
=
PSB _ CONV - 2.5 mW
(8)
Typical startup resistance values for RSTR range from 1 MΩ to 5MΩ to achieve 2 s startup time. The capacitor
bulk voltage for the loss estimation is the highest voltage for the stand-by power measurement, typically 325 VDC
see Equation 9.
,
2
VBLK
=
PRSTR
RSTR
(9)
For the total stand-by power estimation add an estimated 2.5 mW for snubber loss to the converter stand-by
power loss, see Equation 10 and Equation 11.
P
= P
+ 2.5 mW
SB
SB _CONV
(10)
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PSB = PSB _ CONV + PRSTR + 2.5 mW
(11)
8.2.2.2 Input Bulk Capacitance and Minimum Bulk Voltage
Determine the minimum voltage on the input capacitance, CB1 and CB2 total, in order to determine the maximum
Np to Ns turns ratio of the transformer. The input power of the converter based on target full-load efficiency,
minimum input RMS voltage, and minimum AC input frequency are used to determine the input capacitance
requirement.
Maximum input power is determined based on VOCV, IOCC, and the full-load efficiency target, see Equation 12.
VOCV ´ IOCC
P
=
IN
h
(12)
Equation 13 provides an accurate solution for input capacitance based on a target minimum bulk capacitor
voltage. To target a given input capacitance value, iterate the minimum capacitor voltage to achieve the target
capacitance.
æ
ö
÷
æ
ö
÷
÷
ø
VBULK(min)
1
ç
ç
ç
è
2P ´ 0.25 +
´ arcsin
IN
ç
è
2P
÷
2 ´ V
IN(min)
ø
CBULK
=
2
2
2V
(
- VBULK(min) ´ f
LINE
)
IN(min)
(13)
8.2.2.3 Transformer Turns Ratio, Inductance, Primary-Peak Current
The maximum primary-to-secondary turns ratio can be determined by the target maximum switching frequency at
full load, the minimum input capacitor bulk voltage, and the estimated DCM quasi-resonant time.
Initially determine the maximum available total duty cycle of the on time and secondary conduction time based on
target switching frequency and DCM resonant time. For DCM resonant time, assume 500 kHz if you do not have
an estimate from previous designs. For the transition mode operation limit, the period required from the end of
secondary current conduction to the first valley of the VCE voltage is 1/2 of the DCM resonant period, or 1 µs
assuming 500-kHz resonant frequency. DMAX can be determined using Equation 14.
t
æ
ö
R
DMAX = 1-
´ fMAX ÷ - DMAGCC
ç
2
è
ø
(14)
Once DMAX is known, the maximum turns ratio of the primary to secondary can be determined with the equation
below. DMAGCC is defined as the secondary diode conduction duty cycle during constant-current, CC, operation. It
is set internally by the UCC28722 at 0.425. The total voltage on the secondary winding needs to be determined;
which is the sum of VOCV, the secondary rectifier VF, and the cable compensation voltage (VOCBC). For the 5-V
USB charger applications, a turns ratio range of 13 to 15 is typically used, see Equation 15.
DMAX ´ VBULK(min)
NPS(max)
=
DMAGCC ´ V
(
+ VF + VOCBC
)
OCV
(15)
Once an optimum turns ratio is determined from a detailed transformer design, use this ratio for the following
parameters.
The UCC28722 constant-current regulation is achieved by maintaining a maximum DMAG duty cycle of 0.425 at
the maximum primary current setting. The transformer turns ratio and constant-current regulating voltage
determine the current sense resistor for a target constant current.
Since not all of the energy stored in the transformer is transferred to the secondary, a transformer efficiency term
is included in Equation 16. This efficiency number includes the core and winding losses, leakage inductance
ratio, and bias power ratio to rated output power. For a 5-V, 1-A charger example, bias power of 1.5% is a good
estimate. An overall transformer efficiency of 0.9 is a good estimate to include 3.5% leakage inductance, 5% core
and winding loss, and 1.5% bias power.
V
´N
CCR
PS
R
=
´ h
XFMR
CS
2I
OCC
(16)
18
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The primary transformer inductance can be calculated using the standard energy storage equation for flyback
transformers. Primary current, maximum switching frequency and output and transformer power losses are
included in Equation 17 and Equation 18. Initially determine transformer primary current.
Primary current is simply the maximum current sense threshold divided by the current sense resistance.
VCST(max)
=
IPP(max)
RCS
+ VF + VOCBC ´ I
(17)
(18)
2 V
(
)
OCV
OCC
LP
=
2
hXFMR ´ IPP(max) ´ fMAX
The secondary winding to auxiliary winding transformer turns ratio (NAS) is determined by the lowest target
operating output voltage in constant-current regulation and the VDD UVLO of the UCC28722. There is additional
energy supplied to VDD from the transformer leakage inductance energy which allows a lower turns ratio to be
used in many designs Equation 19
VDD(off) + VFA
NAS
=
VOCC + VF
(19)
8.2.2.4 Transformer Parameter Verification
The transformer turns ratio selected affects the transistor VC and secondary rectifier reverse voltage so these
should be reviewed. The UCC28722 does require a minimum on time of the transistor (tON) and minimum DMAG
time (tDMAG) of the secondary rectifier in the high line, minimum load condition. The selection of fMAX, LP and RCS
affects the minimum tON and tDMAG
.
The secondary rectifier and transistor voltage stress can be determined by Equation 20.
V
´
2
IN(max)
VREV
=
+ VOCV + VOCBC
NPS
(20)
For the transistor VC voltage stress, Equation 21, an estimated leakage inductance voltage spike (VLK) needs to
be included.
VCPK = ( VIN(max) ´ 2 )+( VOCV + VF + VOCBC )´ NPS + VLK
(21)
Equation 22 and Equation 23 are used to determine if the minimum tON target of 300 ns and minimum tDMAG
target of 1.2 µs is achieved.
I
´ V
PP max
(
CST min
(
L
)
)
P
t
=
´
ON min
(
)
V
V
´ 2
CST max
(
)
IN max
(
)
(22)
(23)
t
´ V
´ 2
ON
IN max
(
)
t
=
DMAG min
(
)
N
´ V
(
+ V
)
PS
OCV F
8.2.2.5 Output Capacitance
The output capacitance value is typically determined by the transient response requirement from no-load. For
example, in some USB charger applications there is a requirement to maintain a minimum VO of 4.1 V with a
load-step transient of 0 mA to 500 mA . Equation 24 assumes that the switching frequency can be at the
UCC28722 minimum of fSW(min)
.
æ
ç
è
ö
÷
÷
ø
1
I
+ 150 ms
TRAN ç
fSW(min)
COUT
=
VOD
(24)
Another consideration of the output capacitor is the ripple voltage requirement which is reviewed based on
secondary peak current and ESR. A margin of 20% is added to the capacitor ESR requirement in Equation 25.
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VRIPPLE ´ 0.8
=
RESR
IPP(max) ´ NPS
(25)
8.2.2.6 VDD Capacitance, CDD
The capacitance on VDD needs to supply the device operating current until the output of the converter reaches
the target minimum operating voltage in constant-current regulation. At this time, the auxiliary winding can
sustain the voltage to the UCC28722. The total output current available to the load and to charge the output
capacitors is the constant-current regulation target, IOCC. Equation 26 assumes all the output current of the
flyback is available to charge the output capacitance from 0 V to VOCC. If the converter is going to be loaded
during the time the output is ramping from 0 V to VOCC, that load current must be subtracted for the available
output current limit value, IOCC. There is 1 V of margin added to VDD in the calculation.
COUT ´ VOCC
IRUN + I
(
´ 1- D
(
) ´
)
)
DRS(max)
magcc
IOCC
CDD =
VDD(on) - VDD(off) -1 V
(
)
(26)
NOTE
The typical ceramic capacitor of sufficient ratings for use here varies considerably in
effective capacitance as the voltage across the capacitor changes. As the capacitor
voltage increases beyond 25% of its rated voltage, the effective capacitance can become
significantly less than the nominal capacitance at zero bias. This equation calculated the
effective capacitance needed over the 8V to 21V range, not the nominal zero bias
capacitance required. Evaluation of the particular capacitor chosen for this function is
strongly recommended to ensure adequate capacitance over the 8V to 21V range.
8.2.2.7 VS Resistor Divider, Line Compensation, and Cable Compensation
The VS divider resistors determine the output voltage regulation point of the flyback converter, also the high-side
divider resistor (RS1) determines the line voltage at which the controller enables continuous DRV operation. RS1
is initially determined based on transformer auxiliary to primary turns ratio and desired input voltage operating
threshold in Equation 27.
V
IN(run) ´ 2
RS1
=
NPA ´IVSL(run)
(27)
The low-side VS pin resistor is selected based on desired VO regulation voltage in Equation 28.
RS1 ´ VVSR
RS2
=
NAS ´ V
(
+ VF - V
VSR
)
OCV
(28)
The UCC28722 can maintain tight constant-current regulation over input line by utilizing the line compensation
feature. The line compensation resistor (RLC) value is determined by current flowing in RS1 and expected base
drive and transistor turnoff delay in Equation 29. Assume a 50-ns internal delay in the UCC28722.
K
´R ´R ´ t ´N
LC
S1
CS
D
PA
R
=
LC
L
P
(29)
The UCC28722 has adjustable cable drop compensation. The resistance for the desired compensation level at
the output terminals can be determined using Equation 30.
VCBC(max) ´ 3 kW ´ V
(
VVSR ´ VOCBC
+ VF
)
OCV
RCBC
=
- 28 kW
(30)
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8.2.2.8 Startup Resistance and Startup Time
When the VDD capacitor is known, there is a tradeoff to be made between startup time and overall standby input
power to the converter. Faster startup time requires a smaller startup resistance, which results in higher standby
input power in Equation 31.
2 ´ V
IN(min)
RSTR
=
VDD(on) ´CDD
ISTART
+
TSTR
(31)
8.2.3 Application Curves
78%
76%
74%
72%
70%
68%
66%
64%
Efficiency at 115 V RMS
Efficiency at 230 V RMS
10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
Output Power
C001
Figure 21. Output at Start-up 115-V RMS, No Load
Figure 20. Efficiency
Figure 22. Output at Start-up 115-V RMS, 5-Ω Load
Figure 23. Output at Start-up 230-V RMS, No Load
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CH1 = VOCV with 5-V offset, CH2 = IOUT
Figure 25. Load Transients (0.1- to 0.6-A Load Step)
SPACE
Figure 24. Output at Start-up 230-V RMS, 5-Ω Load
CH1 = VOCV with 5-V offset, CH2 = IOUT
Figure 26. Load Transient (0.6- to 0.1-A Load Step)
Figure 27. Output Ripple CH1 = VOCV at Supply Output
9 Power Supply Recommendations
The UCC28722 is intended for AC/DC adapters and chargers with input voltage range of 85 VAC(rms) to 265
VAC(rms) using Flyback topology. This device can be used in other applications and converter topologies with
different input voltages. Ensure that all voltages and currents are within the Recommended Operating Conditions
and Absolute Maximum Ratings of the device. To maintain output current regulation over the entire input voltage
range, design the converter to operate close to fMAX when in full-load conditions. To improve thermal
performance, increase the copper area connected to GND pins.
22
Copyright © 2013–2015, Texas Instruments Incorporated
UCC28722
www.ti.com.cn
ZHCSEK1B –DECEMBER 2013–REVISED OCTOBER 2015
10 Layout
10.1 Layout Guidelines
•
High frequency bypass Capacitor C7 should be placed arcoss Pin 2 and 5 as close as you can get it to the
pins.
•
Resistor R15 and C7 form a low pass filter and the connection of R15 and C7 should be as close to the VDD
pin as possible.
•
•
•
•
C9 should be put as close to CS pin and R10 as possible. This forms a low pass filter with R10.
The connection for C9 and R10 should be as close to the CS pin as possible.
C9 may not be required in all designs. However, it is wise to put a place holder for it in your design.
The VS pin controls the output voltage through the transformer turns ratio and the voltage divider of R7 and
R9. The trace with between the R7, R9 and VS pin should be as short as possible to reduce and eliminate
possible EMI coupling.
•
The IC ground and power ground should meet at the return of the bulk capacitors (C4 and C5). Ensure that
high frequency and high current from the power stage does not go through the signal ground
–
The high frequency and high current path that you need to be cautious of on the primary is C4, C5 +,
T1(P1,P2), Q1e, Q1c, R13 to the return of C4 and C5.
•
•
•
•
Keep all high current loops as short as possible.
Keep all high current and high frequency traces away from or perpendicular to other traces in the design.
Traces on the voltage clamp formed by D1, R1, D4 and C4 as short as possible.
C4 return needs to be as close to the bulk capacitor supply as possible. This reduces the magnitude of dv/dt
caused by large di/dt.
•
Avoid mounting semiconductors under magnetics.
10.2 Layout Example
Çꢀ4
[ine
W1
Çꢀ1
[1
ëhÜÇ-
/ꢁ
wꢁ
/2
w1
W2
5ꢁ
51
/4
Ç1
w3
v1
ëhÜÇ+
Çꢀ3
52
w1ꢁ
w11
buetral
Çꢀ3
Ü1
w10
/3
w2
/8
53
Figure 28. PCB Layout Example
Copyright © 2013–2015, Texas Instruments Incorporated
23
UCC28722
ZHCSEK1B –DECEMBER 2013–REVISED OCTOBER 2015
www.ti.com.cn
Figure 29. 5-W USB Adapter Schematic
24
版权 © 2013–2015, Texas Instruments Incorporated
UCC28722
www.ti.com.cn
ZHCSEK1B –DECEMBER 2013–REVISED OCTOBER 2015
11 器件和文档支持
11.1 器件支持
11.1.1 器件命名规则
11.1.1.1 术语定义
11.1.1.1.1 法拉电容术语
•
•
•
CBULK：CB1 和 CB2 的总输入电容。
CDD：VDD 引脚上所需的最小电容。
COUT：所需的最小输出电容。
11.1.1.1.2 占空比术语
•
•
D
MAGCC：CC 中的二次侧二极管导通占空比，0.425。
DMAX：晶体管导通时间占空比。
11.1.1.1.3 频率术语（以赫兹为单位）
•
•
•
•
f
f
f
f
LINE：最小线路频率。
MAX：转换器的目标满载最大开关频率。
MIN：转换器的最小开关频率，为器件的 fSW(min) 限值增加 15％ 裕度。
SW(min)：最小开关频率（请参见电气特性）。
11.1.1.1.4 电流术语（以安培为单位）
•
•
•
•
•
•
I
I
I
I
I
I
OCC：转换器目标恒流输出。
PP(max)：变压器一次侧最大电流。
START：启动偏置电源电流（请参见电气特性）。
TRAN：所需的正负载阶跃电流。
VSL(run)： VS 引脚运行电流（请参见电气特性）。
DRS：驱动器拉电流（请参见电气特性）。
11.1.1.1.5 电流和电压调节术语
•
•
K
K
AM： 一次侧峰峰值电流比（请参见电气特性）。
LC：电流调节常量（请参见电气特性）。
11.1.1.1.6 变压器术语
•
•
•
•
LP：变压器一次侧电感。
NAS：变压器辅助侧与二次侧的匝数比。
NPA：变压器一次侧与辅助侧的匝数比。
NPS：变压器一次侧与二次侧的匝数比。
11.1.1.1.7 功率术语（以瓦特为单位）
•
•
•
•
•
PIN：转换器的最大输入功率。
P
P
P
P
OUT：转换器的满载输出功率。
RSTR：VDD 启动电阻的功耗。
SB：总待机功耗。
SB_CONV：PSB与启动电阻和缓冲器损耗的差值。
11.1.1.1.8 电阻术语（以 Ω 为单位）
•
•
•
•
R
R
R
CS：一次侧电流编程电阻。
ESR：输出电容器的总 ESR。
PL：转换器输出端的预载电阻。
RS1：高侧 VS 引脚电阻。
版权 © 2013–2015, Texas Instruments Incorporated
25
UCC28722
ZHCSEK1B –DECEMBER 2013–REVISED OCTOBER 2015
www.ti.com.cn
器件支持 (接下页)
•
•
RS2：低侧 VS 引脚电阻。
RSTR ：启动电阻。
11.1.1.1.9 时序术语（以秒为单位）
•
•
•
•
•
TD：包括晶体管关断延迟在内的电流感测延迟；添加 50ns 至晶体管延迟。
T
T
DMAG(min)：二次侧整流器的最短导通时间。
N(min)：晶体管的最短导通时间。
tR：断续导通模式 (DCM) 期间的谐振频率。
ST：启动时间
t
11.1.1.1.10 电压术语（以伏特为单位）
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
V
BLK：用于待机功耗测量的大容量电容最高电压。
VBULK（最小值）：满功率条件下 CB1 和 CB2 的最低电压。
V
V
V
V
V
V
V
V
V
OCBC：输出引脚的目标电缆补偿电压。
CBC(max)：最大转换器输出电流条件下 CBC 引脚的最大电压（请参见电气特性）。
CCR：恒流调节电压（请参见电气特性）。
CST(max)：CS 引脚的最大电流感测阈值（请参见电气特性）。
CST(min)：CS 引脚的最小电流感测阈值（请参见电气特性）。
DD(off)：UVLO 关断电压（请参见电气特性）。
DD(on)：UVLO 导通电压（请参见电气特性）。
OΔ：负载阶跃瞬态期间允许的输出压降。
CPK：高压线条件下的晶体管集电极到发射极电压峰值
VF：电流接近零时的二次侧整流器正向压降。
V
V
V
V
V
V
V
FA：辅助整流器正向压降。
LK：估计的漏感能量复位电压。
OCV：经稳压的转换器输出电压。
OCC：恒流稳压条件下的最低目标转换器输出电压。
REV：二次侧整流器的峰值反向电压。
RIPPLE：满载条件下的输出峰峰值纹波电压。
VSR：VS 输入端的 CV 调节电平（请参见电气特性）。
11.1.1.1.11 交流电压术语（以 VRMS 为单位）
•
•
•
VIN(max)：转换器的最大输入电压。
VIN(min)：转换器的最小输入电压。
VIN(min)：转换器的输入启动（运行）电压。
11.1.1.1.12 效率术语
•
ηSB：无载条件下估算的转换器效率，其中不包括启动电阻或偏置损耗。ηSB：对于一个 5V USB 充电器应
用，60％ 到 65％ 是一个很好的初步估算值。
•
•
η：转换器总体效率。
ηXFMR：变压器一次侧与二次侧之间的功率传输效率。
11.2 文档支持
11.2.1 相关文档
请参见如下文档：《UCC28722/UCC28720 5W USB BJT 反激设计示例》，SLUA700
26
版权 © 2013–2015, Texas Instruments Incorporated
UCC28722
www.ti.com.cn
ZHCSEK1B –DECEMBER 2013–REVISED OCTOBER 2015
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2013–2015, Texas Instruments Incorporated
27
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC28722DBVR
UCC28722DBVT
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
6
6
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
U722
U722
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC28722DBVR
UCC28722DBVT
SOT-23
SOT-23
DBV
DBV
6
6
3000
250
178.0
178.0
9.0
9.0
3.23
3.23
3.17
3.17
1.37
1.37
4.0
4.0
8.0
8.0
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UCC28722DBVR
UCC28722DBVT
SOT-23
SOT-23
DBV
DBV
6
6
3000
250
180.0
180.0
180.0
180.0
18.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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