UCC28730-Q1 [TI]
适用于汽车的零功耗待机 PSR 反激式控制器;
| 型号： | UCC28730-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于汽车的零功耗待机 PSR 反激式控制器 控制器 |
| 文件： | 总43页 (文件大小：1865K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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UCC28730-Q1
ZHCSGD9 –JUNE 2017
适用于汽车的 UCC28730-Q1 零功耗待机 PSR 反激式控制器
1 特性
2 应用
1
•
•
符合汽车应用 要求
具有符合 AEC-Q100 的下列结果：
•
•
•
•
汽车电源
混合和电动汽车
家用电器和工业自动化 SMPS
备用和辅助电源
–
–
–
器件温度等级 1：–40°C 至 +125°C
器件 HBM 分类等级 2：±2kV
器件 CDM 分类等级 C4B：±750V
3 说明
•
•
•
实现零功耗 (< 5 mW) 待机功耗
UCC28730-Q1 隔离式反激电源控制器无需使用光耦合
器即可提供恒压 (CV) 和恒流 (CC) 输出调节。最小开
关频率 30Hz 可促进实现低于 5mW 的无负载功耗。此
器件处理来自一次侧电源开关和辅助反激式绕组的信
息，以对输出电压和电流进行精确控制。
一次侧调节 (PSR) 功能免除了对光耦合器的需求
具有由线路和负载产生±5% 电压和电流变化的调节
能力
•
•
•
•
•
700V 启动开关
83kHz最大开关频率，支持低待机功耗充电器设计
针对最高总体效率的谐振环谷值开关运行
具有频率抖动特性，确保符合 EMI 标准
其内部的 700V 启动开关、动态可控的工作状态和定制
的调制方式支持超低待机功耗，而不会影响启动时间或
输出瞬态响应。UCC28730-Q1 中的控制算法允许工作
效率达到或超过适用标准。带有谷值开关的断续传导模
式 (DCM) 降低了开关损耗。调制开关频率和一次侧峰
值电流振幅（FM 和 AM）可在整个负载和线路范围内
保持高转换效率。
针对金属氧化物半导体场效应晶体管 (MOSFET) 的
已钳制栅极驱动输出
•
•
•
过压、欠压和过流保护功能
可编程电缆补偿
小外形尺寸集成电路 (SOIC)-7 封装
器件信息(1)
器件型号
封装
SOIC (7)
封装尺寸（标称值）
UCC28730-Q1
4.90mm x 3.90mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
无负载时零功耗
简化电路原理图
VBULK
VOUT
IOUT
NP
NS
VSEC
CB1
CB2
UCC24650
COUT
5.1 V +/-5% Cout = 540 mF
5
3
1
2
WAKE VDD
VAC
RPL
ENS GND
DS
Input
Voltage
No-load
Input Power
UCC28730-Q1
DA
115 VRMS
230 VRMS
3.0 mW
3.5 mW
VAUX
NA
1
VDD HV
7
CVDD
M1
RS1
2-A Load Step
DRV
6
5
RLC
2
3
VS
CS
CBC
GND
RS2
RCBC
RCS
4
Switching Pulses
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSCR9
UCC28730-Q1
ZHCSGD9 –JUNE 2017
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 21
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application ................................................. 22
8.3 Do's and Don'ts ...................................................... 33
Power Supply Recommendations...................... 33
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements ............................................... 6
6.7 Switching Characteristics.......................................... 6
6.8 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................. 10
10 Layout................................................................... 34
10.1 Layout Guidelines ................................................. 34
10.2 Layout Example .................................................... 34
11 器件和文档支持 ..................................................... 35
11.1 器件支持................................................................ 35
11.2 文档支持................................................................ 37
11.3 接收文档更新通知 ................................................. 37
11.4 社区资源................................................................ 37
11.5 商标....................................................................... 37
11.6 静电放电警告......................................................... 37
11.7 Glossary................................................................ 37
12 机械、封装和可订购信息....................................... 38
7
4 修订历史记录
日期
修订版本
注意
2017 年 6 月
*
初始发行版
2
Copyright © 2017, Texas Instruments Incorporated
UCC28730-Q1
www.ti.com.cn
ZHCSGD9 –JUNE 2017
5 Pin Configuration and Functions
D Package
7-Pin SOIC
Top View
VDD
VS
1
2
3
4
7
HV
CBC
GND
6
5
DRV
CS
Pin Functions(1)
PIN
I/O
DESCRIPTION
NAME
NO.
VDD is the bias supply input pin to the controller. A carefully-placed by-pass capacitor to
GND is required on this pin.
VDD
1
P
Voltage Sense is an input used to provide voltage feed-back and demagnetization timing to
the controller for output voltage regulation, frequency limiting, constant-current control, line
voltage detection, and output over-voltage detection. This pin is connected to a voltage
divider between an auxiliary winding and GND. The value of the upper resistor of this divider
is used to program the AC-mains run and stop thresholds and line compensation at the CS
pin. This input also detects a qualified wake-up signal when operating in the Wait state.
VS
2
I
CaBle Compensation is a programming pin for compensation of cable voltage drop. Cable
compensation is programmed with a resistor to GND.
CBC
GND
3
4
I
The GrouND pin is both the reference pin for the controller and the low-side return for the
drive output. Special care should be taken to return all AC decoupling capacitors as close as
possible to this pin and avoid any common trace length with power and signal return paths.
G
Current Sense input connects to a ground-referenced current-sense resistor in series with
the power switch. The resulting voltage is used to monitor and control the peak primary
current. A series resistor can be added to this pin to compensate the peak switch current
levels as the rectified bulk voltage varies.
CS
5
I
DRiVe is an output used to drive the gate of an external high-voltage MOSFET switching
transistor.
DRV
HV
6
7
O
I
The High Voltage pin connects directly to the rectified bulk voltage and provides charge to
the VDD capacitor for start-up of the power supply.
(1) P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output
Copyright © 2017, Texas Instruments Incorporated
3
UCC28730-Q1
ZHCSGD9 –JUNE 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
HV
700
VDD
38
V
Voltage
VS
–0.75
–0.5
–0.5
7
V
CS, CBC
5
Self-limiting
50
V
DRV
V
DRV, continuous sink
DRV, source
VS, peak, 1% duty-cycle
mA
mA
mA
°C
°C
Current
Self-limiting
–1.2
Lead temperature 0.6 mm from case for 10 seconds
Storage temperature, Tstg
–65
150
260
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
9
NOM
MAX
UNIT
V
VVDD
CVDD
RCBC
IVS
Bias-supply operating voltage
VDD by-pass capacitor
35
0.047
10
µF
Cable-compensation resistance
VS pin current, out of pin
kΩ
mA
°C
1
TJ
Operating junction temperature
–40
125
6.4 Thermal Information
UCC28730-Q1
D (SOIC)
7 PINS
128.0
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
59.3
66.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
17.0
ψJB
65.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017, Texas Instruments Incorporated
UCC28730-Q1
www.ti.com.cn
ZHCSGD9 –JUNE 2017
6.5 Electrical Characteristics
over operating free-air temperature range, VVDD = 25 V, HV = open, RCBC = open, TA = -40°C to 125°C (unless otherwise
noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
HIGH-VOLTAGE START-UP
IHV
Start-up current out of VDD
Leakage current into HV
VHV = 100 V, VVDD = 0 V, start state
VHV = 400 V, run state, TJ = 25°C
100
250
500
0.5
µA
µA
IHVLKG25
0.01
BIAS SUPPLY INPUT CURRENT
IRUN
Supply current, run
Supply current, wait
Supply current, start
Run state, IDRV = 0 A
2.1
52
18
2.65
75
mA
µA
µA
IWAIT
ISTART
Wait state, IDRV = 0 A, VVDD = 20 V
Start state, IDRV = 0 A, VVDD = 18 V,
IHV = 0 A
30
IFAULT
Supply current, fault
Fault state, IDRV = 0 A
54
75
µA
UNDER-VOLTAGE LOCKOUT
VVDD(on)
VVDD(off)
VDD turn-on threshold
VDD turn-off threshold
VVDD low to high
VVDD high to low
17.5
7.3
21
23
V
V
7.7
8.1
VS Input and Wake-Up Monitor
VVSR
Regulating level(1)
Measured at no-load condition, TJ =
25°C
4.00
4.04
4.08
V(1)
VVSNC
Negative clamp level below GND
Input bias current
IVSLS = –300 µA
VVS = 4 V
190
250
0
325
mV
µA
IVSB
–0.25
0.25
VWU(high)
VWU(low)
CS INPUT
VCST(max)
VCST(min)
KAM
Wake-up threshold at VS, high(2)
VS pin rising
VS pin rising
2
V(2)
Wake-up threshold at VS, low
15
57
105
mV
CS maximum threshold voltage(3)
CS minimum threshold voltage
VVS = 3.7 V
710
230
740
249
770
270
mV(3)
mV
VVS = 4.35 V
AM control ratio, VCST(max)
VCST(min)
/
2.75
2.99
3.20
V/V
VCCR
KLC
Constant-current regulation factor
310
24
319
329
28
mV
A/A
Line compensation current ratio,
IVSLS / current out of CS pin
IVSLS = –300 µA
25.3
DRIVER
IDRS
DRV source current
VDRV = 8 V, VVDD = 9 V
IDRV = 10 mA
20
29
6
35
12
mA
Ω
RDRVLS
VDRCL
RDRVSS
DRV low-side drive resistance
DRV clamp voltage
VVDD = 35 V
13
14.5
190
16
V
DRV pull-down in start state
150
230
kΩ
(1) The regulating level and OV threshold at VS decrease with increasing temperature by 1 mV/°C. This compensation over temperature is
included to reduce the variances in power supply output regulation and over-voltage detection with respect to the external output
rectifier.
(2) Designed for accuracy within ±10% of typical value.
(3) These threshold voltages represent average levels. This device automatically varies the current sense thresholds to improve EMI
performance.
Copyright © 2017, Texas Instruments Incorporated
5
UCC28730-Q1
ZHCSGD9 –JUNE 2017
www.ti.com.cn
Electrical Characteristics (continued)
over operating free-air temperature range, VVDD = 25 V, HV = open, RCBC = open, TA = -40°C to 125°C (unless otherwise
noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
PROTECTION
VOVP
Over-voltage threshold(1)
At VS input, TJ = 25°C
4.52
1.4
4.62
1.5
225
80
4.71
1.6
V(1)
V
VOCP
Over-current threshold
At CS input
IVSL(run)
IVSL(stop)
KVSL
VS line-sense run current
VS line-sense stop current
Current out of VS pin increasing
Current out of VS pin decreasing
190
70
275
100
3.05
µA
µA
A/A
VS line-sense ratio, IVSL(run)
IVSL(stop)
/
2.45
2.8
TJ(stop)
Thermal shut-down temperature
Internal junction temperature
Voltage at CBC at full load
165
°C
CABLE COMPENSATION
VCBC(max) Cable compensation output
2.9
3.13
–15
3.5
20
V
maximum voltage
VCVS(min)
Minimum compensation at VS
VCBC = open, change in VS
regulating level from no load to full
load
–50
mV
VCVS(max)
Maximum compensation at VS
VCBC = 0 V, change in VS regulating
level from no load to full load
275
325
375
mV
6.6 Timing Requirements
MIN
7.0
NOM
8.5
MAX
11.0
280
2.9
UNIT
µs
tWUDLY
tCSLEB
tZTO
Wake-up qualification delay, VVS = 0 V
Leading-edge blanking time , DRV output duration, VCS = 1 V
Zero-crossing timeout delay, no zero-crossing detected
170
1.6
225
2.2
ns
µs
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Maximum switching frequency(1)
TEST CONDITIONS
MIN
76.0
25
TYP
83.3
32
MAX
90.0
37
UNIT
kHz
Hz
fSW(max)
fSW(min)
VVS = 3.7 V
Minimum switching frequency
VVS = 4.35 V
(1) These frequency limits represent average levels. This device automatically varies the switching frequency to improve EMI performance.
6
版权 © 2017, Texas Instruments Incorporated
UCC28730-Q1
www.ti.com.cn
ZHCSGD9 –JUNE 2017
6.8 Typical Characteristics
VVDD = 25 V, TJ = 25°C, unless otherwise noted.
10000
5000
10000
1000
100
10
2000
1000
500
é VDD Turn-Off
å VDD Turn-On
200
100
50
20
10
5
2
1
0.5
1
Start state
Run State
Wait state
Run state, VDD = 25 V
Wait state, VDD = 20 V
Start state, VDD = 18 V
0.2
0.1
0.1
0
5
10
15
20
25
30
35
-50
-25
0
25
50
75
100
125
150
VDD - Bias Supply Voltage (V)
Temperature (°C)
D001
D002
IHV = 0 A
IDRV = 0 A
IHV = 0 A
IDRV = 0 A
图 1. Bias Supply Current vs. Bias Supply Voltage
图 2. Bias Supply Current vs. Temperature
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
500
HV = 400 V
HV = 700 V
HV = 100 V
450
400
350
300
250
200
150
100
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
D004
D003
VVDD = 25 V
VVDD = 0 V
图 3. HV Start-up Current vs. Temperature
图 4. HV Leakage Current vs. Temperature
300
275
250
225
200
175
150
125
100
75
5
4.8
4.6
4.4
4.2
4
VOVP Overvoltage Threshold
VVSR Regulation Reference
Run Threshold
Stop Threshold
50
3.8
3.6
25
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
D005
D006
图 5. VS Line-Sense Current vs. Temperature
图 6. VS Voltages vs. Temperature
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7
UCC28730-Q1
ZHCSGD9 –JUNE 2017
www.ti.com.cn
Typical Characteristics (接下页)
VVDD = 25 V, TJ = 25°C, unless otherwise noted.
260
258
256
254
252
250
248
246
244
242
240
322
321
320
319
318
317
316
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
D008
D007
图 8. CS Minimum Threshold Voltage vs. Temperature
图 7. Constant-Current Regulation Factor vs. Temperature
37
36
35
34
33
32
31
30
29
28
27
26
25
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
D009
D010
VVS = 4.35 V
VVDD = 9 V
VDRV = 8 V
图 9. Minimum Switching Frequency vs. Temperature
图 10. DRV Source Current vs. Temperature
11
10
9
100
90
80
70
60
50
40
30
20
8
7
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
D012
Temperature (°C)
D011
VVS = 0 V
图 12. Wake-Up Qualification Delay Time vs. Temperature
图 11. Wake-Up Lower Threshold Voltage vs. Temperature
8
版权 © 2017, Texas Instruments Incorporated
UCC28730-Q1
www.ti.com.cn
ZHCSGD9 –JUNE 2017
7 Detailed Description
7.1 Overview
The UCC28730-Q1 is an isolated-flyback power supply controller which provides accurate voltage and constant
current regulation using primary-side winding sensing, eliminating the need for opto-coupler feedback circuits.
The controller operates in discontinuous conduction mode with valley switching to minimize switching losses. The
modulation scheme is a combination of frequency modulation and primary peak-current modulation to provide
high conversion efficiency across the load range. The control law provides a wide dynamic operating range of
output power which facilitates the achievement of <5-mW stand-by power.
During low-power operating levels the device has power management features to reduce the device operating
current at switching frequencies less than 28 kHz. The UCC28730-Q1 includes features in the pulse-width
modulator to reduce the EMI peak energy at the fundamental switching frequency and its harmonics. Accurate
voltage and current regulation, fast dynamic response, and fault protection are achieved with primary-side
control. A complete charger solution can be realized with a straightforward design process, low cost, and low
component-count.
7.2 Functional Block Diagram
IHV
VDD
GND
1
4
7
HV
OC FAULT
OV FAULT
POWER
& FAULT
MANAGEMENT
UVLO
21 V / 7.7 V
LINE UVLO
INTERNAL
BIAS
WAIT
WAKE
WAKE SIGNAL
DETECTION
VDD
4.04 V + VCVS
+
VCL
29 mA
CONTROL
LAW
E/A
VS
2
VCST
6
5
DRV
14.5 V
SAMPLER
+
OV FAULT
VOVP
1 / fSW
VALLEY
SWITCHING
S
R
Q
Q
SECONDARY
TIMING
DETECT
CS
+
CURRENT
REGULATION
VCST
LEB
CABLE
COMPENSATION
VCVS
= ICBC
0 V to VCBC(max)
+
x 3 kÈ
28 kÖ
ICBC
CBC
3
IVSLS
LINE
IVSLS / KLC
IVSLS
SENSE
LINE UVLO
+
+
10 kÖ
OC FAULT
1.5 V
2.25 V / 0.8 V
Copyright © 2017, Texas Instruments Incorporated
版权 © 2017, Texas Instruments Incorporated
9
UCC28730-Q1
ZHCSGD9 –JUNE 2017
www.ti.com.cn
7.3 Feature Description
7.3.1 Detailed Pin Description
7.3.1.1 VDD (Device Bias Voltage Supply)
The VDD pin connects to a by-pass capacitor to ground. The turn-on UVLO threshold is 21 V and turn-off UVLO
threshold is 7.7 V with an available operating range up to 35 V on VDD. The typical USB charging specification
requires the output current to operate in Constant-Current mode from 5 V down to at least 2 V, which is easily
achieved with a nominal VVDD of approximately 20 V. The additional VDD headroom up to 35 V allows for VVDD to
rise due to the leakage energy delivered to the VDD capacitor during high-load conditions.
7.3.1.2 GND (Ground)
UCC28730-Q1 has a single ground reference external to the device for the gate-drive current and analog signal
reference. Place the VDD-bypass capacitor close to GND and VDD with short traces to minimize noise on the VS
and CS signal pins.
7.3.1.3 HV (High Voltage Startup)
The HV pin connects directly to the bulk capacitor to provide startup current to the VDD capacitor. The typical
startup current is approximately 250 µA which provides fast charging of the VDD capacitor. The internal HV
startup device is active until VVDD exceeds the turn-on UVLO threshold of 21 V at which time the HV startup
device turns off. In the off state the HV leakage current is very low to minimize stand-by losses of the controller.
When VVDD falls below the 7.7-V UVLO turn-off threshold the HV startup device turns on.
7.3.1.4 DRV (Gate Drive)
The DRV pin connects to the MOSFET gate pin, usually through a series resistor. The gate driver provides a
gate-drive signal limited to 14 V. The turn-on characteristic of the driver is a 29-mA current source which limits
the turn-on dv/dt of the MOSFET drain and reduces the leading-edge current spike, while still providing a gate-
drive current to overcome the Miller plateau. The gate-drive turn-off current is determined by the RDS(on) of the
low-side driver and any external gate drive resistance. Adding external gate resistance reduces the MOSFET
drain turn-off dv/dt, if necessary. Such resistance value is generally higher than the typical 10 Ω commonly used
to damp resonance. However, calculation of the external resistance value to achieve a specific dv/dt involves
MOSFET parameters beyond the scope of this datasheet.
7.3.1.5 CBC (Cable Compensation)
The cable compensation pin is connected to a resistor to ground to program the amount of output voltage
compensation needed to offset cable resistance. The cable compensation circuit generates a 0 to 3.13-V voltage
level on the CBC pin corresponding to 0 A to IOCC maximum output current. The resistance selected on the CBC
pin programs a current mirror that is summed into the VS feedback divider therefore increasing the regulation
voltage as IOUT increases. There is an internal series resistance of 28 kΩ to the CBC pin which sets a maximum
cable compensation for a 5-V output to approximately 400 mV when CBC is shorted to ground. The CBC
resistance value can be determined using 公式 1.
: ;
#"# (≠°∏ ) × 6/#6 + 6& × 3 ´3
6
2#"#
=
F ꢁ8 ´3
66ꢀ2 × 6/#"#
where
•
VCBC(max) is the maximum voltage at the cable compensation pin at the maximum converter output current (see
Electrical Characteristics),
•
•
•
•
VOCV is the regulated output voltage,
VF is the diode forward voltage,
VVSR is the CV regulating level at the VS input (see Electrical Characteristics),
VOCBC is the target cable compensation voltage at the output terminals.
(1)
Note that the cable compensation does not change the overvoltage protection (OVP) threshold, VOVP (see
Electrical Characteristics), so the operating margin to OVP is less when cable compensation is used.
10
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Feature Description (接下页)
7.3.1.6 VS (Voltage Sense)
The VS pin connects to a resistor-divider from the auxiliary winding to ground and is used to sense input voltage,
output voltage, event timing, and Wait-state wake-up signaling. The auxiliary voltage waveform is sampled at the
end of the transformer secondary current demagnetization time to provide an accurate representation of the
output voltage. The waveform on the VS pin determines the timing information to achieve valley-switching, and
the timing to control the duty-cycle of the transformer secondary current when in Constant-Current Mode. Avoid
placing a filter capacitor on this input which interferes with accurate sensing of this waveform.
During the MOSFET on-time, this pin also senses VS current generated through RS1 by the reflected bulk-
capacitor voltage to provide for AC-input Run and Stop thresholds, and to compensate the current-sense
threshold across the AC-input range. For the AC-input Run/Stop function, the Run threshold on VS is 225 µA and
the Stop threshold is 80 µA.
At the end of off-time demagnetization, the reflected output voltage is sampled at this pin to provide regulation
and overvoltage protection. The values for the auxiliary voltage-divider upper-resistor, RS1, and lower-resistor,
RS2, are determined by 公式 2 and 公式 3.
ꢀ × 6
¾
).(≤µÆ ꢁ
231
=
.
× )63, (≤µÆ ꢁ
0!
where
•
VIN(run) is the target AC RMS voltage to enable turn-on of the controller (Run) (in case of DC input, leave out
the √2 term in the equation),
•
•
IVSL(run) is the Run-threshold for the current pulled out of the VS pin during the switch on-time (see Electrical
Characteristics),
NPA is the transformer primary-to-auxiliary turns-ratio.
(2)
231 × 6632
: ;
× 6/#6 + 6& F 6632
23ꢀ
=
.
!3
where
•
•
•
•
•
VOCV is the converter regulated output voltage,
VF is the output rectifier forward drop at near-zero current,
NAS is the transformer auxiliary-to-secondary turns-ratio,
RS1 is the VS divider high-side resistance,
VVSR is the CV regulating level at the VS input (see Electrical Characteristics).
(3)
When the UCC28730-Q1 is operating in the Wait state, the VS input is receptive to a wake-up signal
superimposed upon the auxiliary winding waveform after the waveform meets either of two qualifying conditions.
A high-level wake-up signal is considered to be detected if the amplitude at the VS input exceeds VWU(high) (2 V)
provided that any voltage at VS has been continuously below VWU(high) for the wake-up qualification delay tWDLY
(8.5 us) after the demagnetization interval. A low-level wake-up signal is considered to be detected if the
amplitude at the VS input exceeds VWU(low) (57 mV) provided that any voltage at VS has been continuously below
VWU(low) for the wake-up qualification delay tWDLY (8.5 us) after the demagnetization interval. The high-level
threshold accommodates signals generated by a low-impedance secondary-side driver while the low-level
threshold detects signals generated by a high-impedance driver.
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Feature Description (接下页)
7.3.1.7 CS (Current Sense)
The current-sense pin connects to a series resistor (RLC) to the current-sense resistor (RCS). The maximum
current-sense threshold (VCST(max)) is approximately 0.74 V for IPP(max) and minimum current-sense threshold
(VCST(min)) is approximately 0.25 V for IPP(min). RLC provides the function of feed-forward line compensation to
eliminate changes in IPP with input voltage due to the propagation delay of the internal comparator and MOSFET
turn-off time. An internal leading-edge blanking time of 225 ns eliminates sensitivity to the MOSFET turn-on
current spike. It should not be necessary to place a bypass capacitor on the CS pin. The target output current in
constant-current (CC) regulation determines the value of RCS. The values of RCS and RLC are calculated by 公式
4 and 公式 5. The term VCCR is the product of the demagnetization constant, 0.432, and VCST(max). VCCR is held
to a tighter accuracy than either of its constituent terms. The term ηXFMR accounts for the energy stored in the
transformer but not delivered to the secondary. This term includes transformer resistance and core loss, bias
power, and primary-to-secondary leakage ratio.
Example: With a transformer core and winding loss of 5%, primary-to-secondary leakage inductance of 3.5%,
and bias-power to output-power ratio of 0.5%, the ηXFMR value at full-power is: 1 - 0.05 - 0.035 - 0.005 = 0.91.
6##2 × .03
2#3
=
× D
¥
8&-2
ꢀ × )/##
where
•
•
•
•
VCCR is a constant-current regulation factor (see Electrical Characteristics),
NPS is the transformer primary-to-secondary turns-ratio, (a ratio of 13 to 15 is typical for a 5-V output),
IOCC is the target output current in constant-current regulation,
ηXFMR is the transformer efficiency at full-power output.
(4)
+
× 231 × 2#3 × .0! × ¥$
,#
2,#
=
,
0
where
•
•
•
•
•
KLC is a current-scaling constant for line compensation (see Electrical Characteristics),
RS1 is the VS pin high-side resistor value,
RCS is the current-sense resistor value,
NPA is the transformer primary-to-auxiliary turns-ratio,
tD is the total current-sense delay consisting of MOSFET turn-off delay, plus approximately 50-ns internal
delay,
•
LP is the transformer primary inductance.
(5)
7.3.2 Primary-Side Regulation (PSR)
图 13 illustrates a simplified isolated-flyback convertor with the main voltage regulation blocks of the device
shown. The power train operation is the same as any DCM flyback circuit but accurate output voltage and current
sensing is the key to primary-side control. The output voltage is sensed as a reflected voltage during the
transformer demagnetization time using a divider network at the VS input. The primary winding current is sensed
at the CS input using a current-sense resistor, RCS
.
12
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Feature Description (接下页)
+ VF
-
VBULK
VOUT
COUT
+
Timing
VCL
Primary
Secondary
RLOAD
íave-shape
5iscriminator,
{ampler &
Auxiliary
RS1
RS2
VS
D5
DRV
Control
Law
–
9rror !mplifier
Switching
Period
CS
And Peak
Current
Control
RCS
ùero /rossing
5etector
ZCD
íake {ignal
5etector
WAKE
图 13. Simplified Flyback Convertor (with the main voltage regulation blocks)
In primary-side control, the output voltage is indirectly sensed on the auxiliary winding at the end of the transfer
of stored transformer energy to the secondary. As shown in 图 14 it is clear there is a down slope representing a
decreasing total rectifier VF and resistance voltage drop as the secondary current decreases to zero. To achieve
an accurate representation of the secondary output voltage on the auxiliary winding, the discriminator reliably
blocks the leakage inductance reset and ringing, continuously samples the auxiliary voltage during the down
slope after the ringing is diminished, and captures the error signal at the time the secondary winding reaches
zero current. The internal reference on VS is 4.04 V. Temperature compensation on the VS reference voltage of
-1 mV/°C offsets the change in the forward voltage of the output rectifier with temperature. The resistor divider is
selected as outlined in the VS pin description.
VS Sample
(VOUT + VF) NAS
0 V
-VBULK / NPA
图 14. Auxiliary Winding Voltage
The UCC28730-Q1 VS-signal sampler includes signal discrimination methods to ensure an accurate sample of
the output voltage from the auxiliary winding. There are, however, some details of the auxiliary winding signal
which require attention to ensure reliable operation, specifically the reset time of the leakage inductance and the
duration of any subsequent leakage inductance ring. Refer to 图 15 below for a detailed illustration of waveform
criteria to ensure a reliable sample on the VS pin.
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Feature Description (接下页)
tLK_RESET
tSMPL
VS ring (p-p)
0 V
tDM
图 15. Auxiliary Waveform Details
The first detail to examine is the duration of the leakage inductance reset pedestal, tLK_RESET in 图 15. Since this
can mimic the waveform of the secondary current decay, followed by a sharp downslope, it is important to keep
the leakage reset time to less than 750 ns for IPRI minimum, and to less than 2.25 µs for IPRI maximum.
The second detail is the amplitude of ringing on the VAUX waveform following tLK_RESET. The peak-to-peak voltage
at the VS pin should be less than 125 mV for at least 200 ns before the end of the demagnetization time, tDM. If
there is a concern with excessive ringing, it usually occurs during light-load or no-load conditions, when tDM is at
the minimum. To avoid distorting the signal waveform at VS with oscilloscope probe capacitance, it is
recommended to probe the auxiliary winding to view the VS waveform characteristics. The tolerable ripple on VS
is scaled up to the auxiliary-winding voltage by RS1 and RS2, and is equal to 125 mV x (RS1 + RS2) / RS2.
14
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Feature Description (接下页)
7.3.3 Primary-Side Constant Voltage Regulation
During voltage regulation, the controller operates in frequency modulation and amplitude modulation modes
according to the control law as illustrated in 图 16 below. The control law voltage VCL reflects the internal
operating level based on the voltage-error amplifier output signal. Neither of these signals is accessible to the
user, however the approximate VCL may be inferred from the frequency and amplitude of the current sense signal
at the CS input. As the line and load conditions vary, VCL adjusts the operating frequency and amplitude as
required to maintain regulation of the output voltage. Because the UCC28730-Q1 incorporates internal loop
compensation, no external stability compensation is required.
The internal operating frequency limits of the device are fSW(max) and fSW(min), typically 83.3 kHz and 32 Hz,
respectively. The choice of transformer primary inductance and primary-peak current sets the maximum
operating frequency of the converter, which must be equal to or lower than fSW(max). Conversely, the choice of
maximum target operating frequency and primary-peak current determines the transformer primary-inductance
value. The actual minimum switching frequency for any particular converter depends on several factors, including
minimum loading level, leakage inductance losses, switched-node capacitance losses, other switching and
conduction losses, and bias-supply requirements. In any case, the minimum steady-state frequency of the
converter must always exceed fSW(min) or the output voltage may rise to the overvoltage protection level (OVP)
and the controller responds as described in the Fault Protection Section.
The steady-state Control-Law voltage, VCL, ranges between 1.3 to 4.85 V, depending on load, but may
occasionally move below 0.75 V or above 4.85 V on load transients. Dropping below 0.75 V shifts the switching
frequency to a lower range at light loads, while exceeding 4.85 V enters the constant-current mode of operation.
There are 3 lower operating frequency ranges for progressively lighter loads, each overlapping the previous
range to some extent, to provide stable regulation at very low frequencies. Peak-primary current is always
maintained at IPP(max)/3 in these lower frequency levels. Transitions between levels is automatically accomplished
by the controller depending on the internal control-law voltage, VCL
.
Control-Law Profile in Constant-Voltage (CV) Mode
IPP(max)
IPP
83.3 kHz
fSW
FM
AM
FM
IPP(max) / 3
28 kHz
fSW(min)
=
32 Hz
Light-Load
Operating Levels
1.92 kHz
0 V
0.75 V 1.3 V
2.2 V
3.55 V
4.85 V 5 V
Control-Law Voltage, Internal - VCL
图 16. Frequency and Amplitude Modulation Modes (during voltage regulation)
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Feature Description (接下页)
7.3.4 Primary-Side Constant Current Regulation
Timing information at the VS pin and current information at the CS pin allow accurate regulation of the secondary
average current. The control law dictates that as power is increased in CV regulation and approaching CC
regulation the primary-peak current will be at IPP(max). Referring to 图 17 below, the primary-peak current, turns
ratio, secondary demagnetization time (tDM), and switching period (tSW) determine the secondary average output
current. Ignoring leakage inductance effects, the average output current is given by 公式 6.
I
S ´ NS
IPP
NP
tON
tDM
tSW
UDG-12203
图 17. Transformer Currents Relationship
)
.
¥
¥
00
0
$-
37
)
=
×
×
/54
2
.
3
(6)
When the average output current reaches the CC regulation reference in the current control block, the controller
operates in frequency modulation mode to control the output current, IOCC, at any output voltage down to or
below the minimum operating voltage target, VOCC (as seen in 图 18), as long as the auxiliary winding can keep
VDD voltage above the UVLO turn-off threshold. When VO falls so low that VDD cannot be sustained above
UVLO, the device shuts down.
图 18. Typical Output V-I Target Characteristic
16
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Feature Description (接下页)
7.3.5 Wake-Up Detection and Function
A major feature available at the VS pin is the wake-up function which operates in conjunction with a companion
secondary-side wake-up device, such as the UCC24650. This feature allows light-load and no-load switching
frequencies to approach 32 Hz to minimize losses, yet wake the UCC28730-Q1 from its wait state (sleep mode)
in the event of a significant load step between power cycles. Despite the low frequencies, excessive output
capacitance is not required to maintain reasonable transient response. While in the wait state, the UCC28730-Q1
continually monitors the VS input for a wake-up signal, and when detected, responds immediately with several
high-frequency power cycles and resumes operation as required by the control law to recover from the load-step
transient and restore output voltage regulation.
Because the wake-up feature interrupts the wait state between very low frequency switching cycles, it allows the
use of a much lower output capacitance value than would be required to hold up the voltage without the wake-up
function. It also allows the controller to drop to extremely low switching frequencies at no-load conditions to
minimize switching losses. This facilitates the achievement of less than 5 mW of input power to meet zero-power
stand-by requirements. Use of the UCC28730-Q1 controller alone cannot ensure zero-power operation since
other system-level limitations are also imposed, however, the UCC28730-Q1 and UCC24650 combination goes a
long way to reaching this goal.
Heavy Load Step
IOUT
VNOM
Wake Threshold
VOUT
IWAKE
Wake-up pulse generated by
sinking current out of VSEC
VSEC
VAUX
VS
Wake-up signal detected by primary
controller; switching initiated
图 19. Simplified Wake-Up Operation and Waveforms
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Feature Description (接下页)
The
signals
illustrated
in
图
19
refer
to
circuit
nodes
located
on
the
简化电路原理图 diagram on the first page of this datasheet. The wake-up signal, which is provided by a
secondary-side driver, must meet certain criteria to be considered valid and recognized by the UCC28730-Q1 at
the VS input. To distinguish the signal from the residual resonant ringing that follows a switching power cycle, the
resonant ringing amplitude must diminish and remain below the wake-up signal detection threshold, VWU, for a
fixed qualification time, tWUDLY
.
The UCC28730-Q1 has two such thresholds; one at VWU(low) and one at VWU(high). The lower VWU(low) threshold is
used by converters which incorporate a relatively high-impedance driver for the wake-up signal, while the upper
VWU(high) threshold may be used in converters with a low-impedance wake-up driver. Both thresholds work exactly
the same way. The advantage of the upper threshold is that the UCC28730-Q1 is qualified to accept a strong
wake-up signal without waiting additional time for the resonant ringing to diminish below the lower threshold.
图 20 illustrates the qualification delay period and wake-up response to a low-level wake-up signal. 图 21
illustrates the qualification delay period and wake-up response to a high-level wake-up signal.
Low-Level
Wake-Up Pulse
VVS
VWU(low)
0 V
tWUDLY
t
图 20. Wake-Up Qualification Criteria and Wake-Up Response with Low Wake-Up Signal
High-Level
Wake-Up Pulse
VVS
VWU(high)
0 V
tWUDLY
t
图 21. Wake-Up Qualification Criteria and Wake-Up Response with High Wake-Up Signal
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Feature Description (接下页)
7.3.6 Valley-Switching and Valley-Skipping
The UCC28730-Q1 utilizes valley-switching to reduce switching losses in the MOSFET, to reduce induced-EMI,
and to minimize the turn-on current spike at the current-sense resistor. The controller operates in valley-switching
in all load conditions unless the VDS ringing is diminished to the point where valleys are no longer detectable.
As shown in 图 22, the UCC28730-Q1 operates in a valley-skipping mode (also known as valley-hopping) in
most load conditions to maintain an accurate voltage or current regulation point and still switch on the lowest
available VDS voltage.
VDS
VDRV
图 22. Valley-Skipping Mode
Valley-skipping modulates each switching cycle into discrete period durations. During FM operation, the
switching cycles are periods when energy is delivered to the output in fixed packets, and the power delivered
varies inversely with the switching period. During operating conditions when the switching period is relatively
short, such as at high-load and low-line, the average power delivered per cycle varies significantly based on the
number of valleys skipped between cycles. As a consequence, valley-skipping adds additional low-amplitude
ripple voltage to the output with a frequency dependent upon the rate of change of the bulk voltage. For a load
with an average power level between that of cycles with fewer valleys skipped and cycles with more valleys
skipped, the voltage-control loop modulates the control law voltage and toggles between longer and shorter
switching periods to match the required average output power.
7.3.7 Startup Operation
An internal high-voltage startup switch, connected to the bulk capacitor voltage (VBULK) through the HV pin,
charges the VDD capacitor. This startup switch functions similarly to a current source providing typically 250 µA
to charge the VDD capacitor. When VVDD reaches the 21-V UVLO turn-on threshold, the controller is enabled, the
converter starts switching, and the startup switch turns off.
At initial turn-on, the output capacitor is often in a fully-discharged state. The first 4 switching-cycle current peaks
are limited to IPP(min) to monitor for any initial input or output faults with limited power delivery. After these 4
cycles, if the sampled voltage at VS is less than 1.32 V, the controller operates in a special startup mode. In this
mode, the primary-current-peak amplitude of each switching cycle is limited to approximately 0.67 x IPP(max) and
DMAGCC increases from 0.432 to 0.650. These modifications to IPP(max) and DMAGCC during startup allow high-
frequency charge-up of the output capacitor to avoid audible noise while the demagnetization voltage is low.
Once the sampled VS voltage exceeds 1.36 V, DMAGCC is restored to 0.432 and the primary-current peak
resumes as IPP(max). While the output capacitor charges, the converter operates in CC mode to maintain a
constant output current until the output voltage enters regulation. Thereafter, the controller responds to conditions
as dictated by the control law. The time to reach output regulation consists of the time the VDD capacitor
charges to VVDD(on) plus the time the output capacitor charges.
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Feature Description (接下页)
7.3.8 Fault Protection
The UCC28730-Q1 provides comprehensive fault protection. The protection functions include:
1. Output Overvoltage
2. Input Undervoltage
3. Internal Overtemperature
4. Primary Overcurrent fault
5. CS-pin Fault
6. VS-pin Fault
A UVLO reset and restart sequence applies to all fault-protection events.
The output-overvoltage function is determined by the voltage feedback on the VS pin. If the voltage sample of VS
exceeds 4.6 V for three consecutive switching cycles, the device stops switching and the internal current
consumption becomes IFAULT which discharges the VDD capacitor to the UVLO-turn-off threshold. After that, the
device returns to the start state and a start-up sequence ensues.
Current into the VS pin during the MOSFET on time determines the line-input run and stop voltages. While the
VS pin clamps close to GND during the MOSFET on time, the current through RS1 is monitored to determine a
sample of VBULK. A wide separation of the run and stop thresholds allows clean start-up and shut-down of the
power supply with line voltage. The run-current threshold is 225 µA and the Stop-current threshold is 80 µA. The
input AC voltage to run at start-up always corresponds to the peak voltage of the rectified line, because there is
no loading on CBULK before start-up. The AC input voltage to stop varies with load since the minimum VBULK
depends on the loading and the value of CBULK. At maximum load, the stop voltage is close to the run voltage,
but at no-load condition the stop voltage can be approximately 1/3 of the run voltage.
The UCC28730-Q1 always operates with cycle-by-cycle primary-peak current control. The normal operating
range of the CS pin is 0.74 to 0.249 V. An additional protection occurs if the CS pin reaches 1.5 V after the
leading-edge blanking interval for three consecutive cycles, which results in a UVLO reset and restart sequence.
Normally at initial start-up, the peak level of the primary current of the first four power cycles is limited to the
minimum VCST(min). If the CS input is shorted or held low such that the VCST(min) level is not reached within 4 µs on
the first cycle, the CS input is presumed to be shorted to GND and the fault protection function results in a UVLO
reset and restart sequence. Similarly, if the CS input is open, the internal voltage is pulled up to 1.5 V for three
consecutive switching cycles and the fault protection function results in a UVLO reset and restart sequence.
The internal overtemperature-protection threshold is 165°C. If the junction temperature reaches this threshold,
the device initiates a UVLO-reset cycle. If the temperature is still high at the end of the UVLO cycle, the
protection cycle repeats.
Protection is included in the event of component failures on the VS pin. If complete loss of feedback information
on the VS pin occurs, the controller stops switching and restarts.
20
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7.4 Device Functional Modes
According to the input voltage, the VDD voltage, and the output load conditions, the device can operate in
different modes:
1. At start-up, when VDD is less than the VVDD(on) turn-on threshold, the HV internal current source is on and
charging the VDD capacitor at a (IHV – ISTART) rate.
2. When VDD exceeds VVDD(on), the HV source is turned Off and the device starts switching to deliver power to
the converter output. Depending on the load conditions, the converter operates in CC mode or CV mode.
1. CC mode means that the converter keeps the output current constant. When the output voltage is below
the regulation level, the converter operates in CC mode to restore the output to the regulation voltage.
2. CV mode means that the converter keeps the output voltage constant. When the load current is less than
the current limit level, the converter operates in CV mode to keep the output voltage at the regulation
level over the full load and input line ranges.
3. When operating in CV or CC mode where IPP is greater than 0.55 X IPP(max), the UCC28730-Q1 operates
continuously in the run state. In this state, the VDD bias current is always at IRUN plus the average gate-drive
current.
4. When operating in CV mode where IPP is less than 0.55 X IPP(max), the UCC28730-Q1 operates in the Wait
state between switching cycles and in the run state during a switching cycle. In the Wait state, the VDD bias
current is reduced to IWAIT after each switching cycle to improve efficiency at light loads.
5. The device operation can be stopped by the events listed below:
1. If VDD drops below the VVDD(off) threshold, the device stops switching, its bias current consumption is
lowered to ISTART and the internal HV current source is turned on until VDD rises above the VVDD(on)
threshold. The device then resumes switching.
2. If a fault condition is detected, the device stops switching and its bias current consumption is lowered to
IFAULT. This current level slowly the discharges VDD to VVDD(off) where the bias current changes from
IFAULT to ISTART and the internal HV current source is turned on until VDD rises above the VVDD(on)
threshold.
6. If a fault condition persists, the operation sequence described above in repeats until the fault condition or the
input voltage is removed.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The UCC28730-Q1 device is a PSR controller optimized for isolated-flyback AC-to-DC single-output supply
applications in the 5-W to 25-W range, providing constant-voltage (CV) mode control and constant current (CC)
mode control for precise output regulation. Higher-power, multiple-output applications and other variations may
also be supported. It is capable of switching at a very low frequency to facilitate achieving stand-by input power
consumption of less than 5 mW.
To maintain fast transient response at such low-switching frequencies, the device recognizes a wake-up signal at
the VS input generated by a companion device, the secondary-side voltage monitor UCC24650.
8.2 Typical Application
A typical application for the UCC28730-Q1 includes the compatible UCC24650 Wake-Up Monitor device to
regulate an isolated low-voltage DC output with low output capacitance. When the UCC28730-Q1 is operating in
the low-frequency Wait state, the UCC24650 alerts the UCC28730-Q1 to a sudden load increase, avoiding the
need for extremely high output capacitance to hold up between power cycles. As shown in 图 23, the output
rectification uses a ground-referenced diode to facilitate application of the UCC24650. A ground-referenced
synchronous rectifier may also be used.
注
This figure is simplified to illustrate the basic application of the UCC28730-Q1 and does
not show all of the components and networks needed for an actual converter design, nor
all of the possible circuit variations.
VBULK
VOUT
IOUT
NP
NS
VSEC
CB1
CB2
UCC24650
COUT
5
3
1
2
WAKE VDD
VAC
RPL
ENS GND
DS
UCC28730-Q1
DA
VAUX
NA
1 VDD HV
7
CVDD
M1
RS1
DRV
CS
6
5
RLC
2 VS
3 CBC
GND
RS2
RCBC
RCS
4
Copyright © 2017, Texas Instruments Incorporated
图 23. Simplified Application With Ground-Referenced Diode
22
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Typical Application (接下页)
8.2.1 Design Requirements
The following table illustrates a typical subset of high-level design requirements for a particular converter, of
which many of the parameter values are used in the various design equations in this section.
表 1. Design Example Performance Requirements
PARAMETER
CONDITIONS
MIN
85
NOM
115 / 230
50 / 60
5.0
MAX
264
63
UNITS
VRMS
Hz
VIN
AC-Line Input Voltage
Line Frequency
fLINE
47
VOCV
IOCC
Output Voltage, CV Mode
Output Current, CC Mode
Output Voltage Ripple
Output Over-Voltage Limit
Output Over-Current Limit
Start-Up Input Voltage
Minimum Output Voltage, CC Mode
VIN(min) ≤ VIN ≤ VIN(max), IOUT ≤ IOCC
4.75
2.0
5.25
2.2
V
V
IN(min) ≤ VIN ≤ VIN(max), IOUT = IOCC
2.1
A
VRIPPLE
VIN(min) ≤ VIN ≤ VIN(max), IOUT ≤ IOCC
80
mVpp
V
5.6
2.1
72
A
VIN(run)
VOCC
IOUT = IOCC
IOUT = IOCC
VRMS
V
2
Average of 25%, 50%, 75% 100%
Load, at VIN = 115 VRMS and 230
VRMS
ηAVG
Average Efficiency
80%
75%
At 10 % Load, at VIN = 115 VRMS and
230 VRMS
η10
Light-Load Efficiency
PSTBY
Stand-by Input Power Consumption
At VIN = 115 VRMS and 230 VRMS
4.5
mW
Many other necessary design parameters, such as fMAX and VBULK(min) for example, may not be listed in such a
table. These values may be selected based on design experience or other considerations, and may be iterated to
obtain optimal results.
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8.2.2 Detailed Design Procedure
This procedure outlines the steps to design a constant-voltage, constant-current flyback converter using the
UCC28730-Q1 controller. Refer to 图 23 for component names and network locations. The design procedure
equations use terms that are defined below. The primary-side and secondary-side snubbers or clamps are not
designed in this procedure.
8.2.2.1 Stand-By Power Estimate
The extra-low operating frequency capability and minimal bias power of the UCC28730-Q1, in conjunction with
its companion micro-power wake-up device UCC24650, allow for the achievement of less than 5-mW input
stand-by power consumption under no-load conditions. This is often referred to as zero-power stand-by.
Assuming that no-load stand-by power is a critical design parameter, determine the estimated no-load input
power based on the target maximum switching frequency and the maximum output power. The following
equation estimates the stand-by power of the converter.
6/#6 × )/## × ¶-).
D3" × +!- 2 × ¶-!8
0
34"9
=
(7)
For a typical flyback converter, ηSB may range between 0.5 and 0.7, but the lower factor should be used for an
initial estimate. Also, fMIN should be estimated at 3x to 4x fSW(min) to allow for possible parameter adjustment.
If the PSTBY calculation result is well below 5 mW, there is an excellent chance of achieving zero-power stand-by
in the actual converter. If the result is near 5 mW, some design adjustment to fMAX, fMIN, and ηSB may be needed
to achieve zero-power. If the result is well above 5 mW, there is little chance to achieve zero-power at the target
power level unless additional special circuitry and design effort is applied.
8.2.2.2 Input Bulk Capacitance and Minimum Bulk Voltage
Bulk capacitance may consist of one or more capacitors connected in parallel, often with some inductance
between them to suppress differential-mode conducted noise. EMI filter design is beyond the scope of this
procedure.
Determine the minimum voltage on the input capacitance, CB1 and CB2 total, in order to determine the maximum
NP to NS turns ratio of the transformer. The input power of the converter based on target full-load efficiency,
minimum input RMS voltage, and minimum AC input frequency are used to determine the input capacitance
value.
Maximum input power is used in the CBULK calculation and is determined by the VOCV, IOCC, and full-load
efficiency targets.
6/#6 × )/##
0
).
=
D
(8)
The below equation provides an accurate solution for input capacitance needed to achieve a minimum bulk
valley voltage target VBULK(min), accounting for hold-up during any loss of AC power for a certain number of half-
cycles, NHC, by an AC-line drop-out condition. Alternatively, if a given input capacitance value is prescribed,
iterate the VBULK(min) value until that target capacitance is obtained, which determines the VBULK(min) expected for
that capacitance.
6"5,+ ꢄ≠©Æ ꢅ
1
tN
20 × Lꢀꢁ2ꢂ ꢃ ꢀꢁꢂ .(#
).
ꢃ
× °≤£≥©Æ F
GM
2 × 6
¾
).ꢄ≠©Æ ꢅ
#
"5,+
R
k2 6)2.ꢄ≠©Æ ꢅ F 6"25,+ ꢄ≠©Æ ꢅo × ¶,).%
(9)
24
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ZHCSGD9 –JUNE 2017
8.2.2.3 Transformer Turns Ratio, Inductance, Primary-Peak Current
The maximum primary-to-secondary turns ratio can be determined by the target maximum switching frequency at
full load, the minimum input capacitor bulk voltage, and the estimated DCM quasi-resonant time.
First, determine the maximum duty cycle of the MOSFET based on the target maximum switching frequency,
fMAX, the secondary conduction duty cycle, DMAGCC, and the DCM resonant period, tR. For tR, assume 2 µs (500-
kHz resonant frequency), if you do not have an estimate from experience or previous designs. For the transition
mode operation limit, the time interval from the end of the secondary current conduction to the first resonant
valley of the VDS voltage is ½ of the DCM resonant period, or 1 µs assuming 500 kHz. Actual designs vary. DMAX
can be determined using the equation below.
¥
2
$
-!8
= 1 F $-!'## F l × ¶-!8
p
ꢀ
(10)
DMAGCC is defined as the secondary diode conduction duty cycle during constant current, CC, operation. In the
UCC28730-Q1, it is fixed internally at 0.432. Once DMAX is known, the ideal turns ratio of the primary-to-
secondary windings can be determined with the equation below. The total voltage on the secondary winding
needs to be determined, which is the total of VOCV, the secondary rectifier drop VF, and cable compensation
voltage VOCBC, if used. For 5-V USB charger applications, for example, a turns ratio in the range of 13 to 15 is
typically used.
$
× 6"5,+ (≠©Æ )
-!8
.
=
03(©§•°¨ )
: ;
× 6/#6 ꢀ 6& ꢀ 6/#"#
$
-!'##
(11)
The actual turns ratio depends on the actual number of turns on each of the transformer windings. Choosing NPS
> NPS(ideal) results in an output power limit lower than (VOCV x IOCC) when operating at VIN(min), and line-frequency
ripple may appear on VOUT. Choosing NPS < NPS(ideal) allows full-power regulation down to VIN(min), but increases
conduction losses and the reverse voltage stress on the output rectifier.
Once the actual turns ratio is determined from a detailed transformer design, use this ratio for the following
parameter calculations.
The UCC28730-Q1 constant-current regulation is achieved by maintaining a maximum DMAGCC duty cycle of
0.432 at the maximum primary current setting. The transformer turns ratio and constant-current regulating factor
determine the current-sense resistor, RCS, for a regulated constant-current target, IOCC. Actual implementation of
RCS may consist of multiple parallel resistors to meet power rating and accuracy requirements.
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Since not all of the energy stored in the transformer is transferred to the secondary output, a transformer
efficiency term, ηXFMR, is used to account for the core and winding loss ratio, leakage inductance loss ratio, and
primary bias power ratio with respect to the rated output power. At full load, an overall transformer efficiency
estimate of 0.91, for example, includes ~3% leakage inductance loss, ~5% core and winding loss, and ~1% bias
power. Actual loss ratios may vary from this example.
6##2 × .03
2#3
=
× D
¥
8&-2
ꢀ)/##
(12)
The primary-transformer inductance can be calculated using the standard energy storage equation for flyback
transformers. Primary current, maximum switching frequency and output and transformer power losses are
included in the equation below.
Initially, determine the transformer peak primary current, IPP(max)
.
Peak-primary current is simply the maximum current-sense threshold divided by the current-sense resistance.
6#34 (≠°∏ ꢀ
)
=
00 (≠°∏ ꢀ
2#3
(13)
(14)
Then, calculate the primary inductance of the transformer, LP.
:
;
2 × 6/#6 + 6& + 6/#"# × )/##
,0 =
2
)
00(≠°∏ ꢀ × ¶-!8 × D8&-ꢁ
The auxiliary winding to secondary winding turns ratio, NAS, is determined by the lowest target operating output
voltage in constant current regulation, the VDD turn-off threshold of the UCC28730-Q1, and the forward diode
drops in the respective winding networks.
6
6$$ (ض¶ ) + 6&!
.
!3
=
6/## + 6&
(15)
There is additional energy supplied to VDD from the transformer leakage inductance energy which may allow a
lower turns ratio to be used in many designs.
26
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8.2.2.4 Transformer Parameter Verification
The transformer turns ratio selected affects the MOSFET VDS and secondary rectifier reverse voltage VREV, these
should be reviewed.
The secondary rectifier reverse voltage stress is determined by the equation below. A snubber around the
rectifier may be necessary to suppress any voltage spike, due to secondary leakage inductance, which adds to
VREV
.
6
× ꢁ
¾
).(≠°∏ ꢀ
62%6
=
+ 6/#6 + 6/#"#
.
03
(16)
For the MOSFET VDS peak stress, an estimated leakage inductance voltage spike, VLK, should to be included.
:
;
6$30+ = k6). (≠°∏ ꢀ × ¾2o ꢁ 6/#6 ꢁ 6& ꢁ 6/#"# × .03 ꢁ 6,+
(17)
In the high-line, minimum-load condition, the UCC28730-Q1 requires a minimum on-time of the MOSFET
(tON(min)) and minimum demagnetization time of the secondary rectifier (tDMAG(min)). The selection of fMAX, LP and
RCS affects the actual minimum tON and tDMAG achieved. The following equations are used to determine if the
minimum tON is greater than tCSLEB and minimum tDMAG target of >1.2 µs is achieved.
ꢀ00(≠°∏ )
,
0
¥
=
×
/. (≠©Æ )
+
6
× 2
¾
!-
ꢀ.(≠°∏ )
(18)
(19)
¥
/. (≠©Æ ) × 6
×
2
¾
ꢀ.(≠°∏ )
¥
=
$-!' (≠©Æ )
: ;
× 6/#6 + 6&
.
03
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8.2.2.5 Output Capacitance
With ordinary flyback converters, the output capacitance value is typically determined by the transient response
requirement for a specific load step, ITRAN, sometimes from a no-load condition. For example, in some USB
charger applications, there is requirement to maintain a transient minimum VO of 4.1 V with a load-step of 0 mA
to 500 mA. 公式 20 below assumes that the switching frequency can be at the UCC28730-Q1 minimum of
fSW(min)
.
1
ꢀ42!.
l
+ 1ꢁ0 J≥p
¶
37 (≠©Æ )
#
R
/54 (.Ø _7°´• )
6/¿
(20)
This results in a COUT value of over 17,000 µF, unless a substantial pre-load is used to raise the minimum
switching frequency. However, the wake-up feature allows the use of a much smaller value for COUT because the
wake-up response immediately cancels the Wait state and provides high-frequency power cycles to recover the
output voltage from the load transient. The secondary-side voltage monitor UCC24650 provides the UCC28730-
Q1 with a wake-up signal when it detects a -3% droop in output voltage.
1.2 × )4ꢀ!ꢁ
#
/54
R
:
¤ ;
§6/54 §¥
where
•
(dVOUT/dt) is the slope at which the UCC24650 must detect the VOUT droop. Use a slope factor of 3700 V/s or
lower for this calculation. (21)
The UCC28730-Q1 incorporates internal voltage-loop compensation circuits so that external compensation is not
necessary, provided that the value of COUT is high enough. The following equation determines a minimum value
of COUT necessary to maintain a phase margin of about 40 degrees over the full-load range. KCo is a
dimensionless factor which has a value of 100.
)
/##
#
/54
R +#Ø ×
6/#6 × ¶-!8
(22)
Another consideration for selecting the output capacitor(s) is the maximum ripple voltage requirement,
VRIPPLE(max), which is reviewed based on the maximum output load, the secondary-peak current, and the
equivalent series resistance (ESR) of the capacitor. The two major contributors to the output ripple voltage are
the change in VOUT due to the charge and discharge of COUT between each switching cycle and the step in VOUT
due to the ESR of COUT. TI recommends an initial allocation of 33% of VRIPPLE(max) to ESR, 33% to COUT, and the
remaining 33% to account for additional low-level ripple from EMI-dithering, valley-hopping, sampling noise and
other random contributors. In 公式 23, a margin of 50% is applied to the capacitor ESR requirement to allow for
aging. In 公式 24, set ΔVCQ = 0.33 x VRIPPLE(max) to determine the minimum value of COUT with regard to ripple
voltage limitation. If other allocations of the allowable ripple voltage are desired, these equations may be
adjusted accordingly.
0.ꢀꢀ × 62)ꢁꢁ,% (≠°∏ ꢂ
%32 Q
× 0.50
)
ꢁꢁ(≠°∏ ꢂ × ꢃꢁ3
(23)
)
/##
#
R
/54
¿6#1 × ¶-!8
(24)
Choose the largest value of the previous COUT calculations for the minimum output capacitance. If the value of
COUT becomes excessive to meet a stringent ripple limitation, a C-L-C pi-filter arrangement can be considered to
as an alternative to a simple capacitor-only filter. This arrangement is beyond the scope of this datasheet.
28
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8.2.2.6 VDD Capacitance, CVDD
A capacitor is required on VDD to provide:
1. Run-state bias current during start-up while VDD falls toward UVLO, until VOCC is reached,
2. Wait-state bias current between steady-state low-frequency power cycles and
3. Wait-state bias current between minimum-frequency power cycles while VOUT recovers from a transient
overshoot.
Generally, the value to satisfy (3) also satisfies (2) and (1), however the value for (1) may be the largest if the
converter must provide high output current at a voltage below VOCC during power up.
The capacitance on VDD needs to supply the device operating current until the output of the converter reaches
the target minimum operating voltage in constant-current regulation, VOCC. At that point, the auxiliary winding can
sustain the bias voltage to the UCC28730-Q1 above the UVLO shutdown threshold. The total current available to
charge the output capacitors and supply an output load and is the constant-current regulation target, IOCC
.
公式 25 assumes that all of the output current of the flyback is available to charge the output capacitance until
the minimum output voltage is achieved. For margin, there is an estimated 1 mA of average gate-drive current
added to the run current and 1 V added to the minimum VDD.
#
× 6/##
/##
/54
:
)
;
+ 1 ≠! ×
25.
)
#
6$$
R
66$$ (ØÆꢀ F k66$$ (ض¶ ꢀ + 1 6o
(25)
At light loads, the UCC28730-Q1 enters a Wait-state between power cycles to minimize bias power and improve
efficiency. 公式 26 estimates the minimum capacitance needed to obtain a target maximum ripple voltage on
VDD (VVDD(maxΔ) < 1 V, for example) during the Wait state, which occurs at the lowest possible switching
frequency.
)
7!)4
#
6$$
R
66$$ (≠°∏ ¿ꢀ × ¶37(≠©Æ ꢀ
(26)
Choose the largest value of the previous CVDD calculations for the minimum VDD capacitance.
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8.2.2.7 VS Resistor Divider, Line Compensation, and Cable Compensation
The VS divider resistors determine the output voltage regulation point of the flyback converter. Also, the high-
side divider resistor, RS1, determines the line voltage at which the controller enables continuous DRV operation.
RS1 is initially determined based on the transformer primary to auxiliary turns ratio and the desired input voltage
operating threshold.
ꢀ × 6
¾
).(≤µÆ ꢁ
231
=
.
× )63, (≤µÆ ꢁ
0!
(27)
The low-side VS divider resistor, RS2, is selected based on the desired constant-voltage output regulation target,
VOCV
.
231 × 6632
: ;
× 6/#6 + 6& F 6632
23ꢀ
=
.
!3
(28)
The UCC28730-Q1 can maintain tight constant-current regulation over input line by utilizing the line
compensation feature. The line compensation resistor value, RLC, is determined by various system parameters
and the combined gate-drive turn-off and MOSFET turn-off delays, tD. Assume a 50-ns internal propagation delay
in the UCC28730-Q1.
+
× 231 × 2#3 × .0! × ¥$
,#
2,#
=
,
0
(29)
The UCC28730-Q1 provides adjustable cable compensation of up to approximately +8% of VOCV by connecting a
resistor between the CBC terminal and GND. This compensation voltage, VOCBC, represents the incremental
increase in voltage, above the nominal no-load output voltage, needed to cancel or reduce the incremental
decrease in voltage at the end of a cable due to its resistance. The programming resistance required for the
desired cable compensation level at the converter output terminals can be determined using the equation below.
As the load current changes, the cable compensation voltage also changes slowly to avoid disrupting control of
the main output voltage. A sudden change in load current will induce a step change of output voltage at the end
of the cable until the compensation voltage adjusts to the required level. Note that the cable compensation does
not change the overvoltage protection (OVP) threshold,VOVP (see Electrical Characteristics), so the operating
margin to OVP is less when cable compensation is used. If cable compensation is not required, CBC may remain
unconnected.
6#"# (≠°∏ )
2#"#
=
× ꢀ ´3 F ꢁ8 ´3
6632
6/#"#
×
:
;
6/#6 + 6&
(30)
30
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UCC28730-Q1
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8.2.2.8 VS Wake-Up Detection
The amplitude of the wake-up signal at the VS input must be high enough to be detected. This signal, which
originates on the secondary winding, is limited by the impedances of the wake-up signal driver and the L-C
resonant tank of the transformer windings. The signal is further attenuated by the VS divider resistors. To
maximize the wake-up signal amplitude, the pulse width, tWAKE, of the wake-up signal should be at least 1/4-
wavelength of the switched-node resonant frequency, fRES. The resonant frequency depends on the primary
magnetizing inductance and the total equivalent capacitance at the switching node, that is, the primary-side
MOSFET drain node. The switched-node capacitance, CSWN, includes the MOSFET COSS, the transformer
winding capacitance, and all other stray circuit capacitance attached to the MOSFET drain. Use 公式 31 to
determine fRES. Conversely, if fRES is known by experience or measurement, CSWN can be derived from 公式 31.
1
¶
=
2%3
tN , × #
¥
0
37.
(31)
Since the wake-up pulse width is typically fixed by the driver device, such as the UCC24650, maximum signal
strength is obtained when 公式 32 is true. Since LP is generally fixed by other system requirements, only CSWN
can be reduced to increase fRES, if necessary.
1
¶
R
2%3
4 × ¥7!+%
(32)
公式 33 is used to ensure that there is sufficient amplitude at the VS input to reliably trigger the wake-up function,
where RWAKE_TOT is the total secondary-side resistance of the wake-up signal driver and any series resistance.
An over-drive of 15 mV is added to the wake-up threshold level for margin.
,
27!+% _4/4 × .0ꢀ3
0
¨
R
#
37.
6/54 × .!3
231
k675 (¨Ø∑ ) ꢁ 1ꢂ≠6o × @
23ꢀ
f
F 1j
ꢁ 1A
(33)
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8.2.3 Application Curves
The following figures indicate the transient response of a 5-V, 10-W flyback converter which receives a pulsed
step-load of 2 A while operating in the no-load stand-by condition. 图 27 indicates the no-load stand-by input
power consumption achieved by this converter over the full AC input range. Zero-Power operation is achieved
while retaining fast transient response to a full load step.
VOUT with 5-V offset
5.1 V ±5% COUT = 540 µF
Output Ripple
214-mV Droop
2-A Load Step
2-A Load Step
Switching Pulses
Switching Pulses
图 24. 2-A Load Step During Stand-by Operation
图 25. Transient Response Detail for 2-A Load Step
5
4.5
4
VOUT with 5-V offset
3.5
3
2.5
2
1.5
1
2-A Load Step
0.5
0
85
135
185
235
265
Wake-Up Pulse
Switching Pulses
Input Voltage (VAC
)
D003
图 26. Wake-Up Pulse Triggering Response from
图 27. No-Load Input Power Consumption for a 5-V, 10-W
UCC28730-Q1 Primary-Side Controller
Converter
32
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ZHCSGD9 –JUNE 2017
8.3 Do's and Don'ts
•
•
•
During no-load operation, do allow sufficient margin for variations in VDD level to avoid the UVLO shutdown
threshold. Also, at no-load, keep the average switching frequency, <fSW>, greater than 2 x fSW(min) to avoid a
rise in output voltage.
Do clean flux residue and contaminants from the PCB after assembly. Uncontrolled leakage current from VS
to GND causes the output voltage to increase, while leakage current from HV or VDD to VS causes output
voltage to decrease.
If ceramic capacitors are used for VDD, do use quality parts with X7R or X5R dielectric rated 50 V or higher
to minimize reduction of capacitance due to dc-bias voltage and temperature variation.
•
•
Do not use leaky components if less than 5-mW stand-by input power consumption is a design requirement.
Do not probe the VS node with an ordinary oscilloscope probe; the probe capacitance can alter the signal and
disrupt regulation. Do observe VS indirectly by probing the auxiliary winding voltage at RS1 and scaling the
waveform by the VS divider ratio.
9 Power Supply Recommendations
The UCC28730-Q1 is intended for AC-to-DC adapters and chargers with input voltage range of 85 VAC(rms) to 265
VAC(rms) using flyback topology. It can also be used in other applications and converter topologies with different
input voltages. Be sure that all voltages and currents are within the recommended operating conditions and
absolute maximum ratings of the device.
The DRV output normally begins PWM pulses approximately 55 µs after VDD exceeds the turn-on threshold
VVDD(on). Avoid excessive dv/dt on VDD. Positive dv/dt greater than 1 V/µs may delay the start of PWM .
Negative dv/dt greater than 1 V/µs on VDD which does not fall below the UVLO turn-off threshold VVDD(off) may
result in a temporary dip in the output voltage.
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10 Layout
10.1 Layout Guidelines
In order to increase the reliability and feasibility of the project it is recommended to adhere to the following
guidelines for PCB layout.
1. Minimize stray capacitance on the VS node. Place the voltage sense resistors (RS1 and RS2 in 图 24 through
图 27) close to the VS pin.
2. TI recommends to connect the HV input to a non-switching source of high voltage, not to the MOSFET drain,
to avoid injecting high-frequency capacitive current pulses into the device.
3. Arrange the components to minimize the loop areas of the switching currents as much as possible. These
areas include such loops as the transformer primary winding current loop, the MOSFET gate-drive loop, the
primary snubber loop, the auxiliary winding loop and the secondary output current loop.
10.2 Layout Example
The partial layout example of 图 28 demonstrates an effective component and track arrangement for low-noise
operation on a single-layer printed circuit board. Actual board layout must conform to the constraints on a specific
design, so many variations are possible.
AUX
PRI
Winding
Winding
TRANSFORMER
CVDD1
DVDD
To Bulk Cap +
G
D
S
Q1
To Bulk Cap œ
CVDD2
RVDD
RS1
RS2
VDD
VS
HV
RCS1
UCC28730-Q1
RCS2
RCBC
CBC
GND
DRV
CS
RG
RLC
RCS3
0-È Jumper
To Bulk Cap +
图 28. UCC28730-Q1 Partial Layout Example
34
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UCC28730-Q1
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ZHCSGD9 –JUNE 2017
11 器件和文档支持
11.1 器件支持
11.1.1 器件命名规则
11.1.1.1 电容术语（以法拉为单位）
•
•
•
CBULK：CB1 和 CB2 的总输入电容
CVDD：VDD 引脚所需的最小电容
COUT：所需的最小输出电容
11.1.1.2 占空比相关术语
•
•
•
DMAGCC：CC 模式下二次侧二极管导通占空比，0.432
DMAX：允许的最大 MOSFET 导通时间占空比
NHC：线路降压期间交流线路频率的半周期数
11.1.1.3 频率术语（以赫兹为单位）
•
•
•
•
•
f
f
f
f
f
LINE：最小线路频率
MAX：转换器在满载条件下的最高开关频率
MIN：转换器的实际最小开关频率
SW(max)：控制器的最大开关频率（请参阅Electrical Characteristics）
SW(min)：控制器的最小开关频率（请参阅Electrical Characteristics）
11.1.1.4 电流术语（以安培为单位）
•
•
•
•
•
•
I
I
I
I
I
I
OCC：转换器输出恒流目标
PP(max)：变压器一次侧最大电流
START：启动前 VDD 偏置电流（请参阅Electrical Characteristics）
TRAN：所需的正负载阶跃电流
WAIT：等待状态期间 VDD 偏置电流（请参阅Electrical Characteristics）
VSL(run)：VS 引脚运行电流（请参阅Electrical Characteristics）
11.1.1.5 电流和电压调节术语
•
•
•
KAM：最大/最小初级电流峰值振幅比率（请参阅Electrical Characteristics）
KLC：针对线路补偿的电流调节常量（请参阅Electrical Characteristics）
KCo：稳定性因子 100，用于计算 COUT
11.1.1.6 变压器术语
•
•
•
•
LP：变压器初级电感
NAS：变压器辅助绕组与二次侧绕组匝数比
NPA：变压器一次侧绕组与辅助绕组匝数比
NPS：变压器一次侧绕组与二次侧绕组匝数比
11.1.1.7 功率术语（以瓦特为单位）
•
•
•
PIN：满载时转换器的最大输入功率
POUT：满载时转换器的输出功率
PSTBY：待机时转换器的总输入功率
版权 © 2017, Texas Instruments Incorporated
35
UCC28730-Q1
ZHCSGD9 –JUNE 2017
www.ti.com.cn
器件支持 (接下页)
11.1.1.8 电阻术语（以 Ω 为单位）
•
•
•
•
•
R
CS：一次侧电流编程电阻
RESR：输出电容的总 ESR
RPL：转换器输出端的预载电阻
RS1：高侧 VS 输入电阻
RS2：低侧 VS 输入电阻
11.1.1.9 时序术语（以秒为单位）
•
•
•
•
tD：总电流感测延迟（包括 MOSFET 关断延迟）；在 MOSFET 延迟基础上增加 50ns
tDMAG(min)：二次侧整流器最短导通时间（变压器消磁时间）
tON(min)：MOSFET 最短导通时间
tR：tDMAG 之后的谐振环周期
11.1.1.10 直流电压术语（以伏特为单位）
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
V
V
V
V
V
V
V
V
V
V
V
V
BULK：用于待机功耗测量的大容量电容最高电压
BULK(min)：满功率条件下大容量电容的最小谷值电压
OCBC：输出引脚的目标电缆补偿电压
CBC(max)：最大输出电流条件下 CBC 引脚的最高电压（请参阅Electrical Characteristics）
CCR：恒流调节系数电压（请参阅Electrical Characteristics）
CST(max)：CS 引脚最大电流感测阈值（请参阅Electrical Characteristics）
CST(min)：CS 引脚最小电流感测阈值（请参阅Electrical Characteristics）
VDD(off)：UVLO 阈值关断电压（请参阅Electrical Characteristics）
VDD(on)：UVLO 阈值接通电压（请参阅Electrical Characteristics）
VDD(maxΔ)：等待状态下开关周期间的最大 VDD 压降
OΔ：输出负载瞬态期间允许的输出压降
DSPK：高压线条件下的 MOSFET 漏源电压峰值
VF：电流接近零时的二次侧整流器正向压降
FA：辅助整流器正向压降
VLK：估计的一次侧漏感能量复位电压
V
V
V
V
V
V
OCV：转换器稳压输出电压
OCC：恒流稳压条件下的最低目标输出电压
REV：二次侧整流器的反向峰值电压
RIPPLE：满载条件下的输出峰峰值纹波电压
VSR：VS 输入端的恒压调节电平（请参阅Electrical Characteristics）
ΔVCQ：开关周期间允许的负载放电 COUT 电压变化
11.1.1.11 交流电压术语（以伏特为单位）
•
•
•
VIN(max)：转换器的最大交流输入电压
VIN(min)：转换器的最小交流输入电压
VIN(run)：转换器的启动（运行）输入电压
11.1.1.12 效率术语
•
ηSB：当反激式转换器输出功率为零时估计的内部预载功率效率。此效率的计算方式为：通过 RPL 耗散的转换器
内部预载功率除以转换器在待机状况下的总输入功率 (PSTBY)。在设计开始可使用估计值 50%。
•
•
η：转换器全额输出功率条件下的总体效率
ηXFMR：变压器的功率传输效率
36
版权 © 2017, Texas Instruments Incorporated
UCC28730-Q1
www.ti.com.cn
ZHCSGD9 –JUNE 2017
11.2 文档支持
11.2.1 相关文档
•
•
•
用于快速瞬态 PSR 的 UCC24650 200V 唤醒监控器，SLUSBL6
具有 CVCC 和唤醒监控功能的 UCC28730 零功耗待机 PSR 反激式控制器，SLUSBL5
《UCC28730EVM-552 EVM 用户指南，使用 UCC28730EVM-552》，SLUUB75
11.3 接收文档更新通知
要接收文档更新通知，请导航至德州仪器 TI.com.cn 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可
收到任意产品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2017, Texas Instruments Incorporated
37
UCC28730-Q1
ZHCSGD9 –JUNE 2017
www.ti.com.cn
12 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航栏。
38
版权 © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC28730QDRQ1
ACTIVE
SOIC
D
7
2500 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
28730Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
D0007A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
8
1
.100
[2.54]
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X .050
[1.27]
4
5
7X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4220728/A 01/2018
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0007A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
7X (.024)
[0.6]
(.100 )
[2.54]
SYMM
5
4
4X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220728/A 01/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0007A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7X (.061 )
[1.55]
SYMM
1
8
7X (.024)
[0.6]
(.100 )
[2.54]
SYMM
5
4
4X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4220728/A 01/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
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Copyright © 2020 德州仪器半导体技术（上海）有限公司
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