UCC28742DBVR [TI]
具有 1% 输出调节精度的高效反激控制器 | DBV | 6 | -40 to 125;
| 型号： | UCC28742DBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 1% 输出调节精度的高效反激控制器 | DBV | 6 | -40 to 125 反激控制 控制器 开关 光电二极管 |
| 文件： | 总44页 (文件大小：1664K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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UCC28742
ZHCSHY7A –APRIL 2018–REVISED MAY 2018
具有光耦合器反馈功能的 UCC28742 高效反激式控制器
1 特性
3 说明
1
•
•
•
•
•
•
光耦合反馈可实现精度高达 1% 的调节
UCC28742 离线反激式控制器是一款高度集成的 6 引
脚次级侧稳压 PWM 控制器，适用于高效交流/直流电
源。这是一种隔离式反激电源控制器，使用一个光耦合
器来提供恒定电压 (CV)，从而改善对大型负载阶跃的
瞬态响应。此器件处理来自光耦合反馈和辅助反激式绕
组的信息，以此实现对输出电压和电流的高性能控制。
精确电流限制以及过载超时保护和延迟断续响应
谐振环谷底开关运行模式可实现最高总体效率
最大开关频率为 80kHz
简化电磁干扰 (EMI) 兼容性的频率抖动
针对金属氧化物半导体场效应晶体管 (MOSFET) 的
已钳制栅极驱动输出
UCC28742 采用先进的控制算法来实现高运行效率和
性能。驱动输出接至一个 MOSFET 电源开关。带有谷
值开关的断续传导模式 (DCM) 减少了开关损耗。开关
频率的调制和初级电流峰值振幅（FM 和 AM）在整个
负载和线路范围内保持较高的转换效率。
•
超低启动电流和大型 VDD 迟滞
–
–
高值启动电阻器
低偏置电容
•
故障保护
–
–
–
–
输入低线路
此控制器的最大开关频率为 80kHz，并且一直保持对
变压器内峰值一次侧电流的控制。200Hz 的最小开关
频率有助于实现较低的空载输入功率。
输出过压
过流
短路
器件信息 (1)
•
•
SOT23-6 封装
使用 UCC28742 并借助 WEBENCH® 电源设计器
创建定制设计方案
器件型号
封装
SOT23-6
封装尺寸（标称值）
UCC28742
2.90mm × 1.60mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
2 应用
•
•
•
•
工业和医疗交流/直流电源
智能电表
UPS、服务器 PSU 等的偏置电源
电缆调制解调器、电视、机顶盒和无线路由器的电
源
•
电器的交流/直流电源
简化原理图
10W、5V 交流/直流转换器的典型效率
+
VF -
VBULK
VOUT
85%
82.5%
80%
CB1
CB2
COUT
NP
NS
RSTR
œ
VAC
77.5%
75%
RTL
+
VFA -
VVDD
VAUX
VDD
72.5%
70%
ROPT
NA
CVDD
UCC28742
SOT23-6
RS1
RFB1
67.5%
65%
VE
VS
FB
DRV
CS
IOPT
ZFB
CFB3
RFB3
RS2
115 V RMS
230 V RMS
62.5%
60%
RLC
RCS
GND
RFB2
IFB
RFB4
10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
Output Power
D001
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSD71
UCC28742
ZHCSHY7A –APRIL 2018–REVISED MAY 2018
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 21
8
9
Applications and Implementation ...................... 22
8.1 Application Information............................................ 22
8.2 Typical Application .................................................. 22
8.3 Do's and Don'ts....................................................... 31
Power Supply Recommendations...................... 32
10 Layout................................................................... 32
10.1 Layout Guidelines ................................................. 32
10.2 Layout Example .................................................... 33
11 器件和文档支持 ..................................................... 34
11.1 器件支持 ............................................................... 34
11.2 文档支持 ............................................................... 37
11.3 接收文档更新通知 ................................................. 38
11.4 社区资源................................................................ 38
11.5 商标....................................................................... 38
11.6 静电放电警告......................................................... 38
11.7 术语表 ................................................................... 38
12 机械、封装和可订购信息....................................... 38
7
4 修订历史记录
日期
修订版本
说明
2018 年 5 月
A
最初发布版本。
2
Copyright © 2018, Texas Instruments Incorporated
UCC28742
www.ti.com.cn
ZHCSHY7A –APRIL 2018–REVISED MAY 2018
5 Pin Configuration and Functions
SOT23-6 Package
6-Pin DBV
Top View
VS
FB
VDD
DRV
1
6
5
4
2
3
GND
CS
Pin Functions
PIN
I/O
DESCRIPTION
NAME
CS
NO.
4
The current-sense (CS) input connects to a ground-referenced current-sense resistor in series with the
power switch. The resulting voltage monitors and controls the peak primary current. A series resistor is
added to this pin to compensate for peak switch current levels as the AC-mains input varies.
I
DRV
3
O
DRV is an output pin used to drive the gate of an external high voltage MOSFET switching transistor.
The feedback (FB) input receives a current signal from the optocoupler output transistor. An internal
current mirror divides the feedback current applies it to an internal pullup resistor to generate a control
voltage, VCL. The voltage at this resistor directly drives the control law function, which determines the
switching frequency and the peak amplitude of the switching current.
FB
1
I
The ground (GND) pin is both the reference pin for the controller, and the low-side return for the drive
output. Special care must be taken to return all AC-decoupling capacitors as close as possible to this pin
and avoid any common trace length with analog signal-return paths.
GND
VDD
5
2
G
P
VDD is the bias supply input pin to the device. A carefully placed bypass capacitor to GND is required on
this pin. Typical bypass capacitor values are from 0.047 µF to 10 µF depending on a design.
Voltage sense (VS) is an input used to provide demagnetization timing feedback to the controller to limit
frequency, to control constant-current operation, and to provide output-overvoltage detection. VS is also
used for AC-mains input-voltage detection for peak primary-current compensation. This pin connects to a
voltage divider between an auxiliary winding and GND. The value of the upper resistor of this divider
programs the AC-mains run and stop thresholds, and factors into line compensation at the CS pin.
VS
6
I
Copyright © 2018, Texas Instruments Incorporated
3
UCC28742
ZHCSHY7A –APRIL 2018–REVISED MAY 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
V
VVDD
VS
Bias supply voltage
38
Voltage range
–0.75
–0.5
–0.5
–0.5
7
V
FB
Voltage range
7
V
CS
Voltage range
5
Self-limiting
50
V
VDRV
IDRV
IDRV
IDRV
IDRV
IFB
Gate-drive voltage at DRV
V
DRV continuous sink current
DRV continuous source current
DRV peak sourcing current, VDRV = 10 V to 0 V
DRV peak sink current, VDRV = 0 V to 10 V
FB, peak current
mA
mA
mA
mA
mA
mA
°C
°C
°C
15
Self-limiting
Self-limiting
1.0
IVS
VS, peak, 1% duty-cycle, when detecting line voltage
Operating junction temperature range
Storage temperature
1.2
TJ
–55
–65
150
TSTG
TLEAD
150
Lead temperature 0.6 mm from case for 10 seconds
260
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
V
V(ESD)
V(ESD)
Electrostatic discharge
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM) ESD stress voltage(2)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
35
UNIT
VDD
CDD
IFB
Bias supply operating voltage
9
V
VDD bypass capacitor
0.047
no limit
50
µF
µA
mA
°C
Feedback current, continuous
IVS
VS pin sourcing current when detecting line voltage
Operating junction temperature
1.0
TJ
–40
125
4
Copyright © 2018, Texas Instruments Incorporated
UCC28742
www.ti.com.cn
ZHCSHY7A –APRIL 2018–REVISED MAY 2018
6.4 Thermal Information
UCC28742
THERMAL METRIC
DBV
6 PINS
150
55
UNIT
(1)
θJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
(2)
θJCtop
θJB
Junction-to-case (top) thermal resistance
(3)
Junction-to-board thermal resistance
60
(4)
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
3
(5)
ψJB
55
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
6.5 Electrical Characteristics
Over operating free-air temperature range, VVDD = 25 V, VFB = 0 V, VVS = 4V, –40°C ≤ TA ≤ 125°C, TJ = TA (unless otherwise
noted)
PARAMETER
BIAS SUPPLY INPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IRUN
Supply current, run
Supply current, wait
Supply current, start
Supply current, fault
IDRV = 0, run state
1.30
50
1.80
80
2.40
115
mA
µA
IWAIT
ISTART
IFAULT
IDRV = 0, VVDD = 20 V, wait state
IDRV = 0, VVDD = 17 V, start state
IDRV = 0, fault state
1.50
1.80
2.75
2.40
µA
1.30
mA
UNDER-VOLTAGE LOCKOUT
VVDD(on)
VVDD(off)
VS INPUT
VVSNC
VDD turn-on threshold
VDD turn-off threshold
VVDD low to high
VVDD high to low
17.5
7.25
21.6
7.80
24.5
8.30
V
V
Negative clamp level
Input bias current
IVS = –300 µA
VVS = 4 V
–304
–225
0
–164
0.25
mV
µA
IVSB
–0.25
FB INPUT
IFBMAX
VFBMAX
RFB
Full-range input current
Input voltage at full-range
FB-input resistance
fSW = fSW(min)
IFB = 26 µA
16
0.70
10
23
0.90
14
30
1.10
18
µA
V
ΔIFB = 6 to 26 µA
kΩ
CS INPUT
VCST(max)
VCST(min)
KAM
(1)
Max CS threshold voltage
Min CS threshold voltage
AM control ratio
IFB = 0 µA
710
164
3.55
338
770
190
4.00
363
830
216
4.50
390
mV
mV
V/V
mV
(1)
IFB = 35 µA
VCST(max) / VCST(min)
VCCR
Constant-current regulating level
KLC
Line compensating current ratio,
IVSLS / (current out of CS pin)
IVSLS = –300 µA
23
25
29
A/A
ns
TCSLEB
Leading-edge blanking time
DRV output duration, VCS = 1 V
195
270
350
(1) These threshold voltages represent average levels. This device automatically varies the current sense threshold to improve EMI
performance.
Copyright © 2018, Texas Instruments Incorporated
5
UCC28742
ZHCSHY7A –APRIL 2018–REVISED MAY 2018
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Electrical Characteristics (continued)
Over operating free-air temperature range, VVDD = 25 V, VFB = 0 V, VVS = 4V, –40°C ≤ TA ≤ 125°C, TJ = TA (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DRV
IDRS
DRV source current
VDRV = 5 V, VVDD = 9 V
24
30
6.5
36
12
mA
Ω
RDRVLS
VDRCL
RDRVSS
TIMING
fSW(max)
fSW(min)
tZTO
DRV low-side drive resistance
DRV clamp voltage
IDRV = 10 mA
VVDD = 35 V
8.8
10.6
175
13
V
DRV pull-down in start state
135
250
kΩ
(2)
Maximum switching frequency
Minimum switching frequency
Zero-crossing timeout delay
Delay time before shutdown
IFB = 0 µA
80
140
1.45
85
105
200
2.45
120
130
255
3.30
160
kHz
Hz
µs
IFB = 35 µA
tOVL_TIME
Demag_Duty = VCCR/ VCST(max)
ms
PROTECTION
VOVP
Over-voltage threshold(3)
At VS input, TJ = 25 °C
4.45
1.41
170
60
4.65
1.50
210
75
4.85
1.59
250
90
V
V
VOCP
Over-current threshold(3)
VS line-sense run current
VS line-sense stop current
At CS input
IVSL(run)
IVSL(stop)
KVSL
Current out of VS pin – increasing
Current out of VS pin – decreasing
µA
µA
VS pin, line-sense current ratio,
IVSL(run) / IVSL(stop)
2.50
2.80
165
3.05
A/A
°C
(4)
TJ(stop)
Thermal shut-down temperature
Internal junction temperature
(2) These frequency limits represent average levels. This device automatically varies the switching frequency to improve EMI performance.
(3) The OVP threshold at VS decrease with increasing temperature by 1 mV/℃. This compensation over temperature is included to reduce
the variances in power supply over-voltage detection with respect to the external output rectifier.
(4) Ensured by design. Not tested in production.
6
版权 © 2018, Texas Instruments Incorporated
UCC28742
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ZHCSHY7A –APRIL 2018–REVISED MAY 2018
6.6 Typical Characteristics
VDD = 25 V, unless otherwise noted.
1E-2
1E-3
1E-4
0.1
0.2
0.5
2
5
IRUN VDD = 25 V
IWAIT VDD = 20 V
ISTART VDD = 17 V
20
50
1E-5
éVDD Turn-Off
åVDD Turn-On
200
500
1E-6
1E-7
1E-8
Start State
Run State
Wait State
2000
5000
0
5
10
15
20
25
30
35
40
-50
-25
0
25
50
75
100
125
150
VDD Bias Supply Voltage (V)
TJ Temperature (èC)
D001
D002
图 1. Bias Supply Current vs. Bias Supply Voltage
图 2. Bias Supply Current vs. Temperature
196
300
250
200
150
100
50
IVSL(run)
IVSL(stop)
194
192
190
188
186
184
182
180
0
-50
-25
0
25
50
75
100
125
150
-50 -30 -10 10
30
50
70
90 110 130 150
TJ Temperature (èC)
TJ Temperature (èC)
D003
D004
图 3. Minimum CS Threshold vs. Temperature
图 4. VS Line-Sense Current vs. Temperature
32
31.5
31
215
213
211
209
207
205
203
201
199
197
195
30.5
30
29.5
29
28.5
28
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
TJ Temperature (èC)
TJ Temperature (èC)
D005
D006
图 5. Minimum Switching Frequency vs. Temperature
图 6. DRV Source Current vs. Temperature
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Typical Characteristics (接下页)
VDD = 25 V, unless otherwise noted.
1.2
1.1
1
4.85
4.8
4.75
4.7
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
4.65
4.6
4.55
4.5
4.45
4.4
0
5
10
15
20
25
30
35
40
-50
-25
0
25
50
75
100
125
150
IFB FB Input Current (mA)
TJ Temperature (èC)
D007
D008
图 7. FB Input Voltage vs. FB Input Current
图 8. VS Overvoltage Threshold vs. Temperature
8
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UCC28742
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ZHCSHY7A –APRIL 2018–REVISED MAY 2018
7 Detailed Description
7.1 Overview
The UCC28742 is a flyback power-supply controller which provides high-performance voltage regulation using an
optically coupled feedback signal from a secondary-side voltage regulator. The device provides accurate
constant-current regulation using primary-side feedback. The controller operates in discontinuous-conduction
mode (DCM) with valley-switching to minimize switching losses and allow for the use of low cost output rectifiers.
The control law scheme combines frequency with primary peak-current amplitude modulation to provide high
conversion efficiency across the load range. The control law provides a wide dynamic operating range of output
power which allows the power-supply designer to achieve low standby power dissipation.
During low-power operating conditions, the power-management features of the controller reduce the device-
operating current at switching frequencies below 25 kHz. At and above this frequency, the UCC28742 includes
features in the modulator to reduce the EMI peak energy of the fundamental switching frequency and harmonics.
A complete low-cost and low component-count solution is realized using a straight-forward design process.
7.2 Functional Block Diagram
0.475
120 ms
Delay
/VCST(max)
+
OVL FAULT
OC FAULT
GND
VDD
FB
VCCR
Power
& Fault
Management
OV FAULT
UVLO
22 V / 7.7 V
LINE FAULT
5 V
IFB
5 V
480 kΩ
14 kΩ
VDD
VCL
Control
Law
0.55 V
IFB / 2.5
VCST
30 mA
DRV
10 V
Sampler
+
VS
OV FAULT
1 / fSW
VOVP
175 kꢀ
S
R
Q
Q
Valley
Switching
GND
Secondary
Timing
Detect
CS
+
Current
Regulation
VCST
LEB
IVSLS
Line
Sense
IVSLS / KLC
LINE FAULT
IVSLS
+
+
OC FAULT
10 kꢀ
1.5 V
2.11 V / 0.75 V
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ZHCSHY7A –APRIL 2018–REVISED MAY 2018
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7.3 Feature Description
7.3.1 Detailed Pin Description
7.3.1.1 VDD (Device Bias Voltage Supply)
The VDD pin is typically powered from a rectified auxiliary transformer winding, the same winding that is used to
capture the output voltage level. A bypass capacitor, with minimum value 0.047 μF, on the VDD pin is used for
initially biasing the device to start-up along with a resistive or active source of start-up charging current. UVLO
start / stop levels of 21.6 V / 7.8 V accommodate lower values of VDD capacitance that in turns keeps the start-
up current low, which for resistive start-up has an impact on both stand-by power and power-on delay. A high,
35-V, maximum operating level on VDD alleviates concerns with leakage energy charging of VDD and gives
added flexibility to when varying power supply output voltage must be supported.
7.3.1.2 GND (Ground)
This is an external return pin, and provides the reference point for both external signal and the gate drive of the
device. The VDD bypass capacitor should be placed close to this pin. Critical component GND connections from
the VS, FB and CS pins should have dedicated and short paths to this pin.
10
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ZHCSHY7A –APRIL 2018–REVISED MAY 2018
Feature Description (接下页)
7.3.1.3 VS (Voltage-Sense)
The VS pin connects to a resistor-divider from the auxiliary winding to ground. The auxiliary voltage waveform is
sampled at the end of the transformer secondary-current demagnetization time. The waveform on the VS pin
determines (1) the timing information to achieve valley-switching, (2) the timing to control the duty-cycle of the
transformer secondary current, and (3) the output voltage over-voltage. Avoid placing a filter capacitor on this
input which interferes with accurate sensing of this waveform.
Besides, the VS pin also has these two functions: (4) senses the bulk capacitor input voltage to provide for ac-
input run and stop thresholds, and (5) to compensate the current-sense threshold across the AC-input range.
This information is sensed by monitoring the current pulled out of the VS pin during the MOSFET on-time. During
this time the voltage on the VS pin is clamped to about 250 mV below GND. As a result, the current out of the
pin is determined by the upper VS divider resistor, the auxiliary to primary turns-ratio and the bulk input voltage
level. For the AC-input run/stop function, the run threshold on VS is IVSL(run) (typical 210 µA) and the stop
threshold is IVSL(stop) (typical 75 µA). The values for the auxiliary voltage divider upper-resistor RS1 and lower-
resistor RS2 can be determined by the equations below.
2 ì V
VBULK(run)
IN(run)
RS1
=
ö
NPA ìIVSL(run) NPA ìIVSL(run)
where
•
•
•
•
NPA is the transformer primary-to-auxiliary turns ratio,
VIN(run) is the AC rms voltage to enable turn-on of the flyback converter (run),
VBULK(run) is the DC bulk voltage to enable turn-on of the flyback converter (run),
IVSL(run) is the run-threshold for the current pulled out of the VS pin during the primary MOSFET on-time. (see
the Electrical Characteristics table).
(1)
RS1 ì VOVP
NAS ì (VOV + VF ) - VOVP
R S2
=
where
•
•
•
•
•
VOV is the maximum allowable peak voltage at the converter output,
VF is the output rectifier forward voltage drop at near-zero current,
NAS is the transformer auxiliary to secondary turns ratio,
RS1 is the VS divider upper-resistor resistance,
VOVP is the overvoltage detection threshold at the VS input (see the Electrical Characteristics table).
(2)
Notice that VS pin absolute maximum current IVS in its negative clamping is 1.2 mA. After determined RS1 it is
required to check if VS pin current stays ≤ 1.2 mA. The check is to determine the input voltage ratio in this design
and make VIN(max) / VIN(run) ≤ IVS / IVSL(run) = 1.2 mA / 0.25 mA = 4.8, i.e., VIN(max) / VIN(run) ≤ 4.8. If the design
cannot meet this criterion, external circuit is needed to add in to make sure VS pin current ≤ 1.2 mA, for example,
to use a zener type of device to clamp the transformer aux-winding negative voltage to achieve VIN(max) / VIN(run)
4.8.
≤
7.3.1.4 DRV (Gate Drive)
The DRV pin is connected to the MOSFET gate pin, usually through a series resistor. The DRV provides a gate
drive signal which is clamped to 10-V internally. During turn-on the driver applies a typical 30-mA current source
out of the DRV pin. When the DRV voltage rises to above 9 V the output current is reduced to about 100 µA.
This current brings the DRV voltage to the 10-V clamp level, or to VDD, whichever is less. The 30-mA current
provides adequate turn-on speed while automatically limiting noise generated at turn-on by the MOSFET drain
dv/dt and by the leading edge turn-on current spike. The gate drive turn-off current is internally limited to about
400 mA when DRV is above about 4 V. At lower DRV voltages the current will reduce, eventually being limited
by the low-side on resistance, RDS(on). The drain turn-on and turn-off dv/dt can be further impacted by adding
external resistor in series with DRV pin. The drain current resonances can be damped with a small series gate
resistor, generally less than a 1 Ω.
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Feature Description (接下页)
7.3.1.5 CS (Current Sense)
The current sense pin is connected through a series resistor (RLC) to the current-sense resistor (RCS). The
controller varies the internal current sense threshold between 190 mV and 770 mV, setting a corresponding
control range for the peak-primary winding current to a 4-to-1 range. The series resistor RLC provides an input
voltage feed-forward function. The voltage drop across this resistor reduces primary-side peak current as the line
voltage increases, compensating for the increased di/dt and delays in the MOSFET turn-off. There is an internal
leading-edge blanking time of 270 ns to eliminate sensitivity to the MOSFET turn-on leading edge current spike.
If additional blanking time is needed, a small bypass capacitor, up to 30 pF, can be placed on between CS pin
and GND pin. The value of RCS is determined by the target output current in constant current (CC) regulation.
The values of RCS and RLC can be determined by the equations below. The term ηXFMR is intended to account for
the energy stored in the transformer but not delivered to the secondary. This includes transformer core and
copper losses, bias power, and primary leakage inductance losses.
Example: With a transformer core and copper losses of 3%, leakage inductance caused power losses 2%, and
bias power to output power ratio of 0.5%. The transformer power transfer efficiency is estimated as ηXFMR
=
100% - 3% - 2% - 0.5% = 94.5%
VCCR ìNPS
2 ìIOCC
RCS
=
ì hXFMR
where
•
•
VCCR is a current regulation constant (see the Electrical Characteristics table),
NPS is the transformer primary-to-secondary turns ratio (a typical turns-ratio of 12 to 15 is recommended for 5-
V output as an example),
•
•
IOCC is the target output current in constant-current limit (refer to Constant Current Limit and Delayed
Shutdown for more detail),
ηXFMR is the transformer efficiency.
(3)
KLC ì RS1 ìRCS ì(tD + tGATE_ OFF)ìNPA
RLC
=
LP
where
•
•
•
•
•
•
•
RS1 is the VS pin high-side resistor value,
RCS is the current-sense resistor value,
tD is the current-sense delay (typical 50 ns) plus MOSFET turn-off delay,
tGATE_OFF is the primary-side main MOSFET turn-off time,
NPA is the transformer primary-to-auxiliary turns-ratio,
LP is the transformer primary inductance,
KLC is a current-scaling constant (see the Electrical Characteristics table).
(4)
7.3.1.6 FB (Feedback)
The FB pin connects to the emitter of an analog optocoupler output transistor which usually has the collector
connected to VDD. The current supplied to FB by the optocoupler is reduced internally by a factor of 2.5 and the
resulting current is applied to an internal 480-kΩ resistor to generate the control law voltage (VCL). This VCL
directly determines the converter switching frequency and peak primary current required for regulation per the
control-law for any given line and load condition.
Typical circuit connection between FB and optocoupler along with typical values of resistors and capacitors
should be made as shown in 图 9. The resistors and capacitors in the connections help to stabilize operation
during control mode transition.
12
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Feature Description (接下页)
7.3.2 Secondary-Side Optically Coupled Constant-Voltage (CV) Regulation
图 9 shows a simplified flyback convertor with the main output-regulation blocks of the device shown, along with
typical implementation of secondary-side-derived regulation. The power-train operation is the same as any DCM-
flyback circuit. A feedback current is optically coupled to the controller from a shunt-regulator sensing the output
voltage.
+
VF -
VBULK
VOUT
+
Timing
COUT
Primary
Secondary
RLOAD
RS1
Auxiliary
VCL
Discriminator &
Sampler
VS
Control
Law
GD
DRV
VDD
RS2
–
Minimum
Period
And Peak
Primary Current
CS
RTL
GND
RCS
Zero Crossings
ROPT
RFS
Mirror
Network
FB
IOPT
RFB1
ZFB
IFB
+
VREF
-
RFP
CFS
RFB2
图 9. Simplified Flyback Converter
(with the Main Voltage Regulation Blocks)
In this configuration, a secondary-side shunt-regulator, such as the TL431 (or ATL431), generates a current
through the input photo-diode of an optocoupler. The photo-transistor delivers a proportional current that is
dependent on the current-transfer ratio (CTR) of the optocoupler to the FB input of the UCC28742 controller. This
FB current then converts into the VCL by the input-mirror network, detailed in the device block diagram (see
Functional Block Diagram). Output-voltage variations convert to FB-current variations. The FB-current variations
modify the VCL which dictates the appropriate IPP and fSW necessary to maintain CV regulation. At the same time,
the VS input senses the auxiliary winding voltage during the transfer of transformer energy to the secondary
output to monitor for an output overvoltage condition. When fSW reaches the converter target maximum frequency
(i.e., corresponding de-mag time duty reaches 0.475), Constant Current Limit is triggered and further increases in
VCL cannot increase fSW anymore. (see 图 10, Control Law and Constant Current Limit and Delayed Shutdown)
VS Sample
(VOUT + VF + ISRS) NA / NS
0 V
- (VBLK) NA / NP
图 10. Auxiliary Winding Voltage
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Feature Description (接下页)
The UCC28742 samples the VS input voltage at the end of demagnetization time for output overvoltage
detection and to determine the total demagnetization time for output current control in Constant Current Limit
operation.
In order to maintain best performance of these functions the reset time and ringing of the auxiliary winding
voltage should meet certain guidelines. Referring to 图 11, the width of the leakage spike at the VS input should
be less than tDM_BLANK. Minimum tDM_BLANK is 3 µs at maximum peak priamry current levels and proportionally
less at lower peak primary current levels (the lowest 0.75 µs should be observed at high line and no load
condition). In addition, any ringing following the spike should be reduced to < 160 mVpp (scaled to the VS pin)
200 ns before the end of the demagnetization time.
As mentioned in Device Functional Modes, when IPP < IPP(max), the device operation enters a “Wait” state during
each switching cycle of its non-switching portion as shown in 图 11. In the Wait state, the device bias current
changes to IWAIT (typical 80 µA) from IRUN (typical 1.8 mA), reducing its bias power to help boost efficiency at light
load and to reduce no-load input power.
tLK RESET
Entering —Wait“ State
Ipp < Ipp(max)
VS ring p-p
(scaled)
0 V
RS2/(RS1+RS2
)
tDM_BLANK
tDMAG
tSW
图 11. Auxiliary Waveform Details
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Feature Description (接下页)
7.3.3 Control Law
During voltage regulation (CV mode), the controller operates in frequency modulation mode and peak current
amplitude modulation mode as illustrated in 图 12 below. In CV mode operation, the control consists of four
regions, namely, region FM 1, 2, AM and FM 3. The device internal VCL sets a particular region of operation.
Refer to 图 12 for VCL
.
The device internally limits its operating frequency between fSW(min) and fSW(max), typically between 200 Hz and
105 kHz. The choice of transformer primary inductance and primary-peak current sets the maximum operating
frequency of the converter, which must be equal to or lower than fSW(max). Conversely, the choice of maximum
target operating frequency and primary-peak current determines the transformer primary-inductance value. The
actual minimum switching frequency for any particular converter depends on several factors, including minimum
loading level, leakage inductance losses, switch-node capacitance losses, other switching and conduction losses,
and bias-supply requirements. In any case, the minimum steady-state frequency of the converter must always
exceed fSW(min) or the output voltage may rise to the over-voltage protection level (OVP) and the controller
responds as described in Fault Protection.
To achieve a regulated output voltage in the CV mode operation, energy balance has to be maintained. As the
UCC28742 has a minimum switching frequency typical 200 Hz, together with the energy per switching cycle
determined by converter parameters, such as the transformer primary inductance Lp and the selected RCS
resistor, the converter has a minimum input power. A proper pre-load needs to be selected to ensure that this
minimum energy is balanced during the no-load condition. The selection of the line compensation resistor value
(RLC) connected to the CS pin can impact the energy per switching cycle based on low-line and high-line
conditions. Typical Application section provides a design example to show how to implement these
considerations.
Control-Law Profile in Constant-Voltage (CV) Mode
IPP(max)
105 kHz
IPP
fSW
25 kHz
IPP(max) / 4
FM 1
FM 2
AM
FM 3
3.80 kHz
200 Hz
0 V
0.75 V
1.3 V
2.2 V
3.2 V
4.9 V
5 V
Control Law Voltage, Internal - VCL
26 µA
22.1 µA
19.3 µA
14.6 µA
9.4 µA
0.5 µA
Corresponding Feed-back Current, FB Input - IFB
图 12. Frequency and Amplitude Modulation Modes
(during CV mode)
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Feature Description (接下页)
The steady-state control-law voltage, VCL, ranges between 0.75 V to 4.90 V. Heavy load operation is usually in
Region FM 3 where frequency modulation to output regulation is used and primary-peak current is controlled at
its maximum. The AM region is usually for medium-load range typically from 10% load and above. In this region
switching frequency is fixed at nominal 25 kHz along with primary-peak current varying from 25% to 100% of its
maximum. The low operating frequency ranges are for lighter loads to achieve stable regulation at low
frequencies. In regions FM 1 and 2, peak-primary current is always maintained at IPP(max)/4. Transitions between
levels are automatically accomplished by the controller depending on the internal control-law voltage, VCL and its
corresponding FB pin current IFB. An internal frequency-dithering mechanism is enabled in Region FM 3 to
reduce conducted EMI, and is disabled otherwise. The Wait state is enabled in regions FM 1, 2, and AM, refer to
图 11.
7.3.4 Constant Current Limit and Delayed Shutdown
Timing information at the VS pin and current information at the CS pin allow accurate regulation of the secondary
constant current limit, CCL, thus to achieve load over-current protection. The control law dictates that as power is
increased in CV regulation and approaching CCL the primary-peak current is at IPP(max). Referring to 图 13 below,
the primary peak current (IPP), turns-ratio (NS/NP), secondary demagnetization time (tDMAG), and switching period
(tSW) determine the secondary average output current. Ignoring leakage inductance effects, the average output
current is given by 公式 5. By regulating the secondary rectifier conduction duty cycle, the output current limit is
achieved for given IPP and transformer turns-ratio. When the load increases, the secondary-side rectifier
conduction duty cycle keep increasing. Once this duty cycle reaches preset value of 0.475, the converter
switching frequency stops increasing and starts adjusting to reduce and maintain 0.475 secondary-side duty
cycle. Therefore, the output constant current limit is achieved. Because the current is kept constant, the
increasing load results in lower output voltage.
IPP NP tDMAG
IOUT
=
ì
ì
2
NS
tSW
(5)
i
IPP
ISP x NS/NP
t
tON
tDMAG
tSW
图 13. Transformer Currents
As shown in 图 14 below, CV mode operation is from IO = 0 to < IOCC; at IO = IOCC, the operation enters constant
current limit mode and VO starts to drop as the load resistance becomes further lower while IO is maintained at
IOCC for a time interval specified by tOVL_TIME typically 120 ms then DRV stops to achieve converter output
delayed shutdown. During the 120-ms timing interval, if load IO reduces to < IOCC, the timer will be reset and no
shutdown will occur. The V-I curve corresponding to the operation is shown in 图 14, and the delayed shutdown
timing diagram is shown in 图 15. Note (1) The timer tOVL_TIME is triggered whenever IO reaches IOCC and reset
when IO drops to < IOCC before 120ms-time-out. (2) during 120-ms time interval, when load resistance becomes
so low during constant current interval that causes the device VDD to reach its VVDD(off) and then the shutdown
will be through VDD undervoltage lockout instead of through Constant Current Limit and Delayed Shutdown. In
such a case, the shutdown can happen before 120ms timer out.
16
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Feature Description (接下页)
Vo = VOCV
* VO delayed shutdown, 120ms after IO = IOCC
* Auto-retry after 3 cycles of VDD UVLO Off / On
Vo = IOCC x RLoad
0
IOCC
Output Current Io
图 14. Typical Target Output V-I Characteristics
VBULK
Overload œ Shutdown and Auto œ Restart
VDD(on)
VDD
VDD(off)
2.5 mA
IVDD
mA
2
1.5µA
1.5µA
1.5µA
1.5µA
1.5 µA
t
OVL _ Delay_ TIMER
<120 ms
OVL _ Delay_ TIMER
120 ms
DRV
DRV
IOCC
IOCC
VOCV
Vout
IOUT
VOUT = IOCC x RLOAD
VOUT = IOCC x RLOAD
图 15. Output Delayed Shutdown Timing
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Feature Description (接下页)
7.3.5 Valley-Switching and Valley-Skipping
The UCC28742 utilizes valley switching to reduce switching losses in the MOSFET, reduce induced-EMI, and
minimize the turn-on current spike at the sense resistor. The controller operates in valley-switching in all load
conditions unless the VDS ringing diminished.
Referring to 图 16 below, the UCC28742 operates in a valley-skipping mode in most load conditions to maintain
an accurate voltage or current regulation point and still switch on the lowest available VDS voltage.
VDS
0 V
VDRV
t
0 V
图 16. Valley-Skipping Mode
The UCC28742 forces a controlled minimum switching period corresponding to the power supply operating
frequency. In each switching cycle, after the minimum period is expired, the UCC28742 looks for the next
resonant valley on the auxiliary winding. The controller initiates a new power cycle at this valley point which
corresponds to a reduced voltage level on the power MOSFET. If at the point in time when the minimum period
expires ringing on the transformer winding has decayed such that no further resonant valleys can be detected a
new power cycle is initiated following a fixed time, tZTO. This also applies when primary inductance LP is designed
with a high value that causes de-mag end ringing cycle longer than tZTO. When either happens, the valley
switching is lost but the converter output voltage will still be in regulation.
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Feature Description (接下页)
7.3.6 Start-Up Operation
Upon application of input voltage to the converter, the start up resistance connected to VDD from the bulk
capacitor voltage (VBULK) charges the VDD capacitor. During charging of the VDD capacitor, the device supply
current is typical 1.5 µA. When VDD reaches the 21.6-V UVLO turn-on threshold, the controller is enabled and
the converter starts switching. The peak-primary currents with initial three cycles are limited to IPP(min). This allows
sensing any initial input or output faults with minimal power delivery. When confirmed that the input voltage is
above the programmed converter turn-on voltage and with no faults detected, the start-up process proceeds and
normal power conversion follows. The converter remains in discontinuous conduction mode operation during
charging of the output capacitor(s), maintaining a constant output current until the output voltage is in regulation.
A commonly used initial power-on approach for UCC28742 is to use a start-up resistor, RSTR, to tie VDD to
VBULK, as show in 图 17. With this approach, the VDD pin is connected to a bypass capacitor to ground and a
start-up resistance to the input bulk capacitor (+) terminal. The VDD turn-on UVLO threshold is 21.6 V (VVDD(on)
)
and turn-off UVLO threshold is 7.8 V (VVDD(off)), with an available operating range up to 35 V. The additional VDD
headroom up to 35 V allows for VDD to rise due to the leakage energy delivered to the VDD capacitor in heavy-
load conditions. Also, the wide VDD range provides the advantage of selecting a relatively small VDD capacitor
and high-value startup resistance to minimize no-load standby power loss in the startup resistor.
The RSTR value has an effect to power-on delay time and no-load standby power losses. Both are usually part of
the design specifications. Increasing RSTR reduces standby power losses while also increasing power-on delay
time. A typical range of RSTR is between 1 MΩ and 10 MΩ as a good initial design point for off-line AC-to-DC
adapters. Due to the limited voltage rating, RSTR is normally implemented by two or three resistors in series.
+ VF
-
VBULK
VOUT
CB1
CB2
COUT
NP
NS
RSTR
œ
VAC
RTL
+ VFA
-
VVDD
VAUX
VDD
ROPT
NA
CVDD
UCC28742
SOT23-6
RS1
RFB1
VE
VS
FB
DRV
CS
IOPT
ZFB
CFB3
RFB3
RS2
RLC
RCS
GND
RFB2
IFB
RFB4
图 17. Power-On with Start-Up Resistor
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Feature Description (接下页)
7.3.7 Fault Protection
There is comprehensive fault protection incorporated into the UCC28742. Protection functions include:
•
•
•
•
•
•
•
•
Output Over-Voltage
Input Under-Voltage
Primary Over-Current Fault
CS Pin Open Fault
CS Pin Short-to-GND Fault
VS Pin Fault
Device Internal Over-Temperature
Constant Current Limit and Delayed Output Shutdown - Output Over-Current Protection
Output Over-Voltage: The output over-voltage function is determined by the voltage feedback on the VS pin. If
the voltage sample on VS exceeds 4.65 V (VOVP), for three consecutive switching cycles an OV fault is asserted.
Once asserted the device stops switching, initiating a UVLO reset and re-start fault cycle. During the fault, the
VDD bias current remains at the run current level, discharging the VDD pin to the UVLO turn-off threshold,
VVDD(off). After that, the device returns to the start state, VDD now charging to VVDD(on) where switching is
initiated. The UVLO sequence repeats as long as the fault condition persists.
Input Under-Voltage: The line input run and stop thresholds are determined by current information at the VS pin
during the MOSFET on-time. While the VS pin is clamped close to GND during the MOSFET on-time, the current
through RS1, out of the VS pin, is monitored to determine a sample of the bulk capacitor voltage. A wide
separation of run and stop thresholds allows clean start-up and shut-down of the power supply with the line
voltage. From the start state, the sensed VS current, IVSL, must exceed the run current threshold, IVSL(run) (typical
211 µA), within the first three cycles after switching starts as VDD reaches VVDD(on). If it does not, then switching
stops and the UVLO reset and re-start fault cycle is initiated. Once running, IVSL must drop below the stop level,
IVSL(stop) (typically 75 µA), for three consecutive cycles to initiate the fault response.
Primary Over-Current: The UCC28742 always operates with cycle-by-cycle primary-peak current control. The
normal operating range of the CS pin is 190 mV to 770 mV. If the voltage on CS exceeds the 1.5-V over-current
level, any time after the internal leading edge blanking time and before the end of the transformer
demagnetization, for three consecutive cycles, the device shuts down and the UVLO reset and re-start fault cycle
begins.
CS Pin Open: The CS pin has a 2-µA minimum pull-up that brings the CS pin above the 1.5-V OC fault level if
the CS pin is open. This causes the primary over-current fault after three cycles.
CS Pin Short to GND: On the first, and only the first, cycle at start-up during power on, the device checks to
verify that the VCST(min) threshold is reached at the CS pin within 5 µs of DRV going high. If the CS voltage fails to
reach this level then the device terminates the current cycle and immediately enters the UVLO reset and re-start
fault sequence.
VS Pin: Protection is included in the event of component failures on the VS pin. If the high-side VS divider
resistor opens the controller stops switching. VDD collapses to its VVDD(off) threshold, a start-up attempt follows
with a single DRV on-time when VDD reaches VVDD(on). The UVLO cycle will repeat. If the low-side VS divider
resistor is open then an output over-voltage fault occurs.
Device Internal OTP: The internal over-temperature protection threshold is 165 °C. If the junction temperature of
the device reaches this threshold the device initiates the UVLO reset and re-start fault cycle. If the temperature is
still high at the end of the UVLO cycle, the protection cycle repeats.
Constant Current Limit and Delayed Output Shutdown - Output Over-Current Protection: The load over-
current protection is made precisely using constant current limit and delayed output shutdown as described in
section Constant Current Limit and Delayed Shutdown
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7.4 Device Functional Modes
The UCC28742 operates in different modes according to input voltage, VDD voltage, and output load conditions:
•
At start-up, when VDD is less than the turn-on threshold, VVDD(on) , the device is simply waiting for VDD to
reach this threshold while the VDD capacitor is getting charged.
•
When VDD exceeds VVDD(on), the device starts switching to deliver power to the converter output. The initial 3
switching cycles control the primary-peak current to IPP(min). This allows sensing any initial input or output
faults with minimal power delivery. When confirmed with input voltage above predetermined level and no fault
conditions, start up process proceeds and normal power conversion follows. The converter will remain in
discontinuous current mode operation during charging of the output capacitor(s), maintaining a constant
output current, IOCC, until the output voltage reaches its regulation point. The maximum time duration when IO
stays on IOCC can only last 120 ms, and when 120-ms timer out, the device will initiate shutdown. Therefore, a
design needs to make sure the maximum time when output current reaches and stays on IOCC does not
exceed 120 ms during start. For more details refer to Constant Current Limit and Delayed Shutdown
•
•
When operating with IPP = IPP(max), the UCC28742 operates continuously in the run state. In this state, the
VDD bias current is always at IRUN plus the average gate-drive current.
When operating with IPP < IPP(max), the UCC28742 operates in the wait state between switching cycles and in
the run state during a switching cycle. In the wait state, the VDD bias current is reduced to IWAIT after
demagnetizing time of each switching cycle to improve efficiency at light loads. This helps reduce no-load to
medium-load power losses, particularly for achieving higher efficiency at 10%, 25% load conditions, and
possible at < 50% load conditions, depending on a design.
•
•
The device operation will stop if any events occur as listed below:
–
If VDD drops below the VVDD(off) threshold, the device stops switching, its bias current consumption is
lowered to ISTART until VDD rises above the VVDD(on) threshold. The device then resumes operation through
start-up.
–
If a fault condition is detected, the device stops switching and its bias current consumption becomes
IFAULT. This current level discharges VDD to VVDD(off) where the bias current changes from IFAULT to ISTART
until VDD rises above the VVDD(on) threshold.
If a fault condition persists, the operation sequence described above in repeats until the fault condition or the
input voltage is removed. Refer to Fault Protection for fault conditions and post-fault operation.
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8 Applications and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The UCC28742 device is an SSR controller optimized for isolated-flyback AC-to-DC power supply applications,
typically in the range from 5 W to 50 W, providing constant-voltage (CV) mode control using optocoupler based
feedback. Its advanced control provides high performance operation. The device uses the information obtained
from auxiliary winding sensing (VS) to make an accurate output current limit with time delayed output voltage
shutdown and auto-start retry.
8.2 Typical Application
图 18 illustrates a typical circuit diagram for AC-to-DC power conversion applications. It is a flyback converter
with secondary-side regulation (SSR) controlled by UCC28742. Such applications widely exist in industrial and
medical AC/DC power supplies, and also in ac-dc adapters, etc. The following sub-sections provide critical
design formulas.
+ VF
-
VBULK
VOUT
CB1
CB2
COUT
NP
NS
RSTR
œ
VAC
RTL
+ VFA
-
VVDD
VAUX
VDD
ROPT
NA
CVDD
UCC28742
SOT23-6
RS1
RFB1
VE
VS
FB
DRV
CS
IOPT
ZFB
CFB3
RFB3
RS2
RLC
RCS
GND
RFB2
IFB
RFB4
图 18. Typical Application Circuit
22
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Typical Application (接下页)
8.2.1 Design Requirements
The following table illustrates a typical subset of high-level design requirements for a particular converter of
which many of the parameter values are used in the various design equations in this section. Other necessary
design parameters, VBULK(min) for example, may not be listed in such a table. These values may be selected
based on design experience or other considerations, and may be iterated to obtain optimal results.
表 1. UCC28742 Design Parameters
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
VIN
AC-line input voltage
Line frequency
85
47
115/230
50/60
65
265
63
VRMS
Hz
fLINE
PSTBY
No-load input power
VIN = typ, IO = 0A
mW
OUTPUT CHARACTERISTICS
VO
DC output voltage
VIN = typ, IO = 0 to IOR
VIN = typ, IO = IOR
VIN = min to max
VIN = typ
5
50
V
mV
A
VRIPPLE
IOR
Output voltage ripple
Output rated current
Overload current Limit
2.0
IOVL
2.05
120
A
OVL delay Overload shutdown delay
VIN= typ, IO = IOCC
ms
VIN= typ, average of 25%, 50%,
75%, and 100% Load
ηAVG Average efficiency
82
%
SYSTEMS CHARACTERISTICS
fsw Switching frequency
0.2
65
kHz
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8.2.2 Detailed Design Procedure
This procedure outlines the steps to design a constant output voltage (VOCV) flyback converter using the
UCC28742 controller. Please refer to the 图 18 for circuit details and section for variable definitions used in the
applications equations below.
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the UCC28742 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 VDD Capacitance, CDD
The capacitance on VDD needs to supply the device operating current until the output of the converter reaches
the target minimum operating voltage. At this time the auxiliary winding can sustain the voltage to the
UCC28742. The total output current available to the load and to charge the output capacitors is the constant-
current regulation target. The equation below assumes the output current of the flyback is available to charge the
output capacitance until the minimum output voltage is achieved to maintain VDD above its VVDD(on). The gate-
drive current depends on particular MOSFET to be used. If with an estimated average 1.0 mA of gate-drive
current, CDD is determined by 公式 6, and at IOCC, VOCC = VOCV
.
(6)
8.2.2.3 VDD Start-Up Resistance, RSTR
Once the VDD capacitance is known, the start-up resistance from VBULK to achieve the power-on delay time
(tSTR) target can be determined.
2 ì V
IN(min)
RSTR
=
VDD(on) ìCDD
ISTART
+
tSTR
(7)
24
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8.2.2.4 Input Bulk Capacitance and Minimum Bulk Voltage
Determine the minimum voltage on the input capacitance, CB1 and CB2 total, in order to determine the maximum
Np to Ns turns ratio of the transformer. The input power of the converter based on target full-load efficiency,
minimum input rms voltage, and minimum AC input frequency are used to determine the input capacitance
requirement.
Maximum input power is determined based on VOCV, load current over load IOVL= IOCC, and the full-load efficiency
target. An initial estimate of efficiency can be assumed for full-load efficiency, for example 89% for a converter of
rated power 48 W and output voltage 24 V.
VOCV ìIOCC
P =
IN
h
(8)
公式 9 provides an accurate solution for input capacitance based on a target minimum bulk capacitor voltage. To
target a given input capacitance value, iterate the minimum capacitor voltage to achieve the target capacitance.
≈
∆
’
÷
≈
’
VBULK(min)
1
∆
∆
«
÷
÷
◊
P ì 0.5 + ìarcsin
IN
p
∆
÷
2 ì V
IN(min)
«
◊
CBULK
=
2VI2N(min) - VB2ULK(min) ì f
LINE
(9)
8.2.2.5 Transformer Turns Ratio, Inductance, Primary-Peak Current
The maximum primary-to-secondary turns ratio can be determined by the target maximum switching frequency at
full load, the minimum input capacitor bulk voltage, and the estimated DCM resonant time.
Initially determine the maximum available total duty cycle of the on time and secondary conduction time based on
target switching frequency and DCM resonant time. For DCM resonant time, assume 500 kHz if you do not have
an estimate from previous designs. For the transition mode operation limit, the period required from the end of
secondary current conduction to the first valley of the VDS voltage is ½ of the DCM resonant period, or 1 µs
assuming 500-kHz resonant frequency. DMAX can be determined using 公式 10.
t
≈
’
◊
R
DMAX = 1-
ì fMAX ÷ -DMAGCC
∆
«
2
(10)
Once DMAX is known, the maximum turns ratio of the primary to secondary can be determined with the equation
below. DMAGCC is defined as the secondary diode conduction duty cycle when load current reaches a specified
limit operation. It is set internally by the UCC28742 at 0.475. The total voltage on the secondary winding needs
to be determined; which is the sum of VOCV and the secondary rectifier VF.
DMAX ì VBULK min
(
)
NPS max
=
(
)
DMAGCC ì V
+ VF
OCV
(11)
NPS is determined also with other design factors such as voltage and current ratings of primary MOSFET,
secondary rectifier diode, as well as secondary MOSFET if synchronous rectifier is used. Once an optimum
turns-ratio is determined from a detailed transformer design, use this ratio for the following parameters.
The UCC28742 controller constant current limit is achieved by maintaining DMAGCC = 0.475 at the maximum
primary current setting. The transformer turns ratio and current limit determine the current sense resistor for a
target constant current limit.
Since not all of the energy stored in the transformer is transferred to the secondary, a transformer efficiency term
is included. This efficiency number includes the core and winding losses, leakage inductance ratio, and bias
power ratio to rated output power. A bias power can be initially estimated at 0.1% to 0.5% rated power
depending on power rating. An overall transformer efficiency of 94.5% is a good estimation of assuming 2%
leakage inductance, 3% core and winding loss, and 0.5% bias power.
RCS is used to program the primary-peak current with 公式 12:
VCCR ìNPS
RCS
=
ì hXFMR
2 ìIOCC
(12)
25
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The primary transformer inductance can be calculated using the standard energy storage equation for flyback
transformers. Primary current, maximum switching frequency, output and transformer efficiency are included in
公式 14.
Initially the transformer primary current should be determined. Primary current is simply the maximum current
sense threshold divided by the current sense resistance.
VCST(max)
IPP(max)
=
RCS
(13)
2 ì V
hXFMR ì I2PP(max) ì fMAX
+ VF ì I
OCC
(
)
OCV
LP
=
(14)
The primary inductance LP in 公式 14 also needs to consider primary MOSFET minimum turn on time as
described in Transformer Parameter Verification.
The auxiliary winding to secondary winding transformer turns-ratio (NAS) is determined by the lowest target
operating output voltage VOVL at current limit and above the VDD(off) of the UCC28742. The output voltage
reaches VOVL when output current reaches its limit IOCC; VOVL is determined by IOCC and the expected minimum
load resistance RLOAD at IOCC, i.e., VOVL = IOCC x RLOAD. Note that VOVL can only be maintained within typical
120ms, and after that time, the output voltage will enter the cycle of shutdown and auto-start retry, as described
in Constant Current Limit and Delayed Shutdown, and shown in 图 14 and 图 15. There is additional energy
supplied to VDD from the transformer leakage inductance energy which may allow a slightly lower turns-ratio to
be used in a design. The NAS is then determined by the below equation.
VDD(off) + VFA
NAS
=
VOCC + VF
(15)
8.2.2.6 Transformer Parameter Verification
The transformer turns-ratio selected affects the MOSFET VDS and secondary rectifier reverse voltage so these
should be reviewed. The UCC28742 controller requires a minimum on time of the MOSFET (tON) and minimum
DMAG time (tDMAG(min)) of the secondary rectifier in the high line, under minimum-load condition. The selection of
fMAX, LP and RCS affects the minimum tON and tDMAG
.
The secondary rectifier and MOSFET voltage stress can be determined by the equations below.
VIN max ì 2
(
)
VREV
=
+ VOCV
NPS
(16)
For the MOSFET VDS voltage stress, an estimated leakage inductance voltage spike (VLK) needs to be included.
VDSPK = V
ì 2 + V
+ VF ì N + VLK
OCV
PS
IN max
(
)
(17)
The following equations are used to determine for the minimum tON target of 0.35 µs and minimum de-mag time,
tDMAG(min), target of 1.7 µs. Notice that the minimum tON target of 0.35 µs is determined by CS pin Leading-edge
blanking time, TCSLEB in Electrical Characteristics. The target is to design LP and make tON(min) ≥TCSLEB . But in
very worst normal operation condition, during the tON(min) , the CS pin OCP should not be triggered, i.e., the CS
pin should not reach near 1.41 V defined by VOCP in Electrical Characteristics.
IPP(max)
LP
IN(max) ì 2
tON(min)
=
ì
KAM
V
(18)
(19)
tON(min) ì VIN(max) ì 2
tDMAG(min)
=
NPS ì V
+ VF
OCV
26
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8.2.2.7 VS Resistor Divider and Line Compensation
The VS divider resistors determine the output voltage regulation point of the flyback converter, also the high-side
divider resistor (RS1) determines the line voltage at which the controller enables continuous DRV operation. RS1
is initially determined based on the transformer auxiliary to primary turns-ratio and the desired input voltage
operating threshold.
V
IN(run) ì 2
NPA ìIVSL(run)
IVSL(run) is VS pin run current with a typical value 210 µA for a design. The low-side VS pin resistor is selected
RS1
=
(20)
based on desired output over voltage VOV
.
RS1 ì VOVP
NAS ì (VOV + VF ) - VOVP
R S2
=
(21)
The UCC28742 can maintain tight output current limit over input line by utilizing the line compensation feature.
The line compensation resistor (RLC) value is determined by current flowing in RS1 and expected gate drive and
MOSFET turn-off delay. Assume a 50-ns internal delay in the UCC28742.
KLC ì RS1 ìRCS ì(tD + tGATE_ OFF)ìNPA
RLC
=
LP
(22)
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8.2.2.8 Standby Power Estimate
Assuming no-load standby power is a required design parameter, determine the estimated no-load power based
on target converter maximum switching frequency and output power rating. The following equation estimates the
stand-by power of the converter.
POUT ì fMIN
hìK2AM ì fMAX
PSB _ CONV
@
(23)
The output preload resistor can be estimated by VOCV and the difference between the converter stand-by power
and the no-load bias power PNL_BIAS (that can be set as zero initially and adjust it later, particularly through the
bench test), then the preload resistor value is estimated in 公式 24 :
VO2CV
RPL
=
PSB_CONV - PNL_BIAS
(24)
A physical resistor component RPLmay not be needed as other components on the secondary-side such as
TL431 can already provide enough preload.
The capacitor bulk voltage for the loss estimation is based on the highest voltage for the standby power
measurement, typically as 325 VDC (or AC input of 230 Vrms). Power loss of RSTR is estimated in公式 25:
2
(VBULK - VDD
)
PRSTR
=
RSTR
(25)
The total standby power, including the converter standby power loss, the start-up resistance power, and the
snubber power loss, is estimated in 公式 26:
PSB = PSB _ CONV + PRSTR + PSNBR
(26)
8.2.2.9 Output Capacitance
The output capacitance value is typically determined by the transient response requirement. 公式 27 assumes
that the switching frequency can be at the UCC28742 minimum of fSW(min)
.
≈
’
1
ITRAN
+ 50ms
∆
∆
«
÷
÷
◊
fSW(min)
COUT
=
DVO
(27)
Another consideration of the output capacitor(s) is the ripple voltage requirement. The output capacitors and their
total ESR are the main factors to determine the output voltage ripple. 公式 28 provides a formula to determine
required ESR value RESR, and 公式 28 provides a formula to determine required capacitance. The total output
ripple is the sum of these two parts with scale factors and 10mV to consider other noise as shown in 公式 30,
1
RESR
=
ì VRIPPLE_R
IPP(max) ìNPS
(28)
LP ì IP2P max
1
(
)
COUT =
ì
VRIPPLE_C
4 ì V
OCV
(29)
(30)
VRIPPLE = 0.81ì VRIPPLE_R +1.15ì VRIPPLE_C +10mV
Example: if require VRIPPLE = 70 mV, assume 0.81 × VRIPPLE_R = 1.15 × VRIPPLE_C = 30 mV, then RESR = 4.05
mΩ, and COUT = 643 µF, with assumption of LP = 700 µH, IPP(max) = 0.713 A, NPS = 13, VOCV = 5.3 V.
28
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8.2.2.10 Feedback Loop Design Consideration
Refer to 图 18, the UCC28742 converter feedback network is composed of TL431, optocoupler and several
resistors and capacitors. RFB1 and RFB2 set up the converter output regulation point. A series-resistor RFB3 is
necessary to limit the current into FB and to avoid excess draining of CVDD during this type of transient situation,
although connecting the emitter directly to the FB input of the UCC28742 is possible. However, an unload-step
response may unavoidably drive the optocoupler into saturation which will overload the FB input with full VDD
applied. The value of RFB3 is to limit the excess IFB to an acceptable level when the optocoupler is saturated. The
RFB3 value is chosen to allow the current into the FB pin to reach the 30 µA. the maximum IFB control level. This
will be met if the voltage at IFB can reach 1V at no load conditions. To improve transient response RFB3 can be
bypassed with CFB3
.
RFB4 can be used to set a nominal operating current of the optocoupler to improve the current transfer ratio and
bandwidth of the optocoupler. For low standby power this operating current level should be kept small since it
must be supplied from VDD operating voltage. The value of RFB4 is determined empirically due to the variable
nature of the specific optocoupler chosen for the design. The ratio of RFB4 to RFB3 is typically in a range of 1/10 to
1/4 with typical value of RFB4 in 4 kΩ to 25 kΩ, and RFB3 in 25 kΩ to 200 kΩ. A good starting point is to select
RFB4 around 4 kΩ and RFB3 around 30 kΩ for a design.
The shunt-regulator compensation network, ZFB, is determined using well-established design techniques for
control-loop stability. Typically, a Type-II compensation network is used. An effective approach is to set ZFB to be
a capacitor, ZFB = CFB to form an integrator, and adding a bypass capacitor RFB3 will extend the frequency
response of the optocoupler CTR.
Referring again to 图 18, the shunt-regulator (typically a TL431) current is at about 1 mA even when almost no
optocoupler diode current flows. Since even a near-zero diode current establishes a forward voltage, ROPT is
selected to provide regulator bias current such as for TL431. The optocoupler input diode must be characterized
by the designer to obtain the actual forward voltage versus forward current at the low currents expected. At the
full-load condition of the converter, IFB is around 0.5 µA, ICE may be around (0.4 V / RFB4), and CTR at this level
is about 10%, so the diode current typically falls in the range of 25 µA to 100 µA. Typical opto-diode forward
voltage at this level is about 0.97 V which is applied across ROPT. If ROPT is set equal to 1 kΩ, this provides 970
µA plus the diode current for IOPT
.
As output load decreases, the voltage across the shunt-regulator also decreases to increase the current through
the optocoupler diode. This increases the diode forward voltage across ROPT. CTR at no-load (when ICE is
higher) is generally a few percent higher than CTR at full-load (when ICE is lower). At steady-state no-load
condition, the shunt-regulator current is maximized and can be estimated by and 公式 31. IOPTNL, plus the sum of
the leakage currents of all the components on the output of the converter, constitute the total current required for
use in to estimate secondary-side standby loss.
ICENL
VOPTNL
IOPTNL
=
+
CTRNL
ROPT
(31)
The shunt-regulator voltage can decrease to a minimum, saturated level of about 2 V. To prevent excessive
diode current, a series resistor, RTL, is added to limit IOPT to the maximum value necessary for regulation. 公式
32 provides an estimated initial value for RTL, which may be adjusted for optimal limiting later during the
prototype evaluation process.
VOUTNL - VOPTNL - 2 V
RTL
=
IOPTNL
(32)
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8.2.3 Application Curves
85%
82.5%
80%
6
5
4
3
2
1
0
77.5%
75%
72.5%
70%
67.5%
65%
115 V RMS
230 V RMS
62.5%
60%
10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
Output Power
IOUT (A)
D001
D002
图 19. Efficiency
图 20. Output V-I Curves
图 22. Response to Load Step Changes
图 21. Constant Current Limit and Delayed Shutdown
图 23. Typical VOUT Start Up
图 24. Switching Waveforms (C3 = DRV, C4 = VDS, C2 = VO
Ripple, C1 = IPP
)
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8.3 Do's and Don'ts
•
During no-load operation, do allow sufficient margin for variations in VDD level to avoid the UVLO shutdown
threshold. Also, at no-load, keep the average switching frequency greater than 1.5 × fSW(min) typical to avoid a
rise in output voltage. RLC needs to be adjusted based on no-load operation accounting for both low-line and
high-line operation..
•
•
Do clean flux residue and contaminants from the PCB after assembly. Uncontrolled leakage current from VS
to GND causes the output voltage to increase, while leakage current from VDD to VS can cause output
voltage to increase.
If ceramic capacitors are used for VDD, do use quality parts with X7R or X5R dielectric rated 50 V or higher
to minimize reduction of capacitance due to DC-bias voltage and temperature variation.
•
•
Do not use leaky components if low stand-by input power consumption is a design requirement.
Do not probe the VS node with an ordinary oscilloscope probe; the probe capacitance can alter the signal and
disrupt regulation.
•
•
Do observe VS indirectly by probing the auxiliary winding voltage at RS1 and scaling the waveform by the VS
divider ratio.
Do follow 公式 27 to 公式 30 for COUT
.
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9 Power Supply Recommendations
The UCC28742 is intended for AC-to-DC adapters and chargers with universal input voltage range of 85 VRMS to
265 VRMS, 47 Hz to 63 Hz, using flyback topology. It can also be used in other applications and converter
topologies with different input voltages. Be sure that all voltages and currents are within the recommended
operating conditions and absolute maximum ratings of the device.
10 Layout
10.1 Layout Guidelines
In general, try to keep all high current loop areas as small as possible. Keep all traces with high current and high
frequency away from other traces in the design. If necessary, high frequency/high current traces should be
perpendicular to signal traces, not parallel to them. Shielding signal traces with ground traces can help reduce
noise pick up. Always consider appropriate clearances between the high-voltage connections and any low-
voltage nets.
In order to increase the reliability and feasibility of the project it is recommended to adhere to the following
guidelines for PCB layout. 图 25 shows a typical 10-W, 5-V/2-A converter design schematics.
•
•
Minimize stray capacitance on the VS node. Place the voltage sense resistors (RS1 and RS2 in) close to the
VS pin.
Arrange the components to minimize the loop areas of the switching currents as much as possible. These
areas include such loops as the transformer primary winding current loop (a), the MOSFET gate-drive loop
(b), the primary snubber loop (c), the auxiliary winding loop (d) and the secondary output current loop (e). In
practice, trade-offs may have to be made. Loops with higher current should be minimized with higher priority.
As a rule of thumb, the priority goes from high to low as (a) – (e) – (c) – (d) – (b).
•
•
•
The RLC resistor location is critical. To avoid any dv/dt induced noise (for example MOSFET drain dv/dt)
coupled onto this resistor, it is better to place RLC closer to the controller and avoid nearby the MOSFET.
Using Kelvin connection for long distance connection such as for connection between optocoupler and FB
pin.
To improve thermal performance increase the copper area connected to GND pins.
VBLK
D1
VOUT
+
C02
(a)
CB1
CB2
C01
RPL
NP
NS
L
(e)
œ
RSN1
CSN1
œ
VAC
N
DIN
(c)
Optional and short
across if not used
RSTR
RSN2
D2
(d)
VAUX
RTL
VDD
RG1
Q1
NA
DRV
CDD
UCC28742
SOT23-6
RS1
(b)
ROPT
VS
FB
RLC
IOPT
RS2
CS
RFB1
ZFB
Isolation
Boundary
RCS
GND
RFB2
CY
RFB4
RFB4
CFB
Optocoupler
Kelvin Connection
图 25. 10-W, 5-V/2-A Converter Schematics
32
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10.2 Layout Example
图 26 demonstrates a layout of 10-W, 5-V/2-A converter with trade-offs to minimize the loops while effectively
placing components and tracks for low noise operation on a single-layer printed circuit board. In addition to the
consideration of minimal loops, one another layout guideline is always to use the device GND as reference point.
This applies to both power and signal to return to the device GND pin (pin 5).
D1
Isolation Boundary
Transformer
Loop (c)
Loop (e)
Loop (a)
CO1
Y-Cap
Loop (d)
Kelvin
connection
CB2
UCC28742
Loop (b)
Input Rectifier DIN
Opto Coupler
图 26. Layout Example
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11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 使用 WEBENCH® 工具创建定制设计
请单击此处，使用 UCC28742 器件并借助 WEBENCH® 电源设计器创建定制设计方案。
1. 首先输入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。
3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案以常用 CAD 格式导出
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。
11.1.2 器件命名规则
11.1.2.1 电容术语（以法拉为单位）
CBULK
CDD
CB1 和 CB2 的总输入电容。
VDD 引脚所需的最小电容。
COUT
所需的最小输出电容。
11.1.2.2 占空比术语
DMAGCC CC 中二次侧二极管导通占空比，0.475。
DMAX 最大 MOSFET 导通时间占空比。
11.1.2.3 频率术语（以赫兹为单位）
fLINE
最低线路频率。
fMAX
转换器的最高目标满载开关频率。
fMIN
转换器的最低开关频率，在器件 fSW(min)限值基础上增加 15％ 的裕度。
负载减小后的瞬态开关频率
fSW(lim)
FSW(min)
fSW(max)
最低开关频率（见Electrical Characteristics表）
最大开关频率（见Electrical Characteristics表）
fSW(standby) 轻负载条件下负载变化之前的开关频率
11.1.2.4 电流术语（以安培为单位）
IOCC
转换器输出恒流目标。
IOR
转换器额定输出电流。
IPP(max)
ISTART
ITRAN
变压器一次侧最大电流。
启动偏置电源电流（见Electrical Characteristics表）。
所需的正负载阶跃电流。
IVSL(run)
VS 引脚运行电流（见Electrical Characteristics表）。
34
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UCC28742
www.ti.com.cn
ZHCSHY7A –APRIL 2018–REVISED MAY 2018
器件支持 (接下页)
IWAIT
等待状态期间的 VDD 偏置电流。（见Electrical Characteristics表）。
11.1.2.5 电流和电压调节术语
KAM
KCo
KLC
一次侧峰峰值电流比（见Electrical Characteristics表）。
稳定性因子为 100，用于计算 COUT
电流调节常量（见Electrical Characteristics表）。
。
版权 © 2018, Texas Instruments Incorporated
35
UCC28742
ZHCSHY7A –APRIL 2018–REVISED MAY 2018
www.ti.com.cn
器件支持 (接下页)
11.1.2.6 变压器术语
LP
变压器一次侧电感。
LS
变压器二次侧电感。
NAS
NPA
NPS
NA
变压器辅助绕组与二次侧绕组匝数比。
变压器一次侧绕组与辅助绕组匝数比。
变压器一次侧绕组与二次侧绕组匝数比。
变压器辅助绕组的匝数。
NP
变压器一次侧绕组的匝数。
变压器二次侧绕组的匝数。
NS
11.1.2.7 功率术语（以瓦特为单位）
PIN
转换器最大输入功率。
转换器的满载输出功率。
VDD 启动电阻功耗。
总待机功耗。
POUT
PRSTR
PSB
PSB_CONV
PSB 与启动电阻和缓冲器功耗的差值。
11.1.2.8 电阻术语（以 Ω 为单位）
RCS
RESR
RPL
一次侧电流编程电阻
输出电容的总 ESR。
转换器输出端的预载电阻。
高侧 VS 引脚电阻。
RS1
RS2
低侧 VS 引脚电阻。
RSTR
高电压与 VDD 之间连接的启动电阻
11.1.2.9 时序术语（以秒为单位）
tD
电流感测延迟。
tDMAG(min)
tGATE_OFF
tON(min)
tR
二次侧整流器最短导通时间。
一次侧主 MOSFET 关断时间。
MOSFET 最短导通时间。
tDMAG 之后的谐振环周期。
tSTR
由于 VDD 电容 CDD 需要充电时间所造成的上电延时。
tZTO：未检测到过零点时 VS 引脚上的过零点超时延迟（见Electrical Characteristics表）
tZTO
36
版权 © 2018, Texas Instruments Incorporated
UCC28742
www.ti.com.cn
ZHCSHY7A –APRIL 2018–REVISED MAY 2018
器件支持 (接下页)
11.1.2.10 电压术语（以伏特为单位）
VBLK 或 VBULK Bulk 电容器电压。
VBULK(max)
VBULK(min)
VBULK(run)
VCBC
用于待机功耗测量的 Bulk 电容器最高电压。
满功率条件下 CB1和 CB2 的最低电压。
转换器启动（运行）高电压。
满载时电路板端输出的电缆补偿电压。
VCCR
恒流调节电压（见Electrical Characteristics表）。
恒流输出电压关断的 VS 阈值（见Electrical Characteristics表）
CS 引脚的最大电流感测阈值（见Electrical Characteristics表）。
CS 引脚的最小电流感测阈值（见Electrical Characteristics表）。
VCCUV
VCST(max)
VCST(min)
VDD(off) 或 VVDD(off) UVLO 关断电压（见Electrical Characteristics表）。
VVDD(on) 或 VDD(on) UVLO 导通电压（见Electrical Characteristics表）。
VF
电流接近零时的二次侧整流器正向压降。
辅助整流器正向压降。
VFA
VLK
估计的漏感能量复位电压。
VOCV
VOCC
VOVL
经稳压的转换器输出电压。
恒流稳压条件下的最低目标转换器输出电压。
当输出电流达到其限值 IOCC 时，输出电压会达到 VOVL；VOVL 取决于 IOCC 和 IOCC 下的预期最低负载
电阻 RLOAD，也就是说 VOVL = IOCC x RLOAD
。
VRIPPLE
VVSR
满载条件下的输出峰峰值纹波电压。
VS 输入端的 CV 调节电平（见Electrical Characteristics表）。
11.1.2.11 交流电压术语（以 VRMS 为单位）
VIN(max)
VIN(min)
VIN(run)
转换器的最大输入电压。
转换器的最小输入电压。
转换器输入启动（运行）电压。
11.1.2.12 效率术语
η
转换器总体效率。
η10
10% 负载时的效率。
ηAVG
ηXFMR
25%、50%、75% 和 100% 负载时的算术平均效率。
变压器一次侧与二次侧之间的功率传输效率。
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
•
•
《UCC28742-1EVM-724 评估模块的用法》，SLUUBF1
《UCC28742 设计计算器》，SLUC652
版权 © 2018, Texas Instruments Incorporated
37
UCC28742
ZHCSHY7A –APRIL 2018–REVISED MAY 2018
www.ti.com.cn
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
38
版权 © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC28742DBVR
UCC28742DBVT
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
6
6
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
U742
U742
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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